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    Microcomputer Architecture PDF

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    The document discusses microcomputer architecture. It describes the Harvard and Von Neumann architectures, which differ in whether instructions and data use separate or shared memory and buses. It then focuses on the architecture of the MSP430 microcontroller, including its RISC design, registers, buses, ALU, and memory layout with separate flash, RAM and I/O sections addressable up to 64KB.

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    Microcomputer Architecture PDF

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    Thành Trường
    182 views15 pages
    The document discusses microcomputer architecture. It describes the Harvard and Von Neumann architectures, which differ in whether instructions and data use separate or shared memory and buses. It then focuses on the architecture of the MSP430 microcontroller, including its RISC design, registers, buses, ALU, and memory layout with separate flash, RAM and I/O sections addressable up to 64KB.

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    The document discusses microcomputer architecture. It describes the Harvard and Von Neumann architectures, which differ in whether instructions and data use separate or shared memory and buses. It then focuses on the architecture of the MSP430 microcontroller, including its RISC design, registers, buses, ALU, and memory layout with separate flash, RAM and I/O sections addressable up to 64KB.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    182 views15 pages

    Microcomputer Architecture PDF

    Uploaded by

    Thành Trường
    The document discusses microcomputer architecture. It describes the Harvard and Von Neumann architectures, which differ in whether instructions and data use separate or shared memory and buses. It then focuses on the architecture of the MSP430 microcontroller, including its RISC design, registers, buses, ALU, and memory layout with separate flash, RAM and I/O sections addressable up to 64KB.

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    © All Rights Reserved
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    of 15

    Chapter 2

    Microcomputer architecture
    2.1 Embedded system architecture

    Harvard Architecture
    Physically separate storage and signal pathways for instructions
    and data.

    DATA INSTRUCTION
    MEMORY MEMORY

    Control & Address


    Data Instruction

    Control
    IN
    ALU CONTROL
    OUT

    Status CLOCK

    Microcomputer principles and applications


    2.1 Embedded system architecture

    Von Neumann architecture


    Program instructions and Data are both stored as sequences of bits
    in computer memory.

    MEMORY

    INPUT OUTPUT
    * keyboard
    Address Bus Data Bus
    * monitor
    * mouse
    * printer
    * scanner
    * LEDs
    * A/D PROCESSING UNIT * D/A
    * serial
    * disk
    * disk ALU
    Registers
    Clock
    Program Counter
    Control
    Logic Instruction Register

    Microcomputer principles and applications


    2.2 MSP430 Architecture

    • Reduced instruction set computing (RISC).


    • Complex instruction set computing (CISC).

    Instructions
    and Data

    Processing
    Unit (CPU)

    Input / Output

    Microcomputer principles and applications


    2.2 MSP430 Architecture

    Microcomputer principles and applications


    2.2 MSP430 Architecture

    MSP430 Bus architecture


    Memory Address Bus (uni-directional)
    • Address Space = number of possible memory locations (also
    called the memory size).
    • Memory Address Register (MAR) stores the memory address
    for the address bus (address space).
    • Addresses peripherals as well as memory.
    Memory Data Bus (bi-directional)
    • Addressability = number of bits stored in each memory location.
    • Memory Select (MSEL) connects an addressed memory
    location to the data bus.
    • Memory Write Enable (MWE) is the control signal that is
    asserted when writing to memory.

    Microcomputer principles and applications


    2.2 MSP430 Architecture

    ALU
    • Arithmetic operations: add, subtract.
    • Logical operations: and, xor, bit.
    • Sets condition codes.
    • The word length of a computer is the number of bits processed
    by the ALU.
    Sixteen 16-bit registers
    • R0 (PC) – Program Counter
    ⋄ always points to the next instruction to be fetched.
    ⋄ each instruction occupies an even number of bytes → the
    least significant bit (LSB) of the PC register is always zero.
    ⋄ after fetch of an instruction, the PC register is incremented
    by 2, 4, or 6 to point to the next instruction.

    Microcomputer principles and applications


    2.2 MSP430 Architecture

    • R1 (SP) – Stack Pointer


    ⋄ stores the return address of routines or interrupts on the
    stack.
    ⋄ User programs store local data on the stack.
    ⋄ The SP can be incremented or decremented automatically
    with each stack access.
    ⋄ The stack "grows down" thru RAM and thus SP must be
    initialized with a valid RAM address.
    ⋄ SP always points to an even address, so its LSB is always
    zero.

    Microcomputer principles and applications


    2.2 MSP430 Architecture

    • R2 (SR/CG1) – Status Register


    ⋄ The status of the MSP430 CPU is defined by a set of bits
    contained in register R2.
    ⋄ This register can only be accessed through register
    addressing mode - all other addressing modes are reserved
    to support the constants generator.
    ⋄ The status register is used for clock selection, interrupt
    enable/disable, and instruction result status.

    15 9 8 7 6 5 4 3 2 1 0
    OSC CPU
    Reserved V SCG1 SCG0 GIE N Z C
    OFF OFF

    rw-0

    Microcomputer principles and applications


    2.2 MSP430 Architecture

    • R2 (SR/CG1) – Status Register


    . V: Overflow bit – set when arithmetic operation overflows the
    signed-variable range.
    . SCG1: System clock generator 1 – turns off the SMCLK.
    . SCG0: System clock generator 0 – turns off the DCO dc
    generator.
    . OSCOFF: Oscillator off – turns off the LFXT1 crystal
    oscillator.
    . CPUOFF: CPU off – turns off the CPU.
    . GIE: General interrupt enable – enables maskable interrupts.
    . N: Negative bit – set when the result of a byte or word
    operation is negative.
    . Z: Zero bit – set when the result of a byte or word operation
    is 0.
    . C: Carry bit – set when the result of a byte or word operation
    produces a carry.
    Microcomputer principles and applications
    2.2 MSP430 Architecture

    • R3 (CG2) – Constant Generators


    Six different constants can be generated using R2 and R3,
    without adding a 16-bit extension word of code. The constants
    are selected with the source-register addressing modes (As)

    Register As Constant Remarks


    R2 00 - Register mode
    R2 01 (0) Absolute mode
    R2 10 00004h +4, bit processing
    R2 11 00008h +8, bit processing
    R3 00 00000h 0, word processing
    R3 01 00001h +1
    R3 10 00002h +2, bit processing
    R3 11 0FFFFh -1, word processing

    Microcomputer principles and applications


    2.2 MSP430 Architecture

    • R4-R15 – General Purpose registers


    ⋄ The general purpose registers R4 to R15 can be used as
    data registers, data pointers and indices.
    ⋄ They can be accessed either as a byte or as a word.
    ⋄ Instruction formats support byte or word accesses.
    ⋄ The status bits of the CPU in the SR are updated after the
    execution of a register instruction.

    Microcomputer principles and applications


    2.2 MSP430 Architecture

    MSP430 Control Architecture


    Clock
    • System and peripheral clocks.
    Control Unit
    • The control unit directs the execution of the program.
    • The program counter or PC points to the next instruction to be
    executed.
    • The instruction register or IR contains the current executing
    instruction.
    • The status register or SR contains information about the last
    instruction executed as well as system parameters.
    • The control unit prevents bus conflicts and timing/propagation
    problems.
    • The control unit is a Finite State Machine driven by a clock.

    Microcomputer principles and applications


    2.2 MSP430 Architecture

    MSP430 memory architecture 0xFFFF

    • 64k byte addressable, address space

    Flash (ROM)
    (0x0000 – 0xFFFF).
    • Flash/ROM - Used for both code/data, In-
    terrupt vectors (upper 16 words).
    • RAM - Volatile storage.
    • Peripherals: 0x0100 – 0x01FF 16-bit pe-
    ripherals, 0x0010 – 0x00FF 8-bit peripher-
    als, Special Function Registers (lower 16

    RAM
    bytes).

    I/O
    0x0000

    Microcomputer principles and applications


    2.2 MSP430 Architecture

    Input / Output 0xFFFF

    • Used to get information in and out of the

    Flash (ROM)
    computer.
    • External devices attached to a computer
    are called peripherals.
    • Lower 512 (0x0000 – 0x01FF) of address
    space.

    RAM
    I/O
    0x0000

    Microcomputer principles and applications

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