24 GHZ FMCW Radar

A Single-Chip 24 GHz SiGe BiCMOS Transceiver for Low Cost
FMCW Airborne Radars

Dave Saunders1, Steve Bingham1, Gaurav Menon1, 3, Don Crockett1, Josh Tor1,
Ralph Mende2, Marc Behrens2, Nitin Jain3, Angelos Alexanian3, 4 and Rajanish3
1
US Monolithics, Gilbert, AZ, 85233, USA

Smart Microwave Sensors, Braunschweig, 38106, Germany
3
Anokiwave, San Diego, CA, 92130, USA
4
RFmaker, Somerville, MA, 02144, USA
Abstract The design and measured results of a highly

integrated FMCW radar transceiver are presented. The
transceiver includes a transmitter with +7dBm output power
and -82 dBc/Hz phase noise at 100 kHz, dual I/Q receivers
with 10dB NF and 18 dB gain, PLL, 15-bit DAC,
instrumentation amplifiers, LDO regulators, and a serial
programming interface all designed to operate from -40 to
+125C at 3.5V, 275 mA. Fabricated using Jazz
Semiconductors 0.18 m SiGe BiCMOS process and
packaged in a 32-pin 5 mm x 5 mm QFN, this RFIC has the
highest level of integration at 24 GHz known to the authors.
Index Terms CW radar, Chirp radar, digital-analog
conversion, FM radar, operational amplifiers, radar
receivers, radar transmitters, airborne radar, phase locked
loops, voltage controlled oscillator.
I. INTRODUCTION
Military aircraft manufacturers employ radar sensors to
enable features such as all-weather landing, weapons
control, altimeter, reconnaissance, and navigation. These
multiple applications are normally not satisfied by the
same sensor, making it imperative that each sensor be low
cost, be reliable under all environmental conditions, be
packaged in a small volume, consume low power, and
require little or no post installation alignment. Narrowband
radars in the 24 GHz ISM band are ideal for these
applications, having world-wide spectrum availability,
little degradation from radome material, and significantly
lower cost compared to higher frequency devices. By
modulating the transmitted signal with a combination of a
linear discrete frequency ramp and frequency shift keying
while simultaneously receiving the reflected signal,
accurate measurements of range, range rate, and azimuth
angle of reflectors (two antennas are used) can be
performed in short measurement cycles [1]. When the
relative velocity of the neighboring targets is zero with
respect to the transmitter, the frequency of the reflected
signal is identical to the transmitted frequency. Therefore,
a practical radar sensor must show excellent transmitter-to-
receiver isolation and very low noise at frequencies of only

a few Hertz for maximum sensitivity for distances from a
few meters to hundreds of meters.
The current solution for FMCW radars is to use multiple
chips in which the transmitter and receiver are on separate
die and enclosed in separate metal cavities or to use a
complete discrete implementation based on GaAs
components. Also, in most cases, the oscillator-PLLreference crystal is placed on a different circuit in a
shielded cavity. These do not lead to a low cost solution
and most important, require extensive calibration over
manufacturing runs. The goal of this work was to build a
highly integrated single-chip FMCW transceiver with all
the necessary components on a single-chip and with
adequate transmit-to-receive isolation. This has lead to a
significantly higher performance and lower cost solution
than available prior to this work.
II. SINGLE CHIP SOLUTION
The system-level architecture of the transceiver, shown
in Fig. 1, includes a transmitter with adjustable output
power, dual direct conversion receivers with adjustable
gain, an on-chip voltage controlled oscillator, an internal
DAC for frequency control, a PLL with instrumentation
amplifier for frequency calibration, a serial programming
interface, low drop out DC voltage regulators, and ESD
protection all designed to operate over a temperature
range from -40 to +125C. Shown in Fig. 2, the fully
functional transceiver die including all pads, can be
packaged in a standard 5 mm x 5 mm plastic 32-pin QFN.
A. Transmitter
The transmitter operates in the 24 GHz ISM band.
Within this frequency band, peak emission levels of 20
dBm EIRP are allowed under ETSI rules [2] and 32.7
dBm EIRP under FCC rules [3]. Used in conjunction with
an antenna gain with from 16 to 26 dBi, the RFIC power
LPF
AMP
Cap
Select
Fine
Tune
Coarse
Tune
DAC
VCO
Counter
A/B/R
SPI
TX
VCO
24.125 GHz
AMP
0 90
DAC
PA
x4
PLL Enable
Control
Bits
PLL
INST. AMP
Rx Gain
RX2
LPF
I2
Q2
Fig. 1.
Tx
Gain
Gain
Adjust
AMP
Vreg
SPI
Tx Enable
6.03125 GHz
PLL
Lock
LO1
0 90
Vreg
RX1
Rx Gain
LO2
Vtune
LNA
LPF
VREG
I1
Q1
LNA
LPF
MMIC Architecture Diagram
amplifier is based on a standard cascode topology and is

required to generate over +6 dBm output power. To
accommodate different antenna gain for various
applications and compensate for temperature variation, the
output power can be reduced in steps of less than 1 dB.
The transmitter can be muted with more than 50 dB of onto-off isolation.
B. VCO, x4 Multiplier, and DAC
The 6 GHz VCO is based on a differential crosscoupled design with a bank of switched capacitors to
compensate for process variation. A low noise PTAT and
a 3.1V regulator were used to ensure circuit performance
over PVT. The VCO output is fed to both the PLL and a
two-stage x4 active multiplier used to translate the VCO
output to 24 GHz. A low noise 15-bit DAC is used to
generate a tightly controlled tuning voltage allowing the
frequency to be digitally swept with a resolution of less
than 25 kHz over a frequency range exceeding 200 MHz.
With this tuning range, process compensation, and dc
regulation, the VCO maintains excellent 1/f noise and
achieves a phase noise spectral density of -82 dBc/Hz at
100 kHz offset at 24 GHz with only slight degradation
over temperature. Frequency chirps covering the full ISM
band can be commanded with step times < 100 s.
C. I/Q Receivers
Two direct-conversion receivers are based on a cascode
design with emitter degeneration inductors to achieve
required gain with low noise and high linearity. The
performance at 24 GHz shows 18 dB gain, 10 dB noise
Fig. 2.
MMIC Die Photograph
figure, and -15 dBm input P1dB. The receiver chain

includes a variable gain amplifier with a gain step of 10
dB. The low noise amplifiers feed into the RF port of
Gilbert cell mixers while the LO port is driven by a
buffered version of the transmitted signal. The I/Q network
is implemented using a LC passive filter while the RF path
has a standard T-junction divider with controlled
impedances. The I/Q phase error is +/-5 deg. over all
conditions. The IF ports are DC coupled with a bandwidth
of 250 MHz.
D. PLL
The PLL provides a means of calibrating the output
frequency of the VCO without the need for a second high
frequency oscillator or second frequency reference (patent
pending). The PLL includes a programmable reference
divider, phase frequency detector, charge pump, dual
modulus prescaler, and programmable A/B counters. The
loop filter uses off-chip components due to the large
capacitance needed. The PLL can lock at 0.5 MHz
intervals across the full ISM band. An on-chip lock
detector with a discrete output allows the PLL control to
be monitored.
E. SPI
The digital serial programming interface provides a
standard interface for configuring gains, operating
frequency, and process compensation. The three-line
control uses 16-bit transfers with multiplexed address and
data bits. Secondary registers store more than 60 control
bits, allowing the output power, frequency, and receive
gain to be controlled over a standard interface during

sensor operation.
F. Implementation
The chip was designed in the Jazz SBC18HA with 6
metal layers. The process is based on a 0.18um SiGe
transistor with an FT of 150 GHz. The inductors,
transmission-lines and pads are placed on the top metal
layer (metal 6, 2.8 um aluminum) in balanced-like
transmission line configuration. All critical inductors and
transmission-lines are modeled using full EM simulations
[4] with user defined shields. The S-parameters were
placed in the design files and simulated with standard Jazz
models for the transistors and other passive devices.
G. Packaging
The chip was packaged in a standard 32-pin QFN plastic
package. The bond-wire inductance and the differential
transitions between the chip and the RF board were
simulated using HFSS [5], and compensated using internal
matching networks. Rat-race couplers translate the singleended antenna ports to differential lines. Bias decoupling
capacitors and IF (radar) shaping filters are included on
the RF board.
IV. RFIC TEST RESULTS
Testing of the RFIC has been performed on wafer, on
packaged parts, in RF front-end testing in an anechoic
chamber, in automotive sensors during test drives, in
security sensors for securing perimeters of prisons or high
value facilities, and as an altimeter on an unmanned aerial
vehicle. Die level testing used a wafer probe station with
temperature controlled chuck to obtain performance data
over a temperature range of -40C to +125C. A photo of
the probe station is shown in Figure 4a. Package level
testing was performed using a plunge-to-board, high
frequency socket as shown in Fig. 4b. Test data was also
taken with the packaged part assembled onto an RF frontend (see inset of Fig. 4c). The RF front-end testing was
performed over temperature in an anechoic chamber as
shown in Fig. 4c and has undergone high temperature life
testing at 105C for 2000 hours. The back side of the RF
front-end printed circuit board includes three planar
microstrip antenna arrays one transmit array (19 dBi)
and two receive arrays (12.2 dBi), which interface to
antennas at the top of the chamber.
A. Transmitter Output
The transmitter output power and phase noise are shown
in Fig. 5 and Fig. 6. The measured output power at 24
GHz, which ranges from 23 to 24 dBm EIRP at 23C, has
Fig. 4. Test stations used for performance verification: a)

wafer probe station showing quadrant probe (top), b) socket test
board (middle), and c) RF front end station with circuit board
inset
only 1 dB variation over the full 24 GHz ISM band and

only a 3 dB of variation over the full temperature range.
The phase noise at 100 kHz offset from a 24.125 GHz
carrier varies from -80 to -83 dBc/Hz over the full

temperature range.
105C, LoGain
105C, HiGain
-40C, LoGain
-40C, HiGain
23C, LoGain
23C, HiGain
-84
25.0
24.5
-88
Sensitivity (dBm)
24.0
EIRP (dBm)
23.5
23.0
22.5
22.0
-92
-96
-100
21.5
21.0
105C
20.5
20.0
24.025
-40C
-104
23C
24.025
24.075
24.125
24.175
24.225
Frequency (GHz)
Phase Noise Spectral Density (dBc/Hz)
Fig. 5. Transmit power vs. frequency over the full temperature

range. Data was taken using test set-up shown in Fig. 4c.
-40C
23C
-70
-80
-90
-100
-110
10
100
24.125
24.175
Frequency (GHz)
24.225
Fig. 7. Receiver sensitivity as defined by 10 dB SINAD in

200 Hz bandwidth. Data was taken using test set-up shown in
Fig. 4c.
Laboratory testing of RF front-end, automotive reliability

and drive testing, and field testing of the complete radar
sensor on a UAV with ranges measured up to 600 meters
demonstrate that this single-chip FMCW radar transceiver
exceeds the design goals set by a highly focused, crossfunctional team composed of system, circuit, mechanical,
and manufacturing engineers and, most importantly, can be
produced using high volume, low cost standard SMT
assembly and test techniques. This advanced technology is
available as a packaged MMIC, a RF front-end, and as a
complete sensor with integrated signal processing.
-60
105C
24.075
1000
Offset Frequency (kHz )
Fig. 6. 24 GHz transmit phase noise vs. offset frequency over

full temperature range. Data was taken using test set-up shown in
Fig. 4c.
B. Receiver Sensitivity
The receiver gain flatness, gain adjustment step size, and
high Tx-to-Rx isolation are demonstrated in the plot of
sensitivity versus frequency shown in Fig. 7.
VII. CONCLUSION
The design and measured results of a highly integrated
SiGe BiCMOS FMCW radar transceiver have been
presented. Testing at the wafer and package level has
shown excellent correlation to the simulated results.
ACKNOWLEDGEMENT
The authors acknowledge the assistance and support of
Jazz Semiconductor, Professor Gabriel Rebeiz at UCSD
and many others at USM and SMS. Layout help from
Hani Sidhom is much appreciated. Flight test was courtesy
of Glen Bailey and the team at STARA Technologies Inc.
REFERENCES
[1] M. M. Meinecke, H. Rohling, Combination of FSK and
LFMCW Modulation Principals for Automotive Radars,
German Radar Symposium GRS2000, Berlin, October
2000.
[2] ETSI EN 302 288-1 V1.2.1 (2006-05)
[3] CFR Title 47 Part 15.245
[4] Sonnet Software, http://www.sonnetsoftware.com
[5] Ansoft Corp., http://www.ansoft.com

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What is the goal of this work?

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What are the main components of the transceiver?

What are the main components of the transceiver?

A Single-Chip 24 GHz SiGe BiCMOS Transceiver for Low Cost

FMCW Airborne Radars

US Monolithics, Gilbert, AZ, 85233, USA

Abstract The design and measured results of a highly

receiver isolation and very low noise at frequencies of only

MMIC Architecture Diagram

amplifier is based on a standard cascode topology and is

MMIC Die Photograph

figure, and -15 dBm input P1dB. The receiver chain

gain to be controlled over a standard interface during

Fig. 4. Test stations used for performance verification: a)

only 1 dB variation over the full 24 GHz ISM band and

carrier varies from -80 to -83 dBc/Hz over the full

Phase Noise Spectral Density (dBc/Hz)

Fig. 5. Transmit power vs. frequency over the full temperature

Fig. 7. Receiver sensitivity as defined by 10 dB SINAD in

Laboratory testing of RF front-end, automotive reliability

Offset Frequency (kHz )

Fig. 6. 24 GHz transmit phase noise vs. offset frequency over

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