IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 24, NO.

1, JANUARY 2014 65
UHF Surface Dynamics Parameters
Radar Design and Experiment
Sichao Wang, Biyang Wen, Caijun Wang, Zhisheng Yan, Ke Li, and Jing Yang
AbstractThis letter proposes a new ultra high frequency
(UHF) radar system called UHF surface dynamics parameters
radar (USDPR). The hardware has been developed based on the
surface currents radar (SCR) system for an all-digital receiver
platform, which realizes direct radio frequency (RF) band-pass
sampling and orthogonal demodulation of the amplied echo, as
compared with traditional intermediate frequency (IF) receivers.
Closed-loop test and eld test proves the correctness of the design.
Index TermsAll-digital receiver, band-pass sampling, orthog-
onal demodulation, surface currents, UHF radar.
I. INTRODUCTION
O
VER the last two decades, ultra high frequency (UHF)
radar remote sensing has become a popular non-contact
method of measuring surface currents. The surface currents
radar (SCR) system, developed by Wuhan University in 2005,
has achieved successful result in Tangsun River experiment
[1]. The UHF surface dynamics parameters radar (USDPR)
system upgrades the SCR receiver from super-heterodyne to
direct-sampling architecture. This promising architecture has
been intensively studied in radio synthesis telescope receivers,
receivers supporting cellular and wireless standards, and
ultra-wideband (UWB) receivers recently [2][4].
As demonstrated in Fig. 1, The USDPR system is composed
of antennas, transmitter, receiver, power supply and computer.
Compared with the SCR, the USDPR receiver realizes direct
radio frequency (RF) sampling, which offers mainly two advan-
tages: 1) does not suffer from analog mixer image problem and
local oscillator harmonics problem, 2) owns less amplitude con-
sistence error and phase orthogonality error of the in-phase and
quadrature (I/Q) signal. Compared with other direct RF sam-
pling receivers, the USDPR system implements the coordinate
rotation digital compute (CORDIC) algorithmfor chirp echo de-
modulation, instead of traditional frequency synthesis mul-
tiplying method, which provides mainly two advantages: 1)
saves the overhead of a large quarter-wave sine/cosine look-up
table and a multi-bit complex multiplier, 2) produces less spec-
tral spurs caused by both the phase and amplitude quantization
of the frequency synthesis process [5], [6].
Manuscript received April 16, 2013; revised September 07, 2013; accepted
October 16, 2013. Date of publication November 08, 2013; date of current ver-
sion January 06, 2014. This work was supported by the National Nature Sci-
ence Foundation of China (61001186, 61072086), Specialized Research Fund
for the Doctoral Programof Higher Education(20090141120019) , and Public
Science and Technology Research Funds Projects of Ocean (201205032).
The authors are with the Radar and Signal Processing Laboratory, Elec-
tronic Information School, Wuhan University, Wuhan 430079, China (e-mail:
[email protected]; [email protected]).
Digital Object Identier 10.1109/LMWC.2013.2288268
Fig. 1. UHF radar system architecture.
II. WAVEFORM PARAMETERS DESIGN
The USDPRsystem utilizes frequency modulated interrupted
continuous wave (FMICW) to realize mono-static geometry [7].
The sweep bandwidth is 15.36 MHz and the sweep interval is
0.1024 s, so the sweep rate is and the range res-
olution of 9.77 m. After orthogonal demodulation, the baseband
signal is an analytic signal with only positive frequency spectral
components, and the negative frequency components are elim-
inated. The design species the maximum range of 2.5 Km for
near-shore detection, so the maximal baseband frequency offset
will be 2.5 KHz. In our system, the baseband sampling fre-
quency is 80 KHz and the interrupted pulse repetition frequency
(PRF) is 10 KHz, both are more than that of the offset, therefore
will not cause range aliasing. In addition, the duty cycle of the
interrupted pulse is 46%.
Based on the 340 MHz center frequency, the Bragg-resonant
frequency will be 1.88 Hz. In this design, the frame period is
0.1028 s, which is the sumof 0.1024 s sweep interval and 0.4 ms
transfer time. So the Doppler bandwidth is 9.73 Hz, more than
twice that of the Bragg frequency. Acoherent integration period
contains 1024 frame periods, resulting in a Doppler resolution
of 0.0095 Hz and velocity resolution of 0.42 cm/s. According
to the waveform parameters design stated above, the maximum
current speed that the USDPR system can measure is 1.32 m/s.
III. REALIZATION OF ALL MODULES
A. Analog Board
As shown in Fig. 2, signal from antennas is amplied by low
noise ampliers and ltered by narrow bandwidth lters on the
analog board. In each pulse repetition interval (PRI, 100 s),
the digital board asserts bate ground wave (BGW) pulse during
46.8100 s to the analog board, which allows the echo enter
into the analog board. The analog board achieves 36 dB gain,
122 dBm sensitivity, 76 dB spurious free dynamic range
(SFDR), 60 dB isolation effect and less than 3 dB atness.
B. Frequency Synthesis Board
As shown in Fig. 3, there is a 80 MHz crystal oscillator with
ultra low phase noise on the frequency synthesis board. The
1531-1309 2013 IEEE
66 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 24, NO. 1, JANUARY 2014
Fig. 2. Analog board architecture.
Fig. 3. Frequency synthesis board architecture.
Fig. 4. Digital board architecture.
clock source, after driven by a clock buffer, feeds to the phase
locked loop (PLL). The PLL outputs two signals with the same
initial phase to ensure the system coherence. One (81.92 MHz)
is supplied to the digital board, while the other (983.04 MHz) is
provided to the direct digital synthesizer (DDS) chip as a refer-
ence clock. The digital board issues conguration parameters to
the DDS chip for the generation of the desired FMICW signal.
After back-end analog circuits composed of transformer, lter,
switch and amplier, the signal with 0 dBm is sent to the trans-
mitter. The frequency synthesis board achieves 52 dB SFDR,
and less than 1 dB atness.
C. Digital Board
As shown in Fig. 4, the clock buffer on the digital board re-
ceives 81.92 MHz clock signal from frequency synthesis board
and distributes seven 81.92 MHz clock with the same frequency
and phase to six channel A/D Converters (ADCs) and one eld
programmable gate array (FPGA). The AD9265 from Analog
Devices Inc. (ADI) is equipped with both wide analog band-
width and high resolution to realize the high-speed data ac-
quisition of the amplied echo signal. In the ADC front-end
circuit design, the use of transformer reduces the noise, while
providing a good coupling mechanism for the ultra high fre-
quency input. The FPGA implements CORDIC demodulation
algorithm to mix with the incoming echo, removing its carrier
frequency and slope ramp. Besides, decimation and ltering are
also implemented in FPGA. The processed data is transferred
to the computer using universal serial bus (USB) with a high
speed. Meanwhile, in each PRI, the digital board asserts trans-
mitting pulse (TP) during 046 s to the transmitter, otherwise
the transmitter shuts off. The digital board achieves 86 dBm
quantization level and more than 10 MB/s transfer speed.
D. Transmitter and Antenna
The transmitter of the USDPR system does not need high
power. The transmitter power of the USDPR is up to 1 W. The
antennas consist of a transmitting antenna and six receiving an-
TABLE I
SPECIFICATION OF TRANSMITTER AND ANTENNA
tennas. Seven yagis are used in the USDPR system. The speci-
cations of transmitter and antenna are shown in Table I.
E. Signal Processors Implemented in FPGA
In FPGA, orthogonal demodulation is realized by CORDIC
in rotation mode. Two data inputs of the CORDIC calculator
are congured as the sampled data-stream and zero, while the
phase input is implemented through a frequency accumulator
and a phase accumulator. In each clock cycle, the frequency
accumulator adds itself with a delta frequency tone word
(DFTW) and the phase accumulator, whose initial value is
the frequency tone word (FTW), adds itself with the ever-in-
creasing value stored in the frequency accumulator. The DFTW
and FTW are determined so that the step rate and the lower
ramp limit are exactly the same as those of the sampled version
of the transmitted signal. Cascaded integrator comb (CIC) lter
implements narrowband low-pass lters for I, Q signals with
high decimation rate. Windowing module multiplies pre-stored
read-only memory (ROM) coefcients with CIC output data.
The frequency calculation module receives the data after win-
dowing and performs fast Fourier transform (FFT) to maximize
the signal-to-noise ratio (SNR). As each frequency point repre-
sents 9.77 m, calculating the lower 1024 points is enough for
echo information extraction. Each FFT output point is the sum
of point-by-point products of the input sequence with sequences
representing a sine and a cosine wave. For the sake of saving
resources, this design uses one multiplying accumulation
unit (the operating clock is up to 163.84 MHz), through time
division multiplexing, to accomplish this calculation.
F. Signal Processing in the Computer
Range spectrum is calculated by the FFT within a single
frame, where the range term is predominant as compared with
the Doppler term. Doppler spectrum of a certain range cell is
obtained through the Welchs averaged modied periodogram
method over coherent frames of that range cell based on the
FFT result, since the amplitude changes slightly from frame
to frame, the only variation is the phase factor, which contains
target velocity information [8], [9].
IV. CLOSED-LOOP TEST AND FIELD TEST RESULT
A. Closed-Loop Test
In the closed-loop test, echo signal can be simulated by de-
laying the transmitted signal for a certain period of time. After
WANG et al.: UHF SURFACE DYNAMICS PARAMETERS RADAR DESIGN AND EXPERIMENT 67
Fig. 5. First FFT result of simulation echo.
Fig. 6. Doppler spectrum of eld test.
ADC sampling and FPGA demodulation, the FFT result is sent
to the computer. Fig. 5 shows that the simulation echo appears
in the 192 range cell, which precisely agrees with the time delay
congured in FPGA.
B. Field Test
In order to evaluate the performance of the USDPR system,
an experiment was done at the East China Sea, Zhoushan, Zhe-
jiang, China during August 2012. The yagi antennas are located
about 30 m from the near shore and 3 m above the ocean sur-
face, looking directly across the sea. The transmitter operates
with less than 1 W power.
Fig. 6 shows the Doppler spectrum of the 58th range cell
in channel one. There is a negative peak at Bragg frequency,
and the SNR is about 40 dB. It is generated by rst-order scat-
tering from the Bragg waves which ows radially away from
radar. Positive peak is not obvious, the explanation is: waves
have been driven by the wind blowing away from radar and the
back-scattered energy from waves moving towards radar is rel-
atively small. Also, there are smaller peaks in the vicinity of the
Braggs, which are likely second order scattering effects caused
by double scattering off two ocean waves.
V. CONCLUSION
Based on our experience, it is required that the SNR is more
than 10 dB for measuring ocean surface current. In the USDPR
system, 1545 dB SNR with 1 Km maximum detection range
was achieved with 1 W transmitter and 11.2 dBi gain antennas,
in place of 5 W and 13 dBi gain budget in the SCR system
[1]. Moreover, the USDPR system realizes direct sampling and
CORDIC demodulation. The analog mixer and local oscillator
in the SCR system are therefore eliminated, which improves
both the receiver dynamic range (from 60 to 76 dB) and the sen-
sitivity (from 107 dBm to 122 dBm). Meanwhile, the dig-
ital demodulation implemented in FPGA is more accurate and
repeatable. The tradeoff is the increased requirement for A/D
sampling, such as higher sampling rate and better resolution.
Additionally, the USDPR system uses FMICW, which differs
from FMCW in SCR system, isolation was realized by alter-
nately asserting TP and BGW signal in each PRI, without the
need to set a wire netting between the transmitting antenna and
receiving antennas, or separate them away for more than 40 m.
In conclusion, the innovative architecture of receiver, appro-
priate application of CORDIC for echo demodulation, and the
modied design of waveformparameters were proved to be suc-
cessful in the closed-loop test and eld test.
ACKNOWLEDGMENT
The authors would like to thank Y.W. Tian, J. Tan, D.P. Jiang,
and S.C. Wu for their work in the lab.
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