SN54AHC02, SN74AHC02

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCLS254IJ DECEMBER 1995 REVISED SEPTEMBER 2002

13

12

11

10

1A
1B
2Y
2A
2B

14

1A
1Y
NC
VCC

SN54AHC02 . . . FK PACKAGE
(TOP VIEW)

1B
NC
2Y
NC
2A

13 4Y

2
3

12 4B

11 4A
10 3Y
9 3B

5
6
7

2 1 20 19
18

17

16

15

14
9 10 11 12 13

4B
NC
4A
NC
3Y

2B
GND
NC
3A
3B

VCC
4Y
4B
4A
3Y
3B
3A

VCC

14

3A

1Y

SN74AHC02 . . . RGY PACKAGE

(TOP VIEW)

SN54AHC02 . . . J OR W PACKAGE
SN74AHC02 . . . D, DB, DGV, N, NS
OR PW PACKAGE
(TOP VIEW)

1Y
1A
1B
2Y
2A
2B
GND

ESD Protection Exceeds JESD 22

2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
1000-V Charged-Device Model (C101)

4Y

Operating Range 2-V to 5.5-V VCC

Latch-Up Performance Exceeds 250 mA Per
JESD 17

GND

D
D

NC No internal connection

description/ordering information
The AHC02 devices contain four independent 2-input NOR gates that perform the Boolean function
Y = A S B or Y = A + B in positive logic.
ORDERING INFORMATION
TOP-SIDE
MARKING

QFN RGY

Tape and reel

SN74AHC02RGYR

HA02

PDIP N

Tube

SN74AHC02N

SN74AHC02N

Tube

SN74AHC02D

Tape and reel

SN74AHC02DR

SOP NS

Tape and reel

SN74AHC02NSR

AHC02

SSOP DB

Tape and reel

SN74AHC02DBR

HA02

TSSOP PW

Tape and reel

SN74AHC02PWR

HA02

TVSOP DGV

Tape and reel

SN74AHC02DGVR

HA02

CDIP J

Tube

SNJ54AHC02J

SNJ54AHC02J

CFP W

Tube

SNJ54AHC02W

SNJ54AHC02W

LCCC FK

Tube

SNJ54AHC02FK

SNJ54AHC02FK

SOIC D
40C
40
C to 85C
85 C

55C to 125C

ORDERABLE
PART NUMBER

PACKAGE

TA

AHC02

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN54AHC02, SN74AHC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS254IJ DECEMBER 1995 REVISED SEPTEMBER 2002

FUNCTION TABLE
(each gate)
INPUTS
A

OUTPUT
Y

logic diagram (positive logic)

1A
1B
2A
2B

3
5
6

1Y

3A
3B

2Y

4A
4B

10

9
11
12

13

3Y

4Y

Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W
(see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN54AHC02, SN74AHC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS254IJ DECEMBER 1995 REVISED SEPTEMBER 2002

recommended operating conditions (see Note 4)

SN54AHC02
VCC

Supply voltage

VIH

VCC = 2 V
VCC = 3 V

High-level input voltage

Low-level input voltage

VI
VO

5.5

Output voltage

t/v

5.5

2.1

V
V

0.5

0.9

0.9

1.65

1.65

5.5

5.5

VCC
50

VCC
50

mA

VCC = 3.3 V 0.3 V

VCC = 5 V 0.5 V
VCC = 3.3 V 0.3 V

Input transition rise or fall rate

UNIT

1.5
3.85

VCC = 2 V
VCC = 3.3 V 0.3 V

Low-level output current

MAX

2.1

VCC = 5 V 0.5 V
VCC = 2 V
IOL

MIN

3.85

VCC = 3 V
VCC = 5.5 V

High-level output current

SN74AHC02

0.5

Input voltage

IOH

MAX

1.5

VCC = 5.5 V
VCC = 2 V
VIL

MIN

VCC = 5 V 0.5 V

50

50

100

100

20

20

mA

mA
mA
ns/V

TA
Operating free-air temperature
55
125
40
85
C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
PARAMETER

TEST CONDITIONS

IOH = 50 mA
VOH
IOH = 4 mA
IOH = 8 mA
IOL = 50 mA
VOL
IOL = 4 mA
IOL = 8 mA

MIN

TA = 25C
TYP
MAX

2V

1.9

1.9

1.9

3V

2.9

2.9

2.9

4.5 V

4.4

4.5

4.4

4.4

3V

2.58

2.48

2.48

4.5 V

3.94

3.8

VCC

SN54AHC02
MIN

MAX

SN74AHC02
MIN

MAX

UNIT

3.8

2V

0.1

0.1

0.1

3V

0.1

0.1

0.1

4.5 V

0.1

0.1

0.1

3V

0.36

0.5

0.44

4.5 V

0.36

0.5

0.44

0 V to 5.5 V

0.1

1*

mA

IO = 0
5.5 V
2
VI = VCC or GND
5V
4
10
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.

20

20

mA

10

pF

II
ICC

VI = 5.5 V or GND
VI = VCC or GND,

Ci

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

SN54AHC02, SN74AHC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS254IJ DECEMBER 1995 REVISED SEPTEMBER 2002

switching characteristics over recommended operating free-air temperature range,

VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

LOAD
CAPACITANCE

tPLH
tPHL

A or B

CL = 15 pF

tPLH
tPHL

A or B

CL = 50 pF

MIN

TA = 25C
TYP
MAX

SN54AHC02

SN74AHC02

MIN

MAX

MIN

MAX

5.6*

7.9*

1*

9.5*

9.5

5.6*

7.9*

1*

9.5*

9.5

8.1

11.4

13

13

8.1

11.4

13

13

UNIT
ns
ns

On products compliant to MIL-PRF-38535, this parameter is not production tested.

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER

FROM
(INPUT)

TO
(OUTPUT)

LOAD
CAPACITANCE

tPLH
tPHL

A or B

CL = 15 pF

tPLH
tPHL

A or B

CL = 50 pF

MIN

TA = 25C
TYP
MAX

SN54AHC02

SN74AHC02

MIN

MAX

MIN

MAX

3.6*

5.5*

1*

6.5*

6.5

3.6*

5.5*

1*

6.5*

6.5

5.1

7.5

8.5

8.5

5.1

7.5

8.5

8.5

UNIT
ns
ns

On products compliant to MIL-PRF-38535, this parameter is not production tested.

noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25C (see Note 5)

SN74AHC02

PARAMETER

MIN

MAX

UNIT

VOL(P)
VOL(V)

Quiet output, maximum dynamic VOL

0.8

Quiet output, minimum dynamic VOL

0.8

VOH(V)
VIH(D)

Quiet output, minimum dynamic VOH

4.9

High-level dynamic input voltage

3.5

VIL(D)
Low-level dynamic input voltage
NOTE 5: Characteristics are for surface-mount packages only.

1.5

TYP

UNIT

operating characteristics, VCC = 5 V, TA = 25C

PARAMETER
Cpd

TEST CONDITIONS

Power dissipation capacitance

No load,

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

f = 1 MHz

15

pF

SN54AHC02, SN74AHC02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS254IJ DECEMBER 1995 REVISED SEPTEMBER 2002

PARAMETER MEASUREMENT INFORMATION

From Output
Under Test

RL = 1 k

From Output
Under Test

Test
Point

S1

VCC
Open

TEST

GND

CL
(see Note A)

CL
(see Note A)

S1

tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain

Open
VCC
GND
VCC

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

VCC
50% VCC

Timing Input
tw
tsu

VCC
Input

50% VCC

50% VCC

0V

th

VCC
50% VCC

Data Input

50% VCC

0V

0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC

Input

50% VCC
0V

tPLH
In-Phase
Output

tPHL
50% VCC

tPHL
Out-of-Phase
Output

VOH
50% VCC
VOL

Output
Waveform 1
S1 at VCC
(see Note B)

VOH
50% VCC
VOL

VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS

50% VCC

50% VCC
0V

tPZL

tPLZ
VCC
50% VCC

tPZH

tPLH
50% VCC

VCC

Output
Control

Output
Waveform 2
S1 at GND
(see Note B)

VOL + 0.3 V

VOL

tPHZ
50% VCC

VOH 0.3 V

VOH
0 V

VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TIs terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TIs standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding thirdparty products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

Copyright 2002, Texas Instruments Incorporated