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    High Performance Computing

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    Mohammad Bilal Mirza
    This document outlines the syllabus for a video course on high performance computer architecture. The course covers various topics related to computer architecture including instruction level parallelism techniques like pipelining and branch prediction, memory hierarchies, thread and process level parallelism, and peripheral devices. The course is divided into 5 modules covering review of basic architectural techniques, instruction level parallelism, memory hierarchies, thread level parallelism, and process level parallelism. Modern processors like Pentium and ARM are discussed as examples of deploying instruction level parallelism techniques.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    High Performance Computing

    Uploaded by

    Mohammad Bilal Mirza
    118 views6 pages
    This document outlines the syllabus for a video course on high performance computer architecture. The course covers various topics related to computer architecture including instruction level parallelism techniques like pipelining and branch prediction, memory hierarchies, thread and process level parallelism, and peripheral devices. The course is divided into 5 modules covering review of basic architectural techniques, instruction level parallelism, memory hierarchies, thread level parallelism, and process level parallelism. Modern processors like Pentium and ARM are discussed as examples of deploying instruction level parallelism techniques.

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    HPC in detail

    Original Title

    High performance Computing

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    This document outlines the syllabus for a video course on high performance computer architecture. The course covers various topics related to computer architecture including instruction level parallelism techniques like pipelining and branch prediction, memory hierarchies, thread and process level parallelism, and peripheral devices. The course is divided into 5 modules covering review of basic architectural techniques, instruction level parallelism, memory hierarchies, thread level parallelism, and process level parallelism. Modern processors like Pentium and ARM are discussed as examples of deploying instruction level parallelism techniques.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    118 views6 pages

    High Performance Computing

    Uploaded by

    Mohammad Bilal Mirza
    This document outlines the syllabus for a video course on high performance computer architecture. The course covers various topics related to computer architecture including instruction level parallelism techniques like pipelining and branch prediction, memory hierarchies, thread and process level parallelism, and peripheral devices. The course is divided into 5 modules covering review of basic architectural techniques, instruction level parallelism, memory hierarchies, thread level parallelism, and process level parallelism. Modern processors like Pentium and ARM are discussed as examples of deploying instruction level parallelism techniques.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 6

    NPTEL Syllabus

    High Performance Computer


    Architecture - Video course
    COURSE OUTLINE
    Review of
    Techniques

    Basic

    Organization

    and

    Architectural

    RISC processors
    Characteristics of RISC processors
    RISC Vs CISC
    Classification of Instruction Set Architectures
    Review of performance measurements

    NPTEL
    http://nptel.iitm.ac.in

    Computer
    Science and
    Engineering

    Basic parallel processing techniques: instruction level,


    thread level and
    Pre-requisites:
    process level
    Classification of parallel architectures
    Instruction Level Parallelism
    Basic concepts of pipelining
    Arithmetic pipelines

    Programming and Data


    Structures Operating
    Systems Computer
    Architecture and Organization.
    Additional Reading:

    Instruction pipelines

    SIMA, Advanced Computer


    Architectures, AddisonHazards in a pipeline: structural, data, and control Wesley.
    hazards
    Overview of hazard resolution techniques

    Coordinator:

    Dynamic instruction scheduling

    Prof. Ajit Pal


    Department of Computer
    Science and EngineeringIIT
    Kharagpur

    Branch prediction techniques


    Instruction-level parallelism using software approaches
    Superscalar techniques
    Speculative execution
    Review of modern processors /*The objective is to
    explain how ILP

    techniques have been deployed in modern processors*/


    a. Pentium Processor:
    microarchitectures

    IA

    32

    and

    P6

    b. ARM Processor
    Memory Hierarchies
    Basic concept of hierarchical memory organization
    Main memories
    Cache memory design and implementation
    Virtual memory design and implementation
    Secondary memory technology
    RAID
    Peripheral Devices
    Bus structures and standards
    Synchronous and asynchronous buses
    Types and uses of storage devices
    Interfacing I/O to the rest of the system
    Reliability and availability
    I/O system design
    Platform architecture
    Thread Level Parallelism
    Centralized vs. distributed shared memory
    Interconnection topologies
    Multiprocessor architecture
    Symmetric multiprocessors
    Cache coherence problem
    Synchronization
    Memory consistency
    Multicore architecture
    Review of modern multiprocessors
    Process Level Parallelism
    Distributed computers

    Clusters
    Grid
    Mainframe computers
    COURSE DETAIL

    Module

    Review of
    Basic
    Organization
    and
    Architectural
    Techniques

    Topics

    RISC processors

    No.of
    Hours

    Characteristics of RISC
    processors

    RISC Vs CISC

    Classification of Instruction Set


    Architectures

    Review of performance
    measurements

    Basic parallel processing


    techniques: instruction level,
    thread level and process level

    Classification of parallel
    architectures

    Basic concepts of pipelining

    Instruction pipelines versus


    functional pipelines

    Instruction
    Level
    Parallelism

    Basic concepts of pipelining

    Arithmetic pipelines

    Instruction pipelines

    Hazards in a pipeline: structural,


    data, and control hazards

    Overview of hazard resolution


    techniques

    Dynamic instruction scheduling

    Branch prediction techniques

    Instruction-level parallelism using


    software approaches

    Superscalar techniques

    Speculative execution

    Review of modern processors


    /*The objective is to explain how
    ILP techniques have been
    deployed in modern processors*/
    i. Pentium Processor: IA 32
    and P6 microarchitectures
    ii. ARM Processor

    Memory
    Hierarchies

    Basic concept of hierarchical


    memory organization

    Main memories

    Cache design and optimization

    Virtual memory design and

    implementation

    Memory protection

    Evaluating memory hierarchy


    performance

    RAID

    Thread Level
    Parallelism

    Centralized vs. distributed shared


    memory

    Interconnection topologies

    Synchronization

    Memory consistency

    Review of modern
    multiprocessors

    Process
    Level
    Parallelism

    Distributed computers

    Clusters

    Grid

    Mainframe computers

    Peripheral
    Devices

    Bus structures and standards

    Types and uses of storage


    devices

    Interfacing I/O to the rest of the

    system

    Reliability and availability

    I/O system design

    References:
    1. Hennessey and Patterson, "Computer Architecture: A
    quantitative Approach", Morgan Kaufman.
    A joint venture by IISc and IITs, funded by MHRD, Govt of India

    http://nptel.iitm.ac.in

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