Xilinx XC95108 15PC84C Datasheet

0
XC95108 In-System
Programmable CPLD
DS066 (v4.4) April 3, 2006
Product Specification
Features
Description
7.5 ns pin-to-pin logic delays on all pins

fCNT to 125 MHz
108 macrocells with 2,400 usable gates

Up to 108 user I/O pins
5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 84-pin PLCC, 100-pin PQFP, 100-pin
TQFP, and 160-pin PQFP packages
The XC95108 is a high-performance CPLD providing

advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architecture overview.
Power dissipation can be reduced in the XC95108 by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95108
device.
300
(250)
manc
Typical ICC (mA)
Power Management
erfor
High P
200
(180)
(170)
wer
ow Po
L
100
50
100
Clock Frequency (MHz)

DS066_01_110501
Figure 1: Typical ICC vs. Frequency for XC95108
2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS066 (v4.4) April 3, 2006

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XC95108 In-System Programmable CPLD
3
JTAG Port
JTAG
Controller
In-System Programming Controller
36
Function
Block 1
18
I/O
Macrocells
1 to 18
I/O
Fast CONNECT II Switch Matrix
I/O
I/O
I/O
Blocks
I/O
I/O
I/O
36
Function
Block 2
18
Macrocells
1 to 18
36
Function
Block 3
18
Macrocells
1 to 18
I/O
3
I/O/GCK
36
1
Function
Block 4
18
I/O/GSR
2
Macrocells
1 to 18
I/O/GTS
36
Function
Block 5
18
Macrocells
1 to 18
36
Function
Block 6
18
Macrocells
1 to 18
DS066_02_110101
Figure 2: XC95108 Architecture

Function block outputs (indicated by the bold line) drive the I/O blocks directly.
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DS066 (v4.4) April 3, 2006

Absolute Maximum Ratings

Symbol
Description
Value
Units
0.5 to 7.0
VCC
Supply voltage relative to GND
VIN
Input voltage relative to GND
0.5 to VCC + 0.5
VTS
Voltage applied to 3-state output
0.5 to VCC + 0.5
TSTG
Storage temperature (ambient)
65 to +150
oC
+150
oC
TJ
Junction temperature
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions

Symbol
VCCINT
VCCIO
Parameter
Supply voltage for internal logic
and input buffers
Supply voltage for output drivers
for 5V operation
Commercial TA = 0oC to 70oC

Industrial TA =
40oC
to
+85oC
Commercial TA = 0oC to 70oC

Industrial TA =
40oC
to
+85oC
Supply voltage for output drivers for 3.3V operation
Min
Max
Units
4.75
5.25
4.5
5.5
4.75
5.25
4.5
5.5
3.0
3.6
VIL
Low-level input voltage
0.80
VIH
High-level input voltage
2.0
VCCINT + 0.5
VO
Output voltage
VCCIO
Quality and Reliability Characteristics

Symbol
Parameter
TDR
Data Retention
NPE
Program/Erase Cycles (Endurance)
Min
Max
Units
20
Years
10,000
Cycles
DC Characteristic Over Recommended Operating Conditions

Symbol
VOH
Parameter
Test Conditions
Min
Max
Units
Output high voltage for 5V outputs
IOH = 4.0 mA, VCC = Min
2.4
Output high voltage for 3.3V outputs
IOH = 3.2 mA, VCC = Min
2.4
Output low voltage for 5V outputs
IOL = 24 mA, VCC = Min
0.5
Output low voltage for 3.3V outputs
IOL = 10 mA, VCC = Min
0.4
IIL
Input leakage current
VCC = Max
VIN = GND or VCC
10
IIH
I/O high-Z leakage current
VCC = Max
VIN = GND or VCC
10
CIN
I/O capacitance
VIN = GND
f = 1.0 MHz
10
pF
ICC
Operating supply current

(low power mode, active)
VI = GND, No load
f = 1.0 MHz
VOL
DS066 (v4.4) April 3, 2006

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100 (Typical)
mA
AC Characteristics
Symbol
Parameter
XC95108-7
XC95108-10
XC95108-15
XC95108-20
Min
Max
Min
Max
Min
Max
Min
Max
Units
7.5
10.0
15.0
20.0
ns
4.5
6.0
8.0
10.0
ns
TPD
I/O to output valid
TSU
I/O setup time before GCK
TH
I/O hold time after GCK
ns
GCK to output valid
4.5
6.0
8.0
10.0
ns
16-bit counter frequency
125.0
111.1
95.2
83.3
MHz
Multiple FB internal operating

frequency
83.3
66.7
55.6
50.0
MHz
TPSU
I/O setup time before p-term clock

input
0.5
2.0
4.0
4.0
ns
TPH
I/O hold time after p-term clock input
4.0
4.0
4.0
6.0
ns
P-term clock output valid
8.5
10.0
12.0
16.0
ns
TOE
GTS to output valid
5.5
6.0
11.0
16.0
ns
TOD
GTS to output disable
5.5
6.0
11.0
16.0
ns
TPOE
Product term OE to output enabled
9.5
10.0
14.0
18.0
ns
TPOD
Product term OE to output disabled
9.5
10.0
14.0
18.0
ns
TWLH
GCK pulse width (High or Low)
4.0
4.5
5.5
5.5
ns
Asynchronous preset/reset pulse

width (High or Low)
7.0
7.5
8.0
8.0
ns
TCO
fCNT
(1)
fSYSTEM
(2)
TPCO
TAPRPW
Notes:
1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
VTEST
R1
Output Type
VCCIO
VTEST
R1
R2
CL
5.0V
5.0V
160
120
35 pF
3.3V
3.3V
260
360
35 pF
Device Output
R2
CL
DS067_03_110101
Figure 3: AC Load Circuit
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DS066 (v4.4) April 3, 2006

Internal Timing Parameters

Symbol
Parameter
XC95108-7
XC95108-10
XC95108-15
XC95108-20
Min
Max
Min
Max
Min
Max
Min
Max
Units
Buffer Delays
TIN
Input buffer delay
2.5
3.5
4.5
6.5
ns
TGCK
GCK buffer delay
1.5
2.5
3.0
3.0
ns
TGSR
GSR buffer delay
4.5
6.0
7.5
9.5
ns
TGTS
GTS buffer delay
5.5
6.0
11.0
16.0
ns
TOUT
Output buffer delay
2.5
3.0
4.5
6.5
ns
TEN
Output buffer enable/disable delay
ns
Product Term Control Delays

TPTCK
Product term clock delay
3.0
3.0
2.5
2.5
ns
TPTSR
Product term set/reset delay
2.0
2.5
3.0
3.0
ns
TPTTS
Product term 3-state delay
4.5
3.5
5.0
5.0
ns
0.5
1.0
3.0
4.0
ns
Internal Register and Combinatorial Delays

TPDI
Combinatorial logic propagation delay
TSUI
Register setup time
1.5
2.5
3.5
3.5
ns
THI
Register hold time
3.0
3.5
4.5
6.5
ns
TCOI
Register clock to output valid time
0.5
0.5
0.5
0.5
ns
TAOI
Register async. S/R to output delay
6.5
7.0
8.0
8.0
ns
TRAI
Register async. S/R recover before clock
7.5
10.0
10.0
10.0
ns
TLOGI
Internal logic delay
2.0
2.5
3.0
3.0
ns
TLOGILP Internal low power logic delay
10.0
11.0
11.5
11.5
ns
Feedback Delays
TF
FastCONNECT feedback delay
8.0
9.5
11.0
13.0
ns
TLF
Function block local feedback delay
4.0
3.5
3.5
5.0
ns
TPTA(1) Incremental product term allocator delay
1.0
1.0
1.0
1.5
ns
TSLEW
4.0
4.5
5.0
5.5
ns
Time Adders
Slew-rate limited delay
Notes:
1. TPTA is multiplied by the span of the function as defined in the XC9500 family data sheet.
DS066 (v4.4) April 3, 2006

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XC95108 I/O Pins

Function
Block
Macrocell
PC84 PQ100
TQ100 PQ160
BScan
Order
Function
Block
Macrocell
PC84 PQ100
TQ100 PQ160
BScan
Order
25
321
45
213
15
13
21
318
14
31
29
47
210
16
14
22
315
15
32
30
49
207
21
19
29
312
36
34
57
204
17
15
23
309
17
34
32
54
201
18
16
24
306
18
35
33
56
198
27
303
50
195
19
17
26
300
19
37
35
58
192
20
18
28
297
20
38
36
59
189
10
26
24
36
294
10
45
43
69
186
11
22
20
30
291
11
21
39
37
60
183
12
9[1]
24[1]
22[1]
33[1]
288[1]
12
23
41
39
62
180
13
34
285
13
52
177
14
10[1]
25[1]
23[1]
35[1]
282[1]
14
24
42
40
63
174
15
11
27
25
37
279
15
25
43
41
64
171
16
12[1]
29[1]
27[1]
42[1]
276[1]
16
26
44
42
68
168
17
13
30
28
44
273
17
31
51
49
77
165
18
43
270
18
74
162
158
267
123
159
71
98
96
154
264
57
83
81
134
156
72
99
97
156
261
58
84
82
135
153
258
82
80
133
150
74[1]
1[1]
99[1]
159[1]
255[1]
61
87
85
138
147
75
252
62
88
86
139
144
249
128
141
76[1]
5[1]
3[1]
6[1]
246[1]
63
89
87
140
138
77[1]
6[1]
4[1]
8[1]
243[1]
65
91
89
142
135
10
12
240
10
147
132
11
79
11
237
11
66
92
90
143
129
12
80
10
13
234
12
67
93
91
144
126
13
14
231
13
153
123
14
81
11
15
228
14
68
95
93
146
120
15
82
12
10
17
225
15
69
96
94
148
117
16
83
13
11
18
222
16
94
92
145
114
17
84
14
12
19
219
17
70
97
95
152
111
18
16
216
18
155
108
Notes:
1. Global control pin.
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DS066 (v4.4) April 3, 2006

XC95108 I/O Pins (Continued)

Function
Block
Macrocell
BScan
Order
Function
Block
Macrocell
76
105
91
51
32
52
50
79
102
45
67
65
103
48
33
54
52
82
99
46
68
66
104
45
48
46
72
96
75
73
116
42
34
55
53
86
93
47
69
67
106
39
35
56
54
88
90
48
70
68
108
36
78
87
36
57
55
90
84
50
105
33
72
70
111
30
37
58
56
92
81
51
73
71
113
27
10
84
78
10
107
24
PC84 PQ100
TQ100 PQ160
PC84 PQ100
TQ100 PQ160
BScan
Order
11
39
60
58
95
75
11
52
74
72
115
21
12
40
62
60
97
72
12
53
76
74
117
18
13
87
69
13
112
15
14
41
63
61
98
66
14
54
78
76
122
12
15
43
65
63
101
63
15
55
79
77
124
16
61
59
96
60
16
81
79
129
17
44
66
64
102
57
17
56
80
78
126
18
89
54
18
114
XC95108 Global, JTAG, and Power Pins

Pin Type
PC84
PQ100
TQ100
PQ160
I/O/GCK1
24
22
33
I/O/GCK2
10
25
23
35
I/O/GCK3
12
29
27
42
I/O/GTS1
76
I/O/GTS2
77
I/O/GSR
74
99
159
TCK
30
50
48
75
TDI
28
47
45
71
TDO
59
85
83
136
TMS
29
49
47
73
VCCINT 5V
38,73,78
7,59,100
5,57,98
10,46,94,157
VCCIO 3.3V/5V
22,64
28,40,53,90
26,38,51,88
1,41,61,81,121,141
GND
8,16,27,42,49,60
2,23,33,46,64,71,77,86
100,21,31,44,62,69,75,84
20,31,40,51,70,80,99
GND
100,110,120,127,137
GND
160
No connects
3,5,7,32,38,39,48,53,55,6
5,66,67,83,85,93,109,
118,119,125,130,131,
132,149,150,151
DS066 (v4.4) April 3, 2006

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Device Part Marking and Ordering Combination Information

R
XC95xxx
TQ144
Device Type
Package
This line not

related to device
part number
7C
Speed
Operating Range
Sample package with part marking.
Device Ordering and

Part Marking Number
XC95108-7PC84C
XC95108-7PCG84C
XC95108-7PQ100C
XC95108-7PQG100C
XC95108-7TQ100C
XC95108-7TQG100C
XC95108-7PQ160C
XC95108-7PQG160C
XC95108-7PC84I
XC95108-7PCG84I
XC95108-7PQ100I
XC95108-7PQG100I
XC95108-7TQ100I
XC95108-7TQG100I
XC95108-7PQ160I
XC95108-7PQG160I
XC95108-10PC84C
XC95108-10PCG84C
XC95108-10PQ100C
XC95108-10PQG100C
XC95108-10TQ100C
XC95108-10TQG100C
XC95108-10PQ160C
XC95108-10PQG160C
XC95108-10PC84I
XC95108-10PCG84I
XC95108-10PQ100I
XC95108-10PQG100I
XC95108-10TQ100I
XC95108-10TQG100I
XC95108-10PQ160I
XC95108-10PQG160I
XC95108-15PC84C
Speed
(pin-to-pin
delay)
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
7.5 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
10 ns
15 ns
Pkg.
Symbol
PC84
PGC84
PQ100
PQG100
TQ100
TQG100
PQ160
PQG160
PC84
PCG84
PQ100
PQG100
TQ100
TQG100
PQ160
PQG160
PC84
PCG84
PQ100
PQG100
TQ100
TQG100
PQ160
PQG160
PC84
PCG84
PQ100
PQG100
TQ100
TQG100
PQ160
PQG160
PC84
No. of
Pins
84-pin
84-pin
100-pin
100-pin
100-pin
100-pin
160-pin
160-pin
84-pin
84-pin
100-pin
100-pin
100-pin
100-pin
160-pin
160-pin
84-pin
84-pin
100-pin
100-pin
100-pin
100-pin
160-pin
160-pin
84-pin
84-pin
100-pin
100-pin
100-pin
100-pin
160-pin
160-pin
84-pin
Package Type
Plastic Lead Chip Carrier (PLCC)
Plastic Lead Chip Carrier (PLCC); Pb-Free
Plastic Quad Flat Pack (PQFP)
Plastic Quad Flat Pack (PQFP); Pb-Free
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP); Pb-Free
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Operating
Range(1)
C
C
C
C
C
C
C
C
I
I
I
I
I
I
I
I
C
C
C
C
C
C
C
C
I
I
I
I
I
I
I
I
C
DS066 (v4.4) April 3, 2006

Device Ordering and

Part Marking Number
XC95108-15PCG84C
XC95108-15PQ100C
XC95108-15PQG100C
XC95108-15TQ100C
XC95108-15TQG100C
XC95108-15PQ160C
XC95108-15PQG160C
XC95108-15PC84I
XC95108-15PCG84I
XC95108-15PQ100I
XC95108-15PQG100I
XC95108-15TQ100I
XC95108-15TQG100I
XC95108-15PQ160I
XC95108-15PQG160I
XC95108-20PC84C
XC95108-20PCG84C
XC95108-20PQ100C
XC95108-20PQG100C
XC95108-20TQ100C
XC95108-20TQG100C
XC95108-20PQ160C
XC95108-20PQG160C
XC95108-20PC84I
XC95108-20PCG84I
XC95108-20PQ100I
XC95108-20PQG100I
XC95108-20TQ100I
XC95108-20TQG100I
XC95108-20PQ160I
XC95108-20PQG160I
Speed
(pin-to-pin
delay)
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
15 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
20 ns
Pkg.
Symbol
PCG84
PQ100
PQG100
TQ100
TQG100
PQ160
PQG160
PC84
PCG84
PQ100
PQG100
TQ100
TQG100
PQ160
PQG160
PC84
PCG84
PQ100
PQG100
TQ100
TQG100
PQ160
PQG160
PC84
PCG84
PQ100
PQG100
TQ100
TQG100
PQ160
PQG160
No. of
Pins
84-pin
100-pin
100-pin
100-pin
100-pin
160-pin
160-pin
84-pin
84-pin
100-pin
100-pin
100-pin
100-pin
160-pin
160-pin
84-pin
84-pin
100-pin
100-pin
100-pin
100-pin
160-pin
160-pin
84-pin
84-pin
100-pin
100-pin
100-pin
100-pin
160-pin
160-pin
Package Type
Operating
Range(1)
C
C
C
C
C
C
C
I
I
I
I
I
I
I
I
C
C
C
C
C
C
C
C
I
I
I
I
I
I
I
I
Notes:
1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = 40 to +85C
DS066 (v4.4) April 3, 2006

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Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Additional Information
XC9500 Data Sheets and Application Notes
Online Store
Device Packaging
Revision History
The following table shows the revision history for this document.
10
Date
Version
Revision
12/04/98
3.0
Update AC characteristics and internal parameters.
06/18/03
4.0
Updated format.
08/21/03
4.1
Updated Package Device Marking Pin 1 orientation.
03/01/04
4.2
Updated table on page 8 for PQ160 pins.
04/15/05
4.3
Added asynchronous preset/reset pulse width specification (TAPRPW).
04/03/06
4.4
Added Warranty Disclaimer. Added Pb-Free package ordering information.
www.xilinx.com
DS066 (v4.4) April 3, 2006


Xilinx XC95108 15PC84C Datasheet

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DS066 (v4.4) April 3, 2006

7.5 ns pin-to-pin logic delays on all pins

108 macrocells with 2,400 usable gates

The XC95108 is a high-performance CPLD providing

Typical ICC (mA)

Clock Frequency (MHz)

Figure 1: Typical ICC vs. Frequency for XC95108

DS066 (v4.4) April 3, 2006

XC95108 In-System Programmable CPLD

In-System Programming Controller

Fast CONNECT II Switch Matrix

Figure 2: XC95108 Architecture

DS066 (v4.4) April 3, 2006

XC95108 In-System Programmable CPLD

Absolute Maximum Ratings

Supply voltage relative to GND

Input voltage relative to GND

0.5 to VCC + 0.5

Voltage applied to 3-state output

0.5 to VCC + 0.5

Storage temperature (ambient)

Recommended Operation Conditions

Commercial TA = 0oC to 70oC

Commercial TA = 0oC to 70oC

Supply voltage for output drivers for 3.3V operation

Low-level input voltage

High-level input voltage

Quality and Reliability Characteristics

Program/Erase Cycles (Endurance)

DC Characteristic Over Recommended Operating Conditions

Output high voltage for 5V outputs

IOH = 4.0 mA, VCC = Min

Output high voltage for 3.3V outputs

IOH = 3.2 mA, VCC = Min

Output low voltage for 5V outputs

IOL = 24 mA, VCC = Min

Output low voltage for 3.3V outputs

IOL = 10 mA, VCC = Min

Input leakage current

I/O high-Z leakage current

Operating supply current

DS066 (v4.4) April 3, 2006

XC95108 In-System Programmable CPLD

I/O to output valid

I/O setup time before GCK

I/O hold time after GCK

GCK to output valid

16-bit counter frequency

Multiple FB internal operating

I/O setup time before p-term clock

I/O hold time after p-term clock input

P-term clock output valid

GTS to output valid

GTS to output disable

Product term OE to output enabled

Product term OE to output disabled

GCK pulse width (High or Low)

Asynchronous preset/reset pulse

Figure 3: AC Load Circuit