Use Isplsi 1016ea For New Commercial & Industrial Designs

ispLSI 1016
In-System Programmable High Density PLD Features

HIGH-DENSITY PROGRAMMABLE LOGIC High-Speed Global Interconnect 2000 PLD Gates 32 I/O Pins, Four Dedicated Inputs 96 Registers Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic Security Cell Prevents Unauthorized Copying E2CMOS
Functional Block Diagram
U C SE O is M p M L ER SI C 10 IA 1 D L 6E ES & A IG IN F N D OR S U ST N R EW IA L
Output Routing Pool
A0
B7 B5 B4 B3 B2 B1 B0
Output Routing Pool
A1 A2 A3 A4 A5 A6 A7
D Q
B6
Logic Array
D Q
HIGH PERFORMANCE TECHNOLOGY fmax = 110 MHz Maximum Operating Frequency fmax = 60 MHz for Industrial and Military/883 Devices tpd = 10 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile E2CMOS Technology 100% Tested IN-SYSTEM PROGRAMMABLE In-System Programmable (ISP) 5-Volt Only Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality Reprogram Soldered Devices for Faster Debugging
D Q
GLB
D Q
Global Routing Pool (GRP)
CLK
COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity ispDesignEXPERT LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER PC and UNIX Platforms
Description
The ispLSI 1016 is a High-Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 1016 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. B7 (see figure 1). There are a total of 16 GLBs in the ispLSI 1016 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
1016_09
Specifications ispLSI 1016

Functional Block Diagram
Figure 1. ispLSI 1016 Functional Block Diagram
Generic Logic Blocks (GLBs)

IN 3 MODE/IN 2
The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. The ispLSI 1016 device contains two of these Megablocks.
B7 A1 A2 A3 A4 A5 A6 A7
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3
A0
I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16
B6 B5 B4 B3 B2 B1
I/O 8
I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
Input Bus
Global Routing Pool (GRP)
B0
SDI/IN 0 SDO/IN 1
Clock Distribution Network
Megablock
CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1
ispEN
Y0 Y1/RESET* SCLK/Y2
*Note: Y1 and RESET are multiplexed on the same pin
The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1016 device are selected using the Clock Distribution Network. Three dedicated clock pins (Y0, Y1 and Y2) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the ispLSI 1016 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.
lnput Bus
I/O 4 I/O 5 I/O 6 I/O 7
Output Routing Pool (ORP)
0139B(1a)-isp.eps

Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions

SYMBOL PARAMETER
MIN. 4.75 4.5 4.5 0 MAX. 5.25 5.5 5.5 0.8 Commercial TA = 0C to +70C Supply Voltage Industrial TA = -40C to +85C Military/883 TC = -55C to +125C Input Low Voltage Input High Voltage
o
UNITS
VCC VIL VIH
V V
2.0
Vcc + 1
Table 2- 0005Aisp w/mil.eps
Capacitance (TA=25 C, f=1.0 MHz)

SYMBOL PARAMETER
MAXIMUM1 8
UNITS pf
TEST CONDITIONS
C1 C2
Dedicated Input Capacitance
Commercial/Industrial Military
VCC=5.0V, VIN=2.0V VCC=5.0V, VIN=2.0V VCC=5.0V, VI/O, VY=2.0V

Table 2- 0006
10
pf
I/O and Clock Capacitance
10
pf
1. Guaranteed but not 100% tested.
Data Retention Specifications

PARAMETER Data Retention Erase/Reprogram Cycles
MINIMUM 20 10000
MAXIMUM
UNITS Years Cycles

Table 2- 0008B

Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% to 90% 1.5V 1.5V See figure 2
+ 5V R1 Device Output R2 CL* Test Point
Output Load Conditions (see figure 2)

Test Condition A B R1
DC Electrical Characteristics
PARAMETER
Table 2- 0003
3-state levels are measured 0.5V from steady-state active level.
*CL includes Test Fixture and Probe Capacitance.
R2
CL
470
390 390
35pF 35pF 35pF 5pF
Active High
Active Low
470
390 390
Active High to Z at VOH - 0.5V at VOL + 0.5V
Active Low to Z
470
390
5pF
Table 2- 0004A
Over Recommended Operating Conditions

CONDITION
SYMBOL
MIN. 2.4
TYP.3
MAX. 0.4
UNITS V V A A A A mA mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1
Output Low Voltage
IOL =8 mA
Output High Voltage
IOH =-4 mA
Input or I/O Low Leakage Current isp Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current
0V VIN VIL (MAX.) 0V VIN VIL (MAX.)
-10 10
Input or I/O High Leakage Current
3.5V VIN VCC 0V VIN VIL
-150 -150 -200 150 170
VCC = 5V, VOUT = 0.5V fTOGGLE = 1 MHz
ICC2,4
Operating Power Supply Current
VIL = 0.5V, VIH = 3.0V Commercial Industrial/Military
100 100
1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using four 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25oC. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC. Table 2-0007A-16 w/mil

External Timing Parameters
-110
111
1 tsu2 + tco1
5 2 PARAMETER TEST #
COND.
DESCRIPTION1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback3 Clock Frequency with External Feedback ( Clock Frequency, Max Toggle4
-90
90.9 58.8 125 6 0 9 0 4 4 2 12 17 8 10 15 15 15
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN. MAX. MIN. MAX. 1 2 3 4 5 6 7 8 9 10 14.5 7
1. 2. 3. 4. 5.
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-Bit loadable counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions Section.

tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5
A A A
70.1 125 4.5 0 0 4 4 2
GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock
7.5
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable
8.5 14 15 15
A B
10
10
16 Ext. Sync. Clock Pulse Duration, High 17 Ext. Sync. Clock Pulse Duration, Low
18 I/O Reg. Setup Time before Ext. Sync. Clock (Y1, Y2) 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y1, Y2)
5.5
6.5
Table 2-0030-16/110,90C

External Timing Parameters
-80
80 50 7 0 0 5 5 2 100 15 20 60 38 83 9 0 0 6 6
5 2 PARAMETER TEST #
COND.
DESCRIPTION1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Clock Frequency, Max Feedback3 Clock Frequency with External Feedback (tsu2 1 tco1) + Toggle4 GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock
-60
20 25 13 16 22.5 24 24
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN. MAX. MIN. MAX. 1 2 3 4 5 6 7 8 9
A 10 10 13 10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 12 17 18 18 A B 10 13 C 16 Ext. Sync. Clock Pulse Duration, High 17 Ext. Sync. Clock Pulse Duration, Low 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y1, Y2) 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y1, Y2) 2.5 8.5 6.5
tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5
1. 2. 3. 4. 5.
A A A
Table 2-0030-16/80,60C
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-Bit loadable counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions Section.

Internal Timing Parameters1
2
PARAMETER
DESCRIPTION
-110
-90
UNITS
MIN. MAX. MIN. MAX.
23 24 25 26 I/O Register Hold Time after Clock I/O Register Clock to Out Delay Dedicated Input Delay I/O Register Reset to Out Delay 1.8 2.0 1.7 2.1 1.7 27 28 29 30 31 GRP Delay, 1 GLB Load 0.6 0.8 1.5 2.1 2.8 GRP Delay, 4 GLB Loads GRP Delay, 8 GLB Loads GRP Delay, 12 GLB Loads GRP Delay, 16 GLB Loads 33 34 35 36 37 38 39 40 41 42 43 44 4 Product Term Bypass Path Delay 1 Product Term/XOR Path Delay XOR Adjacent Path Delay3 20 Product Term/XOR Path Delay 5.3 6.1 6.6 8.2 0.5 GLB Register Bypass Delay GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay 0.3 2.9 1.0 3.5 1.6 2.1 8.2 9.0 6.2 GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Clock Delay GLB Product Term Output Enable to I/O Cell Delay 2.8 3.5 45 46 ORP Delay 2.0 0.4 ORP Bypass Delay
Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP tgrp1 tgrp4 tgrp8 tgrp12 tgrp16
20 21 22
I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock
4.1
0.8 1.7
4.5
1.0 2.0 2.0 2.5 2.0
ns ns ns ns ns ns ns
0.7 1.0 1.8 2.6 3.4
ns ns ns ns ns
GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp
6.5 7.0 8.0 9.5 0.5 1.5 2.5 10.0 9.0 7.5
ns ns ns ns ns ns ns ns ns ns ns ns
2.5 0.5
ns ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Hard Macros.

2
PARAMETER
DESCRIPTION
-110
-90
UNITS
MIN. MAX. MIN. MAX.
Clocks tgy0 tgy1/2 tgcp tioy1/2 tiocp
50 51 52 53 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y2 to Global GLB Clock Line Clock Delay, Clock GLB to Global GLB Clock Line 2.9 2.1 0.8 2.1 0.8 2.9 3.8 4.2 3.8 4.2 3.5 2.5 1.0 2.5 1.0 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset to GLB and I/O Registers 7.9
Outputs tob toen todis
47 48 49
Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled
2.1 3.3 3.3
2.5 4.0 4.0
ns ns ns
3.5 4.5 5.0 4.5 5.0
ns ns ns ns ns
Global Reset tgr 55
7.5
ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.

2
PARAMETER
DESCRIPTION
-80
-60
UNITS
MIN. MAX. MIN. MAX.
23 24 25 26 I/O Register Hold Time after Clock I/O Register Clock to Out Delay Dedicated Input Delay I/O Register Reset to Out Delay 1.0 1.3 3.0 2.5 4.0 27 28 29 30 31 GRP Delay, 1 GLB Load 1.5 2.0 3.0 3.8 4.5 GRP Delay, 4 GLB Loads GRP Delay, 8 GLB Loads GRP Delay, 12 GLB Loads GRP Delay, 16 GLB Loads 33 34 35 36 37 38 39 40 41 42 43 44 4 Product Term Bypass Path Delay 1 Product Term/XOR Path Delay XOR Adjacent Path Delay3 20 Product Term/XOR Path Delay 6.5 7.0 8.0 9.5 1.0 GLB Register Bypass Delay GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay 1.0 4.5 1.3 6.0 2.0 2.5 9.0 7.5 GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Clock Delay 10.0 GLB Product Term Output Enable to I/O Cell Delay 3.5 4.6 45 46 ORP Delay 2.5 0.5 ORP Bypass Delay
Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP tgrp1 tgrp4 tgrp8 tgrp12 tgrp16
20 21 22
I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock
5.5
2.0 3.0
7.3
2.7 4.0 4.0 3.3 5.3
ns ns ns ns ns ns ns
2.0 2.7 4.0 5.0 6.0
ns ns ns ns ns
GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp
8.6 9.3 10.6 12.7 1.3 2.7 3.3 13.3 12.0 9.9
ns ns ns ns ns ns ns ns ns ns ns ns
3.3 0.7
ns ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Hard Macros.

2
PARAMETER
DESCRIPTION
-80
-60
UNITS
MIN. MAX. MIN. MAX.
Outputs tob toen todis Clocks tgy0 tgy1/2 tgcp tioy1/2 tiocp
47 48 49
Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled
3.0 5.0 5.0
4.0 6.7 6.7
ns ns ns
50 51 52 53 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y2 to Global GLB Clock Line Clock Delay, Clock GLB to Global GLB Clock Line 4.5 3.5 1.0 3.5 1.0 4.5 5.5 5.0 5.5 5.0 6.0 4.6 1.3 4.6 1.3 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset to GLB and I/O Registers 9.0
6.0 7.3 6.6 7.3 6.6
ns ns ns ns ns
Global Reset tgr 55
12.0
ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
10

ispLSI 1016 Timing Model
I/O Cell GRP Feedback Ded. In GLB ORP I/O Cell
#26 I/O Reg Bypass #20 Input D Register Q RST #21 - 25 GRP 4 #28 GRP Loading Delay #27, 29, 30, 31, 32 4 PT Bypass #33 20 PT XOR Delays #34, 35, 36 #55 D GLB Reg Bypass #37 GLB Reg Delay Q RST ORP Bypass #46 ORP Delay #45 #47 I/O Pin (Output) #48, 49
I/O Pin (Input)
#55 Reset
Y1,2
Y0
Derivations of tsu, th and tco from the Product Term Clock1
tsu
= Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) = (#20 + #28 + #35) + (#38) - (#20 + #28 + #44) 5.5 ns = (1.0 + 1.0 + 8.0) + (1.0) - (1.0 + 1.0 + 3.5) = Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#20 + #28 + #44) + (#39) - (#20 + #28 + #35) 3.0 ns = (1.0 + 1.0 + 7.5) + (3.5) - (1.0 + 1.0 + 8.0)
th
tco
= Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) = (#20 + #28 + #44) + (#40) + (#45 + #47) 16.0 ns = (1.0+ 1.0 +7.5) + (1.5) + (2.5 + 2.5)
Derivations of tsu, th and tco from the Clock GLB1
tsu
= Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) = (#20 + #28 + #35) + (#38) - (#50 + #40 + #52) 5.0 ns = (1.0 + 1.0 + 8.0) + (1.0) - (3.5 + 1.5 + 1.0) = Clock (max) + Reg h - Logic = (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#50 + #40 + #52) + (#39) - (#20 + #28 + #35) 3.5 ns = (3.5 + 1.5 + 5.0) + (3.5) - (1.0 + 1.0 + 8.0)
th
tco
= Clock (max) + Reg co + Output = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) = (#50 + #40 + #52) + (#40) + (#45 + #47) 16.5 ns = (3.5 + 1.5 + 5.0) + (1.5) + (2.5 + 2.5)
1. Calculations are based upon timing specifications for the ispLSI 1016-90.
#38, 39, 40, 41 Clock Distribution #51, 52, 53, 54 #50 Control RE PTs OE #42, 43, CK 44
11

Maximum GRP Delay vs GLB Loads
6 5
ispLSI 1016-60 ispLSI 1016-80 ispLSI 1016-90/-110
GRP Delay (ns)
4 3 2 1
Power Consumption
Power consumption in the ispLSI 1016 device depends on two primary factors: the speed at which the device is operating, and the number of Product Terms used. Fig-
Figure 3. Typical Device Power Consumption vs fmax
ICC can be estimated for the ispLSI 1016 using the following equation: ICC = 31 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.009) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0 4 8 GLB Loads 12 16
0126A-80-16-isp.eps
ure 3 shows the relationship between power and operating speed.
150
ispLSI 1016
ICC (mA)
100
50
10
20
30
40
50
60
70
80
90
100 110
fmax (MHz)
Notes: Configuration of Four 16-bit Counters Typical Current at 5V, 25C
12

Pin Description
PLCC TQFP JLCC PIN NUMBERS PIN NUMBERS PIN NUMBERS
15, 19, 25, 29, 37, 41, 3, 7, 2 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9, 18, 22, 28, 32, 40, 44, 6, 10 9, 13, 19, 23, 31, 35, 41, 1, 40 7 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4 15, 19, 25, 29, 37, 41, 3, 7, 2 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9,
NAME
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 IN 3 ispEN
DESCRIPTION
SDI/IN 0 1
MODE/IN 2 1
SDO/IN 1 1
SCLK/Y2 1
Y0
Y1/RESET
GND VCC
Dedicated input pins to the device. 13 13 14 8 14 36 30 36 24 18 24 33 27 33 11 5 11 35 29 35 1, 23 12, 34 17, 39 6, 28 1, 23 12, 34 Ground (GND) VCC
18, Input/Output Pins - These are the general purpose I/O 22, pins used by the logic array. 28, 32, 40, 44, 6, 10
Input Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input This pin performs two functions. It is a dedicated clock input when ispEN is logic high. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. This pin performs two functions: Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
1. Pins have dual function capability.
Table 2 - 0002C-16-isp
13

Pin Configuration
ispLSI 1016 44-Pin PLCC Pinout Diagram
I/O 27 I/O 26 I/O 25 I/O 24 GND I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 IN 3
6 5 4 3 2 1 44 43 42 41 40 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 I/O 18 I/O 17 I/O 16 IN 2/MODE1 Y1/RESET VCC Y2/SCLK1 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 1016 44-Pin TQFP Pinout Diagram
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
I/O 8

0851-16/TQFP
GND 1 SDO/IN 1
14
I/O 9 I/O 10 I/O 11
ispLSI 1016
Top View
ispEN 1SDI/IN 0 I/O 0 I/O 1 I/O 2 18 19 20 21 22 23 24 25 26 27 28
I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 GND 1 SDO/IN 1
I/O 9 I/O 10 I/O 11
0123A-isp1016
I/O 27
I/O 26 I/O 25
I/O 24
GND I/O 23
I/O 22
44 43 42 41 40 39 38 37 36 35 34
I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC
1 2 3 4 5 6 7 8
I/O 21 I/O 20 I/O 19
IN 3
33 32 31 30 29 28 27 26 25 24 23
I/O 18 I/O 17 I/O 16
IN2/MODE1 Y1/RESET VCC Y2/SCLK1 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 1016
Top View
ispEN 1 SDI/IN 0
I/O 0 I/O 1 I/O 2
9 10 11
12 13 14 15 16 17 18 19 20 21 22

Pin Configuration
ispLSI 1016 44-Pin JLCC Pinout Diagram
I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19
39 38 37 36 35 34
6 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC 7 8 9 10 11 12 13 14 15 16 17
5 4
3 2 1 44 43 42 41 40 I/O 18 I/O 17 I/O 16 IN 2/MODE1 Y1/RESET VCC Y2/SCLK1 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 1016/883
Top View
ispEN 1 SDI/IN 0 I/O 0 I/O 1 I/O 2 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7 GND
IN 3 GND
I/O 8
1 SDO/IN 1
I/O 9 I/O 10 I/O 11
0123-16-isp/JLCC
15

Part Number Description
ispLSI 1016 XXX
Device Family ispLSI Device Number Speed 110 = 110 MHz fmax 90 = 90 MHz fmax 80 = 80 MHz fmax 60 = 60 MHz fmax
X XXX X
Grade Blank = Commercial I = Industrial /883 = 883 Military Process Package J = PLCC T44 = TQFP H = JLCC Power L = Low
Ordering Information
Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended.
0212-80B-isp1016
COMMERCIAL
Family
fmax (MHz)
110 90 90
tpd (ns)
10
Ordering Number
Package
ispLSI 1016-110LJ ispLSI 1016-90LJ
44-Pin PLCC
12 12
44-Pin PLCC
ispLSI 1016-90LT44 ispLSI 1016-80LJ
44-Pin TQFP
ispLSI
80 80 60 60
15 15 20 20
44-Pin PLCC
ispLSI 1016-80LT44 ispLSI 1016-60LJ
44-Pin TQFP
44-Pin PLCC
ispLSI 1016-60LT44
44-Pin TQFP
INDUSTRIAL
Family ispLSI
fmax (MHz)
60 60
tpd (ns)
20 20
Ordering Number ispLSI 1016-60LJI
Package
44-Pin PLCC
ispLSI 1016-60LT44I
44-Pin TQFP
MILITARY/883
Family
fmax (MHz)
60
tpd (ns)
20
Ordering Number
SMD #
Package
ispLSI
ispLSI 1016-60LH/883
5962-9476201MXC
44-Pin JLCC
Table 2-0041-16-isp1016
16

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ispLSI 1016

In-System Programmable High Density PLD Features

Functional Block Diagram

Global Routing Pool (GRP)

Specifications ispLSI 1016

Generic Logic Blocks (GLBs)

Output Routing Pool (ORP)

I/O 0 I/O 1 I/O 2 I/O 3

I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15

Global Routing Pool (GRP)

Clock Distribution Network

CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1

*Note: Y1 and RESET are multiplexed on the same pin

I/O 4 I/O 5 I/O 6 I/O 7

Output Routing Pool (ORP)

Specifications ispLSI 1016

DC Recommended Operating Conditions

VCC VIL VIH

Table 2- 0005Aisp w/mil.eps

Capacitance (TA=25 C, f=1.0 MHz)

Dedicated Input Capacitance

VCC=5.0V, VIN=2.0V VCC=5.0V, VIN=2.0V VCC=5.0V, VI/O, VY=2.0V

I/O and Clock Capacitance

1. Guaranteed but not 100% tested.

Data Retention Specifications

UNITS Years Cycles

Specifications ispLSI 1016

+ 5V R1 Device Output R2 CL* Test Point

Output Load Conditions (see figure 2)

3-state levels are measured 0.5V from steady-state active level.

*CL includes Test Fixture and Probe Capacitance.

35pF 35pF 35pF 5pF

Active High to Z at VOH - 0.5V at VOL + 0.5V

Over Recommended Operating Conditions

VOL VOH IIL IIH IIL-isp IIL-PU IOS1

Output Low Voltage

Output High Voltage

0V VIN VIL (MAX.) 0V VIN VIL (MAX.)

Input or I/O High Leakage Current

3.5V VIN VCC 0V VIN VIL

-150 -150 -200 150 170

VCC = 5V, VOUT = 0.5V fTOGGLE = 1 MHz

Operating Power Supply Current

VIL = 0.5V, VIH = 3.0V Commercial Industrial/Military

Specifications ispLSI 1016

UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns

MIN. MAX. MIN. MAX. 1 2 3 4 5 6 7 8 9 10 14.5 7

70.1 125 4.5 0 0 4 4 2

Specifications ispLSI 1016

UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns

MIN. MAX. MIN. MAX. 1 2 3 4 5 6 7 8 9

Specifications ispLSI 1016

MIN. MAX. MIN. MAX.

1.0 2.0 2.0 2.5 2.0

0.7 1.0 1.8 2.6 3.4

Specifications ispLSI 1016

MIN. MAX. MIN. MAX.

Clocks tgy0 tgy1/2 tgcp tioy1/2 tiocp

Outputs tob toen todis