Ripple Carry and Carry Lookahead Adders: 1 Objectives

Ripple Carry and Carry Lookahead Adders
1 Objectives
Understand the operation of ripple carry and carry lookahead (CLA) adders/subtractors.

Write hierarchical VHDL code for each type of adder/subtractor. Use hierarchical design techniques to implement the adders/subtractors. Synthesize the code in FPGA using the ISE tools. Study the synthesis performance parameters (delay, FPGA resources, power consumption, equivalent gate count).
2 Introduction
We will start by explaining the operation of one-bit full adder which will be the basis for constructing ripple carry and carry lookahead adders/subtractors.
2.1 One-Bit Full Adder

a b
cin
Full Adder
cout
s
Figure 1: One-bit full adder.
A one-bit full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of three inputs and and two outputs and as illustrated in Figure 1. The truth table of the full adder is listed in Table 1.

Table 1: One-Bit Full adder truth table. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1

2.2 Ripple Carry Adder/Subtractor

A simple ripple carry adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the carry output from each full adder connected to the carry input of the next full adder in the chain. Figure 2 shows the interconnection of four full adder (FA) circuits to provide a 4-bit ripple carry adder. Notice from Figure 2 that the input is from the right side because the rst cell traditionally represents the least signicant bit (LSB). Bits and in the gure represent the least signicant bits of the numbers to be added. The sum output is represented by the bits . The main problem with this type of adder is the delays needed to produce the carry out signal and the most signicant bits. These delays increase with the increase in the number of bits to be added.
a3 b3 a2 b2 a1 b1

c4
Full Adder
c3
s3
It is a simple matter to develop a more versatile 2s complement adder/subtractor based on the adder in Fig. 2. References [1, 2] illustrate how an adder/subtractor can be obtained from the simple adder circuit.
a0
b0
Full Adder
c2
Full Adder
c1
Full Adder
c0
s2
s1
s0
Figure 2: 4-bit full adder.
2.3 Carry Lookahead Adder (CLA)

The carry lookahead adder (CLA) solves the carry delay problem by calculating the carry signals in advance, based on the input signals. It is based on the fact that a carry signal will be generated in two cases: (1) when both bits and are 1, or (2) when one of the two bits is and the carry-in is . Thus, one can write,
ai bi
Pi si Gi ci+1
ci

where

and are called the carry generate and carry propagate terms, respectively. Notice that the generate and propagate terms only depend on the input bits and thus will be valid after one and two gate delay, respectively. If one uses the above expression to calculate the carry signals, one does not need to wait for the carry to ripple through all the previous stages to nd its proper value. Lets apply this to a -bit adder to make it clear.
% &$
Putting
in Equation 3, we get (8) (9) (10) (11)

1 6F60A8
1 6258EA8
!
1 8580A
Figure 3: Full adder at stage with

and
shown.

The above two equations can be written in terms of two new signals in Figure 3:

460A8 1

1 62580A7B460A 1

"
8257

7$96 1
625
4
1 @9
32 1
D( C
) (
' (
(1) (2) and , which are shown
(3) (4)
(5) (6) (7)
a3
b3
a2
b2
a1
b1
a0
b0
G3 c4
P3
G2
P2
G1
P1
G0
P0 c0
c3 P3 P2
c2 P1
c1 P0
c0
s3
s2
s1
s0
Figure 4: 4-Bit carry lookahead adder implementation detail.
The disadvantage of CLA is that the carry logic block gets very complicated for more than -bits. For that reason, CLAs are usually implemented as 4-bit modules and are used in a hierarchical structure to realize adders that have multiples of -bits. It is a simple matter to develop a more versatile 2s complement adder/subtractor based on the adder in Fig. 4.
# #
3 Lab Preparation
You must read and follow the instructions in the ISE tutorial provided in the Appendix of the lab manual. The tutorial is also available in the lab webpage for this course. This tutorial must be attempted before start of regular labs.
4 Pre-Lab Report
For your prelab report, you are required to do the following.

1. Write minimized sum of product boolean expression for the and 4
signals of the one-bit

Figure 4 shows that a 4-bit CLA is built using gates to generate the block to generate the carry out signals according to Equations 811.
and
signals and a logic
full adder whose truth table is described in Table 1. 2. Draw icons for the 1-bit full adder and the 4-bit ripple carry adder. Provide also the signal denition tables for both components. 3. Use Figure 2 to illustrate how a carry-ripple adder can be converted into a 2s complement, 4-bit adder/subtractor. 4. Using a 4-bit CLA adder as a building block, draw a block diagram to show how to construct a 16-bit CLA adder. 5. Explain why it is not recommended to design an 8- or 16-bit CLA using equations similar to (8) to (11). 6. Use Figure 4 to illustrate how a carry lookahead adder can be converted into a 2s complement, 4-bit adder/subtractor.
5 Project Requirements
In this project you are required to model, simulate, and implement a ripple carry adder/subtractor and a carry lookahead adder/subtractor.
5.1 Ripple Carry Adder Requirements

1. Model a 1-bit full adder using VHDL behavioral description. 2. Model a 4-bit adder in a separate le using VHDL structural description. The 4-bit adder will use 1-bit full adders as components. 3. Develop a 2s complement, 4-bit adder/subtractor with overow indicator based on the adder you developed in Step 2. 4. Write a testbench to simulate your design and obtain output delay from the waveforms. 5. Synthesize the 2s complement, 4-bit adder/subtractor on the Xilinx board provided. 6. Choose four consecutive toggle switches as one 4-bit input and the other four consecutive toggle switches as the other 4-bit input. You can choose one of the button switches to represent the command add/ . Choose 5 consecutive LEDs to represent the 4-bit output and overow signal. 7. Obtain the main performance parameters (delay, FPGA resources, power consumption, equivalent gate count).
5.2 Carry Lookahead Adder Project Requirements

1. Write a VHDL code for a 4-bit CLA using structural description for the system shown in Figure 4. 2. Develop a 2s complement, 4-bit adder/subtractor with overow indicator based on the adder you developed in Step 1. 3. Write a testbench to simulate your design and obtain output delay from the waveforms. 4. Synthesize the 2s complement, 4-bit adder/subtractor on the Xilinx board provided. 5. Choose four consecutive toggle switches as one 4-bit input and the other four consecutive toggle switches as the other 4-bit input. You can choose one of the button switches to represent the command add/ . Choose 5 consecutive LEDs to represent the 4-bit output and overow signal. 6. Obtain the main performance parameters (delay, FPGA resources, power consumption, equivalent gate count).
6 Lab Report
Your lab report should include the following.
6.1 Ripple Carry Adder

1. Refer to the lab report grading scheme for items that must be present in your lab report. The grading scheme can be accessed on-line at: http://www.ece.uvic.ca/ fayez/courses/ceng441/lab/lab grading scheme.html 2. Find the delay of the 2s complement, 4-bit carry adder/subtractor using the waveform you got from the simulation. 3. List the performance parameters of the 4-bit carry ripple adder/subtractor. 4. Compare the delay you obtain from the synthesis results with the delay of the simulations and comment on your results.
6.2 Carry lookahead adder

1. Refer to the lab report grading scheme for items that must be present in your lab report. 2. Find the delay of the 4-bit carry lookahead adder/subtractor using the waveform you got from the simulation. 6
3. Compare the delay you obtain from the synthesis results with the delay of the simulations and comment on your results. 4. Compare the area of the ripple carry adder with the area of the CLA based on the synthesis results you obtained and comment on the results. 5. Compare the actual delay of the ripple carry adder with the actual delay of the CLA.
7 References
1. R. H. Katz and G. Borriello, Contemporary Logic Design, Prentice Hall, 2005. 2. M. M. Mano and C. R. Kime, Logic and Computer Design Fundamentals, Pearson/Prentice Hall, Upper Saddle River, NJ, 2004.

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Ripple Carry and Carry Lookahead Adders

2.1 One-Bit Full Adder

Table 1: One-Bit Full adder truth table. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1

2.2 Ripple Carry Adder/Subtractor

Figure 2: 4-bit full adder.

2.3 Carry Lookahead Adder (CLA)

in Equation 3, we get (8) (9) (10) (11)

Figure 3: Full adder at stage with

(1) (2) and , which are shown

(5) (6) (7)

Figure 4: 4-Bit carry lookahead adder implementation detail.

1. Write minimized sum of product boolean expression for the and 4

signals of the one-bit

signals and a logic

5.1 Ripple Carry Adder Requirements

5.2 Carry Lookahead Adder Project Requirements

6.1 Ripple Carry Adder

6.2 Carry lookahead adder

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