Vizio Vw32l Hdtv10a Service Manual
Vizio Vw32l Hdtv10a Service Manual
Vizio Vw32l Hdtv10a Service Manual
V, Inc
320A Kalmus Drive Costa Mesa, CA 92626
TEL : +714-668-0588 FAX :+714-668-9099
Top Confidential
Table of Contents
CONTENTS PAGE
Sections
1. Features 1-1
2. Specifications 2-1
8. Waveforms 8-1
Appendix
1. Main Board Circuit Diagram
Block Diagram
IBM and IBM products are registered trademarks of International Business Machines
Corporation.
Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc.
VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards
Association (VESA).
No part of this document may be copied, reproduced or transmitted by any means for any
purpose without prior written permission from VINC.
FCC INFORMATION
This equipment has been tested and found to comply with the limits of a Class B digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses and can radiate radio frequency energy, and if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is
no guarantee that the interference will not occur in a particular installation. If this equipment
does cause unacceptable interference to radio or television reception, which can be
determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures -- reorient or relocate the receiving
antenna; increase the separation between equipment and receiver; or connect the into an
outlet on a circuit different from that to which the receiver is connected.
FCC WARNING
To assure continued FCC compliance, the user must use a grounded power supply cord and
the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized
changes or modifications to Amtrak products will void the user’s authority to operate this
device. Thus VINC Will not be held responsible for the product and its safety.
CE CERTIFICATION
This device complies with the requirements of the EEC directive 89/336/EEC with regard to
“Electromagnetic compatibility.”
SAFETY CAUTION
Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL);
Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric
Appliance Control Act); or an AC cord that meets the local safety standards.
8. On Screen Display: user can define display mode (i.e. color, brightness,
contrast, sharpness, backlight), sound setting, TV channel program,
aspect and gamma or reset all setting.
3. Input Connectors
1 x RF Connector for internal ATSC/QAM/NTSC Hybrid Tune
2x HDMI with HDCP plus Stereo Audio (RCA)
2x Component YPbPr plus Stereo Audio
1x RGB PC(WXGA) plus Stereo Audio
1x Composite Video plus stereo Audio
4. POWER SUPPLY
Input Voltage Level: 100~240 Vac, 50/ 60 Hz
Power Consumption: 180W MAXPower OFF: to less than 3W MAX
6. ENVIRONMENT
5-1. Operating Temperature: 5c~35c (Ambient)
5-2. Operating Humidity: Ta= 35 ¶C, 90%RH (Non-condensing)
5-3. Operating Altitude: 0 - 14,000 feet (4267.2m)(Non-Operating)
Precaution
Please pay attention to the followings when you use this TFT LCD module.
1. OPERATING PRECAUTIONS
(1) The spike noise causes the mis-operation of circuits. It should be lower
than following voltage :
V=·200mV(Over and under shoot voltage)
(2) Response time depends on the temperature. (In lower temperature, it
becomes longer.)
(3) Brightness depends on the temperature. (In lower temperature, it becomes
lower.)And in lower temperature, response time (required time that
brightness is stable after turned on) becomes longer.
(4) Be careful for condensation at sudden temperature change. Condensation
makes damage to polarizer or electrical contacted parts. And after fading
condensation, smear or spot will occur.
(5) When fixed patterns are displayed for a long time, remnant image is likely
to occur.
(6) Module has high frequency circuits. System manufacturers shall do
sufficient suppression to the electromagnetic interference. Grounding and
shielding methods may be important to minimize the interference.
CONFIDENTIAL – DO NOT COPY Page 2-2
File No. SG-0212
2. HANDLING PRECAUTIONS FOR PROTECTION
(1) The protection film is attached to the bezel with a small masking tape.
When the protection film is peeled off, static electricity is generated
between the film and polarizer. This should be peeled off slowly and
carefully by people who are electrically grounded and with well ion-blown
equipment or in such a condition, etc.
(2) When the module with protection film attached is stored for a long time,
sometimes there remains a very small amount of glue still on the bezel after
the protection film is peeled off.
(3) You can remove the glue easily. When the glue remains on the bezel
surface or its vestige is recognized, please wipe them off with absorbent
cotton waste or other soft material like chamois soaked with
normal-hexane.
[MENU]
“MENU” button could star the OSD which could adjust the performance and set up the setting
between the different input sources. There are the structures.
TV Source
!
a. Volume (0~100, 25)
b. Bass (0~100, 50)
c. Treble (0~100, 50)
d. Balance (-50~50, 0)
e. Surround (ON/OFF)
!
a. Language (English/ Français / EspaĖol)
b. Sleep Timer (OFF/30Min/60Min/90Min/120Min)
c. Analog CC (OFF/CC1~4)
d. Digital CC (OFF/Service1~6)
e. Digital CC Style
1. Caption Style (As Broadcaster/Custom)
2. Size (Large/Small/Medium)
3. Font Color (White/Green/Blue/Red/Cyan/Yellow/Magenta/Black)
4. Font Opacity (Solid/Translucent/Transparent)
5. Background Color (White/Green/Blue/Red/Cyan/Yellow/Magenta/Black)
6. Background Opacity (Solid/Translucent/Transparent)
7. Window Color (White/Green/Blue/Red/Cyan/Yellow/Magenta/Black)
8. Window Opacity (Solid/Translucent/Transparent)
g. Rest All Setting (OK/Cancel)
!
a. Auto Adjust
b. Backlight (0~100, 90)
c. Contrast (0~100, 50)
d. Brightness (0~100, 50)
e. Color Temperature (6500/9300/Custom)
f. H-Size (0~255, 127)
g. H-Position (0~100, 0
h. V-Position (0~100, 0
i. Fine Tune (0~31, 0
!
a. Picture Mode (Standard/Movie /Game / Custom)
b. Backlight (0~100, 90)
c. Contrast (0~100, 50)
d. Brightness (0~100, 50)
e. Color (saturation)(0~100, 50)
f. Tint (hue) (-32~32, 0)
g. Sharpness (0~7, 4)
h. Color Temperature (Cool/Normal/Warm/Custom)
!
a. Volume (0~100, 25)
b. Bass (0~100, 50)
c. Treble (0~100, 50)
d. Balance (-50~50, 0)
e. Surround (ON/OFF)
!
a. Picture Mode (Standard/Movie /Game / Custom)
b. Backlight (0~100, 90)
c. Contrast (0~100, 50)
d. Brightness (0~100, 50)
e. Color (saturation)(0~100, 50)
f. Tint (hue) (-32~32, 0)
g. Sharpness (0~7, 4)
h. Color Temperature (Cool/Normal/Warm/Custom)
!
a. Volume (0~100, 25)
b. Bass (0~100, 50)
c. Treble (0~100, 50)
d. Balance (-50~50, 0)
e. Surround (ON/OFF)
f. Speakers (ON/OFF)
!
a. Language (English/ Français / EspaĖol)
b. Sleep Timer (OFF/30Min/60Min/90Min/120Min)
c. Analog CC (OFF/CC1~4/TT1~4)
d. Digital CC (OFF/CC1~4/Service1~6)
e. Digital CC Style
g. Rest All Setting (OK/Cancel)
[INFO]
“INFO” button could show an information bar which displays the information about
the input signal on our LCD TV.
Pin Description
1 Red
2 Green
3 Blue
4 Ground
5 Ground
6 R-Ground
7 G-Ground
8 B-Ground
10 Ground
11 No Connection
12 (SDA)
14 V-Sync
15 (SCL)
˄ ˈ
ˉ ˄˃
˄˄ ˄ˈ
1, 2 = GND
3 = Luminance (Y)
4 = Chrominance(C)
Signal Specification
F-Type TV RF connector
a. Signal Level 60dBμV typical
b. System: NTSC
c. Frequency: 55~801MHz (NTSC)
PC connector 15 pin male D-sub connector
a. Pin Assignment Refer to Section 2.3.10
b. Signal Level Video (R, G, B): Analog 0.7Vp-p/75ȍ
Sync (H, V): TTL level
c. Sync Type TTL (Separate / Composite) or Sync. On Green
d. Sync polarity Positive or Negative
e. Video Amplitude RGB: 0.7Vp-p
f. Frequency H: support to 30K~70KHz
V: support to 50~85Hz
Pixel Clock: support to 110MHz
Pin Description
1 “POWRSW_ON/OFF”
2 “+12V”
3 “+12V”
4 “+12V”
5 “+12V”
6 “GND”
7 “GND”
8 “GND”
9 “5VSB”
10 “5VSB”
11 “5VSB”
12 “PWM_DIM”
13 “BL ON/OFF”
Pin Description
1 “AMBER”
2 “WHITE”
3 “5VSB”
4 “5VSB”
5 “IR”
6 “GND”
7 “GND”
8 “KEYPAD-ADC1”
9 “KEYPAD-ADC2”
10 “DV33SB”
Pin Description
1 “R+”
2 “R-”
3 “L-”
4 “L+”
MT5371
҇. GENERAL DESCRIPTION
The MediaTek MT5371 consists of a DTV backend decoder and a TV controller and offers
high integration for advanced applications in main stream integrated digital television
market. The MT5371 combines a transport de-multiplexer, a high definition MPEG-2 video
decoder, an AC3 audio decoder, an LVDS transmitter, and an NTSC/PAL/SECAM video
decoder with a 3D comb filter. The MT5371 enables consumer electronics manufactures
to build high quality, feature-rich DTVs.
Reliable Analog Technology: The MT5371 integrates high speed VGA ADC, high
resolution Video/Audio ADC, 90db Audio DACs. The MT5371 provides very fine quality for
the iDTV markets.
҈. Features of MT5371
1. Key Features:
1. A transport de-multiplexer
2. An MPEG-2 video decoder
3. An AC3 audio decoder
4. A 3D comb TV decoder
5. PIP/POP mode
6. An HDMI receiver
7. A set of three VGA ADCs
2. Host CPU:
1. ARM 926
2. 16K I-Cache and 16K D-Cache
3. 8K Data TCM and 8K Instruction TCM
4. JTAG ICE interface
5. Watch Dog timers
6. Built-in CPI analyzer
4. MPEG-2/JPEG Decoder:
1. Supports one MPEG-2 HD decoder
2. MPEG compliant with DV, MP@ML, MP@HL and MPEG-1 video standards
3. JPEG decode base-line or progressive JPEG file
5. 2D Graphics:
1. Supports multiple color modes
2. Point, horizontal/vertical line primitive drawings
3. Rectangle fill and gradient fill functions
4. Bitblt with transparent, alpha blending, alpha composition and stretch
5. Font rendering by color expansion
6. YCbCr to RGB color space transfer
7. Supports off-line scaler
6. OSD Plane:
1. Three linking list OSD with multiple color modes
2. Two OSD with scaler
3. Square size, 32x32 or 64x64 pixel, hardware cursor
8. LVDS:
1. One 10-bit channel or dual 6/8-bit channel
2. Built-in spread spectrum for EMI performance
3. Supports 6/8/10-bit format output
4. Programmable panel timing output
20. Peripherals:
1. Two UARTs with a transmitter and a receiver FIFO, one of them has a hardware flow
control
2. Three serial interfaces, one is the master for general purposes, one is the master for
the HDMI key, and the remaining one is the slave for the HDMI EDID data
4. Three PWMs
5. IR blaster and receiver
6. Real-time clock and watchdog controller
7. Smart Card reader
8. PCMCIA/POD/CI interfaces
9. Supports three NOR flash or one NOR and one NAND flash
10. Supports CableCARD host control bus
21. IC Outline:
1. The MT5371 is delivered in 588-ball BGA package
2. 3.3V/1.2V and 2.5V for DDR1; 1.8V for DDR2
2. DC Characteristics
1. GENERAL DESCRIPTION
The MT5112BD is a highly integrated single-chip for digital terrestrial HDTV and digital
cable TV de-modulation. The chip is designed specifically for the digital terrestrial HDTV
and CATV receivers, and is fully compliant with ATSC A/53, SCTE DVS-031, and ITU J.83
Annex B standards.
MT5112BD accepts the tuner IF output centered at 44MHz or 43.75MHz, or the low IF
signals from a down-converter. With good adjacent channel immunity, additional IF SAW
filters for adjacent channel rejection can be saved. An on-chip programmable
gain-controlled amplifier (PGA) is designed to provide extra signal gain when the tuner
output level is low. The amplified IF signal is then sample and digitized for further
demodulation process.
MT5112BD keeps A/D input power level at a desired level so as to maximize the received
SNR. It measures the power level of the digitized samples and provide two signals (both
sigma-delta encoded; one delayed and one non-delayed) for front-end gain control
purpose. The signals is low-pass filtered before connected to tuner or IF gain stages.
For the 8-VSB reception, the carrier frequency offset is estimated and compensated by a
fully digital synchronizer. It also controls the rate conversion in the digital re-sampling
device by estimating the sampling frequency offset; hence no external VCXO is required.
The digital synchronizer simultaneously offers very wide frequency acquisition range and
stable tracking capability. This makes MT5112BD robust work under severe impairment
conditions.
The MT5112BD is equipped with a powerful equalizer for mitigating the multi-path effects
due to terrestrial propagation of 8-VSB signals. The delicate equalizer design makes the
MT5112BD boast its ability for strong echo cancellation. With this powerful equalizer, the
MT5112BD can not only easily pass the tests of A74 equalization mask, ATTC channel
ensembles, CRC channel ensembles, but also provide superior capability of live signal
receptions.
The MT5112BD also utilizes a powerful equalizer for performing channel equalization in
cable environments. The MT5112BD equipped with this powerful equalizer can easily
pass the SCTE channel tests and offer stable and excellent live signal receptions.
The following FEC decoder corrects most of the errors by the concatenation of the TCM
and Reed-Solomon decoders with an in-between de-interleaver. Specifically for the digital
cable TV reception, the MT5112BD first detects and aligns de-puncturing timing of the
received sequence before TCM decoding. Besides, two synchronization circuits are each
inserted before the de-interleaver and after the Reed-Solomon decoder to automatically
delineate the FEC frames and transport stream packets respectively. An on-chip error rate
estimator can simultaneously monitor the receiving qualities at the three stages: the
equalizer output, the TCM decoder, and the transport stream packets. At the last stage,
the MT5112BD incorporates a buffer to smooth out the uneven arrival time of transport
stream packets. The chip finally outputs the smoothed decoded MPEG-2 transport stream
packets in either the serial or parallel transport stream format.
MT8291E
1. Overview
The MT8291E is a highly integrated stereo audio codec The MT8291E performs stereo
analog-to-digital and two digital-to-analog conversions with single-ended analog voltage
input and output. It’s up to 24-bits serial values at sample rates up to 192 kHz.
A 7:1 stereo input multiplexer and an automatic level control are included. The PGA is
available for line inputs and provides gain/attenuation of 21dB in 0.5 steps.
2. BLOCK DIAGRAM
3. Key Features
1. 48-pin LQFP package
2. 2 Vrms DAC output
3. MUTE and RESET function
4. 7-channel input multiplexer with ADC programmable gain amplifier’s (PGA’s) gain from
+21 dB to -21dB in 0.5dB step
5. Two individual sets of I2S ports simultaneously support different sample rates for the
ADC and DACs and then outputs from DAC1 and DAC2 independently
TDA8946
In L32 TV the TDA8946AJ is a dual-channel audio power amplifier with DC gain control. It
has an output power of 2 Γҏ10 W at an 8 Γҏload and a 12 V supply.
Block diagram
Flash: MX29LV320CTTC
The MX29LV320AT/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and
2M words of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable
read/write non-volatile random access memory.
The MX29LV320AT/B is packaged in 48-pin TSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard EPROM programmers. The standard
MX29LV320AT/B offers access time as fast as 70ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention, the MX29LV320AT/B
has separate chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure
and programming. The MX29LV320AT/B uses a command register to manage this
functionality. MXIC Flash technology reliably stores memory contents even after 100,000
erase and program cycles.
Legend:
L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0Γ0.5V, VHH=11.5-12.5V, X=Don't Care,
AIN=Address IN, DIN=Data IN,DOUT=Data OUT
Notes:
1. When the WP/ACC pin is at VHH, the device enters the accelerated program mode. See
"Accelerated Program Operations" for more information.
2. The sector group protect and chip unprotect functions may also be implemented via
programming equipment. See the "Sector Group Protection and Chip Unprotection"
section.
3. If WP/ACC=VIL, the two outermost boot sectors remain protected. If WP/ACC=VIH, the
two outermost boot sector protection depends on whether they were last protected or
unprotected using the method described in "Sector/Sector Block Protection and
Unprotection". If WP/ACC=VHH, all sectors will be unprotected.
5. Address are A20:A0 in word mode (BYTE=VIH), A20:A-1 in byte mode (BYTE=VIL).
Notes:
1.Code=00h means unprotected, or code=01h protected.
2.Code=99 means factory locked, or code=19h not factory locked.
Legend:
X=Don't care
RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE or CE pulse.
PD=Data to be programmed at location PA. Data is latched on the rising edge of WE or CE
pulse.
SA=Address of the sector to be erased or verified. Address bits A20-A12 uniquely select any
sector.
ID=22A7h(Top), 22A8h(Bottom)
Notes:
1.All values are in hexadecimal.
2.Except when reading array or Automatic Select data, all bus cycles are write operation.
3.The Reset command is required to return to the read mode when the device is in the
Automatic Select mode or if Q5 goes high.
4.The fourth cycle of the Automatic Select command sequence is a read cycle.
5.The data is 99h for factory locked and 19h for not factory locked.
6.The data is 00h for an unprotected sector/sector block and 01h for a protected
sector/sector block. In the third cycle of the command sequence, address bit A20=0 to
verify sectors 0~31, A20=1 to verify sectors 32~70 for Top Boot device.
STANDBY MODE
MX29LV320AT/B can be set into Standby mode with two different approaches. One is
using both CE and RESET pins and the other one is using RESET pin only.
When using both pins of CE and RESET, a CMOS Standby mode is achieved with both
pins held at Vcc ±0.3V. Under this condition, the current consumed is less than 0.2uA
(typ.). If both of the CE and RESET are held at VIH, but not within the range of VCC ± 0.3V,
the device will still be in the standby mode, but the standby current will be larger. During
Auto Algorithm operation, Vcc active current (ICC2) is required even CE = "H" until the
operation is completed. The device can be read with standard access time (tCE) from
either of these standby modes.
When using only RESET, a CMOS standby mode is achieved with RESET input held at
Vss Γҏ0.3V, Under this condition the current is consumed less than 1uA (typ.). Once the
RESET pin is taken high, the device is back to active without recovery delay.In the standby
mode the outputs are in the high impedance state, independent of the OE
input.MX29LV320AT/B is capable to provide the Automatic Standby Mode to restrain
power consumption during readout of data. This mode can be used effectively with an
application requested low power consumption such as handy terminals.
To active this mode, MX29LV320AT/B automatically switch themselves to low power
mode when MX29LV320AT/B addresses remain stable during access time of tACC+30ns.
It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current
consumed is typically 0.2uA (CMOS level).
RESET OPERATION
01The RESET pin provides a hardware method of resetting the device to reading array
data. When the RESET pin is driven low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET pulse. The device also resets the
internal state machine to reading array data.
Notes:
1.Performing successive read operations from the erase-suspended sector will cause Q2
to toggle.
2.Performing successive read operations from any address will cause Q6 to toggle.
3.Reading the byte/word address being programmed while in the erase-suspend program
mode will indicate logic "1" at the Q2 bit.
However, successive reads from the erase-suspended sector will cause Q2 to toggle.
4. Initialization
Only one of the following two conditions must be met.
• No power sequencing is specified during power up or power down given the following
criteria:
VDD and VDDQ are driven from a single power converter output
VTT meets the specification
A minimum resistance of 42 ohms limits the input current from the VTT supply into any
pin and VREF tracks VDDQ /2 or The following relationships must be followed:
VDDQ is driven after or with VDD such that VDDQ < VDD + 0.3V
VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3V
VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3V
Once the 200μs delay has been satisfied, a Deselect or NOP command should be applied,
and CKE must be brought HIGH. Following the NOP command, a Precharge ALL
command must be applied. Next a Mode Register Set command must be issued for the
Extended Mode Register, to enable the DLL, then a Mode Register Set command must be
issued for the Mode Register, to reset the DLL, and to program the operating parameters.
200 clock cycles are required between the DLL reset and any read command.
A Precharge ALL command should be applied, placing the device in the “all banks idle”
state Once in the idle state, two auto refresh cycles must be performed. Additionally, a
Mode Register Set command for the Mode Register, with the reset DLL bit deactivated (i.e.
to program operating parameters without resetting the DLL) must be performed.
Following these cycles, the DDR SDRAM is ready for normal operation.
DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a
valid MRS command to either the base or extended mode registers without affecting the
contents of the memory array. The contents of either the mode register or extended mode
register can be modified at any valid time during device operation without affecting the
state of the internal address refresh counters used for device refresh.
6. Burst Definition
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit A3. The ordering of accesses
within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Burst Definition on page 11.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of
a Read command and the availability of the first burst of output data. The latency can be
programmed 2 or 2.5 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is
available nominally coincident with clock edge n + m. Reserved states should not be used
as unknown operation or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with
bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by
issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8
set to one, and bits A0-A6 set to the desired values. A Mode Register Set command
issued to reset the DLL should always be followed by a Mode Register Set command to
select normal operating mode. All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved states should not be used as
unknown operation or incompatibility with future versions may result.
9. Capacitance
PI3HDMI412FT
Pericom Semiconductor’s PI3HDMI series of switch circuits are targeted for
high-resolution video networks that are based on DVI/HDMI standards, and TMDS signal
processing. ThePI3HDMI412FT-A is an 8- to 4-Channel Mux/DeMux Switch. The device
multiplexes differential signals to one of two corresponding outputs. The switch is
bidirectional and offers little or no attenuation of the high-speed signals at the outputs. It is
designed for low bit-to-bit skew and high channel-to-channel noise isolation.
The allowable data rate of 5.0Gbps provides the resolution required by the next generation
HDTV and PC graphics. Three differential channels are used for data (video signals for
DVI or audio/video signals for HDMI), and one differential channel is used for Clock for
decoding the TMDS signals at the outputs.
Because of its passive bidirectional feature, this switch can be used either at the video
drivers side or at the receiver side. For PC graphics applications, the device sits at the
drivers side to switch between multiple display units such as PC LCD monitor, projector,
TV, etc. For consumer video applications, the device sits at the receiver end to switch
between the sources components such as DVD, D-VHS, STB, etc.
Maximum Ratings
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical
Characteristics for the applicable device type.
2. Typical values are at TA = 25°C ambient and maximum loading.
Switching Waveforms
CH1 GP (C89)
HDMI 1&2
CH1 HDMIDDCSCL_0(R235) ; CH2 HDMICAB0 (Q8 PIN3)
Start
N0
1. Is Power board output 5V(F2)?
2. Is J1 connector good?
LED is lighted
3. Is DC-DC OK?
(Orange) 4. Is U8 pin2 (3.3V) working ok?
Yes
It is in power saving
N0 1. Check video cable
LED is lighting? 2. Is the timing supported?
3. Check sync input
4. Check VGASOG rout if
analog (SOG) (C88)
Yes
N0
Yes
Yes
N0 It means data to LVDS
1. Is J7 connecting OK?
U11has no data 2. Check J1 +5V (F2) & +12V (F1)
3. Is panel ok?
out? 4. Check P3 D-sub Input correct
5. Check analog input route
Yes
END
Start
N0
Yes
1. Check P11 signal
N0
2. Check signal between P2 and
U14 (IF AV1/AV2 mode)
3. Check Tuner &U14 (IF TV mode)
U4 input correct? 4. Check U14 POWER +3.3V
Yes
N0
Yes
END
Start
N0
Yes
N0
Yes
N0
Yes
N0
Is LVDS output
1. Check U4
correct ?
2. Check U4 power 3.3V&1.25v&1.8v
Yes
END
Start
N0
Yes
N0
N0
Is HDMI output
1. Check DVD output
orrect ? Yes
END
Start
N0
The voltage is about + 5V
1. Check power board
J1 PIN9,10,11
2. Check power cable, F2 & connection J1
3. Check U8 pin1 (+5V) & pin2 (+3.3V)
Yes
N0
The voltage is about + 12V while power switch on
J1 PIN 2,3,4,5 1. Is J1 connection good
2. Check J1 Pin1 is up to about 3.3V?
3. Check power board
4. Check F1.
Yes
N0
The voltage is about +5V while power switch on
U1 pin 5 6 7 8 1. Check F2 & U1
2. Check OPWRSB (R20)
3. Check U1 pin1&2 or pin 3&4, should have -1V more.
Yes
N0
The voltage is about +3.3V
U2, U4, U8 & U33 1. Check F2 & U1
2. Check U2, U4, U8 & U33
Yes
N0
The voltage is about +1.6V
U6 pin 5, 6 1. Check F2 & U1
2. Check U6
Yes N0
Yes
N0
The voltage is about +2.6V while power switch on
U10 pin2 1.Check J1 Connect
2.Check U10
END
Start
N0
Support DDC1/2B
1. Analog cable ok?
Is Analog DDC OK?
2 .Check signal (U21 to P3)
3. Check U21 Voltage
4. Is protocol compliant?
Yes
N0
Support DDC1/2B
1. Analog cable ok?
Is HDMI DDC OK?
2. Check signal (U23 to P6)
3. Check signal (U25 to P7)
4. Is protocol compliant?
Yes
END
Digital
Video bus Power Board AC IN
Speakers
J2 j7 J1 J6
Main Board
The two ports of HDMI signals pass a HDMI signal switch (PI3HDMI412FT-A).
MT5371 processes HDMI signals directly, then transform video signal to LVDS and
audio signal to I2S. LVDS are transmitted to LCD device, and I2S signals to U22 .
The passing signals are processed as other audio signals.
Main broad block diagram shows the routes of these signals in our system.
ORRESET
RESET
HDMI1
PI3HDMI412FT
FLASH
HDMI2 29LV320CTTC-70G
24c02 24c02
LVDS
HDMI EDID ROM
HDMI L/R NT5DS32M16BS-5T
R L MT5371
DDR RAM
24C02
D-SUB
37" LPL LCD PANEL
VGA L/R
PC AUDIO
Y1
27MHZ
L1
Pb1 7 KEY ADC
R1 KEY BOARD IR BOARD
Pr1
COMPONENT
COMPONENT1 AUDIO1 IR&BACKLIGHT IR&BACKLIGHT
BACKLIGHT
Y2
Pb2 L2 MUTE/VOL
R2
Pr2 I2S
COMPONENT
COMPONENT2 AUDIO2
I2S 10W
L
L1
L TDA8946AJ
R1
MT8291 AMP
R
AV1
10W
COMPOSITE R
NTSC CVBS
SIF
TUNER TS0DATA[0..7]
FAT IN+ TS DATA
FAT IN-
IF AGC
MT5112
RESET(GPIO0)/TS(GPIO18)=>MT5371
TUNER I2C
25MHZ
SW1,SW2,
0220-7020-0130 SW TACT 6*6mm 180' 160g SFKHHAM2525 L-F 7
SW3,SW4,SW5,SW6,SW7
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0304-1000-0113 CONN HDMI 19P 90' SMD With Flange (392M19-H58) L-F P6,P7 2 ʳ
Q1,Q10,Q16,Q17,Q18,Q19,
4,Q5,Q8,Q9
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0451-1250-1066 WAFER 1.25mm 10P 90' DIP KINK (M240110R) L-F CON1 1 ʳ
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3632-0082-0312 PACKING ASS'Y VW32L HDTV10A
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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3632-0092-0331 PANEL ASS'Y VW32L HDTV10A_LPL (ABS, BLK)
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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3632-0012-0156 DISPLAY BD ASS'Y VX32L HDTV
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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3632-0062-0393 ACCESSARY ASS'Y VW32L HDTV10A
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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3632-0142-0150 MAIN BD ASS'Y VW32L HDTV10A (HDCP)
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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3642-0022-0189 IR BD ASS'Y GV42L HDTV
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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363200120156M DISPLAY BD ASS'Y VX32L HDTV MI
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
1 CON1 0451-1250-1066 WAFER 1.25mm 10P 90' DIP KINK (M240110R) L-F 1
2 SS 0451-1250-1063 WAFER 1.25mm 10P 90' KINK (A1251WR0-10P)
3 CON3 0451-1250-0366 WAFER 1.25mm 3P 90' DIP KINK (M24013R) L-F 1
4 SS 0451-1250-0363 WAFER 1.25mm 3P 90' KINK (A1251WR0-3P) L-F
5 J2 0451-2000-0466 WAFER 2.0mm 4P 90' DIP KINK (M24264R) L-F 1
6 SS 0451-2003-0463 WAFER 2.00mm 4P 90' KINK (A2001WR2-4P) L-F
7 SW1 0220-7020-0130 SW TACT 6*6mm 180' 160g SFKHHAM2525 L-F 1
8 SW2 0220-7020-0130 SW TACT 6*6mm 180' 160g SFKHHAM2525 L-F 1
9 SW3 0220-7020-0130 SW TACT 6*6mm 180' 160g SFKHHAM2525 L-F 1
10 SW4 0220-7020-0130 SW TACT 6*6mm 180' 160g SFKHHAM2525 L-F 1
11 SW5 0220-7020-0130 SW TACT 6*6mm 180' 160g SFKHHAM2525 L-F 1
12 SW6 0220-7020-0130 SW TACT 6*6mm 180' 160g SFKHHAM2525 L-F 1
13 SW7 0220-7020-0130 SW TACT 6*6mm 180' 160g SFKHHAM2525 L-F 1
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!
363200120156S DISPLAY BD ASS'Y VX32L HDTV SMD
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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363201420150A MAIN BD ASS'Y VW32L HDTV10A AI
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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363201420150M MAIN BD ASS'Y VW32L HDTV10A MI
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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363201420150S MAIN BD ASS'Y VW32L HDTV10A SMD
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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!
364200220189M IR BD ASS'Y GV42L HDTV MI
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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!
364200220189S IR BD ASS'Y GV42L HDTV SMD
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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!
363201420150B MAIN BD ASS'Y VW32L HDTV10A SMD BOT
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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363201420150T MAIN BD ASS'Y VW32L HDTV10A SMD TOP
ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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231 SS 0112-3474-1636 C/M Multi. 0.47uF 16V Y5V 0603 L-F
232 C119 0111-3102-5117 C/M MULTI 1000PF 50V X7R 0402 1
233 SS 0112-3102-5117 C/M Multi. 1000PF 50V X7R 0402
234 C121 0111-3224-2516 C/M Multi. 0.22uF 25V X7R 0603 1
235 SS 0112-3224-2516 C/M Multi. 0.22uF 25V X7R 0603
236 C122 0111-3474-1636 C/M Multi. 0.47uF 16V Y5V 0603 1
237 SS 0112-3474-1636 C/M Multi. 0.47uF 16V Y5V 0603 L-F
238 C123 0111-3474-1636 C/M Multi. 0.47uF 16V Y5V 0603 1
239 SS 0112-3474-1636 C/M Multi. 0.47uF 16V Y5V 0603 L-F
240 C124 0111-3102-5117 C/M MULTI 1000PF 50V X7R 0402 1
241 SS 0112-3102-5117 C/M Multi. 1000PF 50V X7R 0402
242 C126 0111-3474-1636 C/M Multi. 0.47uF 16V Y5V 0603 1
243 SS 0112-3474-1636 C/M Multi. 0.47uF 16V Y5V 0603 L-F
244 C127 0111-3224-2516 C/M Multi. 0.22uF 25V X7R 0603 1
245 SS 0112-3224-2516 C/M Multi. 0.22uF 25V X7R 0603
246 C128 0111-3224-2516 C/M Multi. 0.22uF 25V X7R 0603 1
247 SS 0112-3224-2516 C/M Multi. 0.22uF 25V X7R 0603
248 C129 0111-3224-2516 C/M Multi. 0.22uF 25V X7R 0603 1
249 SS 0112-3224-2516 C/M Multi. 0.22uF 25V X7R 0603
250 C13 0111-3103-1617 C/M Multi. 0.01uF 16V X7R K 0402 1
251 SS 0112-3103-1617 C/M Multi. 0.01uF 16V X7R K 0402
252 C130 0111-3104-1617 C/M Multi. 0.1uF 16V X7R 0402 1
253 SS 0112-3104-1617 C/M Multi. 0.1uF 16V X7R 0402
254 C131 0111-3104-1617 C/M Multi. 0.1uF 16V X7R 0402 1
255 SS 0112-3104-1617 C/M Multi. 0.1uF 16V X7R 0402
256 C14 0111-3569-5107 C/M Multi. 5.6pF 50V NPO 0402 1
257 SS 0112-3569-5107 C/M Multi. 5.6pF 50V NPO 0402
258 C15 0111-3150-5107 C/M Multi. 15PF 50V NPO 0402 1
259 SS 0112-3150-5107 C/M Multi. 15PF 50V NPO 0402
260 C157 0111-3475-1135 C/M MULTI 4.7uF 10V Y5V 0805 1
261 SS 0112-3475-1135 C/M MULTI 4.7uF 10V Y5V 0805
262 C158 0111-3106-1114 C/M MULTI 10uF 10V X7R K 1206 1
263 SS 0112-3106-1114 C/M Multi. 10UF 10V X7R 1206
264 C16 0111-3473-2517 C/M Multi. 0.047uF 25V X7R 0402 1
265 SS 0112-3473-2517 C/M Multi. 0.047uF 25V X7R 0402
266 C17 0111-3103-1617 C/M Multi. 0.01uF 16V X7R K 0402 1
267 SS 0112-3103-1617 C/M Multi. 0.01uF 16V X7R K 0402
268 C19 0111-3103-1617 C/M Multi. 0.01uF 16V X7R K 0402 1
269 SS 0112-3103-1617 C/M Multi. 0.01uF 16V X7R K 0402
270 C207 0111-3104-1617 C/M Multi. 0.1uF 16V X7R 0402 1
271 SS 0112-3104-1617 C/M Multi. 0.1uF 16V X7R 0402
272 C21 0111-3104-5166 C/M MULTI 0.1UF 50V X7R J 0603 1
273 SS 0112-3104-5166 C/M Muitl. 0.1uF 50V X7R J 0603
274 C22 0111-3106-1114 C/M MULTI 10uF 10V X7R K 1206 1
275 SS 0112-3106-1114 C/M Multi. 10UF 10V X7R 1206
276 C24 0111-3180-5107 C/M Multi. 18PF 50V NPO 0402 1
277 SS 0112-3180-5107 C/M Multi. 18PF 50V NPO 0402
278 C25 0111-3180-5107 C/M Multi. 18PF 50V NPO 0402 1
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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ITEM M/S LOCATION PART NO. DESCRPTION QTY REMARK
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