VIZIO GV42L HDTV Service Manual
VIZIO GV42L HDTV Service Manual
VIZIO GV42L HDTV Service Manual
V, Inc
320A Kalmus Drive Costa Mesa, CA 92626
TEL : +714-668-0588 FAX :+714-668-9099
Top Confidential
Table of Contents
CONTENTS PAGE
Sections
1. Features 1-1
2. Specifications 2-1
8. Waveforms 8-1
Appendix
1. Main Board Circuit Diagram
2. Main Board PCB Layout
Block Diagram
IBM and IBM products are registered trademarks of International Business Machines
Corporation.
Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc.
VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards
Association (VESA).
No part of this document may be copied, reproduced or transmitted by any means for any
purpose without prior written permission from VINC.
FCC INFORMATION
This equipment has been tested and found to comply with the limits of a Class B digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses and can radiate radio frequency energy, and if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is
no guarantee that the interference will not occur in a particular installation. If this equipment
does cause unacceptable interference to radio or television reception, which can be
determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures -- reorient or relocate the receiving
antenna; increase the separation between equipment and receiver; or connect the into an
outlet on a circuit different from that to which the receiver is connected.
FCC WARNING
To assure continued FCC compliance, the user must use a grounded power supply cord and
the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized
changes or modifications to Amtrak products will void the user’s authority to operate this
device. Thus VINC Will not be held responsible for the product and its safety.
CE CERTIFICATION
This device complies with the requirements of the EEC directive 89/336/EEC with regard to
“Electromagnetic compatibility.”
SAFETY CAUTION
Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL);
Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric
Appliance Control Act); or an AC cord that meets the local safety standards.
9. On Screen Display: user can define display mode (i.e. color, brightness,
contrast, sharpness, backlight), sound setting, PIP, TV channel program,
aspect and gamma or reset all setting.
2. OPTICAL CHARACTERISTICS
Viewing Angle (CR>10)
Left: 89°typ.
Right: 89°typ.
Top: 89°typ.
Bottom: 89°typ.
4.Input Connectors
RJ11, D-SUB15PIN (MINI, 3rows), Headphone, HDMIX2, RCAX3 (component), RCAX2
(AUDIO in), RCAX3 (composite), RCAX2 (AUDIO in), S-Video, Tuner
5. POWER SUPPLY
Power Consumption: 280W MAX
Power OFF: to less than 3W MAX
7. ENVIRONMENT
5-1. Operating Temperature: 5c~35c (Ambient)
5-2. Operating Humidity: Ta= 35 ¶C, 90%RH (Non-condensing)
5-3. Operating Altitude: 0 - 14,000 feet (4267.2m)(Non-Operating)
(2) You should consider the mounting structure so that uneven force (ex. Twisted stress)
is not applied to the module. And the case on which a module is mounted should
have sufficient strength so that external force is not transmitted directly to the
module.
(3) Please attach the surface transparent protective plate to the surface in order to
protect the polarizer. Transparent protective plate should have sufficient strength in
order to the resist external force.
(4) You should adopt radiation structure to satisfy the temperature specification.
(5) Acetic acid type and chlorine type materials for the cover case are not desirable
because the former generates corrosive gas of attacking the polarizer at high
temperature and the latter causes circuit break by electro-chemical reaction.
(7) When the surface becomes dusty, please wipe gently with absorbent cotton or other
soft materials like chamois soaks with petroleum benzene. Normal-hexane is
recommended for cleaning the adhesives used to attach front / rear polarizers. Do not
use acetone, toluene and alcohol because they cause chemical damage to the
polarizer.
(8) Wipe off saliva or water drops as soon as possible. Their long time contact with
polarizer causes deformations and color fading.
(9) Do not open the case because inside circuits do not have sufficient strength.
(2) Response time depends on the temperature. (In lower temperature, it becomes
longer.)
(5) When fixed patterns are displayed for a long time, remnant image is likely to occur.
(6) Module has high frequency circuits. System manufacturers shall do sufficient
suppression to the electromagnetic interference. Grounding and shielding methods
may be important to minimize the interference.
(2) When the module with protection film attached is stored for a long time, sometimes
there remains a very small amount of glue still on the bezel after the protection film is
peeled off.
(3) You can remove the glue easily. When the glue remains on the bezel surface or its
vestige is recognized, please wipe them off with absorbent cotton waste or other soft
material like chamois soaked with normal-hexane.
TV Source
A. Picture Adjustř
a. Picture Mode (Standard/Movie /Game / Custom)
b. Backlight (0~100)
c. Contrast (0~100)
d. Brightness (0~100)
e. Color (saturation)(0~100)
f. Tint (hue) (0~100)
g. Sharpness (0~7)
h. Color Temperature (Cool/Normal/Warm/Custom)
i. Advanced Picture Adjust
B. Audio Adjustř
a. Volume (0~100)
b. Bass (0~100)
c. Treble (0~100)
d. Balance (0~100)
e. Surround (ON/OFF)
f. Speakers (ON/OFF)
D. TV Tuner Setupř
a. Tuner Mode (Cable/Air)
b. Auto Search
c. Skip Channel
d. Digital Audio Out (PCM/Dolby Digital)
e. Time Zone
(Eastern/Indiana/Central/Mountain/Arizona/Pacific/Alaska/Hawaii)
E. Parental Controlř
a. Parental Lock Enable (ON/OFF)
b. TV Rating
c. Move Rating
d. Block Unrated TV (NO/Yes)
e. Access Code Edit
RGB Mode
A. Picture Adjustř!
a. Auto Adjust
b. Backlight (0~100)
c. Contrast (0~100)
d. Brightness (0~100)
e. Color Temperature (9300/6300/Custom)
f. Tint (0~100)
g. H-Size (0~255)
h. Horizontal Shift (0~63)
i. Fine Tune (0~31)
C. Special Featuresř!
a. Language (English/Français/EspaĖol)
b. Sleep Timer (OFF/30Min/60Min/90Min/120Min)
c. PIP Position (TL/TC/TR/ML/MR/BL/BC/BR)
d. Rest All Setting
AV COMPONENT MODE
A. Picture Adjustř!
a. Picture Mode (Standard/Movie /Game / Custom)
b. Backlight (0~100)
c. Contrast (0~100)
d. Brightness (0~100)
e. Color (saturation)(0~100)
f. Tint (hue) (0~100)
g. Sharpness (0~7)
h. Color Temperature (Cool/Normal/Warm/Custom)
i. Advanced Picture Adjust
B. Audio Adjustř!
a. Volume (0~100)
b. Bass (0~100)
c. Treble (0~100)
d. Balance (0~100)
e. Surround (ON/OFF)
f. Speakers (ON/OFF)
D. Parental Controlř!
a. Parental Lock Enable (ON/OFF)
b. TV Rating
c. Move Rating
d. Block Unrated TV (NO/Yes)
e. Access Code Edit
HDMI MODEř
A. Picture Adjustř!
a. Picture Mode (Standard/Movie /Game / Custom)
b. Backlight (0~100)
c. Contrast (0~100)
d. Brightness (0~100)
e. Color (saturation)(0~100)
f. Tint (hue) (0~100)
g. Sharpness (0~7)
h. Color Temperature (Cool/Normal/Warm/Custom)
i. Advanced Picture Adjust
B. Audio Adjustř!
a. Volume (0~100)
b. Bass (0~100)
c. Treble (0~100)
d. Balance (0~100)
e. Surround (ON/OFF)
f. Speakers (ON/OFF)
Pin Description
1 Red
2 Green
3 Blue
4 Ground
5 Ground
6 R-Ground
7 G-Ground
8 B-Ground
10 Ground
11 No Connection
12 (SDA)
13 H-Sync (Composite
Sync)
14 V-Sync
15 (SCL)
˄ ˈ
ˉ ˄˃
˄˄ ˄ˈ
F-Type TV RF connector
a. Signal Level 60dBμV typical
b. System NTSC
c. Frequency 55~801MHz (NTSC)
Component 2
a. Frequency H: 15.734KHz V: 60Hz (NTSC-480i)
H: 31KHz V: 60Hz (NTSC-480p)
H: 45KHz V: 60Hz (NTSC-720p)
H: 33KHz V: 60Hz (NTSC-1080i)
b. Signal level Y: 1Vp-p Pb: Ć0.350Vp-p Pr: Ć0.350Vp-p
c. Impedance 75
Pin Description
1 “+5V”
2 “+3.3V”
3 “ADCKEY”
4 “LED”
5 “PWR KEY”
6 “GND”
7 “GND”
8 “IR”
J7 CONNECTION (TOPШBOTTOM)
Pin Description
1 “POWRSW”
2 “+12V”
3 “+12V”
4 “+12V”
5 “GND”
6 “GND”
7 “GND”
8 “GND”
9 “GND”
10 “+5V”
11 “+5V”
12 +5V
13 “PWM”
14 “BL ON/OFF”
BOLOCK DIAGRAM
2. Decoder
TVD
1.Single 2nd generation TV decoder
2.Automatic TV standard detection supporting NTSC, NTSC-4.43, PAL (B, G, D, H, M, N, I, Nc),
PAL (Nc), PAL, SECAM
3.Enhanced 2nd generation NTSC/PAL Motion Adaptive 3D comb filter
4.Motion Adaptive 3D Noise Reduction
5.Embedded VBI decoder for Closed-Caption/XDS/ Teletext/WSS/VPS
6.Supporting Macro vision detection
YPbPr/Scart/D-connector
1.Supporting HDTV 480i/480p/576i/576p/720p/1080i input
2.Smart detection on Scart function for European region
3.Smart detection on D-connector for Japan region
4.Supporting SCART RGB inputs mixed with composite signal by adjustable horizontal delay
Digital port
1.1 digital port supporting DVI 24-bit RGB or CCIR-656/601 digital video input format
2.1 additional 8 bit digital port for ITU656 video format
VBI
1.Dual VBI decoders for the application of V-Chip/Closed-Caption/XDS/ Teletext/WSS/VPS
2.Supporting external VBI decoder by YPrPb input
3.VBI decoder up to 1000 pages Teletext.
3. Support Formats:
Support NTSC, NTSC-4.43
Automatic Luma / Chroma gain control
Automatic TV standard detection
NTSC Motion Adaptive 3D comb filter
Motion adaptive 3D Noise Reduction
VBI decoder for closed-caption/XDS/Teletext/WSS/VPS
Macro vision detection
4. 2D-Graphic/OSD processor
Embedded two backend RGB domain OSD planes and one YUV domain OSD plane. to support
Main/PIP Teletext/Close-caption functions together with setup menu
1.Supporting alpha blending among these two planes and video
2.Supporting Text/Bitmap decoder
3.Supporting line/rectangle/gradient fill
4.Supporting bitblt
5.Supporting color Key function
6.Supporting Clip Mask
7.65535/256/16/4/2-color bitmap format OSD,
8.Automatic vertical scrolling of OSD image
9.Supporting OSD mirror and upside down
CONFIDENTIAL – DO NOT COPY Page 7-5
File No. SG-0198
5. Microprocessor interface
When power is supplied and power key is pressed then the rest circuit lets Reset to low state that
will reset the MTK8202 to initial state. After that the Reset will transits to high state and the
MTK8202 start to work that microprocessor executes the programs and configures the internal
registers. The execution speed of CPU is 162 MHz.
2.Contrast/Brightness/Sharpness Management
Sharpness and DLTI/DCTI
Brightness and contrast adjustment
Black level extender
White peak level limiter
Adaptive Luma/Chroma management
3.De-interlacing
2nd generation advanced Motion adaptive de-interlacing
Automatic detect film or video source
3:2/2:2 pull down source detection
Main/PIP 2 independent de-interlacing processor
4.Scaling
2nd generation high resolution arbitrary ratio vertical/horizontal scaling of video,
from 1/32X to 32X
Advanced linear and non-linear Panorama scaling
Programmable Zoom viewer
Picture-in-Picture (PIP)
Picture-Out-Picture (POP)
5.Display
Advanced dithering processing for LCD display with 6/8/10 bit output
10bit gamma correction
Supporting alpha blending for Video and two OSD planes
Frame rate conversion
2.For single DDR, 8202 only support 1080i bob mode de-interlacing. (Non-3D de interlace)
3.With single DDR, it is suggested not to support PIP/POP features. Due to DDR Bandwidth
limitation on PIP/POP when single DDR.
1. COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the
command register. Writing incorrect address and data values or writing them in the
improper sequence will reset the device to the read mode. Table 5 defines the valid
register command sequences. Note that the Erase Suspend (B0H) and Erase Resume
(30H) commands are valid only while the Sector Erase operation is in progress.
3. READ/RESET COMMAND
The read or reset operation is initiated by writing the read/reset command sequence into the
command register. Microprocessor read cycles retrieve array data. The device remains enabled
for reads until the command register contents are altered. If program-fail or erase-fail happen, the
write of F0H will reset the device to abort the operation. A valid command must then be written to
place the device in the desired state.
5. RESET COMMAND
Writing the reset command to the device resets the device to reading array data. Addresses bits
are don't care for this command. The reset command may be written between the sequence
cycles in an erase command sequence before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device ignores reset commands until the operation
is complete. The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to reading array data
(also applies to programming in Erase Suspend mode). Once programming begins, however, the
device ignores reset commands until the operation is complete. The reset command may be
written between the sequence cycles in an SILICON ID READ command sequence. Once in the
SILICON ID READ mode, the reset command must be written to return to reading array data (also
applies to SILICON ID READ during Erase Suspend). If Q5 goes high during a program or erase
operation, writing the reset command returns the device to reading array data (also applies during
Erase Suspend).
WM8776 Application
The WM8776 is a high performance, stereo audio codec with five channel input selector. The
WM8776 is ideal for surround sound processing applications for home hi-fi, DVD-RW and other
audiovisual equipment. Etch ADC channel has programmable gain control with automatic level
control. Digital audio output word lengths from 16-32 bits and sampling rates from 32kHZ to 96KHZ
are supported. The DAC has an input mixer allowing an external analogue signal to be mixed with
the DAC signal. There are also Headphone and line outputs, with control for the headphone
The WM8776 supports fully independent sample rates for the ADC and DAC. The audio data
interface supports I2S, left justified, right justified and DSP formats.
BLOCK DIAGRAM
3. HDCP Decryption
The MT8293 external EEPROM for encrypt HDCP keys. HDCP decryption contains all
necessary logic to decrypt the incoming audio and video data. The decryption process is
entirely controlled by the host microprocessor through a set sequence of register reads
and wires through the DDC channel. Pre-programmed HDCP keys and key Selection
Vector are used in the decryption process. A resulting calculated to an XOR mask during
each clock cycle to decrypt the audio/video data in sync with the host.
TDA8946 Application
In L32 TV the TDA8946AJ is a dual-channel audio power amplifier with DC gain control. It has an
output power of 2 u10 W at an 8 :load and a 12 V supply.
1. Input configuration
The TDA8946AJ inputs can be driven symmetrical (floating) as well as asymmetrical. In the
asymmetrical mode one input pin is connected via a capacitor to the signal source and the other
input is connected to the signal ground. The signal ground should be as close as possible to the
SVR (electrolytic) capacitor ground. Note that the DC level of the input pins is half of the supply
voltage VCC, so coupling capacitors for both pins are necessary
MT5351 Application :
MediaTek MT5351 is a DTV Backend Decoder SOC which support flexible transport demux , HD
MPEG-2 video decoder , JPEG decoder , MPEG1,2,MP3,AC3 audio decoder , HDTV encoder . The
MT5351 enables consumer electronics manufactures to build high quality , feature-rich DTV , STB or
other home entertainment audio/video device.World-Leading Technology : HW support worldwide
major broadcast network and CA standards , include ATSC , DVB , OpenCable , DirectTV ,
MHP.Rich Feature for high value product : To enrich the feature of DTV , the MT5351 support
1394-5C component to external DVHS . Dual display , PIP/POP and quad pictures provide user a
whole new viewing experience.Credible Audio/Video Quality : The MT5351 use advanced
motion-adaptive de-interlace algorithm to achieve the best movie/video playback , The embedded
4X over-sample video DAC could generate very fine display quality . Also , the audio 3D surround
and equalizer provide professional entertainment.
1 . Host CPU:
1. ARM 926EJ
2.16K I-Cache and 16K D-Cache
3. 8K Data TCM and 8K instruction
4. JTAG ICE interface
5. Watch Dog timers
2 . Transport Demuxer :
1. Support 3 independent transport stream inputs
2. Support serial/parallel interface for each transport stream input
3. Support ATSC , DVB , and MPEG2 transport stream inputs.
4. Programmable sync detection.
5. Support DES/3-DES De-scramble.
6. 96 PID filter and 128 section filters.
7. Support TS recording via IEEE1394 interface.
3 . MPEG2 Decoder :
1. Support dual MPEG-2 HD decoder or up to 8 SD decoder.
2. Complaint to MP@ML , MP@HL and MPEG-1 video standards.
4 . JPEG Decoder :
1. Decode Base-line or progressive JPEG file.
5 . 2D Graphics :
1. Support multiple color modes.
2. Point , horizontal/vertical line primitive drawing.
3. Rectangle fill and gradient fill functions.
4. Bitblt with transparent , alpha blending , alpha composition and stretch.
5. Font rendering by color expansion.
6. Support clip masks.
7. YCrCb to RGB color space transfer.
6 . OSD Display :
1. 3 linking list OSDs with multiple color mode.
2. OSD scaling with arbitary ratio from 1/2x to 2x.
3. Square size , 32x32 or 64x64 pixel , hardware cursor.
CONFIDENTIAL – DO NOT COPY Page 7-32
File No. SG-0198
7 . Video Processing :
1. Advanced Motion adaptive de-interlace on SDTV resolution.
2. Support clip
3. 3:2/2:2 pull down source detection.
4. Arbitrary ratio vertical/horizontal scaling of video , from 1/15X to 16X.
5. Support Edge preserve.
6. Support horizontal edge enhancement.
7. Support Quad-Picture.
8 . Main Display :
1. Mixing two video and three OSD and hardware cursor.
2. Contrast/Brightness adjustment.
3. Gamma correction.
4. Picture-in-Picture( PIP ).
5. Picture-Out-Picture( POP ).
6. 480i/576i/480p/576p/720p/1080i output
9 . Auxiliary Display :
1. Mixing one video and one OSD.
2. 480i/576i output.
10 . TV Encoder :
1. Support NTSC M/N , PAL M/N/B/D/G/H/I
2. Macrovision Rev 7.1.L1
3. CGMS/WSS.
4. Closed Captioning.
5. Six 12-bit video DACs for CVBS , S-video or RGB/YPbPr output.
14 . Audio :
15 . Peripherals :
1. Three UARTs with Tx and Rx FIFO , two of them have hardware flow control.
2. Two serial interfaces , one is master only the other can be set to master mode or slave mode.
3. Two PWMs.
4. IR blaster and receiver.
5. IEEE1394 link controller.
6. IDE bus : ATA/ATAPI7 UDMA mode 5 , 100MB/s.
7. Real-time clock and watchdog controller.
8. Memory card I/F : MS/MS-pro ,SD ,CF ,and MMC
9. PCMCIA/POD/CI interface
The MX29LV320AT/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and 2M words
of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile
random access memory.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and
programming. The MX29LV320AT/B uses a command register to manage this functionality. MXIC
Flash technology reliably stores memory contents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing and low internal electric fields for erase and
programming operations produces reliable cycling.
The MX29LV320AT/B uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and
auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V
to VCC + 1V.
Legend:
L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0Γ0.5V, VHH=11.5-12.5V, X=Don't Care,
AIN=Address IN, DIN=Data IN,DOUT=Data OUT
Notes:
1. When the WP/ACC pin is at VHH, the device enters the accelerated program mode. See
"Accelerated Program Operations" for more information.
2.The sector group protect and chip unprotect functions may also be implemented via programming
equipment. See the "Sector Group Protection and Chip Unprotection" section.
3.If WP/ACC=VIL, the two outermost boot sectors remain protected. If WP/ACC=VIH, the two
outermost boot sector protection depends on whether they were last protected or unprotected
using the method described in "Sector/Sector Block Protection and Unprotection". If
WP/ACC=VHH, all sectors will be unprotected.
4.DIN or Dout as required by command sequence, data polling, or sector protection algorithm.
5.Address are A20:A0 in word mode (BYTE=VIH), A20:A-1 in byte mode (BYTE=VIL).
Notes:
1.Code=00h means unprotected, or code=01h protected.
2.Code=99 means factory locked, or code=19h not factory locked.
Legend:
X=Don't care
RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE or CE pulse.
PD=Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse.
SA=Address of the sector to be erased or verified. Address bits A20-A12 uniquely select any sector.
ID=22A7h(Top), 22A8h(Bottom)
Notes:
1.All values are in hexadecimal.
2.Except when reading array or Automatic Select data, all bus cycles are write operation.
3.The Reset command is required to return to the read mode when the device is in the Automatic
Select mode or if Q5 goes high.
4.The fourth cycle of the Automatic Select command sequence is a read cycle.
5.The data is 99h for factory locked and 19h for not factory locked.
6.The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
In the third cycle of the command sequence, address bit A20=0 to verify sectors 0~31, A20=1 to
verify sectors 32~70 for Top Boot device.
7.Command is valid when device is ready to read array data or when device is in Automatic Select
mode.
8.The system may read and program functions in non-erasing sectors, or enter the Automatic Select
mode, when in the erase Suspend mode. The Erase Suspend command is valid only during a
sector erase operation.
9.The Erase Resume command is valid only during the Erase Suspend mode.
RESET OPERATION
01The RESET pin provides a hardware method of resetting the device to reading array data. When
the RESET pin is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all output pins, and ignores all read/write commands for the duration
of the RESET pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET pulse. When RESET is held at VSSΓ0.3V, the
device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSSΓ0.3V, the
standby current will be greater.The RESET pin may be tied to system reset circuitry. A system reset
would that also reset the Flash memory, enabling the system to read the boot-up firm-ware from the
Flash memory.
Notes:
1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.
2.Performing successive read operations from any address will cause Q6 to toggle.
3.Reading the byte/word address being programmed while in the erase-suspend program mode will
indicate logic "1" at the Q2 bit.
However, successive reads from the erase-suspended sector will cause Q2 to toggle.
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the
bidirectional DQ and DQS signals.
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12
to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register
Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the
desired values. A Mode Register Set command issued to reset the DLL should always be followed
by a Mode Register Set command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test
modes and reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Active
The Active command is used to open (or activate) a row in a particular bank for a subsequent access.
The value on the BA0,BA1 inputs selects the bank, and the address provided on inputs A0-A12
selects the row. This row remains active (or open) for accesses until a Precharge (or Read or Write
with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with Auto Precharge)
command must be issued and completed before opening a different row in the same bank.
Write
The Write command is used to initiate a burst write access to an active (open) row. The value on the
BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j =
don’t care] for x8; where [i = 9, j = 11] for x4) selects the starting column location. The value on input
A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being
accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row
remains open for subsequent accesses. Input data appearing on the DQs is written to the memory
array subject to the DM input logic level appearing coincident with the data. If a given DM signal is
registered low, the corresponding data is written to memory; if the DM signal is registered high, the
corresponding data inputs are ignored, and a Write is not executed to that byte/column location.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before
RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued
each time a refresh is required.The refresh addressing is generated by the internal refresh controller.
This makes the address bits “Don’t Care” during an Auto Refresh command. The 256Mb DDR
SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8Ӵs (maximum).
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the
system is powered down.When in the self refresh mode, the DDR SDRAM retains data without
external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident
with CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is
automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read
command can be issued). Input signals except CKE (low) are “Don’t Care” during Self Refresh
operation.
Operations:
Reads
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read
bursts are initiated with a Read command.
The starting column and bank addresses are provided with the Read command and Auto Precharge
is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is
accessed starts precharge at the completion of the burst, provided tRAS has been satisfied. For the
generic Read commands used in the following illustrations, Auto Precharge is disabled.
During Read bursts, the valid data-out element from the starting column address is available
following the CAS latency after the Read command. Each subsequent data-out element is valid
nominally at the next positive or negative clock edge (i.e. at the next crossing of CK and CK). The
following timing figure entitled “Read Burst: CAS Latencies (Burst Length=4)” illustrates the general
timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output
data. The initial low state on DQS is known as the read preamble; the low state coincident with the
last data-out element is known as the read postamble . Upon completion of a burst, assuming no
other commands have been initiated, the DQs and DQS goes High-Z. Data from any Read burst
may be concatenated with or truncated with data from a subsequent Read command. In either case,
a continuous flow of data can be maintained. The first data element from the new burst follows either
the last element of a completed burst or the last desired data element of a longer burst which is
being truncated. The new Read command should be issued x cycles after the first Read command,
where x equals the number of desired data element pairs (pairs are required by the 2n prefetch
architecture). This is shown in timing figure entitled “Consecutive Read Bursts: CAS Latencies (Burst
Length =4 or 8)”.A Read command can be initiated on any positive clock cycle following a previous
Read command. Nonconsecutive Read data is shown in timing figure entitled “Non-Consecutive
Read Bursts: CAS Latencies (Burst Length = 4)”. Full-speed Random Read Accesses: CAS
Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on
following:
Writes
Write bursts are initiated with a Write command, as shown in timing figure Write Command on
following: The starting column and bank addresses are provided with the Write command, and Auto
Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being
accessed is precharged at the completion of the burst. For the generic Write commands used in the
following illustrations, Auto Precharge is disabled.
During Write bursts, the first valid data-in element is registered on the first rising edge of DQS
following the write command, and subsequent data elements are registered on successive edges of
DQS. The Low state on DQS between the Write command and the first rising edge is known as the
write preamble; the Low state on DQS following the last data-in element is known as the write
postamble.
Write Command
CH1 HDMIMCLK (U19 PIN 79) ;CH2 HDMIBCLK (U19 PIN 76)
DTV HD
CH1 VOB0 (RP35)
Start
N0
1. Is Power board output
+5V?
LED is lighted
2. Is J7 connector good?
3. Is DC-DC OK?
4. Is U6&U4 (3.3V) working ok?
Yes
It is in power saving
N0 1. Check video cable
LED is lighting? 2. Is the timing supported?
3. Check sync input
4. Check VGASOG rout if analog
(SOG)
Yes
N0
Yes
Yes
N0 It means data to LVDS
1.Is J5 connecting OK?
U11 no data out? 2.Check J7 +5V&+12V
3.Is panel ok?
4. Check P3 D-sub Input correct
5. Check analog input route
Yes
END
Start
N0
1.Check video
Input signal good?
2.Check DVD player
Yes
1.Check P2&P12 signal
N0
2.Check signal between P2 and
U11 (IF AV1/AV2 mode)
3.Check Tuner &U11 (IF TV mode)
U11 input correct? 4.Check P12 (IF S-Video)
5.Check U11 POWER +3.3V
6.Check Y1 is OK?
Yes
N0
Yes
N0
Yes
END
Start
N0
1.Check video
Input signal good? 2.Check host’s setting
Yes
N0
Yes
N0
1.Check signal between U11&P4
U11 input correct? 2.Check U11 Clock (27MHZ)
Yes
N0
1.Check U11
LVDS output correct ? 2.Check U11 power 3.3V&1.25v&1.8v
Yes
END
Start
N0
Yes
N0
Yes
Yes
END
Start
N0
The voltage is about + 5V
1.Check power board
J7 PIN10,11,12 2.Check power cable
connection J7
Yes
N0
The voltage is about + 12V while
power switch on
J7 PIN 2,3,4 1.J7 connection good
2.Check J7 Pin1 is up to 3V?
3.Check power board
Yes
N0
The voltage is about +5V while
power switch on
U1 pin 5 6 7 8 1.J1 connection good
2. Check U11 GPIO_7 Pin
Yes
N0
The voltage is about +3.3V
1.J1 to connection good?
U4 pin2 2.Check U4
Yes
N0
The voltage is about +3.3V
1.J1 to connection good?
U6 pin 2 2.Check U6
Yes N0
The voltage is about +1.8V while
power switch on
U5 pin2 1.Check U5
Yes
N0
The voltage is about +3.3V
while power switch on
U8 pin2 1.Check J1 Connect
2.Check U8
END
Start
N0
Support DDC1/2B
1.Analog cable ok?
Analog DDC OK? 2.Check signal (U20 to P3)
3.Check U20 Voltage
4.Is compliant protocol?
Yes
N0
Support DDC1/2B
1.Analog cable ok?
HDMIDDC OK? 2.Check signal (U32 to P10)
3. Check signal (U34 to P11)
4.Is compliant protocol?
Yes
END
Digital
Video bus Power Board AC IN
Speakers
J6 j5 J7 J4
Main Board
The TV system block diagram is powered by power board that transforms AC source
of 100V~240V AC +/- 10% @ 50/60 HZ into DC 5V & 12V& 24Vsource. The main
board receives different types of video signal into the MTK8202 Ic. Afterward, the
MTK8202 Ic process the signals control the various functions of the monitor and
outputs control signal, video signal and power to the 42” WXGA panel to be
displayed.
The power send to the panel is first processed by the inverter. The function of the
inverter is to step up the voltage supplied by the main board to the power that is
needed to light up the lamps in the panel. Simultaneously, the digital video signals are
processed in the panel and the outcome determines the brightness, pixel on/off and
the color displayed on the panel. The analog video signals of S-video, YPbPr, TV, PC
and A/V all video signals are translated from analog signals into MTK8202 generates
the vertical and horizontal timing signals for display device. The analog audio of
s-video, YpbPr, TV, PC and A/V is transmitting to the WM877 processed.
ʳ
VIZIO GV42L HDTV_LG
0000-0000-0002 ʳ ʳ ʳ ʳ
0043-0704-3509 IC SWITCH PI5C3257QE QSOP 16PIN LF DU7 U33 2 ʳ
0185-1152-0073 FUSE 125V/1.5A SMD (R45101.5) L-F F1 F4 F6 3 ʳ
0185-1152-0073 FUSE 125V/1.5A SMD (R45101.5) L-F F1 F2 F3 3 ʳ
0185-1302-0073 FUSE 125V/3A SMD (R451003) LF F4 1 ʳ
0280-2500-0012 X'TAL 25MHZ 49/US 30PPM 20PF LF DY1 1 ʳ
0280-2700-0012 X'TAL 27MHZ 49/US 30PPM 20PF 40ohm Y1 1 ʳ
0286-2700-0024 OSC 27MHz 25ppm 3.3V SMD VCXO DX1 1 ʳ
0410-5000-5610 TRANSISTOR MMBT3904LT1G SOT-23 L-F Q2 Q38 2 ʳ
Q1 Q10 Q11
Q12 Q15 Q18 Q19
Q20 Q21 Q23 Q24
0410-5000-5610 TRANSISTOR MMBT3904LT1G SOT-23 L-F 23
Q25 Q27 Q28 Q29
Q3 Q31 Q32 Q33
Q39 Q4 Q5 Q9 ʳ
0410-5000-5710 TRANSISTOR MMBT3906LT1G SOT-23 L-F Q22 1 ʳ
0420-1004-9621 MOSFET N-CH 2N7002E-T1-E3 SMD (SOT-23) L-F Q13 Q14 Q34 3 ʳ
0420-1005-4601 POWER MOS IRF7316TRPBF SMD 8PIN LF U1 1 ʳ
0420-1006-2622 MOSFET N-CH 11A 30V FDS6690A SOP-8 LF U25 1 ʳ
0430-0001-8015 IC CD4052BNSR 16PIN SOP16 L-F U22 U29 2 ʳ
0430-1010-8615 IC TTL LOGIC CD74HC157M96 SOIC 16PIN LF U30 1 ʳ
0430-1010-9088 IC DUAL OP AMP NJM4558M-TE3_PB SO8(DMP8) L-F U21 1 ʳ
0430-3004-3011 IC AT24C16AN-10SU-2.7 SO-8 L-F U28 1 ʳ
0430-3006-9011 IC AT24C04N-10SU-2.7 SO-8 L-F U17 1 ʳ
0430-3039-3645 IC MX29LV160CTTC-70G 48PIN TSOP LF U12 1 ʳ
0430-3039-4645 IC MX29LV320CTTC-70G 48PIN TSOP LF DU14 1 ʳ
0430-3039-6011 IC AT24C02BN-10SU-1.8 8Pin SOIC L-F U20 U32 U34 3 ʳ
0430-4013-3109 IC TDA8946AJ 17PIN DIP LF U24 1 ʳ
0430-6002-8079 IC AP1117E25LA SOT-223 L-F DU3 U16 2 ʳ
0430-6005-5079 IC AP1117E18LA LF SOT-223 U10 U5 U7 U9 4 ʳ
0430-6007-5079 IC AP1117E33LA LF SOT-223 DU2 U4 U6 U8 4 ʳ
0430-6007-7072 IC N2576SG-5 SMD 5PIN (TO-263) L-F U4 1 ʳ
0430-6009-1051 IC AMC1117SKF-ADJ SMD 3PIN SOT-223 LF DU4 U18 2 ʳ
0430-6010-9028 IC G2996F1Uf 8PIN SOP-8(FD) LF DU17 U15 2 ʳ
0430-6011-1072 IC N2576SG-ADJ TO-263 5PIN LF U1 1 ʳ
0430-6011-3210 IC MC7805CTG 3PIN TO-220 LF DU1 1 ʳ
0430-6015-5079 IC STEP DOWN CONVERTER AP1513SA SOP 8PIN LF DU5 DU6 2 ʳ
0430-6015-8079 IC DC/DC CONVERTER AP1522WA SOT23-5 5PIN LF DU18 1 ʳ
0430-6016-7099 IC RESET STL8110GCL300 3V SOT-23 3PIN LF U27 1 ʳ
0430-7027-3699 IC WM8776SEFT 48PIN TQFP L-F U23 1 ʳ
0430-7031-9603 IC DDR 16Mx16 NT5DS16M16CS-5T 66PIN TSOPII LF DU15 DU16 2 ʳ
0430-7035-1999 IC MT5351AG 471PIN BGA LF DU9 1 ʳ
0430-7037-4629 IC DDR 8Mx16 V58C2128164SBI5 66PIN TSOP-II LF U13 U14 2 ʳ
0430-7041-6999 IC HDMI CINEMA RECEIVER MT8293AE-L 128Pin QFP LF U19 1 ʳ
0430-7042-8999 IC SCALER MT8202AG/BD-L BGA 388PIN LF U11 1 ʳ
0430-7043-1999 IC DEMODULATOR MT5112BD LQFP 100PIN LF DU8 1 ʳ
0430-7044-1092 IC SWITCH PI3HDMI412FTZHE TQFN 42PIN LF U31 1 ʳ
0460-1005-0560 WH A2001H02-5P/A2001H02-4P 1007#24 220mm ʳ ʳ ʳ
0460-1008-0501 WH A2001H02-8P/A2001H02-4P+5P UL20276#28 795/700mm ʳ ʳ ʳ
0460-1015-0130 WH A2001-15P/5P+A2512H00-13P 1007#24 160/320+CORE ʳ ʳ ʳ
0460-1110-0070 WH A2512H00-10P/A2501H02-8P 1007#22 410mm +CORE ʳ ʳ ʳ
0460-4131-0040 WH FI-W31S/P240430 UL20276#30 340mm Core*2 ʳ ʳ ʳ
0980-0103-3060 MODULE TUNER DTVS205CH201A L-F DTU1 1 ʳ
ʳ
PART NO DESCRIPTION LOC QTY REMARK
ʳ
Chapter 12-1 Complete Parts List