Coby Hanoch

𝗔𝗦𝗛𝗟𝗜𝗡𝗚 𝗔𝗡𝗗 𝗘𝗠𝗕𝗘𝗖𝗢𝗦𝗠 𝗧𝗢 𝗔𝗖𝗖𝗘𝗟𝗘𝗥𝗔𝗧𝗘 𝗥𝗜𝗦𝗖-𝗩 𝗩𝗘𝗖𝗧𝗢𝗥 𝗤𝗘𝗠𝗨 𝗘𝗠𝗨𝗟𝗔𝗧𝗜𝗢𝗡. Ashling and our partner Embecosm are working with the RISE (RISC-V Software Ecosystem) project to optimize RISC-V vector instructions emulation for QEMU the open-source emulator. Our goal is to ensure that RISC-V vector instruction powered binaries run at rocket 🚀 🚀 🚀 speed under QEMU by mapping the RISC-V vector instructions to the best hardware equivalents on the host, leveraging up to 256-bit SIMD vectors for maximum performance. The RISC-V Software Ecosystem (RISE) Project focuses on accelerating the development of open-source software for the RISC-V architecture. See: https://riseproject.dev/ #RISCV #QEMU

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In order to have strong #ReRAM technology you need to have a very strong team of experts in multiple fields. I don't believe any company has such a strong combination of experts as Weebit Nano Ltd has, from the 13 PhDs we have in Physics and Chemistry developing the device, to the strong process team, as well as our very strong analog and digital design teams. This blog by Eran Briman explains the importance of each pillar and how the combination enables such a strong technology

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Great OFC coverage by LightCounting. TeraSignal’s Intelligent Re-Driver in CMOS is changing the power, reliability and performance calculus between DSP and LPO modules.

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🌟 𝑾𝒉𝒂𝒕 𝒊𝒔 𝒂 𝑺𝒖𝒏𝒅𝒂𝒚 𝒘𝒊𝒕𝒉𝒐𝒖𝒕 𝒂 𝒈𝒓𝒆𝒂𝒕 𝒓𝒆𝒂𝒅? Check out this insightful article on the challenges and costs of porting, the fundamental differences between CPUs and GPUs, hardware-software mismatch, and the immense demand for supercomputing power driven by AI and machine learning needs! 🌐 How NextSilicon effectively addresses these limitations and needs! Published by insideHPC 🔗 𝑹𝒆𝒂𝒅 𝑻𝒉𝒆 𝑨𝒓𝒕𝒊𝒄𝒍𝒆 𝑷𝒂𝒊𝒏 𝒐𝒇 𝑷𝒐𝒓𝒕𝒊𝒏𝒈: 𝑻𝒉𝒆 𝑳𝒊𝒎𝒊𝒕𝒂𝒕𝒊𝒐𝒏𝒔 𝒂𝒏𝒅 𝑪𝒐𝒔𝒕𝒔 𝒐𝒇 𝑮𝑷𝑼-𝑫𝒓𝒊𝒗𝒆𝒏 𝑯𝑷𝑪-𝑨𝑰 https://lnkd.in/dA4YUfXZ I’d love to hear your perspectives on navigating these challenges! #CPUs #GPUs #FPGAs #HPCHardware  #HPCSoftware  #MachineLearning #supercomputing #NextSilicon #Maverick #TechInsights #AI

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A very interesting blog by Giuseppe Piccolboni of Weebit Nano Ltd about the use of our #ReRAM for #neuromorphic applications

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The market for embedded #NVM is expanding quickly, with various technologies competing for different applications. Want to hear more? Read this article I recently posted on embedded.com. #ReRAM #semiconductor

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**Innovative CXL 3.0 Controller FPGA proven IP Core for all Small & Medium Enterprises : Redefining High-Speed Connectivity** **Comprehensive Protocol Support:**   - **CXL.io, CXL.mem, and CXL.cache:** Implements advanced protocols for seamless data transmission. **Versatile Device Compatibility:**   - **Type 1, Type 2, and Type 3 Support:** Compatible with diverse device types, enhancing system flexibility. **Next-Generation Specification Compliance:**   - **CXL 3.0:** Fully compliant with the latest specification for future-proof capabilities. **Optimized Data Transfer Efficiency:**   - **Multiple Flit Modes:** Supports 68B and 256B flit modes, optimizing data throughput. - **Latency-Optimized FLIT Mode:** Minimizes transfer delays, improving system performance. **Flexible Interface Configuration:**   - **Adaptable PIPE 6.x Specification:** Configurable interface widths (32-bit, 64-bit, 128-bit) for seamless integration. **Scalable Lane Operation:**   - **Multi-Lane Support:** Operates at x16, x8, x4, x2, and x1 lane configurations, optimizing bandwidth efficiency. **Specialized Data Handling Interfaces:**   - **Native Qbit Interface:** Specifically designed for CXL.mem and CXL.cache applications, ensuring reliable data transactions. **Enhanced Performance Features:**   - **Sync Header Bypass:** Streamlines data flow by bypassing synchronous header processing. **Power Efficiency and Reliability:**   - **Comprehensive Power Management:** Supports all low-power states for energy efficiency. - **Advanced RAS Features:** Includes Viral and Data Poisoning for enhanced system resilience. **Seamless Integration and Serviceability:**   - **Hot-Plug Capabilities:** Allows devices to be inserted or removed without interrupting operations. **Advanced Endpoint Capabilities:**   - **RCiEP (CXL 1.1 Support):** Integrates RC Integrated Endpoint functionality for versatile endpoint configurations. **Efficient Memory Coherence:**   - **Back Invalidation Request/Response:** Ensures efficient data coherence in CXL.mem operations. **Driving Innovation Forward:** Elevate your infrastructure with our CXL 3.0 Controller IP Core, ideal for high-performance computing, AI, and data-intensive applications.

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There are some 8'' LNOI samples for testing now. 🤝 #8inchLNOI LN is 300nm, SiO2 is 4.4um, Si (low resistivity) LN is 400nm, SiO2 is 4.4um, Si (low resistivity)

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Check out my new blog on using our #radhard #MCU to reconfigure #Space deployed #FPGA. Please reach out if you have interest and we can provide specific details on how to deploy

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Let's unravel the reality of EMC (Electromagnetic Compatibility) challenges! Anton Tishchenko, aka Doctor EMC, joins the Altium OnTrack podcast to expose industry norms and reveal how some companies have resigned to EMC failures as inevitable. This refreshingly candid conversation with our own Zachariah Peterson uncovers the demotivating effects of this acceptance and explores potential solutions. Don't miss this insightful discussion around simulation tools, budget constraints, and the expertise needed to navigate this critical domain. Listen now: https://bit.ly/4aTh17g #podcast #altium #industrynorms #electronicdesign

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Join Inbar Weintrob, VP Silicon Technologies at proteanTecs, at #Chipex Conference in Tel Aviv next week for a deep dive into next-generation power management solutions. The talk, "Application-Specific Power Reduction Based on Chip Telemetry," will explore the limitations of conventional Adaptive Voltage Scaling (AVS) and introduce a novel approach that leverages deep data analytics to optimize voltage reduction under any workload. This cutting-edge technology has demonstrably achieved 9%-14% power savings compared to traditional methods. Key takeaways from the talk: - Understanding the limitations of conventional AVS methods and their impact on power reduction. - Discovering how real-time telemetry of chip behavior enables optimal voltage scaling for specific workloads. - Exploring the safety mechanisms that ensure reliable operation under dynamic conditions. Looking forward to meeting you at #ChipEx2024 Kobi Dekter Shelley Lan

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Adisyn Announces Strategic Collaboration With 2D Generation to Advance AI and Semiconductor Technology. Adisyn has entered a binding collaboration with 2D Generation Ltd, a prominent international semiconductor IP business incorporated in Israel. This partnership aims to generate transformational opportunities in the AI space, leveraging Adisyn’s expertise in data centre management, managed IT services, and cybersecurity, alongside 2D Generation’s industry-leading capabilities in developing next-generation AI semiconductor solutions. Announcement Highlights: - Collaboration with leading semiconductor IP business 2D Generation to generate transformational opportunities in the AI space, leveraging AI1's learnings in data centres and cybersecurity. - 2D Generation is developing applications to enable the next generaton of high performance, energy-efficient semiconductor solutions for AI and datacentres. - 2D Generation is a founding partner in the EU's Connecting Chips Joint Undertaking Research and innovation partners include NVIDIA, IMEC, Valeo, Applied Materials, NXP and Unity. To view the full announcement click here: https://lnkd.in/gBcDrNfM #adisynltd #adisyn #ai1 | Video via TechInvest Magazine

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part 3 of the history of Meinberg includes introducing NTP in 1999 to bring millisecond-level timing to the network and introducing the IMS (intelligent modular synchronization) platfom in 2013. it's modular and hot-swappable.

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1200V 900A Hybrid module. With SiC SBD diode inside，the turn on switching loss is reduced to a very low level.

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Cadence introduces the Janus NoC for SoC designs.

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For those companies in Israel: AI represents a potentially huge leap forward for verification. A number of companies, including Breker, are now including AI algorithms in several verification solutions to expand their effectiveness.  However, this is scratching the surface of the real possibilities afforded by this technology. Breker, the test content generation leader, is expanding their use of AI in partnership with several leading semiconductor companies.  We are proposing an environment where we can easily provide scenario descriptions, control coverage, and drive execution platforms using AI generated test content. VerifyGPT is closer than you think. Come see David Kelf, Breker’s CEO, at ChipEx in Tel Aviv on May 7th, 2024 discuss the state of the art so far, what is being used for SystemVIP’s such as RISC-V and Coherency, and how we reach the inevitable reality of AI-based verification. Presentation will be from 12:20 - 12:40pm https://lnkd.in/g65VEGw3 #systemverilog #pss #uvm #systemvip #riscv #verification

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Have a look at how Cybord can help Electronic Manufacturing Companies save millions. By utilizing AI and Big Data, we are revolutionizing quality assurance in electronics manufacturing. Our Visual Deep-AI technology can analyze components, detect defects, and predict potential issues, saving companies millions and ensuring user safety. Elevate your assembly line and book a demo today!

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