Irect Emory Address AND Dma Controller: By: Vrunda Shah Vardhani Vangara Rutvi Shah Kangan Shukla

DIRECT MEMORY ADDRESS
AND 8237 DMA CONTROLLER
By:
Vrunda Shah
Vardhani Vangara
Rutvi Shah
Kangan Shukla
INTRODUCTION
 The DMA I/O technique provides direct

access to the memory while the
microprocessor is temporarily disabled.
 This chapter also explains the operation of
disk memory systems and video systems
that are often DMA-processed.
 Disk memory includes floppy, fixed, and
optical disk storage. Video systems
include digital and analog monitors.
BASIC DMA OPERATION
 Two control signals are used to request
and acknowledge a direct memory access
(DMA) transfer in the microprocessor-
based system.
 HOLD pin is an input used to request a
DMA action.
 HLDA pin is an output that
acknowledges the DMA action.
– HOLD is sampled in any clocking cycle
– when the processor recognizes the hold, it stops
executing software and enters hold cycles
– HOLD input has higher priority than INTR or
NMI
– the only microprocessor pin that has a higher
priority than a HOLD is the RESET pin
BASIC DMA DEFINITIONS
 Direct memory accesses normally occur between an
I/O device and memory without the use of the
microprocessor.
 Memory & I/O are controlled simultaneously.
 which is why the system contains separate memory and I/O
control signals
 A DMA read causes the MRDC and IOWC signals to
activate simultaneously.
 transferring data from memory to the I/O device
 A DMA write causes the MWTC and IORC signals to
both activate.
 8086/8088 require a controller or circuit such as
shown in Fig 13–2 for control bus signal generation.
 The DMA controller provides memory with its
address, and controller signal (DACK) selects the I/O
device during the transfer.
8237 PIN DEFINITIONS
 Clock input is connected to the system clock

signal as long as that signal is 5 MHz or less.
 in the 8086/8088 system, the clock must be inverted
for the proper operation of the 8237
 Chip select enables 8237 for programming.
 The CS pin is normally connected to the output of
a decoder.
 The reset pin clears the command, status,
request, and temporary registers.
 It also clears the first/last flip-flop and sets
the mask register.
 A logic 0 on the ready input causes the
8237 to enter wait states for slower
memory components.
 A hold acknowledge signals 8237 that the
microprocessor has relinquished control of
the address, data, and control buses.
 DMA request inputs are used to request a
transfer for each of the four DMA channels.
 Data bus pins are connected to the processor
data bus connections and used during the
programming of the DMA controller.
 I/O read is a bidirectional pin used during
programming and during a DMA write cycle.
 I/O write is a bidirectional pin used during
programming and during a DMA read cycle.
 End-of-process is a bidirectional signal used as
an input to terminate a DMA process or as an
output to signal the end of the DMA transfer.
 A0-A3 -These address pins select an internal
register during programming and provide part of
the DMA transfer address during a DMA action.
 HRQ- Hold request is an output that connects
to the HOLD input of the microprocessor in
order to request a DMA transfer.
 DACK0–DACK3 -DMA channel acknowledge
outputs acknowledge a channel DMA request.
These outputs are programmable as either
active-high or active-low signals.
 Address enable signal enables the DMA
address latch connected to the DB7–DB0
pins on the 8237.
 Address strobe functions as ALE, except
it is used by the DMA controller to latch
address bits A15–A8 during the DMA transfer.
 Memory read is an output that causes memory
to read data during a DMA read cycle.
 Memory write is an output that causes memory
to write data during a DMA write cycle.
 The current address register holds a 16-bit
memory address used for the DMA transfer.
 each channel has its own current address
register for this purpose.

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DIRECT MEMORY ADDRESS

AND 8237 DMA CONTROLLER

 The DMA I/O technique provides direct

 Clock input is connected to the system clock

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