Programmable Interval Timer 8253

We cannot generate time delay precisely using delay routines

PIT (programmable Interval Timer), facilitates the generation of accurate time delays
PIT used to bring down the frequency to the desired level
When PIT used as timing and delay generation peripheral, 8086 will be free the task
related to counting process and can execute the program in memory
Programmable Interval Timer 8253

8253 generates accurate time Delays & can be used for applications such as a real-
time clock,an event counter, a square wave generator, acomplex-wave generator, etc.
16-Bit Counters, each with a max. count rate of2.6MHz

Architecture of 8253
PIT 8253
8253 contains three identical 16 bit counters that can operate independently, in any one of
the 6 modes
Three counters are independent of each other in operation but they are identical in
organization
These all are 16 bit, presettable, down counters able to operate in BCD/Hexadecimal
mode.
 Each of the three counter has 3 pins associated
CLK: input clock frequency
OUT: can be square wave, or one shot
GATE: Enable (high) or disable (low) the counter

8-bit Data bus, bidirectional data buffer interfaces internal circuit of 8253 to
microprocessor system bus
Data is transmitted or received by the buffer upon the execution of IN or OUT instruction
The READ/WRITE logic controls the direction of the data buffer depending upon
whether it is a READ/WRITE operation. It has 5 signals RD, WR, CS, address lines
A1 & A2
The specialty of the 8253 counter is that they can beeasily read online without disturbing
the clock inputto the counter.
This facility is called On The Fly reading of countersand invoked by a mode control
word.

Control Word Register 8253

Control Word is selected when A0, A1 as both 1s
 Control Word accepts information from data busand stores in register(Control Word
Register)
The register controls the operation mode of eachregister, selection of Binary/BCD
counting andloading of each counting register
CWR is only write register, we cant read itscontents.

Modes of Operation
8253 can operate in any one of 6 modes
A control word must be written in the controlword register by the microprocessor to
initializeeach of the counters of 8253 to decides itsoperating mode
Gate of a counter is used to disable or enablecounting
Mode 0: Interrupt on terminal count
Mode 1: HW triggered / programmable one shot
Mode 2: Rate Generator (DividebyN counter)
Mode 3: Square wave rate generator
Mode 4: Software triggered strobe
Mode 5: Hardware triggered strobe

Mode 0 (Interrupt on terminal count)

In this mode, initially the OUT is low
Once a count is loaded in the register, thecounter is decremented every cycle &
whencount reaches zero, OUT goes high
This can be used as interrupt
The OUT remains high until a new count or acommand word is loaded

Mode 1 (HW triggered / programmable one shot (monoshot))

In this mode 8253 is used as MonostableMultivibrator
 In this mode, OUT is initially high
When GATE is triggered, OUT goes low, and atthe end of count, OUT goes high again,
thusgenerating a one-shot pulse
The duration of the quasi stable state of themonostablemultivibrator, is decided by
countloaded in count register

Mode 2 (Rate Generator (DividebyN counter))

This mode is used to generate a pulse equal tothe clock period at a given interval
When a count is loaded, the OUT stays high untilcount reaches 1 & then OUT goes low
for oneclock period
The count is reloaded automatically & pulse isgenerated continuously

Mode 3 (Square Wave Rate Generator)

In this mode, when a count is loaded, OUT is high
The count is decremented by two at every CLKcycle, & when it reaches zero OUT goes
low, &count is reloaded again
The frequency of the square wave is equal tofrequency of CLK divided by count
Mode 4 (Software Triggered Strobe)
Here the OUT is initially high
It goes low for one CLK period at end of Count
This low pulse is used as a strobe

Mode 5 (Hardware Triggered Strobe)

This mode is triggered by rising pulse at the gate
Initially, OUT is low, and when Gate pulse istriggered from low to high, count begins
At end of count, OUT goes low for one CLK period
Direct Memory Access (DMA)
Direct memory access (DMA) is a feature of moderncomputer systems that allows certain
hardwaresubsystems to read/write data to/from memory withoutmicroprocessor
intervention, allowing the processor todo other work.
Here an external device takes over the control of systembus from the CPU.
DMA is for high-speed data transfer from/to mass storage peripherals, e.g. hard disk
drive, magnetic tape, CD-ROM, and sometimes video controllers.
Typically, the CPU initiates DMA transfer, does otheroperations while the transfer is in
progress, and receivesan interrupt from the DMA controller once the operationis
complete.
Basic DMA Terminology
DMA Channel: system pathway used bya device to transfer information directlyto and
from memory.
DMA Controller: dedicated hardwareused for controlling the DMA operation.
DMA Controller 8237
8237, is capable of transferring a byte or a bulk ofdata between system memory and
peripherals ineither direction.
Memory to memory data transfer facility is alsoavailable in this peripheral.
As in the case of 8257, the 8237 also supports fourindependent DMA channels which
may beexpanded to any number by cascading morenumber of 8237.
8237 is not a discrete component in modernmicroprocessor-based systems.
It appears within many system controller chip sets
8237 is a four-channel device compatiblewith 8086/8088, adequate for small systems -
expandable to any number of DMA channel inputs
8237 is capable of DMA transfers at rates up to 1.6Mbytes per second.
Each channel is capable of addressing a full64K-byte section of memory and transfer up
to 64K byteswith a single programming
Internal Architecture of 8237

8237 contains 3 basic Blocks

The timing and control block generates the internaltimings and external control
signals.
The program command control block decodes thevarious commands given to the
8237 by the CPUbefore servicing a DMA request. It also decodes themode control
word used to select the type of theprogrammed DMA transfer.
The Priority Encoder block resolves priority betweenthe DMA channels requesting
the servicessimultaneously.
Internal Registers
Base address register: To store the initial addressfrom where data transfer will take
place
Base word count register: To store the number oftransfers to be performed
Current address register: To store the currentaddress from where data is being
transferred
Current word count register: To store the numberof transfers remaining to be
performed
Temporary address register: To hold address ofdata during memory-to-memory
transfer
Temporary word count register: To hold number of transfersto be performed in
memory-to-memory transfer
 Mode register: 8-bit register which stores the channel to beused, the operating mode,
i.e. the transfer mode, andother transfer parameters
Command register: 8-bit register which initializes thechannel to be used for data
transfer
Request register: 8-bit register used to indicate whichchannel is requesting for data
transfer
Mask register: 8-bit register used to mask a particularchannel from requesting for
DMA service
Status register: 8-bit register used to indicate whichchannel is currently under DMA
service and some otherparameters
8237 pin out
CLK: System clock 5 MHz or less
CS : Chip select enables 8237
RESET: clears the command, status, request, temporary registers & sets mask register
READY: 0 for inserting wait states for slower components
HLDA: Signals that the p has realised buses
DREQ3 DREQ0: DMA request input for each of four channel
DB7-DB0: Data Bus pins - bidirectional
IOR : Bidirectional pin; in Slave mode to read registers & in Master Mode to access data
from peripherals
IOW : Bidirectional pin; in Slave mode to load information's into 8237 & in Master
Mode used to transfer data to peripherals
EOP : End of process is a bidirectional signal used as input to terminate a DMA process
or as output to signal the end of the DMA transfer
A3-A0: Address pins for selecting internal registers
A7-A4: Outputs that provide part of the DMA transfer address
HRQ: (Hold Request)an O/P for request a DMA transfer
DACK3-DACK0: DMA acknowledge for each channel.
AEN: Address Enable Signal
ADSTB: Address strobe functions as ALE
MEMR : Memory read output used in DMA read cycle to read data
MEMW : Memory write output used in DMA write cycle to write data
Modes of 8237
The 8237 operates in four different modes,depending upon the number of bytes
transferredper cycle and number of ICs used
Single Transfer Mode
Block Transfer Mode
Demand Transfer Mode
Cascade Transfer Mode
Single - One DMA cycle, one CPU cycle interleaveduntil address counter reaches zero.
(only one byte istransferred per request)
Block - Transfer progresses until the word countreaches zero, may be due to EOP signal
goes active.(a block of data is transferred)
Demand - Transfers continue until TC or EOP goesactive or DRQ goes inactive. The
CPU is permitted touse the bus when no transfer is requested.
Cascade - Used to cascade additional DMAcontrollers. DREQ and DACK is matched
with HRQ andHLDA from the next chip to establish a priority chain.Actual bus signals is
executed by cascaded chip.
Why 8259?
If we are working with an 8086, we have a problemhere because the 8086 has only
two interrupt inputs,NMI and INTR.
If we save NMI for a power failure interrupt, this leavesonly one interrupt for all the
other applications. Forapplications where we have interrupts from multiplesource, we
use an external device called a PriorityInterrupt Controller ( PIC ) to the interrupt
signalsinto a single interrupt input on the processor.
8259
8259 Controller, takes care of a number ofsimultaneously appearing interrupts request
alongwith their types and Priority
Manage 8 interrupts according to the instructionswritten into its control registers
Mask each interrupts request individually
Setup to accepts either request level-triggered oredge triggered interrupt
Expanded to 64 priority levels by cascadingadditional 8259
Work with 8085 MP mode or 8086/8088 MP mode

Architecture 8259

Description of 8259
 Interrupt Request Register (IRR): The interrupts at IRQinput lines are handled by
Interrupt Request internally.IRR stores all the interrupt request in it in order to servethem
one by one on the priority basis.
In-Service Register (ISR): This stores all the interruptrequests those are being served,
i.e. ISR keeps a trackof the requests being served.
Interrupt Mask Register (IMR): This register stores the bitsrequired to mask the
interrupt inputs. IMR operates onIRR at the direction of the Priority Resolver.
Priority Resolver: This unit determines the priorities of the interruptrequests appearing
simultaneously. The highestpriority is selected and stored into thecorresponding bit of
ISR during INTA pulse.The IR0 has the highest priority while the IR7 has thelowest one,
normally in fixed priority mode.The priorities however may be altered byprogramming
the 8259A in rotating priority mode.
Interrupt Control Logic: This block manages theinterrupt and interrupt acknowledge
signals to be sentto the CPU for serving one of the eight interruptrequests. This also
accepts the interrupt acknowledge(INTA) signal from CPU that causes the 8259A
torelease vector address on to the data bus.
Data Bus Buffer: This tristate bidirectional bufferinterfaces internal 8259A bus to the
microprocessorsystem data bus. Control words, status and vectorinformation pass
through data buffer during read orwrite operations.
Read/Write Control Logic: This circuit accepts anddecodes commands from the CPU.
This block alsoallows the status of the 8259A to be transferred on tothe data bus.
Cascade Buffer/Comparator: This block stores andcompares the IDs all the 8259A
used in system. Thethree I/O pins CASO-2 are outputs when the 8259A isused as a
master. The same pins act as inputs whenthe 8259A is in slave mode.
Interrupt Sequence in an 8086 system
One or more IR lines are raised high that setcorresponding IRR bits.
8259A resolves priority and sends an INTsignal to CPU.
The CPU acknowledge the interrupt withINTA pulse.
Upon receiving an INTA signal from the CPU,the highest priority ISR bit is set and
thecorresponding IRR bit is reset. The 8259Adoes not drive data bus during this
period.
The 8086 will initiate a second INTA pulse.During this period 8259A releases an 8-
bitpointer on to data bus from where it is readby the CPU.
This completes the interrupt cycle.
The ISR bit is reset at the end of the secondINTA pulse if automatic end of
interrupt(AEOI) mode is programmed. Otherwise ISRbit remains set until an
appropriate EOIcommand is issued at the end of interruptsubroutine.
Pin Details
CS: This is an active-low chip select signal forenabling RD and WR operations of
8259A. INTAfunction is independent of CS.
 WR: This pin is an active-low write enable input to8259A. This enables it to accept
command wordsfrom CPU.
RD: This is an active-low read enable input to 8259A.A low on this line enables 8259A
to release status ontothe data bus of CPU.
D0-D7: These pins from a bidirectional data bus thatcarries 8-bit data either to control
word or from statusword registers. This also carries interrupt vectorinformation.
CAS0 CAS2 Cascade Lines: A signal 8259A provides eightvectored interrupts. If more
interrupts are required, the8259A is used in cascade mode. In cascade mode, amaster
8259A along with eight slaves 8259A can provideupto 64 vectored interrupt lines. These
three lines act asselect lines for addressing the slave 8259A.
SP/EN (Slave program / enable): This pin is a dual purposepin. When the chip is used in
buffered mode, it can be usedas buffered enable to control buffer transreceivers. If this
isnot used in buffered mode then the pin is used as input todistinguish master/slave PIC
whether the chip is used as amaster (SP =1) or slave (EN = 0).
INT: This pin goes high whenever a valid interruptrequest is asserted. This is used to
interrupt the CPUand is connected to the interrupt input of CPU.
IR0 IR7 (Interrupt requests): These pins act asinputs to accept interrupt request to the
CPU.
INTA ( Interrupt acknowledge ): This pin is an inputused to strobe-in 8259A interrupt
vector data on tothe data bus. In conjunction with CS, WR and RDpins, this selects the
different operations like, writingcommand words, reading status word, etc.