Static Timing Analysis

Nakkala Suresh
Two Methods:
Static Timing Analysis
Static Timing Analysis is a method for determining if
a circuit meets timing constraints without having to
simulate
Much faster than timing-driven, gate-level simulation
Proper circuit functionality is not checked
Vector generation NOT required

Dynamic Timing Analysis
Determines the full behavior of the circuit for a given
set of input stimulus vectors


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Advantages and Disadvantages
Static Timing Analysis
+ faster because it is not necessary to simulate the
logical operation of the circuit
+ checks all the possible paths

- only check the timing, not the functionality
- less accurate

Dynamic Timing Analysis
+ can check the timing and the functionality
+Very Accurate

- consumes more run time
- dependent on stimulus vectors
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When the Timing Analysis is Done?
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Logic Synthesis
Design For test
Floor planning
Constraints
(clocks, input drive,
output load)
Static Timing Analysis
Static Timing Analysis
(estimated parasitics)
Pre layout STA
Post layout STA
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Floor planning
Clock Tree Synthesis
Place and Route
Parasitic Extraction
SDF
(extracted parasitics)
Constraints
(clocks, input drive,
output load)
Static Timing Analysis
(estimated parasitics)
Static Timing Analysis
(extracted parasitics)
Static Timing Analysis
Inputs:
gate-level netlist (.db, Verilog, VHDL); delay
information in SDF format; timing constraints in
Synopsys Design Constraints (SDC) format
Verifies the design timing using information provided
in the technology library
Outputs:
Timing Report
Timing Models
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Timing Checks performed:
Setup, hold, recovery, and removal constraints
User-specified data-to-data timing constraints
Clock-gating setup and hold constraints
Minimum period and minimum pulse width for
clocks
Design rules (minimum/maximum transition time,
capacitance, and fanout)
Bus contention and floating net conditions

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Static Timing Analysis (Violation Checks)
STA engine breaks the design down into a set of
timing paths, calculates the signal
propagation delay along each path, and
checks for violations of timing constraints
inside the design and at the input/output
interface.

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Timing Paths
Each path has a startpoint and an endpoint.

The startpoint is a place in the design where data is launched by
a clock edge. The data is propagated through combinational
logic in the path and then captured at the endpoint by
another clock edge.

The startpoint of a path is a clock pin of a sequential element, or
possibly an input port of the design (because the input data
can be launched from some external source).

The endpoint of a path is a data input pin of a sequential
element, or possibly an output port of the design (because
the output data can be captured by some external sink).
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Timing Paths
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Timing paths
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Path 1 Path 2 Path 3
Path 4
Path 1 starts at an input port and ends at the data input of a sequential
element.
Path 2 starts at the clock pin of a sequential element and ends at the data
input of a sequential element.
Path 3 starts at the clock pin of a sequential element and ends at an output
port.
Path 4 starts at an input port and ends at an output port.
A combinational logic cloud might contain multiple paths. Tool
uses the longest path to calculate a maximum delay or the
shortest path to calculate a minimum delay.

Clock path (a path from a clock input port or cell pin, through
one or more buffers or inverters, to the clock pin of a
sequential element) for data setup and hold checks
Clock-gating path (a path from an input port to a clock-gating
element) for clock-gating setup and hold checks
Asynchronous path (a path from an input port to an
asynchronous set or clear pin of a sequential element) for
recovery and removal checks
Critical Path (path between an input and an output with the
maximum delay) for finding the maximum frequency
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Path Types:
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Delay Calculation
The total delay of a path is the sum of all cell and net
delays in the path
Cell Delay
Cell delay is the amount of delay from input to output
of a logic gate in a path

Net Delay
Net delay is the amount of delay from the output of a
cell to the input of the next cell in a timing path
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Constraint Checking
A setup constraint specifies how much time is
necessary for data to be available at the input of a
sequential device before the clock edge that captures
the data in the device. This constraint enforces a
maximum delay on the data path relative to the
clock path.
A hold constraint specifies how much time is
necessary for data to be stable at the input of a
sequential device after the clock edge that captures
the data in the device. This constraint enforces a
minimum delay on the data path relative to the clock
path.

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Constraint Checking
The amount of time by which a violation is
avoided is called the slack. E.g.: for a setup
constraint, if a signal must reach a cell input at
no later than 8 ns and is determined to arrive
at 5 ns, the slack is 3 ns.
A slack of 0 means that the constraint is just
barely satisfied.
A negative slack indicates a timing violation.

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Setup and Hold Checking for Flip-Flops



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STA engine assumes that signals are to be propagated
through each data path in one clock cycle.
Therefore, when it performs a setup check, it verifies
that the data path delay is small enough so that the
data launched from FF1 reaches FF2 within one clock
cycle
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Setup check: The longest possible delay along
the data path and the shortest possible delay
along the clock path between FF1 and FF2

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Hold check: The data launched from FF1 reaches FF2 no
sooner than the capture clock edge for the previous clock
cycle.
This check ensures that the data already existing at the input of
FF2 remains stable long enough after the clock edge that
captures data for the previous cycle. Tool considers the
shortest possible delay along the data path and the longest
possible delay along the clock path between FF1 and FF2. A
hold violation can occur if the clock path has a long delay

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Timing Exceptions
Paths that are not intended to operate or different.

False path A path that is never sensitized due to
the logic configuration, expected data sequence, or
operating mode.

Multicycle path A path designed to take more than
one clock cycle from launch to capture.

Minimum/maximum delay path A path that must
meet a delay constraint that you specify explicitly as
a time value.
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Critical path
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Critical path
the path which creates Longest delay is the critical path
False path
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Mux 1
C C1 C2 A
B
Mux 2
S
B1 B2
OUT
Single Cycle path
A Single-cycle path is a timing path that is
designed to take only one clock cycle for the
data to propagate from the startpoint to the
endpoint.
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Multi-cycle paths
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2 clock period delay
Multi cycle path
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Clock Skew
Clock skew is due to different delays on different
paths from the clock generator to the various
flip-flops.
Different length wires (wires have delay)
Gates (buffers) on the paths

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Clock Latency
Difference between the reference (source) clock
slew to the clock tree endpoint signal slew
values

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INV
Rise=7
Fall=4
Rise=7
Fall=4
Rise=7
Fall=4
Rise=7
Fall=4
Rise=7
Fall=4
Rise=7
Fall=4
Rise=7
Fall=4
CLK
CLKA
CLKB
CLKC
INV
INV
INV INV INV
BU
F
BU
F
Timing Analysis Example:
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Max Freq = 1/17
= 58.8 Mhz
Thank you
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