Single-Stage Three-phase Power-Factor-Correction Circuit Using Three Isolated Single-phase SEPIC Converters Operating in CCM

Rajapandian Ayyanar and Ned Mohan

Department of Electrical and Computer Engineering University of Minnesota Minneapolis, MN 55455 USA Email: raia@,ece.umn.edu, mohan@,ece.umn.edu
Abstract - A single-stage three-phase power-factorcorrection circuit is developed using three isolated single-phase SEPIC-based power-factor-correction circuits operating in continuous-current mode. This approach is found to be attractive for low to medium power applications and when stringent THD and EMI specifications have to be met, such as power supplies for avionics systems. Use of isolated single-phase circuits also avoids the problems associated with the interaction among three phases. Detailed design criteria for the power and control stages of the single-phase SEPIC power-factor-correction circuit are presented. Issues specific to the three-phase implementation, such as current sharing at the input, are discussed. Simulation and experimental results corresponding to a 500W three-phase prototype switching at l O O l c H z are reported.

Jian Sun
Rockwell Collins 400 Collins Road NE Cedar Rapids, IA 52498-3161, USA Email: [email protected]

voltage for the load. The overall efficiency of three-stage power processing is low, even if the individual stages might be very efficient. The overall power-density also suffers with this approach. As a solution to these problems, a single-stage threephase PFC converter is presented in this paper. The converter consists of three isolated single-phase PFC modules using the SEPIC converter. Analysis of the SEPIC converter as a PFC circuit is presented along with detailed design criteria for the main power components. Simulation and experimental results for a 500W prototype are reported. 11. COMPARISON OF DIFFERENT TOPOLOGIES The application considered here, namely avionics power systems, has stringent limits on each of the individual harmonic currents as well as tight restrictions on the amount of high-frequency ripple current. Also, the required power level is fairly low, typically less than one kW.. Hence complex control strategies involving digital control can not be justified. The conventional three-phase, continuous-current-mode (CCM) six-switch PWM boost or buck-type converters, while capable of meeting the harmonic distortion limits, suffer from the problem of very high switch ratings, especially in the isolated versions, and complex control [1,2]. The stringent harmonic requirements rule out the use of the family of threephase single-switch solutions [3]. Converters with discontinuous input current [4] also seem to be unattractive for the targeted applications because of their high voltage stress on switches as well as EM1 considerations. Using three single-phase PFC circuits (one per phase) is an attractive approach to three-phase rectification because single-phase PFC circuits have been well studied, documented and supported with dedicated integrated circuits from numerous vendors. Reference [5] discusses the use of three single-phase non-isolated PFC circuits for three-phase rectification. Since the three individual units are not isolated, the main problem of this approach is the interaction among the three phases which necessitates the use of additional circuit techniques such as split inductors and split freewheeling diodes. The phase interaction problem can be solved by using isolated single-phase PFC modules. The isolation also makes

I. INTRODUCTION Two major trends in switch-mode power supplies motivate the development of single-stage power-factor-correction (PFC) circuits. The first is the stringent specifications on the allowable current distortion drawn from the ac mains. The second is the need for low dc supply voltage for digital integrated circuits which is projected to be as low as 0.5V in a few years from now. Single-stage PFC circuits by definition draw near sinusoidal currents and provide well regulated output voltage with galvanic isolation between the input ac and the output dc voltages. Single-switch non-isolated boost converter is a popular topology for single-phase power-factor correction, while the six-switch PWM boost converter is a standard solution for A drawback Of nonthree-phase isolated boost topologies is that their output voltage is higher than the peak of the input ac voltage. Buck-derived topologies do not suffer from this problem, but the output voltage still needs to be above approximately 200V if the switch ratings are not to be compromised. It is commonly believed that converting a high dc voltage (e.g. 200V) to a low dc voltage (e.g. 1.5V) is inefficient mainly because of the large transformer turns-ratio. Hence most dstributed powersystems using three-phase ac inputs involve three stages of power processing: 1) a PFC pre-regulator that converts the three-phase ac to non-isolated, high voltage dc (above 200V), 2) an isolated dc-dc converter that converts the high voltage DC to a low, intermediate dc bus voltage and 3) a point-ofload dc-dc converter that generates the required low supply
This work was sponsored by Rockwell Collins through a research

contract
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it possible to convert three-phase ac power to a medium dc voltage in a single stage (without using an additional dc/dc converter which would be needed when non-isolated topologies are used). Unfortunately, the conventional isolated version of the boost converter is not ideally suited for this application because of its high voltage stress on power devices in CCM and high input current distortion in DCM. Reference [6] discusses the use of three single-phase flybackbased PFC converters for three-phase applications. The main drawback of this flyback-based approach is the discontinuous currents drawn from the input which necessitates the use of large EM1 filters. In this paper, use of three isolated SEPIC converters for three-phase PFC applications is analyzed. The SEPIC converter resembles the boost converter at its input side, hence has the same features as the boost converter in terms of low input current distortion and smaller EM1 filter. At the output side, the SEPIC converter is similar to a flyback converter where isolation is achieved without the penalty of increased voltage rating as in the case of isolated boost. It shall be pointed out that a basic analysis and design of isolated SEPIC converters for three-phase PFC applications has been presented in [ 7 ] . 111. DESCRIPTION OF THE CHOSEN CONFIGURATION The schematic diagram of the proposed approach is shown in Fig. 1. The three single-phase SEPIC-based PFC modules are connected in delta at the input side (wye connection is

possible too, with or without the neutral), and in parallel at the output side. The converters operate in the continuous conduction mode. The current drawn by each of the individual converters is controlled to be in phase with its own input voltage (i.e, line to line voltage) by duty-ratio modulation. The control technique involves an independent, large-bandwidth, inner current loop (average current mode control) for each of the three phases, and a common outer voltage loop. The current reference for the inner current loop is obtained from the individual input voltages (rectified) and suitably scaled by the output of the common voltage controller.
As far as the individual modules are concerned, the operation is identical to that of a single-phase PFC circuit. Hence we need to consider only the single-phase operation for analysis. (Issues specific to the three-phase connection are discussed in Section V.) Since the switching frequency (1OOkHz) is much higher than the line frequency (60% or 400Hz), the converter can be analyzed using the quasisteady-state approximation [ 7 ] . Quasi-steady-state basically means that each line cycle is made up of a sequence of steady-state conditions, each corresponding to a different instantaneous value of the input voltage. This allows us to replace the PWM switch by its equivalent ideal transformer model [8] as shown in Fig. 2. This average model can be used (I) to obtain the frequency response plots for various transfer functions for designing closed-loop controllers and (2), to analyze the line-frequency behavior of various components.

Fig. 1. Schemataic diagram of the three-phase PFC using three single-phase SEPIC converters.

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The operation of the converter can be better understood by studying the various waveforms obtained through simulation of both the actual switching model and the averaged model shown in Fig. 2. Figure 3 shows the various waveforms corresponding to the switching model as well as the average model. The current through the input-side inductor tracks the rectified input voltage, due to the controller action. The voltage across the coupling capacitor CC,just as in a DC-DC converter, follows the input voltage, which in this case is a rectified sinusoidal voltage, as shown in Fig. 3a. The current through the capacitor is proportional to the derivative of the above voltage and is shown in Fig. 3b for both the switching model and the average model. The amplitude of the line frequency component of the capacitor current is given by vc-,pk 2nf;,, c , . This amplitude is independent of the load current and is negligibly small compared to the reflected load current.

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Figure 3c shows the current through the output diode. As seen from the average model, the diode current has a dc component equal to the load current and a large ac component at twice the line frequency. The low-frequency component of the diode current is given by (1). ZDo =-

(d) Duty-ratio (control voltage for the switching model) over a line frequency cycle Fig. 3. Switching and average waveforms of various parameters

Design criteriafor the power stage components

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2vo The reflected load current on the primary side has identical waveform as that of the diode current, but scaled by the transformer turns-ratio. Since the line frequency component of the capacitor (CC) current is very small, the current through Lz, which is actually the magnetizing current of the transformer, is nearly the same as the diode current reflected to the primary side. Fig. 3d shows the instantaneous dutyratios over a line-frequency cycle, and is close to that given by (2).

The choice of the transformer turns-ratio is a trade-off between various parameters like the voltage and current ratings of the switch and diodes, transformer losses, etc. Higher turns-ratio (meaning larger secondary voltage) results in lower switch voltage rating, but higher peak and RMS current rating. Higher turns-ratio also results in higher voltage rating for the output diodes. In the prototype the choice of turns-ratio was based mainly on limiting the switch voltage stress to less than 500V. The design of the input inductor and the primary inductance of the transformer is a compromise between performance and size. Large value of inductance especially for the transformer results in smaller current ripple and reduced core loss. It also results in CCM operation over a wider range of input voltage, which results in lower input

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current distortion. These advantages however are at the cost of increased inductor and transformer size and their conduction losses. One way to determine suitable inductance values would be to select e,,, such that CCM operation is < 8 < K -ecrit at the minimum expected ensured for load. The condition for ensuring CCM above e,,, is given in [7,9] and is repeated in (3).

transfer function has a pole at the origin, a pair of undamped complex poles and a pair of complex zeroes. The location of both the poles and the zeroes depend on the instantaneous duty-ratio, and hence keep varying over a line period. Also, Lz for practical values of L1, and C,, the pole pair occurs at a lower frequency than the complex zero pair, thus introducing a large, sudden phase-lag. The actual frequency response of TL I d are obtained by PSPICE simulation of the low-frequency average model in Fig. 2. The results are shown in Fig. 4 for various values of input voltage (ranging from 5OV to 300V). Operation in CCM is assumed in obtaining these plots. The steady state duty-ratio for each value of input voltage is obtained using (2). The plots correspond to the specifications and component values used in the prototype which are given in Section VI. Note the large phase-lag near the 8 to lOlCHz range due to the complex poles - the phase overshoots beyond the 180 point. Also, unlike the boost PFC where the gain becomes independent of the instantaneous input voltage at higher frequencies, the SEPIC has a loop gain that varies significantly with input voltage even at high frequencies. Use of R-C damping network across the coupling capacitor Cc is suggested in [7] in order to better shape the loop gain and to avoid the phase excursion below the -180 point. The choice of the values of the RC network is a compromise between improvement in the phase plot of the current loop transfer function and the losses in the damping network. In the present work, a combination of above mentioned R-C damping network and a modified compensation structure (instead of just a P-I controller)

where, Leq = * , n -turns-ratio LI +L2 M = -, Vg -peak input voltage Y,

RL - maximum load resistance, T, -switching period

The input side inductor L1 is chosen based on the maximum allowable high-frequency ripple in the input current, and Lz is then selected using (3). The value of coupling capacitance needs to satisfy two restrictions - it should be high enough such that the highfrequency ripple is fairly low, and it should be low enough such that the capacitor voltage can follow the line-frequency input voltage. Very low value for the coupling capacitor results in increased voltage stress across the main switch. IV. CONTROLLER DESIGN The transfer function from duty-ratio to the inductor current is given in [7] using the small-signal average model and with
the assumption of very large output filter capacitor. The

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Fig. 7. Simulated input line current and its spectrum corresponding to single-phase operation.
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Fig. 6. Structure of the compensator for the current loop

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shown in Fig. 6, is used to obtain sufficient phase margin without suffering from high power loss in the damping network. The compensator involves a pole at the origin, two zeroes before the worst-case complex poles and two more poles to be placed at higher frequencies to ensure fast gain roll-off at high frequencies. The overall loop gain with the RC damping network and the compensator included, is shown in Fig. 5. As seen, there is sufficient phase margin under all operating conditions. Fig. 7 shows the simulated (PSPICE) input current waveform and its spectrum corresponding to single-phase operation obtained using the above mentioned control scheme.

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Fig. 8. Simulated line current and spectrum corresponding t three-phase operation. o

W. EWERIMENTAL RESULTS
The specifications of the prototype are as follows. 200Vrms, line to line, 3-phase, 60Hz Input voltage Output voltage 28V DC, isolated Max. load 500W (170W/phase) Switching frequency 1OOkHz Each phase module is controlled by using a Unitrode UC3854A integrated PFC control chip. No elaborate EM1 filters were included, except for 0.15pF capacitors at the input of each module. Fig. 9 shows the input voltage and line current corresponding to single-phase operation, at different load conditions. Fig. 10 shows the line currents at full-load corresponding to three-phase operation. The THD at full-load for both the single-phase and the three-phase operation are less than 5%. Fig. 11 compares the output voltages corresponding to the single-phase and three-phase operation. The low-frequency ripple (120Hz) in the output voltage at full-load for the single-phase case is about 7V pk-pk, where as it is negligible for the three-phase operation. The measured efficiency of the converter at full-load is 85%. The major losses are the core and winding losses in the transformer, conduction losses of output diodes and switching and conduction losses of the MOSFETs.

v. ISSUES RELATED TO THREE PHASE IMPLEMENTATION

Fig. 8 shows the simulated line current waveform and its spectrum corresponding to three-phase operation with the three single-phase modules connected in delta at the input. As seen, the triplen harmonics that are present in the singlephase currents (Fig. 7) are totally eliminated. The single-phase PFC converters result in large ripple in the output voltage at twice the line frequency. Hence, in order to prevent this large ripple from affecting the reference of the inner current loop, the bandwidth of the outer voltage loop is made extremely small. With three-phase operation under balanced conditions, there is no low-frequency ripple in the output voltage. Hence, the outer voltage loop can be designed for higher bandwidth, resulting in faster dynamic response.
As mentioned earlier, the outer voltage loop is common to all the three phases, and the output of the voltage loop scales the current reference for the individual phases. Since the output voltage is isolated, the feedback signal (scaling factor) from the output voltage loop has to pass through an isolation barrier - either magnetic or opto-isolation. In order to ensure identical current sharing among the three phases, both at the input as well as at the output sides, it is essential that this scaling factor is the same for all the phases. Best results are obtained when all the compensation for the voltage loop is done at the secondary side and the error signal is passed to the primary side of the individual phases using closely matched opto-isolators.

V. I CONCLUSIONS
Use of three isolated CCM SEPIC converters for single-stage three-phase ac/dc conversion is analyzed in this paper. The three single-phase modules are connected in delta at the input and i parallel at the output. The individual modules have n

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Fig. 9. Experimental line currents corresponding to single-phase operation. (a) full-load, (b) 10% load.

Fig. 10. Three-phase line currents at full-load

independent average-mode current controllers driven by a common outer voltage loop. The proposed approach is found to be suitable for low to medium power systems and when stringent THD and EM1 specifications are to be met. The switch VA ratings as well as the ratings of passive components are less than those in other approaches with comparable performance. Another important advantage of the proposed approach is its simple control which can be identical to that commonly used for singlephase PFC circuits. Design criteria for the power stage as well as the controller stage are discussed in detail. Simulation and experimental results from a 500W prototype switching at 1OOkHz confirm the expected features of the proposed approach.

[5]

[6]

[7]

[8]

[9]

G. Spiazzi, F.C.Lee, "Implementation of Single-phase Boost Power Factor Correction Circuits in Three-phase Applications", Proceedings o IECON'94, pp. 250-255 f M.J.Kocher, R.L.Steigerwa1, 'An ac-dc converter with high quality input waveform", IEEE Trans. on Indusm'al Applications 1983., IA19(4), ~ ~ 5 8 6 - 5 9 9 . G. Spiazzi, P.Mattavelli, "Design criteria for power factor preregulators based on SEPIC and Cuk converters in CCM", f Proceedings o IAS'94, pp. 1084-1088. V.Vorperian, "Simplified analysis of PWM converters using the model of the PWM switch Part I and 11" , IEEE Trans. on Aerospace and Elect. Systems, 1990, pp. 490-505. D.S.L.Simonetti, JSebastian et al., "Design criteria for SEPIC and Cuk converters as powerfactor preregulators in discontinuous f conduction mode", Proceedings o IECON'92, pp.283 - 288.

IREFERENCES S.Manias and P.D. Ziogas, "A novel sine wave ac to dc converter with high frequency transformer isolation," IEEE Trans. on Ind. Electron, NOV.1985, pp 430-438. S. Manias et al, "A 3 phase inductor fed SMR converter with high frequency isolation, high power density and improved power factor," IEEE PESC 1987, pp. 253-263. E. Ismail and R.W.Erickson, "A single transistor t h e phase resonant switch for high quality rectification" PESC'92, pp. 1341 - 1351. J.W. Kolar et al., "A novel three-phase single switch discontinuousmode ac-dc buck-boost converter with high quality input current waveform" IEEE Trans. on Power Electonics, 1994, PE-9, pp. 160172.

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