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    Ratioed Logic

    Uploaded by

    manansakhiya3112

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Ratioed Logic

    Uploaded by

    manansakhiya3112
    1 views9 pages

    Copyright

    © © All Rights Reserved

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    PDF, TXT or read online from Scribd

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    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    1 views9 pages

    Ratioed Logic

    Uploaded by

    manansakhiya3112

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 9

    Ratioed Logic

    1
    © Digital
    EE141 Integrated Circuits2nd Combinational Circuits
    Ratioed Logic

    VDD VDD VDD

    Resistive Depletion PMOS


    Load RL Load VT < 0 Load
    VSS
    F F F
    In1 In1 In1
    In2 PDN In2 PDN In2 PDN
    In3 In3 In3

    VSS VSS VSS


    (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

    Goal: to reduce the number of devices over complementary CMOS

    2
    © Digital
    EE141 Integrated Circuits2nd Combinational Circuits
    Ratioed Logic
    VDD

    • N transistors + Load
    Resistive
    Load • VOH = V DD
    RL

    • VOL = RPN
    F RPN + RL

    In1 • Assymetrical response


    In2 PDN
    In3 • Static power consumption

    • tpL= 0.69 RLCL


    VSS

    3
    © Digital
    EE141 Integrated Circuits2nd Combinational Circuits
    Active Loads
    VDD VDD

    Depletion PMOS
    Load VT < 0 Load
    VSS
    F F
    In1 In1
    In2 PDN In2 PDN
    In3 In3

    VSS VSS

    depletion load NMOS pseudo-NMOS

    4
    © Digital
    EE141 Integrated Circuits2nd Combinational Circuits
    Pseudo-NMOS

    VDD

    F
    CL
    A B C D

    VOH = VDD (similar to complementary CMOS)

    V OL 2 kp
      2
    k n  VDD – V Tn  V OL – -------------  = ------  V DD – VTp 
     2  2

    kp
    V OL =  VDD – V T  1 – 1 – ------ (assuming that V T = V Tn = VTp )
    kn

    SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!


    5
    © Digital
    EE141 Integrated Circuits2nd Combinational Circuits
    Pseudo-NMOS VTC

    3.0

    2.5

    2.0 W/Lp = 4

    1.5
    Vout [V]

    W/Lp = 2
    1.0

    W/Lp = 0.5 W/Lp = 1


    0.5

    W/Lp = 0.25
    0.0
    0.0 0.5 1.0 1.5 2.0 2.5
    Vin [V]

    6
    © Digital
    EE141 Integrated Circuits2nd Combinational Circuits
    Improved Loads
    VDD VDD

    M1 M2

    Out Out

    A
    A PDN1 PDN2
    B
    B

    VSS VSS

    Differential Cascode Voltage Switch Logic (DCVSL)

    7
    © Digital
    EE141 Integrated Circuits2nd Combinational Circuits
    DCVSL Example

    Out

    Out

    B B B B

    A A

    XOR-NXOR gate
    8
    © Digital
    EE141 Integrated Circuits2nd Combinational Circuits
    Try 3 input or 4 input XOR using DCVSL Logic

    9
    © Digital
    EE141 Integrated Circuits2nd Combinational Circuits

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