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    EC6201D-Digital Integrated Circuit Design Dhanaraj K. J. Assistant Professor ECED, NIT Calicut

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    Soutik Dey

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    EC6201D-Digital Integrated Circuit Design Dhanaraj K. J. Assistant Professor ECED, NIT Calicut

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    Soutik Dey
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    L6

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    5 views13 pages

    EC6201D-Digital Integrated Circuit Design Dhanaraj K. J. Assistant Professor ECED, NIT Calicut

    Uploaded by

    Soutik Dey

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 13

    EC6201D- Digital Integrated Circuit Design

    Dhanaraj K. J.
    Assistant Professor
    ECED, NIT Calicut

    1
     In reality the drain current will not abruptly drop to zero when VGS is
    reduced to VTH. There is still some more drain conduction below
    threshold and this is known as subthreshold conduction.

     This current is due to the weak inversion in the channel between flat
    band and threshold. Ie band-bending between zero and 2F. Ie the
    transition from “on” to “off” condition is not abrupt but gradual.
    2
     For VGS<VT, the current actually decays in an exponential fashion
    similar to the operation of a BJT. In the absence of a conducting
    channel, the n+(source)-p(bulk)-n+(drain) actually from a parasitic BJT.
    The current can be approximated as
     qVGS 
        DS  
     qV 

    ID  ISe  mkT  1  e  kT  
     
     
    2  qV 
         T 
    I S   nCox  m  1  e  mkT 
    W kT
    L  q 

    C  Cit Cd depletion capacitance


    m  1 d Cit interface state capacitance due to
    Cox interface states at the Si-SiO2 interface

    3
     The slope of log10(ID) Vs VGS is called
    Subthreshold swing.
     The reciprocal of this slope is called
    Subthreshold slope (S).

    2.3mkT
    S
    q

    Typical value is 70mV/decade at room temperature

     A small value of S means a small change in the input bias can


    modulate the output current considerably

    4
    VGS  V T
    |V GS|
    Ron
    S D

    5
    Consider a capacitor discharging from VDD to
    VDD/2 through an NMOST

    One approach is to average the resistance


    considering the average of the resistance values
    at the end points of transition

    Ron  Ron (t1 )  Ron (t 2 )


    1

    1
    Ron (VDD )  Ron (VDD / 2)
    2 2
    1 VDD VDD / 2 
      '  ' 
    2  I Dsat 1  VDD  I Dsat 1  VDD / 2
    3 VDD  5 
    Ron  '
    4 I Dsat 1  6 VDD 
    6
    Another approach is to average the resistance in the
    entire region of operation
    If VDD/2>VDSAT, then the complete region
    of operation is the saturation region
    W  
    2
     VGS  VT VDSAT 
    VDSAT
    I D  I Dsat
    '
    1  VDS  '
    I Dsat   nCox  
    L  2 
    VDD / 2
    1 V
    Ron 
     VDD / 2 
    VDD
    I Dsat 1  V 
    '
    dV

    1 VDD / 2
    2  1 x 2 x3

     2VDD I Dsat
    ' 
    1 VDD
    1  du
     u
    ln1  x   x    ....
    2 3

    3 VDD  7 
    Ron  '
    1   V
     9 DD 
    4 I Dsat
    7
     Same as NOT gate

    Truth Table

    V+ and V-  supply rails


    VH and VL  high and low logic
    levels at the output
    Voltage Transfer Characteristic (VTC)
    8
    Vout

    V f VOH = f(VOL)
    OH VOL = f(VOH)
    Vout=Vin
    VM = f(VM)

    VM Switching Threshold

    V OL

    V OL V Vin
    OH

    Nominal Voltage Levels

    9
    Noise
    margin high
    “ 1” V
    OH
    NMH
    V V
    out IH
    V
    OH
    Undefined
    Region
    Noise
    margin low
    V
    IL
    NML
    “ 0” V
    OL

    V
    OL
    V
    IL
    V
    IH
    V
    in
    NM H  VO H  VI H
    NM L  VI L  VO L
    10
    VIL Maximum input voltage which can be interpreted as logic 0
    VIH Minimum input voltage which can be interpreted as logic 1

    Vout These two critical voltage points are defined as the points on the VTC where
    dVout
     1
    V Slope = -1 dVin
    OH
    Vout  f (Vin )
    If the output voltage deviated from its nominal value
    due to a small perturbation Vnoise,
    Slope = -1
    V
    OL V 'out  f (Vin  Vnoise )
    V V V
    IL IH df (Vin )
    in
     f (Vin )  Vnoise  H .O.T .
    Hence the valid regions are defined dVin
    such that in those regions noise dVout
    amplification wont happen.
     f (Vin )  Vnoise
    dVin
    11
    V DD
    V DD Vin-logic Vout-logic

    RL 0 VDD
    RL VDD VDD-IDRL

    V out
    V out

    V in
    V in

    Vin-logic Vout-logic

    0 1
    1 0 12
    13

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