LECTURE 15

Processor Design
Fundamental Concepts
Primary functions of processor:
• Execute sequence of instructions stored in
main memory
• Main memory is external to CPU so
instructions must be fetched first before they
can be executed
Sequence of operations involved in executing
an instruction constitute an instruction cycle
Memory-Processor Organization
Instruction cycle
An instruction cycle has two major phases:
• Fetch cycle - fetching the instruction from
main memory
• Execution cycle:
- Decoding the instruction
- Fetching the required operands
- Performing the required operation specified
by the operation code(opcode)
Instruction cycle
• An instruction cycle is defined by a sequence
of micro operations each of which involve
register operation
• Time required for the shortest defined CPU
micro operation is defined by CPU cycle time
• The reciprocal of CPU cycle time is CPU clock
rate measured in mega herts
Program execution
Program is executed as follows:
1. Processor fetches one instruction from memory
and performs the operation specified by the
operation code
2. Instructions are fetched from successive
memory locations until a jump or branch
instruction is encountered
3. Processor keeps track of the next address of
memory location of the next instruction to be
fetched using the program counter(PC)
Program execution steps
4.The contents of program counter (PC) are
updated to point to the address of the
memory location of the next instruction
in the sequence
5. A branch instruction may load a different
value into the PC
Instruction register(IR)
• The instruction register (IR) is one of the most
important registers in the CPU
• Instructions are fetched from main memory
into this register
Assume that each instruction is made up of 4
bytes and is stored in one word memory.
To execute an instruction the processor has to
perform the following steps:
Executing an instruction
1.Processor fetches the contents of memory
location pointed to by the PC and load them
into the instruction register (IR):
IR← PC
2.Assume memory is byte addressable,
increment contents of the PC by 4:
PC ← PC + 4
3.Carry out operation specified by instruction in
IR
Cases of instructions occupying more
than one word
If instruction occupies more than one word then
Steps 2 and 3 must be repeated as many times
as necessary to fetch the complete instruction
The diagram below shows the fetch and execute
cycles
Fetch and execute cycles
Basic CPU organization
Most CPU designs are based on two premises:
1. CPU must be as fast(measured by its cycle
time) as available technology permits. As cost
invariably increases with speed, the number
of components in the CPU must be relatively
small
2. Main memory of relatively relatively large
capacity is needed to store programs and
data required by the CPU.
Program execution by the CPU
1. Fetch required operands (instructions
and operational data) from main memory
to CPU registers
2. Compute the desired results in the CPU
3. Transfer the results from CPU to main
memory
Fetching a word from memory
To fetch a word from memory, the processor does
the following:
1.Processor has to specify the address of memory
location where the word is stored and requests a
Read operation
2. The processor transfers the required address to
the MAR whose outputs are connected to the
address lines of the memory bus and at the same
time issues a Read operation to memory
MDR register
The required data received from memory are
stored in the MDR from where they are
transferred to other registers.
The MDR register has four control signals:
MDRin
MDRout
MDRinE
MDRoutE
MDR register (Diagram)
MDR control lines
MDRin - Controls control connection to the
internal bus and is used to transfer data from
the processor registers to the MDR
MDRout - Is used to transfer data from the MDR
to the processor registers
MDRinE - Is used to transfer data from main
memory into the MDR
MDRoutE Is used to transfer data from the MDR
register to main memory
Memory Read and Write operations
• During these operations timing of internal
processor operations must be coordinated with
the response of the addressed device on memory
bus
• Processor completes one internal data transfer in
one clock cycle. Speed of the addressed device
varies with the device.
• The processor waits until it receives an indication
that the requested Read operation has been
completed
Memory Function completed(MFC)
The MFC signal is used to indicate to the
processor that the assigned operation has
been completed.
Example of a Read operation
Consider the instruction: Move (R1), R2
Actions needed to execute the read
instruction: Move (R1), R2
1. MAR ← [R1]
2. Start Read operation on the bus
3. Wait for MFC response from memory
4. Load MDR from the memory bus
5. R2 ← [MDR]
These actions can be carried out as separate
steps but some can be combined.
• Each action can be completed in one clock
cycle except 3 which requires one or more
clock cycles depending on the speed of the
addressed device.
See the timing diagram below for Read
operation in a processor
Read operation timing diagram
Writing Word into a memory location
Storing a Word in Memory
Writing a word into a memory location follows a similar
procedure as reading a word
• The desired address is loaded into MAR.
• The data to be written are loaded into MDR
• A Write command is issued.
Hence, executing the instruction Move R2,(R 1) requires
the following sequence:
1. R1out, MARin,
2. R2out, MDRin, Write
3. MDRoutE, WMFC
Write operation
As in the case of the read operation,
the Write control signal causes the memory bus
interface hardware to issue a Write command
on the memory bus.
The processor remains in step 3 until the
memory operation is completed and an MFC
response is received.
Execution of a Complete Instruction
A complete instruction has the following
operations/ commands:
1. Fetch operation
2. Fetching operands(Operational data)
3. Arithmetic or logic operation
4. Write/store operation
Consider the instruction:
Add (R3),R1
This instruction adds the contents of a memory
location pointed to by R3 to register R1.
Executing this instruction requires the
following actions:
1. Fetch the instruction.
2. Fetch the first operand (the contents of the
memory location pointed to by R3).
3. Perform the addition.
4. Load the result into R1.
Sequence of micro operations to
execute a complete instruction
Diagram showing single organization
of the data path inside a processer
Complete instruction executes
proceeds as follows:
Step 1: instruction fetch initiated by loading
contents of the PC into MAR and sending a
Read request to memory.
Select signal is set to 4 and the MUX selects
constant 4. Constant 4 is added to the
operand at input B(which is the contents of
the PC) and result stored in register Z
Complete instruction execution(Cont)
Step 2
Updated value of PC is moved from Z back to PC,
while waiting for memory response.
Step 3
The word fetched from memory is loaded in the
IR and this marks the end of the Fetch phase
Complete instruction execution(cont)
Step 4
Instruction decoding circuit interprets contents
of IR and this enables the control circuits to
activate the control signals of the execution
phase.
The contents of R3 are transferred to the MAR
and a memory read operation is initiated.
Complete instruction execution(cont)
Step 5
The contents of R1 are transferred to register Y
to prepare for the addition operation.
When the read operation is completed, the
memory operand is available in register MDR
Step 6
The addition operation is performed. The
contents of MDR are gated to the Bus and also
to the B input of ALU.
Execution of a complete instruction
Register Y is selected as the second input to the
ALU by choosing select Y.
Step 7
The sum(result of addition operation) is stored
in register Z and then transferred to R1.
The End signal causes a new instruction Fetch
cycle by returning to step 1.