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    Module 11 Fetch Decode Execute Cycle V1

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    JASPER PAYAPAYA
    The document describes the fetch-decode-execute cycle of a microprocessor, where the program counter fetches instructions from memory one at a time, sending the address to the memory address register and loading the instruction into the instruction register to be decoded and executed. It explains how data is fetched from memory using addresses and transferred to and from registers like the memory data register. The connections between the processor and main memory involve registers like the program counter, memory address register, and memory data register that control fetching instructions and data from memory.

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    Module 11 Fetch Decode Execute Cycle V1

    Uploaded by

    JASPER PAYAPAYA
    95 views16 pages
    The document describes the fetch-decode-execute cycle of a microprocessor, where the program counter fetches instructions from memory one at a time, sending the address to the memory address register and loading the instruction into the instruction register to be decoded and executed. It explains how data is fetched from memory using addresses and transferred to and from registers like the memory data register. The connections between the processor and main memory involve registers like the program counter, memory address register, and memory data register that control fetching instructions and data from memory.

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    The document describes the fetch-decode-execute cycle of a microprocessor, where the program counter fetches instructions from memory one at a time, sending the address to the memory address register and loading the instruction into the instruction register to be decoded and executed. It explains how data is fetched from memory using addresses and transferred to and from registers like the memory data register. The connections between the processor and main memory involve registers like the program counter, memory address register, and memory data register that control fetching instructions and data from memory.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    95 views16 pages

    Module 11 Fetch Decode Execute Cycle V1

    Uploaded by

    JASPER PAYAPAYA
    The document describes the fetch-decode-execute cycle of a microprocessor, where the program counter fetches instructions from memory one at a time, sending the address to the memory address register and loading the instruction into the instruction register to be decoded and executed. It explains how data is fetched from memory using addresses and transferred to and from registers like the memory data register. The connections between the processor and main memory involve registers like the program counter, memory address register, and memory data register that control fetching instructions and data from memory.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 16

    Microprocessors

    Module 11
    Fetch decode execute
    cycle
    1. Orient the students on the fetch-decode-execute cycle
    of a microprocessor.
    2. Orient the students on how addresses are decoded.
    Von Neumann architecture means that programs
    (together with data) are stored in main memory during
    execution.

    also known as the Stored Program Architecture or the


    Fetch-Decode-Execute Architecture.
    Example of a typical assembly language instruction:
    ADD R0, LOCA
    The given instruction requires the performance of
    several steps:
    1. The instruction must be transferred or fetched from
    the MM into the CPU.
    2. The operand at LOCA must be fetched and added to
    the contents of R0.
    3. The resultant sum is stored in register R0.
    In order to fetch/read an instruction or data from main
    memory:
    1. The CPU first sends the address of the memory
    location to be read.
    2. The CPU then issues or sends the read signal to the
    memory.
    3. The word is then read out of memory and is loaded
    into a CPU internal register.
    4. end operation
    In order to store/write data into main memory:
    1. The CPU first sends the address of the memory
    location to be written.
    2. The CPU sends the data or word to be written to
    memory.
    3. Then the CPU then sends the write signal.
    4. end operation
    Connection
    s between
    the
    processor
    and the
    main
    memory:
    Connection
    s between
    the
    processor
    and the
    main
    memory:
    The PC (Program Counter) contains the memory address
    of the instruction to be executed. During execution, the
    contents of the PC are updated to point to the next
    instruction.

    The MAR (Memory Address Register) holds the address


    of the location to or from which data are to be
    transferred.
    The MDR (Memory Data Register) contains the data to be
    written or read out of the addressed location.

    The IR (Instruction Register) contains the instruction that


    is being executed.
    Operating Steps:
    1. PC is set to point to the first instruction of the
    program (the operating system loads the memory
    address of the first instruction).
    2. The contents of the PC are transferred to the MAR
    (which are automatically transmitted to the MM) and a
    Read signal is sent to the MM.
    3. The addressed word is read out of MM and loaded into
    the MDR.
    4. The contents of MDR are transferred to the IR. The
    instruction is ready to be decoded and executed.
    5. During execution, the contents of the PC are
    incremented or updated to point to the next instruction.
    If operand or data needed by the instruction resides in
    MM:
    • 1. It will have to be fetched by sending its address to the MAR and initiating a
    read cycle.
    • 2. When the operand has been read from MM into the MDR, it may be
    transferred from the MDR to the ALU
    • If result is to be stored in MM:
    • 1. The result is sent to the MDR.
    • 2. The address of the location where the result is to be stored is sent to the
    MAR and a write cycle is initiated.
    S. Mathur(2016), Microprocessor and Microcontrollers,
    PHI Learning and Private Limited
    Taylor and Francis Group. Essentials of Computer
    Architecture. CRC Press, Comer, D. (2017).
    Jones and Bartlett Learning, Computer Organization And
    Architecture (10th Ed.), Stallings, (2016)

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