Assignment 2011

EEN3096 ASSIGNMENT DESIGN AND BUILD A PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER Introduction The objective of this group assignment
is to design and build a phase-locked loop (PLL) frequency synthesizer using a PLL integrated circuit (IC) such as 74HC4046. The minimum required synthesizers specifications are as follows. Frequency range: up to 10 MHz or better Output voltage range: 0 to 5 V The final prototype should be in the form of printed circuit board (PCB) at least. Other specifications are at students discretions. A technical report is to be submitted together with the prototype. The report should contain but not limited to discussions on the theory, the design, and the evaluation, of the prototype. Getting started Students may form a team of 5 members, better from the same tutorial group. We are not responsible to find you a group, so find it yourself as early as you can. Works are expected to start right from day 1 of the trimester. Because PLL lectures are given only in the later part of the trimester, students are expected to do prior readings on PLL and related topics. Laboratory experiment CE2: Design of PLL will strengthen your knowledge about PLL. A brief outline of the assignment tasks is given below. 1. Form team (select a group leader), read on PLL and related topics. Write a (<12) pages proposal with content: Cover page include your Project title and Group member name with student ID, Email and Telephone number Introduction (Literature review on what is PLL? what is Frequency synthesizer? what is the function of frequency synthesizer? what is the main component use to construct frequency synthesizer? The application of frequency synthesizer?) Methodology (How are you going to start the project? What is the subtasks (step 2-6 below in details) assigned to group members (who is doing what?) , Gunn Chart-time line estimation) Expected Outcome (Budget estimation and what outcome will you get? (A frequency synthesizer with features..) References Proposal due date submission: 13 Nov, 2011 (Fri) before 12pm to Mr. Wong Wai Kit at R2/007 FET Building. Late submit for 1 working day minus 5 marks
2. Design the prototype, which includes functional design, system level design, and circuit design. 3. Implement the design. 4. Test the prototype functionality. 5. Package the final prototype. 6. Evaluate the prototype performance. 7. Write final report. Electronics components can be purchased from local electronic shops. Larger ones include www.icmaster.com.my, my.farnell.com or www.rsmalaysia.com. Expenses are to be shared out among team members. It is at students discretion if they were to spend time searching for cheap components or to spend more. Submission Students are to demo the final prototype and submit a technical report to Mr. Wong Wai Kit at R2/007 FET Building before Monday 9 January 2012 5.00pm. Late submit for 1 working day minus 5 marks Final technical report guideline: Cover page include your Project title and Group member name with student ID, Email and Telephone number Table of content List of table (if any) List of diagram (if any) Introduction Discussion Results Conclusions Recommendations (Future works) if necessary References Appendices Late submissions are subject to penalty. Please put the team members name on both the prototype and the report. There is a demo session of 10 minutes each group in Week 12 during tutorial/lecture section. Please record a good video clip regarding the prototype performance at lab for demo. A bad video clip will result in redo the demo at lab lively. Make sure every member is involved. Group leader may report sleepy member and penalty will grant to the sleepy member. Marks distribution: 1. Project proposal 2. Final demonstration 3. Final Technical Report + Prototype [20] [50] 30 demo + 20 Q&A [30]
Remarks 1. You have 3 months if you start from day 1. 2. Marks are given on, but not limited to, the design, the implementation, the functionality, the packaging, and the performance analysis, of the prototype. The technical report plays a very important role of informing and convincing the examiners of your achievements. 3. The assignment is meant to be open whereby minimum criteria are set and other things are at students discretions. There is plenty room for innovations. The final prototype can be an advanced unit having dozens of features or a simple one meeting the minimum criteria. Students should tradeoff between their goals and constraints. As far as marks are concern, the usual engineering cost-performance tradeoff applies. 4. There are lots of engineering elements in this assignment and they are not limited only to technical issues. Item 2 above is a good example. Enjoy the assignment. 5. Plagiarism is strictly prohibited. Proper acknowledgement must be given to information sources in the report.

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EEN3096 ASSIGNMENT DESIGN AND BUILD A PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER Introduction The objective of this group assignment

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