The document discusses the AXI protocol, which is a third generation interface standard for connecting intellectual property modules in systems on chip. It describes the five channels that compose AXI, including read/write address and data channels. Transaction flow control using request/acknowledge handshaking is covered along with burst operations and low power features. Benefits of AXI include flexibility and availability of third party tools, while limitations relate to burst length and crossing boundaries. A comparison is made between the AHB and AXI bus architectures.
The document discusses the AXI protocol, which is a third generation interface standard for connecting intellectual property modules in systems on chip. It describes the five channels that compose AXI, including read/write address and data channels. Transaction flow control using request/acknowledge handshaking is covered along with burst operations and low power features. Benefits of AXI include flexibility and availability of third party tools, while limitations relate to burst length and crossing boundaries. A comparison is made between the AHB and AXI bus architectures.
The document discusses the AXI protocol, which is a third generation interface standard for connecting intellectual property modules in systems on chip. It describes the five channels that compose AXI, including read/write address and data channels. Transaction flow control using request/acknowledge handshaking is covered along with burst operations and low power features. Benefits of AXI include flexibility and availability of third party tools, while limitations relate to burst length and crossing boundaries. A comparison is made between the AHB and AXI bus architectures.
The document discusses the AXI protocol, which is a third generation interface standard for connecting intellectual property modules in systems on chip. It describes the five channels that compose AXI, including read/write address and data channels. Transaction flow control using request/acknowledge handshaking is covered along with burst operations and low power features. Benefits of AXI include flexibility and availability of third party tools, while limitations relate to burst length and crossing boundaries. A comparison is made between the AHB and AXI bus architectures.
Mitesh Khadgi For queries, contact: [email protected] Introduction • AXI, the third generation of AMBA interface AMBA 3 specification, is targeted at high performance, high clock frequency system designs and suitable for high speed sub-micrometer interconnect: separate address/control and data phases • support for unaligned data transfers using byte strobes • burst based transactions with only start address issued & issuing of multiple outstanding addresses • easy addition of register stages to provide timing closure • AXI consist of five different channels: Read Address Channel • Write Address Channel • Read Data Channel • Write Data Channel • Write Response Channel 5 Channels of AXI AXI Read operation architecture: AXI Write operation architecture: Transaction channel handshake pairs: Handshake process: • All five channels use the same VALID/READY handshake to transfer data and control information. This two-way flow control mechanism enables both the master and slave to control the rate at which the data and control information moves. The source generates the VALID signal to indicate when the data or control information is available. The destination generates the READY signal to indicate that it accepts the data or control information. Transfer occurs only when both the VALID and READY signals are HIGH.
There are three scenarios when the transfer happens as shown
below: Handshaking control signals Signal Description: Read data channel signals Master Slave configuration connected via interface through interconnect Burst length and size • There are different encoding techniques used in AXI for burst length, busrt size, burst type, cache encoding, protection, atomic access, response, Burst Type Cache, Protection, and Lock Response signals Timing Diagrams for read burst, overlapping read burst and write burst Overlapping read bursts Write burst Low-power interface signals: Low power control signals Denial of a low power request Difference between Exclusive access and Locked access • The basic process for an exclusive access is: A master performs an exclusive read from an address location • At some later time, the master attempts to complete the exclusive operation by performing an exclusive write to the same address location • The exclusive write access of the master is signalled as: • Successful if no other master has written to that location between the read and write accesses • Failed if another master has written to that location between the read and write accesses. In this case the address location is not updated • Locked access: When the ARLOCK[1:0] or AWLOCK[1:0] signals for a transaction show that it is a locked transfer then the interconnect must ensure that only that master is allowed access to the slave region until an unlocked transfer from the same master completes signalling the release of the locked trasnfer. The arbiter within the interconenct is used to enforce this restriction. Burst operation • In AXI channel, the number of data transfers in a single burst are called as beats. Burst Transfer Type Normal/Privileged access • Normal/Privileged is used by some masters to indicate their processing mode. A privileged processing mode typically has a greater lever of access within a system. Different kinds of burst type • Fixed burst: In a fixed burst, the address remains the same for every transfer in the burst. This burst type is for repeated accesses to the same location such as when loading or emptying a peripheral FIFO. Incrementing burst: In an incrementing burst, the address for each transfer in the burst is an increment of the previous transfer address. The increment value depends on the size of the transfer. For example, the address for each transfer in a burst with a size of four bytes is the previous address plus four. Wrapping burst: A weapping burst is similar to an incrementing burst, in that the address for each transfer in the burst is an increment of the previous transfer address. However, in a wrapping burst the address wraps around to a lower address when a wrap boundary is reached. The wrap boundary is the size of each transfer in the burst multiplied by the total number of transfers in the burst. There are two restrictions for wrapping bursts: the start address must be aligned to the size of the transfer and the length of the burst must be 2, 4, 8, or 16. AXI Benefits • Faster testbench development and more complete verification of AMBA AXI 3.0/4.0 designs • Easy to use command interface simplifies testbench control and configuration of master and slave • Simplifies results analysis • Runs in every major simulation environment Drawbacks of AXI • The AMBA AXI4 has limitations with respect to the burst data and beats of information to be transferred • The burst must not cross the 4k boundary. Bursts longer than 16 beats are only supported for the INCR burst type • Both WRAP and FIXED burst types remain constrained to a maximum burst length of 16 beats. These are the drawbacks of AMBA AXI system which need to be overcome AXI features • AMBA AXI 3.0/4.0 Verification IP provides a smart way to verify the AMBA AXI 3.0/4.0 component of a SOC or a ASIC • AMBA AXI 3.0/4.0 VIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non- standard verification environment Summary of AXI • Productivity—By standardizing on the AXI interface, developers need to learn only single protocol for IP • Flexibility • AXI4 memory mapped interfaces and allows burst of up to 256 data transfer cycles with just a single address phase • AXI4-Stream removes the requirement for an address phase altogether and allows • unlimited data burst size • Availability—By moving to an industry-standard, access to a worldwide community of ARM Partners. • Many IP providers support the AXI protocol • A robust collection of third-party AXI tool vendors is available that provide a variety of verification, system development, and performance characterization tools Comparison betweenAMBA AHB and AMBA AXI Bus System Modeling Simulation study between AMBA AHB and AMBA AXI Results Difference between AXI3 and AXI4 • AXI3 Vs AXI4 The difference between AXI3 and AXI4 1. AXI3 supports burst lengths up to 16 beats only. While AXI4 supports burst lengths of up to 256 beats. 2. AXI3 supports write interleaving. AXI4 does NOT support write interleaving 3. AXI3 supports locked transfers, AXI4 does NOT support locked transfers 4. AXI4 supports QoS, AXI3 does NOT suppor QoS. I have seen many IP providers e.g. Synopsys supporting burst lengths up to 256 beats in AXI3 I have also seen many IP providers e.g. Synopsys NOT supporting write interleaving in AXI3. Looks like the industry norm is to use AXI3 with burst lenghts up to 256 beats without support for write Interleaving. Thank You ☺
