FSM Implementation of I2C Protocol and Its Verification Using Verilog

International Journal of Advances in Engineering and Management (IJAEM)
Volume 3, Issue 9 Sep 2021, pp: 1058-1060 www.ijaem.net ISSN: 2395-5252
FSM implementation of I2C protocol and

its verification using verilog
1
Tapaswi SJ1, Dr.Kiran V2
Student, Department of ECE, RV College of Engineering, Bangalore, Karnataka
2
Associate Professor, Department of ECE, RV College of Engineering, Bangalore, Karnataka
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Submitted: 10-09-2021 Revised: 19-09-2021 Accepted: 23-09-2021
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ABSTRACT: Present day‟s technology has I. INTRODUCTION

reached a goal where an entire system can be The inter integrated Circuit Bus is
implemented on a single chip which is nothing but synchronous bi-directional half duplex (one
called system on chip (SOC). It involves directional communication at a given time) two
microcontrollers and various peripheral devices wire serial interface bus. The concept of I2C bus
with each peripheral device having its own was developed by „Philips semiconductor‟ in early
intellectual property (IP) named as IP cores. Serial 1980‟s. The original intension of I2C was to
Communication is established between these IP provide an easy way to connection between a
cores using various protocols like RS232, RS422 microprocessor/microcontroller and peripheral
and UART etc. These protocols perform point to chips. The I2C bus comprise of two bus lines,
point communication which requires huge wiring namely Serial Clock – SCL and Serial Data – SDA.
connections, multiplexing of all the bus SCL line is responsible for generating synchronous
connections to deliver the information to the IP clock pulses and SDA is responsible for
Cores. To overcome this I2C protocol is developed transmitting the serial data across devices. I2C bus
by Philips, which is a two line communication. is shared bus system to which many number of I2C
Here only two pins i.e., SCL, SDA establish devices can be connected, Devices connected to the
connection between various devices considering I2C bus can act as either „Master‟ device or „Slave‟
one as master and other as slave. These two pins device. The „Master‟ device is responsible for
communicate using particular commands like start, controlling the communication by
address, read/write, acknowledgement and stop initiating/terminating data transfer, sending data
commands. Both 7-bit and 10-bit addressing and generating synchronous clock pulses. „Slave‟
formats can be used, 10-bit addressing supports devices wait for the commands from the master and
1024 devices and 7-bit addressing supports 127 respond upon receiving the commands. „Master‟
devices. and „Slave‟ devices can act as either transmitter or
Keywords: I2C Communication, Verilog HDL, receiver. Regardless whether a master is acting as
FSM Model, Timing Diagram, Synchronous transmitter or receiver, the synchronization clock is
communication. generated by the „Master‟ device only [3].
Figure 1:I2C Bus interfacing diagram
FEATURES  No need of prior agreement on data transfer

 Only two common bus lines (wires) are rate like in UART communication. So the data
required to control any device/IC on the I2C transfer speed can be adjusted whenever
network required
DOI: 10.35629/5252-030910581060 Impact Factor value 7.429 | ISO 9001: 2008 Certified Journal Page 1058
 Simple mechanism for validation of data the logic „high‟ level by resistors connected to a
transferred single positive supply, usually +3.3 V or +5 V but
 Uses 7-bit addressing system to target a designers are now moving to +2.5 V and towards
specific device/IC on the I2C bus 1.8 V in the near future. All the connected devices
 I2C networks are easy to scale. New devices have open-collector (open drain for CMOS - both
can simply be connected to the two common terms mean only the lower transistor is included)
I2C bus line driver stages that can transmit data by pulling the
bus low, and high impedance sense amplifiers that
II. LITERATURE SURVEY monitor the bus voltage to receive data. Unless
I2C uses only two pins SCL, SDA to devices are communicating by turning on the lower
establish connection between various devices transistor to pull the bus low, both bus lines remain
considering one as master and other as slave. These „high‟. To initiate communication a chip pulls the
two pins communicate using particular commands SDA line low. It then has the responsibility to drive
like start, address, read/write, acknowledgement the SCL line with clock pulses, until it has finished,
and stop commands. Both 7-bit and 10-bit and is called the bus „master‟ [2].
addressing formats can be used. 10-bit addressing
supports more addressing lines i.e., 1024 compared III. METHODOLOGY
to 127 addressing lines in 7-bit mode [1]. The designed I2C protocol is based on FSM (Finite
The „bus‟ wires are named SDA (Serial State Machine) model. The different states are
data) and SCL (Serial clock), these two bus wires explained as follows.
have the same configuration. They are pulled-up to
Figure 2:FSM model of I2C
 State 0 - Idle: No operation. Both SCL and  State 4 – Acknowledgment: If an address

SDA lines are pulled up to high level through frame was successfully received by the slave,
pull up resistors as shown in Figure 1. an ACK bit is returned to the master from the
 State 1 – Start: The SDA line switches from a slave.
high voltage level to a low voltage level before  State 5 – Data: A 8 bit data will be sent to the
the SCL line switches from high to low. slave from the master or 7 bit data will be
 State 2 – Address: Master will send a 7 bit received by the master from the slave
unique address to the slave when the master depending upon read/write bit sent in state 3.
wants to communicate with it.  State 6 – Acknowledgment: If a data frame
 State 3 – Read/Write bit: Master will send a was successfully received by the slave/master,
single bit specifying whether the master is an ACK bit is returned to the master/slave
sending data to the slave (low voltage level) or from the slave/master
requesting data from it (high voltage level).  State 7 – Stop: The SDA line switches from a
low voltage level to a high voltage level after
the SCL line switches from low to high.
Figure 3:Timing diagram for Read/ Write Operations
IV. RESULT using Verilog HDL using the Xilinx ISE tool. The
In this work, I2C communication protocol timing wave formsof the simulation is shown in
is demonstrated using FSM modeling approach and figure 4.
the functionality of the designed FSM is verified
Figure 4:timing waveforms of simulation
V. SUMMARY Transactions on Consumer Electronics, Vol.

I2c is one of the most widely used on chip 49, No. 4, Nov. 2003.
communication protocols. This paper aims to [6]. Peter Corcoran, “Two Wires and 30 Years:
provide the understanding of this protocol and the A Tribute and Introductory Tutorial to the
basic hardware implementation of the protocol I2C Two-Wire Bus” U.S. Patent 4 689 750,
using Verilog HDL. Aug. 25, 1987
REFERENCE
[1]. Lakshmi ManasaKappaganthu, Durga
Prakash M, “I2C Protocol and its Clock
Stretching Verification using System
Verilog and UVM”. International
Conference on Inventive Communication
and Computational Technologies (ICICCT
2017)
[2]. "I2C Licensing Information". nxp.com.
Archived from the original on 2017-01-10.
Retrieved 2018-04-29.
[3]. Imran Ali, Sung Hun Cho, Dong Gyu Kim,
Muhammad Riaz Ur Rehman and Kang-
Yoon Lee, “A Design of Ultra Low Power
I2C Synchronous Slave Controller with
Interface Voltage Level Independency in
180 nm CMOS Technology” 978-1-5386-
2285-8/17/$31.00 ©2017 IEEE
[4]. Zheng-wei HU, “I2C Protocol Design for
Reusability,” Third International
Symposium on Information Processing,
North China Electric Power University,
Baoding, China.
[5]. J. W. Bruce, “Personal Digital Assistant
(PDA) Based I2C Bus Analysis,” IEEE

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International Journal of Advances in Engineering and Management (IJAEM)

Volume 3, Issue 9 Sep 2021, pp: 1058-1060 www.ijaem.net ISSN: 2395-5252

FSM implementation of I2C protocol and

ABSTRACT: Present day‟s technology has I. INTRODUCTION

Figure 1:I2C Bus interfacing diagram

FEATURES  No need of prior agreement on data transfer

Figure 2:FSM model of I2C

 State 0 - Idle: No operation. Both SCL and  State 4 – Acknowledgment: If an address

Figure 3:Timing diagram for Read/ Write Operations

Figure 4:timing waveforms of simulation

V. SUMMARY Transactions on Consumer Electronics, Vol.

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