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Nhà của tôi  Khoá học  2223H_ELT3047E_70  General  Bài kiểm tra cuối kỳ
Kiến trúc máy tính (2223H_ELT3047E_70) Bài kiểm tra

cuối kỳ
Bắt đầu vào lúc Wednesday, 16 August 2023, 8:09 AM

Trạng thái Đã xong
Kết thúc lúc Wednesday, 16 August 2023, 9:38 AM
Thời gian thực hiện 1 giờ 29 phút
Câu Hỏi 1 Hoàn thành
Which of the following design choices is a feature of the microarchitecture?
a. The machine does not have a subtract unit
b. The machine uses 2's complement representation for integers
c. The machine does not have a subtract instruction
d. The machine uses 3 addressing modes

Suppose we have two implementations of the same instruction set architecture. Computer A has a clock
cycle time of 200 ps and a CPI of 2.5 for some program. Computer B has a clock cycle time of 400 ps and
a CPI of 2.0 for the same program. Which computer is faster for this program and by how much?
a. Computer B is 1.25 times as fast as computer A for this program
b. Computer B is 1.6 times as fast as computer A for this program
c. Computer A is 1.25 times as fast as computer B for this program
d. Computer A is 1.6 times as fast as computer B for this program
ALU instructions are responsible for 60% of your code run time. How much do we have to improve the
speed of the ALU unit if we want the program to run 3 times faster, assuming the new ALU unit does not
affect the other instructions in your code?
a. 10 times
b. 6 times
c. 4 times
d. Impossible
Which of the following is NOT a valid storage model for ISA design?
a. Accumulator
b. General purpose register
c. Specific purpose register
d. Stack
In RISC–V ISA, lw instruction belongs to what type of instruction format?
a. B-type
b. S-type
c. I-type
d. R-type
Which of the following is NOT a valid RISC-V assembly instruction
a. xori a1, a1, 1
b. j done
c. addi a0, a2, a1
d. beq a0, a1, else
Assume that PC=0x0000F000 when the instruction 'beq x9, x0, End' is being fetched. What is the memory
address of the label "End" if it is 3 instructions below the beq in the code.
a. 0x0000F00C
b. 0x0000F010
c. 0x0000EFF4
d. 0x0000EFF0
An ISA uses 16-bit fixed-length codeword and has 32 general purpose registers in total. If the encoding
consists of 3 fields for an opcode and 2 register operands, what is the maximum number of instructions
this ISA might have?
a. 16
b. 64
c. 128
d. 32
Immediate Generator (Imm. Gen.) is used in which following phase of instruction execution?
a. Execution (EX)
b. Write back (WB)
c. Instruction decode (ID)
d. Instruction fetch (IF)
Suppose a datapath has operation times for I & D memories, ALU, Decode & register file access are 250 ps,
200 ps, 100 ps respectively. What's the clock rate for single-cycle implementation if we ignore delays in the
PC register, mux, extender, and wires?
a. 1 GHz
b. 5 GHz
c. 4 GHz
d. 1.25 GHz
Assume that individual stages of the datapath have the following latencies: IF=200 ps, ID = 120 ps, EX =
100 ps, MEM = 180 ps, WB = 120 ps. What is the execution time for the instruction “beq t1, t2, end” in a
single-cycle processor?
a. 540 ps
b. 420 ps
c. 600 ps
d. 720 ps
Suppose x3 initially contains 0x215A6B83. After the following code runs, what is the value of x6 in a big-
endian system?
sw x3, 0(x2)
lbu x6, 3(x2)
a. 0x5A
b. 0x21
c. 0x6B
d. 0x83
Given:
I-cache miss rate = 1%, D-cache miss rate = 1%
Miss penalty = 100 cycles
Base CPI (ideal cache) = 1
Load & stores are 25% of instructions
What is the percentage of time on memory stall?
a. 55.6%
b. 66.7%
c. 44.4%
d. 50.0%
Suppose the following repeating pattern (e.g., in a loop) of branch outcomes: True, True, Not True, Not
True, True. What is the accuracy of the 2-bit predictor for the first 5 branches in this pattern, assuming that
the predictor starts off with the predict bit equals to 10 (weak taken)?
a. 80%
b. 20%
c. 60%
d. 40%
What is the size of a page table if each page holds 8KB of data on a 32-bit virtual address system,
assuming that each entry of the page table has a size of 4 bytes?
a. 2MB
b. 3MB
c. 5MB
d. 4MB
Write down the tag (in binary format) for the request address 0xd0fe if the system uses a 512-byte direct-
mapped cache with two-word blocks.
Answer: 0001000101101010
Given a 2-way associative cache with two-word blocks and a total size of 4 blocks, determine if following
memory references (given as word addresses) is a hit or a miss, assuming the cache is initially empty.
0x04: Miss
0x06: Miss
0x05: Hit
0x07: Hit
Apart from data, caches also require SRAM to store metadata such as tags and valid bits. Calculate the
total number of bits required to implement a cache with two-word blocks that can hold up to 4KB of data.
Assume that the caches are byte addressable, and that addresses and words are 32 bits.
(Note: fill in the answer box with only numerical value, leaving out the unit. For example: "28866 bits" is the
WRONG answer, the correct one is "28866" only)
Answer: 43520
Suppose you executed the code below on a pipelined processor that does NOT handle data hazards:
lw x1, 4(x2)
add x5, x0, x1
and x1, x1, x2
Inserting NOP instructions where necessary to make the above code running correctly in the pipeline.
lw x1, 4(x2)
NOP
NOP
add x5, x0, x1
and x1, x1, x2

Given a datapath in the below Figure:
Determine the following signals when executing the instruction “beq t1, t2, end” in the datapath.
ImmSel= B
BrUn= Don't care
ASel= 1
BSel= 1
◄ Course information Chuyển tới... Lecture 1 slides ►

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Vương Hoàng Minh  VM

Kiến trúc máy tính (2223H_ELT3047E_70) Bài kiểm tra

Bắt đầu vào lúc Wednesday, 16 August 2023, 8:09 AM

Câu Hỏi 1 Hoàn thành

Which of the following design choices is a feature of the microarchitecture?

a. The machine does not have a subtract unit

b. The machine uses 2's complement representation for integers

c. The machine does not have a subtract instruction

d. The machine uses 3 addressing modes

a. Computer B is 1.25 times as fast as computer A for this program

b. Computer B is 1.6 times as fast as computer A for this program

c. Computer A is 1.25 times as fast as computer B for this program

d. Computer A is 1.6 times as fast as computer B for this program

Câu Hỏi 3 Hoàn thành

Câu Hỏi 4 Hoàn thành

b. General purpose register

c. Specific purpose register

In RISC–V ISA, lw instruction belongs to what type of instruction format?

Câu Hỏi 6 Hoàn thành

Which of the following is NOT a valid RISC-V assembly instruction

a. xori a1, a1, 1

c. addi a0, a2, a1

d. beq a0, a1, else

Câu Hỏi 7 Hoàn thành

Câu Hỏi 9 Hoàn thành

b. Write back (WB)

c. Instruction decode (ID)

d. Instruction fetch (IF)

Câu Hỏi 10 Hoàn thành

Câu Hỏi 12 Hoàn thành

lbu x6, 3(x2)

Miss penalty = 100 cycles

Base CPI (ideal cache) = 1

Load & stores are 25% of instructions

What is the percentage of time on memory stall?

Câu Hỏi 14 Hoàn thành

Câu Hỏi 15 Hoàn thành

Câu Hỏi 17 Hoàn thành

Câu Hỏi 18 Hoàn thành

add x5, x0, x1

and x1, x1, x2

add x5, x0, x1

and x1, x1, x2

Given a datapath in the below Figure:

BrUn= Don't care

◄ Course information Chuyển tới... Lecture 1 slides ►

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