Asus Prime h310m-k r2.0

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PAGE TITLE

PRIME H310M-K R2.0


Rev 1.01A 2018.06
ITP

RVP8 DDR4 2133/2400


on Board Channel A
DDR4 2133/2400

PCIEx16
Intel Processor DDR4 2133/2400
Channel B
x16
DDR4 2133/2400
PCIE X16 SLOT1
COFFEELAKE
DDI B
Display Port(預留)
LGA-1151 Pin Socket
DDI C
HDMI(預留)
DDI D
DVI

DMI
RTD 2166 VGA

PCI-EX1_1 PCIE GEN2 PCIE5


Audio
AZALIA
INTEL Codec Realtek ALC887

PCIE8
PCI-EX1_2 PCIE GEN2 PCIE6
PCIE GEN2 LAN RTL8111H

PCIE13/SATA0
SATA 6Gb/s SATA6G port 1/2
PCIE14/SATA1
PCH
PCIE15/SATA2
SATA 6Gb/s SATA6G port 3/4
PCIE16/SATA3

Integrated
Clock
USB3_1
FRONT U31G1_12 USB3.1 gen1 USB3_2

USB3_3
BACK U31G1_34 USB3.1 gen1 USB3_4

USB_5
BACK LAN_USB56 USB3.0 USB_6

USB_7
FRONT USB78 USB2.0 USB_8 SIO
NCT5582D
USB_9
FRONT USB910 USB2.0 USB_10
SPI
TPM

SPI FLASH

<Variant Name>

Title : Block Diagram


ASUSTek COMPUTER INC.
Engineer: Bing-jie_Wang
Size Project Name Rev
R1.00
A2 SKYLAKE CHIPSET DEMO
Date: Monday, June 11, 2018 Sheet 1 of 113
Intel Processor

coffeeake ICG : Integrated Clock Gen.

LGA-1151 Pin Socket

SIO
NCT5582D 22ohm 24MHz CLKOUT_CPUPCIBCLK 100M
CLKOUT_LPC0

CLKOUT_CPUNSSC 24M

CLKOUT_CPUBCLK 100M

22ohm 24MHz
TPM CLKOUT_LPC1
CLKOUT_ITPXDP XDP
INTEL
KABYLAKE
PCH
XTAL 24M
Integrated
32.768 Clock
100M
CLKOUT_PCIE0 PCIE X1 SLOT2
100M
100M CLKOUT_PCIE1
CLKOUT_PCIE15

CLKOUT_PCIE2 100M
100M
PCIE X1 SLOT1 CLKOUT_PCIE14 100M
CLKOUT_PCIE3
100M 100M
CLKOUT_PCIE4
CLKOUT_PCIE13

100M 100M
CLKOUT_PCIE12 CLKOUT_PCIE5

100M 100M
PCIE X16_1(CPU) CLKOUT_PCIE11 CLKOUT_PCIE6 LAN Intel RTL8111H

100M
100M
CLKOUT_PCIE10 CLKOUT_PCIE7 M.2 SLOT1

100M 100M
CLKOUT_PCIE9 CLKOUT_PCIE8 <Variant Name>

Title : Clock Distribution


ASUSTek COMPUTER INC.
Engineer: KENNY_CHEN
Size Project Name Rev
A3 SKYLAKE CHIPSET DEMO R1.00

Date: Monday, June 11, 2018 Sheet 2 of 113


PCI_Express x 16_1 <17>O_X16_RST#
PWRGD

PCI_Express x 1_1,2 <17>O_X1_RST#

PWRGD

SIO PCH
NCT5582D Cannon lake

PROCESSOR
<5>PWRBTN# RSTOUT1# Coffeelake
PS_IN#
64ms de-bounce
RSTOUT2#

<16>S_PLTRST# <16>H_CPURST#
LRESET# PLTRST# PLTRST_PROC# RESET#
*5
VCCIO VR <11>VCCIO Come with +3V,+12V
VCCIO_EN
<11.1>VCORE EN <4>O_RSMRST# <1>S_RTCRST#
VCOREN_EN RSMRST# RSMRST# RTCRST#
<6>O_IOPWRBTN# <1>S_SRTCRST# <13.1>VR ready
PS_OUT# PWRBTN# SRTCRST# &SLP_S3 control
POWER SUPPLY VCCST_PWRGD
16ms de-bounce
<10>12V,5V,3V
Main PWR
<3>SB POWER <4.1> / <8>S_SLP_S4# BATTERY
VSB SUSC# SLP_S4#
<9>ATX_PSON#_R
<2>AC Power PSON# PSON# *1 <4.2> / <7>S_SLP_S3#
Switch On SUSB# SLP_S3# <15>H_CPUPWRGD
PWROK PROCPUPWRGD PWRGOOD

PWROK *2 <14>CLK OUT <18>VRM_SVID


VR_Ready SYS_PWROK SVID
<13.1>VR ready
VCCST_PWRGD &SLP_S3 control VBOOT
*1
PSON# is inverted by SLP_S3#,
but gated and delayed by PCH_PWROK
PWRBTN#

*2
PWROK will assert when +3V
arrives
at +2.65V then delay 300ms~500ms
to assert PWROK <13>O_PWROK

Vcore Controller
SVID
<12>VCORE&VCCGT
VBOOT

<11.1>VCORE EN
<13>P_VR_READY_10 VR_ON
PGOOD

ASP1400(ASP1401)

<Variant Name>

Title : Signal & Reset map


CHIP SOCKET or SLOT
ASUSTek COMPUTER INC.
Engineer: Bing-jie_Wang
Size Project Name Rev
A3 SKYLAKE CHIPSET DEMO R1.00

Date: Monday, June 11, 2018 Sheet 3 of 113


+12V_S0IX 10V(0.2A) LM2665M6 P_VDDQ_PHASE_20
or
S0 2 step charge pump

+12V_CPU Switch ON/OFF


Linear Switching

Control signal Power Rail


ASP1401BMNTXG 3+1
PK616BA*3+PK618BA*6 VCORE+VCCGT 0.55 ~ 1.55V
+12V_CPU +VCCIO_PG
PK616BA*1+PK618BA*1 S0

VCCSA 1.05V(11.1A)
+12V
VCCIO 0.95V (6.4A)
AS358MTR-E1+PK616BA*1
S0
+12V、+3V

+5V
+5V +5VSB_DUAL UP1540PDDA VDDQ 1.2V (22.5A) VTTDDR 0.6V (0.6A)
PK616BA*1 + EMB20P03A UP8815PDDA
S0~S5 PK616BA*1+PK616BA*1 S0/S3 S0
+5VSB

S_SLP_S0#_IDLE

+5V
+5V_S0IX 5V (0.2A)
AP2301GN*1
+5VSB S0

VPPDDR 2.5V (4A)


TPS54328DRCR
S0/S3

+5VSB +1.0V_A 1.05V (6A) VCCST_VCCSFR 1.05V(0.25A)


EMB20P03A +1.8V_A_PG AP2306GN
RT6220AGQUF S0~S5 S0,S3
+5VSB_ATX S0/S3/S5/DS5

+5VSB_ATX

3.3V

+3VSB_ATX
UZ2085G-AD-TN3-R

S0~S5

+3VSB_ATX
+3V_S0IX 3.3V (6A)
PEA16BA +EMF44P02V <Variant Name>
S0
+3V +3V
Title : POWER FLOW
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
S_SLP_S0#_IDLE
Size Project Name
KabyLake DEMO Rev
A3 R1.00

Date: Monday, June 11, 2018 Sheet 5 of 113


SU1L SU1J
SU1I BD34 AB18
VSS_156 VSS_3
A25 A42 BD39 AB20
VSS_1 VSS_299 VSS_158 VSS_6
A30 D45 BD7 AB21
VSS_4 VSS_300 VSS_160 VSS_9
P22 BG44 BE2 AB25 M11 AU22 1 ST6 /X/SPTH
VSS_297 VSS_301 VSS_162 VSS_12 VSS_47 RSVD_11
AV38 BF44 BF43 AB29 L42 V11 TP_PCH_AU22 1 ST7 /X/SPTH
VSS_157 VSS_302 VSS_164 VSS_15 VSS_44 RSVD_15
AV45 BF45 BF5 AB4 L4 V13 TP_PCH_V11 1 ST8 /X/SPTH
VSS_159 VSS_303 VSS_166 VSS_18 VSS_41 RSVD_14
AV8 BF2 BG18 AB42 L35 M33 TP_PCH_V13 1 ST9 /X/SPTH
VSS_161 VSS_304 VSS_168 VSS_21 VSS_38 RSVD_13
AY11 W29 BG23 AC10 L15 N33 TP_PCH_M33 1 ST10 /X/SPTH
VSS_163 VSS_305 VSS_170 VSS_24 VSS_35 RSVD_12
AY19 A35 BG28 AC11 L13 TP_PCH_N33
VSS_165 VSS_7 VSS_172 VSS_27 VSS_32
AY37 A40 BG32 AC14 K8 P27 1 ST11 /X/SPTH
VSS_167 VSS_10 VSS_174 VSS_30 VSS_29 RSVD_10
AY4 A41 BG37 AC16 K45 T27 TP_PCH_P27 1 ST12 /X/SPTH
VSS_169 VSS_13 VSS_176 VSS_33 VSS_26 RSVD_9
AY42 AA17 BG40 AC38 K38 N29 TP_PCH_T27 1 ST13 /X/SPTH
VSS_171 VSS_16 VSS_178 VSS_36 VSS_23 RSVD_8
AY8 AA18 BG9 AC4 K36 P29 TP_PCH_N29 1 ST14 /X/SPTH
VSS_173 VSS_19 VSS_181 VSS_39 VSS_20 RSVD_7
B25 AA20 C1 AC5 K35 AP29 TP_PCH_P29
VSS_175 VSS_22 VSS_183 VSS_42 VSS_17 RSVD_4
B3 AA21 A12 AC7 K33 T24 TP_PCH_AN29 1 ST16 /X/SPTH
VSS_177 VSS_25 VSS_185 VSS_45 VSS_14 RSVD_6
B30 AA26 C2 AC8 GND K3 P24 TP_PCH_T24 1 ST17 /X/SPTH
VSS_179 VSS_28 VSS_187 VSS_48 VSS_11 RSVD_5
B35 AA28 C37 AD1 K27 TP_PCH_P24
VSS_180 VSS_31 VSS_189 VSS_50 VSS_8
B4 AA29 A6 AD18 K13 AU3
VSS_182 VSS_34 VSS_191 VSS_52 VSS_5 PREQ# S_XDP_PREQ# (38)
B41 AB17 C9 AD20 K11 AR1
VSS_184 VSS_37 VSS_193 VSS_54 VSS_2 PRDY# S_XDP_PRDY# (38)
BA13 AC32 D1 AD21 AV2
VSS_186 VSS_40 VSS_195 VSS_56 CPU_TRST# S_XDP_TRST# (38)
BA17 AE4 D10 AD25 /X/SPTH ST168 1 T33 AL1
VSS_188 VSS_43 VSS_197 VSS_58 RSVD_17 PCH_TRIGOUT
BA29 AE8 D12 AD29 /X/SPTH ST169 1 TP_PCH_T33 T35 AJ2
VSS_190 VSS_46 VSS_199 VSS_60 RSVD_16 PCH_TRIGIN

2
BA31 AF18 D15 AD45 TP_PCH_T35
VSS_192 VSS_49 VSS_201 VSS_62
BA37 AF20 D16 AE11 SR1733
VSS_194 VSS_51 VSS_203 VSS_64
BA4 AF21 B12 AE14 1KOhm
VSS_196 VSS_53 VSS_205 VSS_66
BA42 AF25 D19 AE32 N/A
VSS_198 VSS_55 VSS_207 VSS_68
BB40 AF28 D21 AE33 REV = <REV>
KABYLAKE_PCH
VSS_200 VSS_57 VSS_209 VSS_70 (36) H_CPU_TRIGGER

1
BC38 AF29 D24 AE38
VSS_202 VSS_59 VSS_211 VSS_72 SR242
BC40 AF4 D25 AK29 02001-00780000 CRB 1K ohm tie to GND
VSS_204 VSS_61 VSS_213 VSS_74
BC9 AF42 D29 AK30 1 2
VSS_206 VSS_63 VSS_215 VSS_76
BD11 AG18 D30 AK32 (36) S_CPU_TRIGGER S_CPU_TRIGGER_R
VSS_208 VSS_65 VSS_217 VSS_78
BD16 AG20 D33 AK35
VSS_210 VSS_67 VSS_219 VSS_80 30Ohm
BD2 AG21 D35 AK39 GND
VSS_212 VSS_69 VSS_221 VSS_82
BD21 AG23 D36 AL4
VSS_214 VSS_71 VSS_223 VSS_84
BD25 AG25 D39 AL42
VSS_216 VSS_73 VSS_225 VSS_86
F2 AG26 D44 AM10
VSS_218 VSS_75 VSS_227 VSS_88
E31 AG28 D7 AM11
VSS_220 VSS_77 VSS_229 VSS_90
E6 AG29 P13 AM13
VSS_222 VSS_79 VSS_231 VSS_92
E8 AH11 P15 AM17
VSS_224 VSS_81 VSS_233 VSS_94
F39 AH13 P17 AM19
VSS_226 VSS_83 VSS_235 VSS_96
F43 AH30 P19 AM24
VSS_228 VSS_85 VSS_237 VSS_98
G4 AH32 P31 AM27
VSS_230 VSS_87 VSS_239 VSS_100
G40 AH33 P33 AM29
VSS_232 VSS_89 VSS_241 VSS_102
G42 AH38 P35 AM32
VSS_234 VSS_91 VSS_243 VSS_104
F6 AJ1 P4 AM33
VSS_236 VSS_93 VSS_245 VSS_106
G9 AJ17 P42 AM4
VSS_238 VSS_95 VSS_247 VSS_108
H11 AJ18 P8 AN45
VSS_240 VSS_97 VSS_249 VSS_110
H13 AJ20 R1 AP10
VSS_242 VSS_99 VSS_251 VSS_112
H17 AJ21 R32 AP11
VSS_244 VSS_101 VSS_253 VSS_114
H19 AJ23 T10 AP13
VSS_246 VSS_103 VSS_255 VSS_116
H22 AJ25 T14 AP15
VSS_248 VSS_105 VSS_257 VSS_118
H24 AJ26 T22 AP22
VSS_250 VSS_107 VSS_259 VSS_120
H27 AJ28 T29 AP27
VSS_252 VSS_109 VSS_261 VSS_122
H29 AJ29 T32 AP31
VSS_254 VSS_111 VSS_263 VSS_124
H33 AJ45 T36 AP33
VSS_256 VSS_113 VSS_265 VSS_126
H35 AK10 T38 AP34
VSS_258 VSS_115 VSS_267 VSS_128
H38 AK14 Y38 AP39
VSS_260 VSS_117 VSS_324 VSS_130
H4 AK16 Y4 T4
VSS_262 VSS_119 VSS_325 VSS_269
H42 AK17 Y8 W26
VSS_264 VSS_121 VSS_326 VSS_316
H9 AK18 T42 V16
VSS_266 VSS_123 VSS_327 VSS_271
J4 AK26 T5 V17
VSS_268 VSS_125 VSS_328 VSS_273
M36 AK28 U4 V18
VSS_270 VSS_127 VSS_329 VSS_275
M38 AM14 U42 V30
VSS_272 VSS_129 VSS_330 VSS_277
M4 AN14 V10 V32
VSS_274 VSS_131 VSS_331 VSS_279
M8 AP19 V14 V33 HEATSINK_PCH
VSS_276 VSS_133 VSS_332 VSS_281
M9 AR22 W3 V38 1
VSS_278 VSS_135 VSS_317 VSS_283
N13 AR27 AR13 V4
VSS_280 VSS_137 VSS_132 VSS_285
N15 AU29 AR31 V8
VSS_282 VSS_139 VSS_134 VSS_287
N19 AU33 AR33
VSS_284 VSS_141 VSS_136
N22 AV1 AR4 W18
VSS_286 VSS_143 VSS_138 VSS_290
N24 AV10 AT10 W20 2
VSS_288 VSS_145 VSS_140 VSS_292
N31 AV15 AT13 W21
VSS_289 VSS_147 VSS_142 VSS_294
N42 AV24 AT35 W23 HEATSINK
VSS_291 VSS_149 VSS_144 VSS_296
P10 AV27 AT37 W25
VSS_293 VSS_151 VSS_146 VSS_298 13071-00354800
P12 AV33 AT42
VSS_295 VSS_153 VSS_148 s_hsk_2p_1433x1925_prime
AV35 AU11 A44
VSS_155 VSS_150 VSS_306
AU17 BE1
VSS_152 VSS_307
BD30 BD1
KABYLAKE_PCH VSS_154 VSS_308
REV = <REV> W45 B1
02001-00780000 VSS_318 VSS_309
Y13 A2
VSS_319 VSS_310
Y14 B2
VSS_320 VSS_311
GND GND Y30 A3
VSS_321 VSS_312
Y32 A4
VSS_322 VSS_313
Y33 B44
VSS_323 VSS_314
BG14 B45
VSS_333 VSS_315

REV
KABYLAKE_PCH
= <REV>
02001-00780000

www.teknisi-indonesia.com
GND GND

Title : LYNX (GND)


ASUSTek Computer Inc.
Engineer: IAN
Size Project Name Rev
A3 Z87-PRO R1.02A

Date: Monday, June 11, 2018 Sheet 61 of 113


+3VSB
Strap
SR27
1 2 /X
4.7KOHM S_GPP_B22
SR30
2 1 /X
20KOhm

GND Boot BIOS Destination


0 SPI (Default)
1 LPC

+3VSB
Strap
SR31 SU1K
1 2 /X IPD O AR24
GPP_B22/GSPI1_MOSI
4.7KOHM S_GPP_B18 /X/SPTH ST197 1 S_GPP_B22 I AP24 AT45 I
GPP_B21/GSPI1_MISO GPP_D9
S_GPP_B21 I BF24 AV39 I
GPP_B20/GSPI1_CLK GPP_D10
SR32 1KOhm /X /X/SPTH ST222 1 I BF25 AT38 I
GPP_B19/GSPI1_CS# GPP_D11
2 1 S_GPP_B19 AT41 I
GPP_D12
IPD O BE26
GPP_B18/GSPI0_MOSI
S_GPP_B18 I BG25 AT39 I
GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#
GND I AY24 AT44 I
GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#
I AV22 AP43 I
GPP_B15/GSPI0_CS# GPP_D14/ISH_UART0_TXD /SML0BCLK/I2C2_SCL
0 = Disable “No Reboot” mode. (Default) AP44 I
GPP_D13/ISH_UART0_RXD /SML0BDATA/I2C2_SDA
1 = Enable “No Reboot” mode (PCH will disable the TCO I BG39 S_GPP_D13
Timer system reboot feature). This function is useful GPP_C9/UART0_TXD
when running ITP/XDP. /X/SPTH ST199 1 I BA39
GPP_C8/UART0_RXD
S_GPP_C8 I BC45
(72) M2_CONFIG3/PRESENT# GPP_C11/UART0_CTS#
S_GPP_C11 I BF39
(105) USBPWR_SW# GPP_C10/UART0_RTS#
S_GPP_C10
I BA35 BE36 I
GPI PU GPP_C15/UART1_CTS#/ISH_UART1_ CTS# GPP_H20/ISH_I2C0_SCL
I BA45 AY31 I S_GPP_H20 S_PCB1
GPP_C14/UART1_RTS#/ISH_UART1_ RTS# GPP_H19/ISH_I2C0_SDA
I BA44 S_GPP_H19 S_PCB0
GPP_C13/UART1_TXD/ISH_UART1_TXD
I BB45 BF36 I 1 ST214 /X/SPTH
(58) ME_UNLOCK GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H22/ISH_I2C1_SCL
ME_UNLOCK BF37 I S_GPP_H22
GPP_H21/ISH_I2C1_SDA
I AW42 S_GPP_H21 S_PCB2
GPP_C23/UART2_CTS#
@:GP_TYPEC_PWR_CTL 確認Demo pull up 是否上件 /X/SPTH ST204 1 I AW43
GPP_C22/UART2_RTS#
S_GPP_C22 I BA33
GPP_C21/UART2_TXD
I AY44 BE19 I
GPP_C20/UART2_RXD GPP_A23/ISH_GP5
GPP_C19 please change name to project need BG16 I
GPP_A22/ISH_GP4
I AW44 BF18 I
GPP_C19/I2C1_SCL GPP_A21/ISH_GP3
I AY35 BF19 I
GPP_C18/I2C1_SDA GPP_A20/ISH_GP2
I AY33 BE18 I
GPP_C17/I2C0_SCL GPP_A19/ISH_GP1
I AY45 BD19 I
(35) S_CFG9 GPP_C16/I2C0_SDA GPP_A18/ISH_GP0
S_GPP_C16 I AU44 BE17 I
GPP_D4/ISH_I2C2_SDA/ISH_I2C3_ SDA GPP_A17/ISH_GP7
I AN44
(97) O_RI# GPP_D23/ISH_I2C2_SCL/ISH_I2C3_ SCL
S_GPP_D23

KABYLAKE_PCH
REV = <REV>
02001-00780000

+3VSB

(13) P_+VCCIO_OV#_1_10
PCB Rev. Strap
+3V

2
3

3
D SR1830
8.2KOhm
SQ217
/X
11

1
1
H2N7002 G S_GPP_D13 /X /X /X
S 8.2KOhm 8.2KOhm 8.2KOhm
2

2
2
SR37 SR39 SR64

1
N/A SQ217C1 SR1831
1.5PF/50V 8.2KOhm

2
/X N/A

1
S_PCB0
S_PCB1
S_PCB2

GND GND

1
1
8.2KOHM 8.2KOHM 8.2KOHM
8.2KOHM SRN214B SRN214C SRN214A
SRN211A

2
2
GND

Title : SPTH (GPIO)

ASUSTek Computer Inc.


Engineer: Morse_Peng
Size Project Name Rev
A3 SkyLake VC R1.00

Date: Monday, June 11, 2018 Sheet 62 of 113


+3VSB

SR707 SR708

1
4.7KOHM 4.7KOHM
+3VSB
N/A N/A +3V

2
connect to PCI&PCIE
SLOT

4
SRN202C SRN202D SRN202A
SR1613 1 2 0Ohm /X 1KOHM 1KOHM 1KOHM SRN202B
(51,69) S_SMBCLK_SLOT
1KOHM

SR1612 1 2 0Ohm /X
(51,69) S_SMBDATA_SLOT

3
SQ1A
2N7002KDW

(58) S_SMBCLK_VSB S_SMBCLK_MAIN (6,39,40,48)


6 1

SQ1B

2
2N7002KDW
N/A
(58) S_SMBDATA_VSB S_SMBDATA_MAIN (6,39,40,48)
3 4

5
2

2
N/A
SC56 SC57 +12V
10PF/50V 10PF/50V

1
/X /X SR304 1 2 1KOhm

mbs_r0603

1
SQ1C1 +3VSB
1.5PF/50V 3 SQ3
/X C PMBS3904 SR305 1KOhm
GND

2
B 1 1 2

E /X
Place near PCH /X
2
GND

1
SQ3C1
GND 3 1.5PF/50V

3
D
SQ40 /X

2
H2N7002
11
(58,65) S_PWROK
G /X
S

1
SQ40C1 2

2
1.5PF/50V GND
/X

2
GND GND

SPTH (SMBUS/CLRTC)
Title :
ASUSTek Computer Inc.
Engineer: Morse_Peng
Size Project Name Rev
A3 SkyLake VC R1.00

Date: Monday, June 11, 2018 Sheet 63 of 113


POWER FLOW NOT SUPPORT DSW
Power plane

Control link
+5VSB_ATX RT8065 +3VSB_ATX 0OHM SR81
SR79
2 1 1 2 /X
0603 0402
+3VSB +3VSB_ADV S_SUSWARN# S_SUSACK#
/X s_short_r0603_nomask

S_DPWROK (58)
O_RSMRST# S_DPWROK
EUP EUP

DSW
PMOS 0OHM DSW
PMOS 0OHM +3VSB_ADV if have one on SIO side,delet this 1
SR80
2 /X
0402

if NO DSW , please use shortpin

SUPPORT DSW
Power plane Control link
+5VSB +3VSB 0OHM

(58) S_SUSWARN#

(58) S_SUSACK#

PS:the common part design by (64,96) O_RSMRST#


power team,no-eup part and eup
part in SIO demo circuit
No-EUP Part

EUP Part

DSW Part

SR1627
1 2 /X
(58,64) S_RSMRST# 0402 O_RSMRST# (64,96)

SR85
1 2 /X/NO-DSW
(58,64) S_RSMRST# 0402 P_+1.0A_PG_10 (19)
S_RSMRST#

+5VSB_ATX
+1.0V_A
2

SR1639
10KOhm
2

SR1645 47KOhm
3
3

mbs_r0603 D
SQ10
1

/SPTH
H2N7002
11 N/A
1

G
S
3 2
2
1

C SQ50 SQ10C1
1 B PMBS3904 1.5PF/50V
N/A /X
2

E
2
1

SC202
4.7UF/6.3V GND
2

GND GND
GND

Title : SPTH (DSW SEQUENCE)


ASUSTek Computer Inc.
Engineer: IAN
Size Project Name Rev
A3 SkyLake VC R1.00

Date: Monday, June 11, 2018 Sheet 64 of 113


PCH_PWRGD & VCCST_PWRGD SR1640
Sequence Control Ckts 1 2 /X
0402 O_PWROK (20,96,105,113)

+3VSB +3V

2
SR127 SR128
8.2KOhm 8.2KOhm
/X

1
S_PWROK (58,63)
S_PWROK
3

3
D
SQ7

1
H2N7002 SC24
11 /X 1.5PF/50V
G /X
S

2
2

2
1
SQ7C1
1.5PF/50V
/X

2
SQ6A
2 2N7002KDW GND GND
(23) P_VR_READY_10
/SPTH

1
GND

1
SQ6AC1 VCCST_VCCSFR
1.5PF/50V
/X

2
SR129
1KOhm
GND N/A

1
S_VCCST_PWRGD (35)

SQ6B

3
2N7002KDW
5 /SPTH

1
SC26

4
1.5PF/50V

1
SQ6BC1 /X

2
1.5PF/50V
/X

2
GND GND GND GND

1. PCH will have a minimum of a 1ms delay from


PCH_PWROK to assertion of PROCPWRGD.
2. PLTRST# = AND (PCH_PWROK, SYS_PWROK, PROCPWRGD)
Refer to PDG Figure 40-1 SKL S Flow Diagram for
PCH_SYSPWROK Sequence Control Ckts SYS_PWROK/PCH_PWROK Generation
3. It is recommended that SYS_PWROK be
asserted after both PWROK assertion and processor
PCH does not monitor
4. PCH_PWROK and SYS_PWROK both needs to be high
to exit reset, but either signal can come up first.
SYS_PWROK be asserted after both PWROK assertion
and processor core VR PWRGD assertion.

SR132
1 2 /X
0402 S_SYSPWROK (58)
P_VR_READY_10
PU on PCH side

+VCC_EOPIO_PWRGD (OD)

+VCC_EDRAM_PWRGD (OD)

SPTH (PCH/SYS/PROC_PWROK)
Title :
ASUSTek Computer Inc.
Engineer: IAN
Size Project Name Rev
A3 SkyLake VC R1.00

Date: Monday, June 11, 2018 Sheet 65 of 113


0.3G Beta

Standard Circuit

BIOS SPI

+3VSB
SD203
+3V_SPI REV. F1_0.3G_Beta

SMD BIOS 2 SPI /X/SPI


3
1
靠近PCH擺放 BAT54CW
+3V_SPI

SR1642 1KOhm
N/A
SR26
F_BIOS_WP# 2
SR1643 1
1KOhm
N/A 1 2
F_SPI_HOLD# 2 1
0Ohm

1
F1U1
1 8 SC910 mbs_r0603
CS# VCC
F_SPI_CS1#_R 2 7 0.1UF/16V /X
DO(IO1) HOLD#/RESET(IO3)

2
F_SPI_MISO 3 6 F_SPI_HOLD# /X
F_BIOS_WP# 4
WP#(IO2) CLK
5 F_SPI_CLK PEAK 30mA
GND DI(IO0)
SR1644 F_SPI_MOSI
W25Q128JVSIQ
F_BIOS_WP# 2 1
GND
1KOhm
/X

Default /X,FOR GND


DISABLING GND +3V_SPI
EXTERNAL FLASH
PROTECTION 靠近PCH擺放

1 2 SRN209A
(55) S_SPI_MISO 15OHM
F_SPI_MISO
3 4 SRN209B SPI
(55) S_SPI_MOSI 15OHM
15Ohm F_SPI_MOSI 1 2
1 2 3 4 F_BIOS_WP#
(55) S_SPI_CLK
SR571 F_SPI_CLK 5 6
F_SPI_CS1#_R 7 8 F_SPI_CLK
(55) S_SPI_CS0#
F_SPI_CS1#_R F_SPI_MISO 9 F_SPI_MOSI
F_SPI_HOLD#
HEADER_2X5P_K10
7 8 SRN209D
(55) S_SPI_IO2 15OHM 12G06110010M
F_BIOS_WP#
5 6 mbs_hd_2x5p_79_k10_pin_lf3
SRN209C
(55) S_SPI_IO3 15OHM
F_SPI_HOLD# N/A

GND

HEADER擺放在trace路徑上

<Variant Name>

Title : SINGLE BIOS

ASUSTek COMPUTER INC.


Engineer: IAN
Size Project Name Rev
R1.02A
A3 Z87-PRO
Date: Monday, June 11, 2018 Sheet 67 of 113
+3VSB +3V_ATX +12V +12V +3V_ATX

PCIEX1_1

S_SMBCLK_SLOT B1 A1
+12V_1 PRSNT1#
S_SMBDATA_SLOT B2 A2
+12V_2 +12V_3
B3 A3
RSVD1 +12V_4
B4 A4
GND1 GND6
B5 A5
SMCLK JTAG2
B6 A6
SMDAT JTAG3
B7 A7
GND2 JTAG4
B8 A8
+3.3V_1 JTAG5
B9 A9
JTAG1 +3.3V_2
B10 A10
3.3Vaux +3.3V_3
B11 A11
WAKE# PWRGD O_X1_RST# (69,72,96)
S_WAKE#

1
XCX73 X5R 0.1UF/16V
2 1 XC74
(56) S_X1_SL1_TXP
2 1 S_X1_SL1_TXP_C 1.5PF/50V
(56) S_X1_SL1_TXN

2
XCX74 S_X1_SL1_TXN_C
0.1UF/16V
/X
X5R
GND
B12 A12
RSVD2 GND7
B13 A13
Near Connector (Void) GND3 REFCLK+ CK_100M_X1SL1P (54)
B14 A14
HSOP0 REFCLK- CK_100M_X1SL1N (54)
B15 A15
HSON0 GND8
B16 A16
GND4 HSIP0 S_X1_SL1_RXP (56)
B17 A17
(54) PCIEX1_SL1_PRSNT# PRSNT2_1# HSIN0 S_X1_SL1_RXN (56)
B18 A18
GND5 GND9

如果是H310 chipset,則cap SLC4

2
電容請用料11V232104370, 0.1UF/16V
X7R
P_GND1
1
2

1
同時CAP VCC 不需要挖空 /X
P_GND2

SLOT_36P
GND 12003V00082100 GND
GND
mbs_slot_pci_ep_36p_2h_lf3

+3VSB +3V_ATX +12V +12V +3V_ATX

PCIEX1_2

S_SMBCLK_SLOT B1 A1
+12V_1 PRSNT1#
S_SMBDATA_SLOT B2 A2
+12V_2 +12V_3
B3 A3
如果是H310 chipset,則cap B4
RSVD1
GND1
+12V_4
GND6
A4

電容請用料11V232104370, B5
B6
SMCLK JTAG2
A5
A6
delete for 108x used

同時CAP VCC 不需要挖空 B7


SMDAT
GND2
JTAG3
JTAG4
A7
B8
+3.3V_1 JTAG5
A8 +3V_ATX delete it
B9
JTAG1 +3.3V_2
A9
for EMS
B10 A10
3.3Vaux +3.3V_3
B11 A11
WAKE# PWRGD O_X1_RST# (69,72,96) EL 820U:11V040827130

1
S_WAKE# PL 560U:11031V0004F300
XCX84 0.1UF/16V + X1CE2

1
2 1 X5R 560UF/6.3V
(56) S_X1_SL2_TXP
2 1 S_X1_SL2_TXP_C XC75 11031V0004F300
(56) S_X1_SL2_TXN

2
XCX85 S_X1_SL2_TXN_C
0.1UF/16V 1.5PF/50V mbs_cpl_560u6d3vsha_lfh_ms

2
X5R N/A
/X

GND
B12 A12 GND
RSVD2 GND7
B13 A13
GND3 REFCLK+ CK_100M_X1SL2P (54)
B14 A14
HSOP0 REFCLK- CK_100M_X1SL2N (54)
B15 A15
Near Connector (Void) HSON0 GND8
B16
GND4 HSIP0
A16
S_X1_SL2_RXP (56)
+5V delete it
(54) PCIEX1_SL2_PRSNT#
B17
PRSNT2_1# HSIN0
A17
S_X1_SL2_RXN (56) for EMS
B18 A18
GND5 GND9
EL 820U:11V040827130

1
PL 560U:11031V0004F300
SLC5 + X1CE1
2

0.1UF/16V 1 560UF/6.3V
P_GND1
X7R 2 11031V0004F300
1

P_GND2

2
/X mbs_cpl_560u6d3vsha_lfh_ms
/X
SLOT_36P
GND 12003V00082100 GND
GND GND
mbs_slot_pci_ep_36p_2h_lf3
EL/PL colay
to SB SMBus(standby
power)

(51,63) S_SMBCLK_SLOT
(51,63) S_SMBDATA_SLOT

(51,58,72,89) S_WAKE#

<Variant Name>

Pull-high at SB side
Title : PCIEX1_1

ASUSTek COMPUTER INC.


Engineer: KENNY_CHEN
Size Project Name Rev
R1.02A
A3 Z87-PRO
Date: Monday, June 11, 2018 Sheet 69 of 113
P_GT_CSN1A_10 (10)
P_GT_CSN1A_10

2
PC1001
0.1UF/16V

1
PR1003

P_GT_PHASE1_10 (10)
P_GT_CSP1A_10 2 1

6.8KOhm

2
PR1005 PR1006
10Ohm

2
PC1004
0.1UF/16V 90.9KOHM

1
/X P_GT_CSREFA_10

1
DGND PC1005
1000PF/50V

2
DGND
PR1016

P_VCORE_VCC5_20
1 2
P_GT_ILIMA_10 P_GT_CSCOMPA_10
20KOHM

PR1000 2200PF/50V
PC1000

2
49.9Ohm

1
2 1 1 2 PTR1001 PR1024

2
1 2 P_VCORE_DIFF_R_10 P_VCORE_FB_R_10 2 1 60.4KOhm PC1008 PC1009
PR1002 PC1002 PR1042 100KOhm 2200PF/50V
330PF/50V 220PF/50V

2
4.7KOHM
2KOhm

1
1KOhm 2 1 PR1026
1 2 47PF/50V PC1003 1 2 1 2

1
PR1007 P_GT_CSPA_R_10 P_GT_CSPA_R2_10
PR1124 0Ohm P_GT_CSSUMA_10
mbs_r0603
300KOhm

P_VCORE_CSCOMP_10

P_VCORE_CSSUM_10
P_VCORE_CSREF_10
P_VCORE_COMP_10

P_VCORE_CSN3_10
P_VCORE_CSP4_10

P_VCORE_CSP3_10
PC1006

P_VCORE_DIFF_10
P_VCORE_VSN_10
P_VCORE_VSP_10

P_VCORE_ILIM_10
P_VCORE_FB_10
PR1008

470PF/50V
+3V 1 2
P_VCORE_VRHOT#_R_4 P_VCORE_IOUT_10

1KOhm PR1011

2
VCCST_VCCSFR 402Ohm

1KOhm
PR1009

2
PR1013

100Ohm PR1014
13.7KOhm

1
1UF/16V PC1007

PR1015

1
45.3Ohm PR1012

57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
2

2
mbs_c0603 PR1010 PU1000

1
+5VSB +5V +5V

0402
+3V

1
+12V_CPU VCCIO DGND

100Ohm

GND5
GND4
GND3
GND2
GND1
VSN
VSP
DIFF
FB
COMP
CSCOMP
ILIM
CSSUM
CSREF
NC2
NC1
CSP3
CSN3
2
/X
PR1017

1KOhm

1
2

PR1018 /X DGND 1 39
/X IOUT CSP2

1
2

1KOhm PR1019 PR1020 P_VCORE_IOUT_R_10 2 38 P_VCORE_CSP2_10


EN CSN2
PR1116 PR1022 /X 8.2KOhm DGND PR1023 10Ohm O_VCORE_EN_10 3 37 P_VCORE_CSN2_10
SDIO CSP1
2.2Ohm 2.2Ohm /NOS0IX mbs_r0603 8.2KOhm H_SVID_DATA 12 2
1 P_SVID_DATA 4 36 P_VCORE_CSP1_10
ALERT# CSN1
mbs_r0603 mbs_r0603 /X H_SVID_ALERT# 1
PR1021 2
0Ohm P_SVID_ALERT# 5 35 P_VCORE_CSN1_10
SCLK TSENSE
1

5% 5% H_SVID_CLK PR1025 49.9Ohm P_SVID_CLK 6 34 P_VCORE_TM_10


VR_RDY PWM1/SV_ADDR P_VCORE_PWM1_10 (7)
1

/NOS0IX/NOSIOSEQ P_VRM_PGD_10 7 33 P_VCORE_PWM1_10


0.01UF/16V

/X VCC PWM2/VBOOT P_VCORE_PWM2_10 (7)


P_VCORE_VCC5_20 8 32 P_VCORE_PWM2_10
VRSHDN PWM3/ICCMAX
PC1011

P_VCORE_PWM3_10 (7)
0.1UF/16V

0.1UF/16V
1

P_VCORE_VRSHDN_4 9 06095-01610300 31 P_VCORE_PWM3_10


PC1012

PC1016
VRMP SM_ADDR
PC1010 P_VCORE_VRMP_10 10 30 P_VCORE_SM_ADDR_10
OCPL_VRHOT# DRON P_VCORE_DRON_10 (6,7,10)
2

1UF/16V P_VCORE_VRHOT#_4 11 29 P_VCORE_DRON_10


2

SM_SDA PWM2A/VBOOTA
2

mbs_c0603 PR1027 PC1014 P_SMB_DATA_4 12 28 P_GT_PWM2A_10


2

470PF/50V
SM_SCL PWM1A/ICCMAXA P_GT_PWM1A_10 (10)
2.7KOHM /X PC1015 PR1028 P_SMB_CLK_4 13 27 P_GT_PWM1A_10
1

PR1030

PR1031

PR1032

PR1033
IOUTA TSENSEA

249KOhm
2 1 P_GT_IOUTA_R_10

CSCOMPA
/NOSIOSEQ /X 47PF/50V P_GT_IOUTA_10 P_GT_TMA_10
1

PC1017

CSSUMA
CSREFA

100KOhm
2

COMPA
/X PC1013 47PF/50V /X 499Ohm

CSN1A

CSN2A
CSP1A

CSP2A

10KOhm

10KOhm
DIFFA
VSNA
1

ILIMA
VSPA

2
47PF/50V PR1029

FBA
2
/X
12KOhm
ASP1401CTBMNTXG

14
15
16
17
18
19
20
21
22
23
24
25
26
DGND DGND DGND DGND DGND DGND DGND DGND P_VCORE_CSN1_10 (7)

1
P_VCORE_CSN1_10

1
+3V

2
1 DGND PC1023

P_GT_CSCOMPA_10
1KOhm PR1034

1KOhm PR1035

P_GT_CSSUMA_10
P_GT_CSREFA_10
2 DGND DGND DGND DGND 0.1UF/16V

P_GT_COMPA_10

2P_GT_CSN1A_10

1
P_GT_CSP1A_10

P_GT_CSP2A_10
P_GT_DIFFA_10
P_GT_VSNA_10

P_GT_ILIMA_10
P_GT_VSPA_10
2

P_GT_FBA_10
PR1036 PR1047
HEADER_1X3P
PHD1000 1 2
PR1037
0402 P_VCORE_PHASE1_10 (7)
s_hd_1x3p_100_ns S_SMBDATA_MAIN P_VCORE_CSP1_10 1 2
/X 1 /X 2 6.8KOhm
1

0402
/X /X S_SMBCLK_MAIN
PR1038 /X PC1018 PR1039
1 2 2 1 2KOhm
47PF/50V

47PF/50V

1KOhm
PC1019

PC1020

P_VCORE_CSN2_10 (7)
P_VCORE_CSN2_10
15PF/50V

1
PR1040 PC1021 PR1041 PC1022

P_VCORE_VCC5_20
mbs_r0603
1

1 2 2 1 1 2 2 1

2
49.9Ohm P_GT_DIFFA_R_10 P_GT_FBA_R_10 PC1030
8.2KOhm 0.1UF/16V

1
330PF/50V 2200PF/50V
2

/X /X
PR1051

P_VCORE_PHASE2_10 (7)
DGND P_VCORE_CSP2_10 1 2
6.8KOhm

PR1043 100Ohm PR1044 1.5KOhm PR1045 100Ohm PR1046 1.5KOhm


P_VCORE_CSN3_10 (7)
P_VCORE_CSN3_10
2 1 2 1 P_GT_VSNA_10 2 1 2 1 P_VCORE_VSN_10
PC1025 PC1026

2
1

PC1024 PC1029 PC1034


(6,37) H_GT_VSS_SENSE (6,36) H_VSS_SENSE
1

GND PC1027 1000PF/50V 1 2 GND PC1028 1000PF/50V 1 2 0.1UF/16V

1
1000PF/50V /X 1000PF/50V 1000PF/50V /X 1000PF/50V
PR1053
2

2
2

(6,37) H_GT_VCC_SENSE (6,36) H_VCC_SENSE


P_VCORE_PHASE3_10 (7)
VCCGT PR1048 100Ohm DGND VCORE PR1049 100Ohm DGND P_VCORE_CSP3_10 1 2
6.8KOhm
2 1 P_GT_VSPA_10 2 1 P_VCORE_VSP_10

PC1032
1

PC1031 PC1033
1000PF/50V 2 1 1000PF/50V
/X /X
2

0.01UF/16V

PJP1000
DGND 1 2 DGND

SHORT_PIN
/X
GND DGND

PC1036

PC1037

PC1039
PR1057

1 2
(23) P_+VCCIO_PG_10

0.1UF/16V

0.1UF/16V

0.1UF/16V
0402

2
O_VCORE_EN_10
/X PR1061 PR1062 PR1063

2
10Ohm 10Ohm 10Ohm

1
P_VCORE_DRON_10 (6,7,10)

1
O_VCORE_EN_10 (12,23)
/X /X /X
PR1054 PR1058

2
1 2 1 2 P_VCORE_CSREF_10

1
P_VCORE_TM_10 P_GT_TMA_10 PR1064 PR1065 PR1066
P_VRM_PGD_10 (23)
PC1040
22OHM 22OHM
DGND 1000PF/50V
P_VCORE_TM_R_10

P_VCORE_VRSHDN_4 (57)

2
0.1UF/16V

0.1UF/16V

1% 1% PR1067 90.9KOHM 90.9KOHM 90.9KOHM


P_GT_TMA_R_10
PC1035

PC1038

1
1 2
S_SMBDATA_MAIN (39,40,48,63)
2

P_VCORE_ILIM_10 P_VCORE_CSCOMP_10
PR1055 PR1060 37.4KOhm DGND
2

S_SMBCLK_MAIN (39,40,48,63)

2
732Ohm 732Ohm PTR1003
1

H_VCC_SENSE (6,36)

1
PC1041
1

1
2

100KOhm PR1070 PC1042


H_VSS_SENSE (6,36)
PTR1000 PTR1002 130KOhm 3300PF/50V

2
220PF/50V
H_GT_VCC_SENSE (6,37)
10KOHM 10KOHM PR1073

1
1 2 1 2
H_GT_VSS_SENSE (6,37)
1

P_VCORE_CSP_R_10 PR1122
P_VCORE_CSP_R2_10 0Ohm P_VCORE_CSSUM_10
180KOhm
H_SVID_CLK (35)

H_SVID_DATA (35) GND


GND
H_SVID_ALERT# (35)

P_VCORE_VRHOT#_R_4 (35)

P_GT_PWM2A_10 P_VCORE_PWM2_10

P_CPU_GND_GT (37)
2

PR1068 PR1069

P_CPU_GND_VCORE (37)

10KOhm 10KOhm

PR1071 PR1072
1

P_GT_BOOT_R 1 2 P_CPU_GND_GT P_VCORE_BOOT_R 1 2 P_CPU_GND_VCORE


2

SHORTPIN_0402 SHORTPIN_0402
PR1074 PR1075
49.9KOhm TEMP_M05_0040 49.9KOhm TEMP_M05_0040
/X /X
1

DGND DGND

Title
<Title>

Size Document Number Rev


E <Doc> <RevCode>

Date: Monday, June 11, 2018 Sheet 6 of 113


+12V_CPU
+5VSB
+12V_CPU

1
PD1000 P_VCORE_L+12V_S
BAT54CW

1
PR1076 PC1045
0Ohm 1UF/16V

2
5% mbs_c0603
mbs_r0603

1
/X PR1077 5% PQ1011
1 2 PR1078 1Ohm PC1044 0.1UF/16V GND

5
D PK616BA
P_DRIVER1_VCC_20 5%
2.2OHM P_VCORE_BST1_20 mbs_r0603 P_VCORE_BST1_R_20 1 2 PR1079 1Ohm
mbs_r0805 11V233104370 4
PU1010 G S
P_VCORE_R_HG1_20
PC1059

1
11 mbs_r0603
GND4
10 470PF/16V

1
2
3
GND3
9 11G233047101390 VCORE
GND2

2
1 8 07005-A0540000
(6) P_VCORE_PWM1_10 PWM BST PL1010
PR1081 2 7 P_VCORE_BST1_20
NC DRVH
1 2 3 6 P_VCORE_HG1_20
(6,10) P_VCORE_DRON_10 EN SW

P_VCORE_PH1_SNU_10
P_OD#1_10 4 5 P_VCORE_PHASE1_20 mbs_powpak_5p_203x242_colay 1 2
VCC DRVL

1
49.9Ohm P_VCORE_VCC1_R_20 P_VCORE_LG1_20 PC1046
0.68UH
PQ1012 PQ1014 4700PF/50V
NCP81166AMNTBG
mbs_dfn_8p_s79_p_on_2v_half 09011-00011300

5
D PK6B0SA D PK6B0SA

2
1
PC1047
1UF/16V 4 4

1
2
mbs_c0603 G S G S PJP1001 PJP1002

1
SHORTPIN SHORTPIN

1
PC1048 PR1082

1
2
3

1
2
3
/X /X
2200PF/50V 1Ohm

2
GND /X mbs_powpak_5p_203x242_colay mbs_powpak_5p_203x242_colay

2
2
07005-A1100000 07005-A1100000

GND GND GND GND GND

(6) P_VCORE_PHASE1_10

(6) P_VCORE_CSN1_10

VCORE
P_VCORE_L+12V_S
VRM Input CAP

11031-0004F300

11031-0004F300

11031-0004F300

11031-0004F300
560UF/6.3V PCE1010

560UF/6.3V PCE1012

560UF/6.3V PCE1013
560UF/6.3V PCE1011
P_VCORE_L+12V_S

270UF/16V PCE1000

270UF/16V PCE1001
+12V_CPU

11031-0006F200

11031-0006F200
1
+5VSB
PC1049 P_VCORE_L+12V_S
1UF/16V

1
mbs_c0603
+ + + +
2

1
PD1001
2

BAT54CW PQ1021 + +

2
PR1083 PR1085 0.1UF/16V
PC1050 GND

5
D PK616BA
0Ohm 5%

2
5% P_VCORE_BST2_20 P_VCORE_BST2_R_20 1 2 PR1084 1Ohm
3

mbs_r0603 1Ohm 11V233104370 4


1

PU1020 G S
mbs_r0603 P_VCORE_R_HG2_20
PC1060

1
/X 5% 11 mbs_r0603
GND4
10 470PF/16V

1
2
3
GND3
9 11G233047101390
GND2

2
1 8 07005-A0540000
(6) P_VCORE_PWM2_10 PWM BST PL1020
PR1087 49.9Ohm 2 7 P_VCORE_BST2_20 GND
NC DRVH
1 PR10882 3 6 P_VCORE_HG2_20 GND
EN SW

P_VCORE_PH2_SNU_10
P_VCORE_DRON_10 1 2 P_OD#2_10 4 5 P_VCORE_PHASE2_20 mbs_powpak_5p_203x242_colay 1 2
VCC DRVL

1
P_DRIVER2_VCC_20 P_VCORE_VCC2_R_20 P_VCORE_LG2_20 PC1051
0.68UH
2.2OHM PQ1022 PQ1024 4700PF/50V
NCP81166AMNTBG
mbs_dfn_8p_s79_p_on_2v_half 09011-00011300

1
D PK6B0SA D PK6B0SA

2
1

mbs_r0805 PJP1003 PJP1004


PC1052 SHORTPIN SHORTPIN
1UF/16V 4 4
/X /X
2

mbs_c0603 G S G S

2
1
PC1053 PR1089

1
2
3

1
2
3
2200PF/50V 1Ohm

2
/X mbs_powpak_5p_203x242_colay mbs_powpak_5p_203x242_colay

2
07005-A1100000 07005-A1100000
VCORE

GND GND GND GND GND GND

(6) P_VCORE_PHASE2_10

(6) P_VCORE_CSN2_10

1
PC1065 PC1066 PC1067 PC1068
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V

2
/X /X /X /X

GND

P_VCORE_L+12V_S
+12V_CPU

1
+5VSB
PC1054
1UF/16V

2
mbs_c0603
2

PD1002
PR1091 0.1UF/16V PQ1031
BAT54CW PC1055
2

GND
5

D PK616BA
PR1090 P_VCORE_BST3_20 P_VCORE_BST3_R_20 1 2 5%
0Ohm 1Ohm 11V233104370 PR1092 1Ohm
3

5% mbs_r0603 4
PU1030 G S
mbs_r0603 5% P_VCORE_R_HG3_20
PC1061
1

11 mbs_r0603
GND4
/X 10 470PF/16V
1
2
3

GND3
9 11G233047101390
GND2
2

1 8 07005-A0540000
(6) P_VCORE_PWM3_10 PWM BST PL1030
PR1094 49.9Ohm 2 7 P_VCORE_BST3_20
NC DRVH
1 PR10952 3 6 P_VCORE_HG3_20 mbs_powpak_5p_203x242_colay
EN SW

P_VCORE_PH3_SNU_10
P_VCORE_DRON_10 1 2 P_OD#3_10 4 5 P_VCORE_PHASE3_20 1 2
VCC DRVL

1
P_DRIVER3_VCC_20 P_VCORE_VCC3_R_20 P_VCORE_LG3_20 PC1056
PQ1032 0.68UH
2.2OHM PQ1034 4700PF/50V
NCP81166AMNTBG
mbs_dfn_8p_s79_p_on_2v_half 09011-00011300
5

1
D PK6B0SA D PK6B0SA

2
1

PJP1005 PJP1006
mbs_r0805
PC1057 SHORTPIN SHORTPIN
1UF/16V 4 4
/X /X
2

mbs_c0603 G S G S
1

2
1

PC1058 PR1096
1
2
3

1
2
3

2200PF/50V 1Ohm
2

/X mbs_powpak_5p_203x242_colay mbs_powpak_5p_203x242_colay
2

07005-A1100000 07005-A1100000

GND GND GND GND GND GND

(6) P_VCORE_PHASE3_10

(6) P_VCORE_CSN3_10

<Variant Name>

Title : VCORE DRIVER

ASUSTek COMPUTER INC.


Engineer: RAY
Size Project Name Rev
R1.00
A1 SkyLake VC
Date: Monday, June 11, 2018 Sheet 7 of 113
P_VCORE_L+12V_S

+12V_CPU
+5VSB P_VCORE_L+12V_S

1
PC1301
1UF/16V

2
mbs_c0603

1
2
PD1300
PR1301 BAT54CW
0Ohm PQ1311
5% PR1302 1Ohm PC1302 0.1UF/16V PK616BA GND

5
D
mbs_r0603 5% 5%

3
1
P_GT_BST1_20 mbs_r0603 P_GT_BST1_R_20 1 2 PR1303 1Ohm
/X 11V233104370 4
PU1310 G S
P_GT_R_HG1_R_20
PC1305

P_GT_DRIVER_VCC_20

1
11 mbs_r0603
GND4
10 470PF/16V

1
2
3
GND3
9 11G233047101390 VCCGT
GND2

2
1 8 07005-A0540000
(6) P_GT_PWM1A_10 PWM BST PL1310
PR1304 2 7 P_GT_BST1_20
NC DRVH
1 2 PR1305 3 6 P_GT_R_HG1_20
(6,7) P_VCORE_DRON_10 EN SW
1 2 P_GT_OD#1_10 4 5 P_GT_PHASE1_20 mbs_powpak_5p_203x242_colay 1 2
VCC DRVL

1
49.9Ohm P_GT_VCC1_R_20 P_GT_LG1_20 PC1303

P_GT_PH1_SNU_10
PQ1312 0.68UH
2.2OHM 4700PF/50V
NCP81166AMNTBG
mbs_dfn_8p_s79_p_on_2v_half PQ1314 09011-00011300

5
D D PK6B0SA

2
1
mbs_r0805 PK618BA
PC1300
1UF/16V 4 4

1
2
mbs_c0603 G S G S PJP1300 PJP1301

1
SHORTPIN SHORTPIN

1
PC1304 PR1306

1
2
3

1
2
3
/X /X
2200PF/50V /X 1Ohm

2
GND /X mbs_powpak_5p_203x242_colay

2
mbs_powpak5p_203x242_col_ns

2
07005-A1100000

GND GND GND GND GND

07005-A1090000
(6) P_GT_PHASE1_10

(6) P_GT_CSN1A_10

P_VCORE_L+12V_S
VRM Input CAP VCCGT

11031-0004F300

11031-0004F300
270UF/16V PCE1300
11031-0006F200

560UF/6.3V PCE1310

560UF/6.3V PCE1311
1

1
+ + +
2

2
<Variant Name>

Title : VCCGT DRIVER


GND
GND

ASUSTek COMPUTER INC.


Engineer: RAY
Size Project Name Rev
R1.00
A2 SkyLake VC
Date: Monday, June 11, 2018 Sheet 10 of 113
VDDQ

+12V
PQ1501
PK616BA

1
5
D
07005-A0540000 PC1530
PR1500
22UF/6.3V

2
1 2 4

2
0402 /X
PC1500 P_VCCSA_Gate1/2_1_10 G S
0.1UF/16V /X mbs_powpak_5p_203x242_share

1
mbs_c0603 GND

1
2
3
1
PC1501
VCCSA
PU1501
GND 100PF/50V

2
1 8
(13) P_VCCIO_OUT_1_10
P_VCCIO_OUT_1_10 2
VOUT1 VCC
7 PR1502 PR1503 10Ohm PJP1500
(1.05V)
(13) P_VCCIO_IN_1-_10 VIN1- VOUT2
P_VCCIO_IN_1-_10 3 6 P_VCCSA_OUT_2_10 1 2 1 2
(13) P_VCCIO_IN_1+_10 VIN1+ VIN2-
P_VCCIO_IN_1+_10 4 5 P_VCCSA_IN_2-_10 2 1 P_VCCSA_FB_SHORTPIN_10
GND VIN2+
P_VCCSA_IN_2+_10 SHORTPIN

P_VCCSA_FB_10

1
2
1KOhm /X
AS358MTR-E1

2
PR1504 + PCE1511
4.7KOhm PR1506 560UF/4V
mbs_r0603 PJP1501 100Ohm

2
GND 1 2 mbs_r0603
H_VCCSA_VCC_SENSE (36) mbs_cpl_560u6d3vsha_lfh_ms

1
/X

1
SHORTPIN /X 11031-0002F500

1
GND PC1503 PJP1502
1 2 GND
H_SAIO_VSS_SENSE (13,36)
/X 1000PF/50V

2
PR1507 SHORTPIN /X
2 1
(58) P_+VCCSA_OV#_1_10

10.5KOHM GND GND


+3VSB

2
PR1509
10KOhm

1
2

1
P_+VCCSA_OV#_1_10 VCCSA show value VCCSA show value EL-CAP PL-CAP PR1510
4.53KOhm PC1504
1KOHM 0OHM 0.47UF/6.3V

2
1 1.05V 1.054V PR1500

1
P/N:10V212100210 P/N:10V212000040

0 1.15V 1.154V GND GND

+5VSB
EL-CAP PL-CAP

2
820UF/6.3V 560UF/4V
PCE1511 PR1514 P_VCCSA_IN_2+_10
3
P/N:11V040827130 11031V0002F000 18KOHM

3
D

PQ1505

1
11 H2N7002
mbs_r0603
P_VCCSA_C1_10 G
S
2

2
3 PQ1504
PR1512 5.6KOhm C PMBS3904

1
1 B 07V3N2339040
(6,23) O_VCORE_EN_10
O_VCORE_EN_10 2 1 P_VCCSA_B1_10 PC1517
E
/X 10PF/50V

2
2
/X

1
PC1505
0.1UF/16V
/X

2
GND
PR1516 5.6KOhm

(13,23) P_+VCCIO_EN_10
2 1 GND GND GND

PR1513 0Ohm /X
2 1

<Variant Name>

Title : VCCSA
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
A3 KabyLake DEMO R1.00

Date: Monday, June 11, 2018 Sheet 12 of 113


EL-CAP PL-CAP
1KOHM 0OHM
VDDQ PR1600
P/N:10V212100210 P/N:10V212000040

PQ1601
PK616BA

5
D
PC1630
PR1600
22UF/6.3V
2 4 1 2
/X 0402
S G P_VCCIO_Gate_1_10
/X

teknisi indonesia

1
VCCIO GND PC1601

3
2
1
mbs_powpak_5p_203x242_share
100PF/50V
(1.05V)

2
07005-A0540000
PJP1603 PR1603 10Ohm PR1604
P_VCCIO_OUT_1_10 (12)
1 2 1 2 P_VCCIO_OUT_1_10
P_VCCIO_IN_1-_10 (12)
P_VCCIO_FB_SHORTPIN_10 2 1 P_VCCIO_IN_1-_10
P_VCCIO_IN_1+_10 (12)

2
SHORTPIN 1KOhm PR1605 P_VCCIO_IN_1+_10
/X 4.7KOhm
1
2

mbs_r0603
PR1606 + PCE1611

P_VCCIO_FB_10
100Ohm 560UF/4V PR1607

1
mbs_r0603 11031V0002F500 2 1
(62) P_+VCCIO_OV#_1_10
2

/X
mbs_cpl560u6d3v6d3x9lfh_ms
1

10.5KOHM GND
PJP1601
1 2
H_VCCIO_VCC_SENSE (13,36)

GND GND SHORTPIN /X

1
PC1602 PJP1602
1 2
H_SAIO_VSS_SENSE (12,13,36)
/X 1000PF/50V

2
SHORTPIN /X

EL-CAP PL-CAP
GND GND

820UF/6.3V 560UF/4V

PCE1611 P/N:11V040827130 11031V0002F000

H_VCCIO_VCC_SENSE (13,36)

H_SAIO_VSS_SENSE (12,13,36)

P_+VCCIO_OV#_1_10 VCCIO show value VCCIO design value

1 1.05V 1.054V

0 1.15V 1.154V

+3VSB
2

PR1613
10KOhm
1

+5VSB P_VCCIO_IN_1+_10
2

PR1614
4.53KOhm PC1609
2

0.47UF/6.3V
1
2

PR1616
18KOHM GND GND
3
3

D
1

PQ1604
mbs_r0603
11 H2N7002
P_+VCCIO_EN_C_10 G
S
3 2
2

PR1621 5.6KOhm C
1

1 B
(12,23) P_+VCCIO_EN_10 PMBS3904
P_+VCCIO_EN_10 2 1 P_+VCCIO_EN_B_10 PC1613
E PQ1605
10PF/50V
2

2
1

PC1611
0.1UF/16V /X GND
/X
2

GND

GND GND

Title
<Title>

Size Document Number Rev


A3 <Doc> <RevCode>

Date: Monday, June 11, 2018 Sheet 13 of 113


VCCIO VCCSA
1

1
PCB1600 PCB1601 PCB1602 PCB1603 PCB1604 PCB1500 PCB1501 PCB1502 PCB1503 PCB1504 PCB1505
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
2

2
/X /X /X /X /X

GND GND

VCORE

VCCGT
1

1
PCB1000 PCB1001 PCB1002 PCB1003 PCB1004 PCB1005 PCB1006 PCB1007
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
2

1
PCB1300 PCB1301 PCB1302 PCB1303 PCB1304 PCB1305 PCB1306 PCB1307 PCB1308
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V

2
GND /X /X /X /X /X /X /X

GND

VCCGT

VCORE

1
PCB1309 PCB1310 PCB1311 PCB1312
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V

2
/X /X /X /X
1

PCB1008 PCB1009 PCB1010 PCB1011 PCB1012 PCB1013 PCB1014 PCB1015 PCB1016


22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
2

/X /X /X /X /X /X /X /X /X GND

GND

<Variant Name>

Title : VCCGT DRIVER

ASUSTek COMPUTER INC.


Engineer: RAY
Size Project Name Rev
R1.00
A3 SkyLake VC
Date: Monday, June 11, 2018 Sheet 16 of 113
+5VSB_DUAL +3VSB
+5VSB 20170923:S0-->S3,there's a power down glich with 5V_S0IX control,so we change the control to 3V_S0IX,as well,PR2232 is recified to 0402 22kohm
Tss=(VFB*Css)/Iss
=(0.765V*4.7NF)/2uA
=1.798ms +5VSB_ATX +5VSB_ATX

2
P_+1.0A_L+5VSB_S PC2204

1
PR2231 PR2200 PR2230 1UF/16V

1
10KOhm 10KOhm PC2203 mbs_c0603

2
10KOhm /X /X PC2201 PC2202 0.1UF/16V VPPDDR

1
PU2211

2
mbs_c0603 PR2201 PR2202 P_+VPPDDR_EN_10
22UF/6.3V 22UF/6.3V

2
1

2
mbs_c0603 9 3 1KOhm 8.2KOhm
/X VIN1 VREG5 PC2205
10 5 P_+2V5_PVCC_10 GND mbs_r0603 mbs_r0603 3 PQ2202

3
VIN2 GND1 D
mbs_c0603
GND GND GND 8 +VPPDDR_PGD_RR_10 PL2211 /NODDR4SEQ /X H2N7002

2
VBST

1
1 7 P_+2V5_BST_20 1 2 1 2 PR2203 /NODDR4SEQ
EN SW2
P_+VPPDDR_EN_10 4 6 P_+2V5_SW 11
SS SW1 0.1UF/16V (19,96) O_3VSBSW#
P_+2V5_SS_10 11 2 PC2206 2.2UH 2 1 P_VPPDDR_COMP_GATE_10 G
GND2 VFB S
12 2 1 PR2232 40.2KOhm 2

2
GND3

1
13 1 2

P_+2V5_FB_10
1

GND4 +3V mbs_r0603


PR2228 PC2208 22PF/50V PC2215 PC2210 PC2223 PC2218 PC2219
/NODDR4SEQ
10KOhm 4700pF/50V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22KOhm

2
TPS54328DRCR
PC2200 PR2204 PJP2201 /S0IX/NODDR4SEQ
2

/X /X
0.1UF/16V 1 2 1 2 3
2

PR2205 C PQ2203
/X P_+2V5_FB_R_10
1

/X 1 B
49.9KOHM SHORTPIN GND GND GND GND GND PMBS3904
+5V
/X 2 1 P_S_SLP_S4#_10

1
GND PR2206 40.2KOhm E
2 /NODDR4SEQ

1
22KOhm mbs_r0603 PC2214
GND 0.1UF/16V
GND GND /NOS0IX/NODDR4SEQ /X

2
PR2208
GND GND
GND
(17,19,58,96) S_SLP_S4#
1 2 GND
8.2KOhm /X

1
PC2207

1
PR2207 0.1UF/16V
13KOhm /NODDR4SEQ
If using P_VDDQ_SIO_EN_10 from SIO control VDDQ EN,then

2
/NODDR4SEQ
+VPPDDR_PGD_10 need to VPPDDR pull high,that is,PR2210 need

2
mounted and PR2011 need /X.
+5VSB

VPPDDR
+VPPDDR_PGD_10 (17,96)

2
P_+2V5_PVCC_10
PR2209
PR2210 8.2KOhm 3
1

3
D
PR2211 mbs_r0603 GND GND
8.2KOhm 100KOhm PQ2201

1
mbs_r0603 11 H2N7002
PR2212 /DDR4SEQ
/NODDR4SEQ P_VPPDDR_PG_G2_10 G
2

S
1 2 3 2

2
+VPPDDR_PGD_RR_10 +VPPDDR_PGD_10 PR2214 C

1
PR2215
0Ohm VPPDDR 1 B
1

2 1 P_VPPDDR_PG_G1_10 PMBS3904
SHORTPIN_0402
/X PC2217
E PQ2200

1
8.2KOhm PC2216 10PF/50V

2
TEMP_M05_0040 0.1UF/16V 2
/X /X
2

2
P_+1.0A_L+5VSB_S (19) +5VSB_ATX
GND P_+1.0A_L+5VSB_S
If using TPS54328 ,then PR2215/PR2214/PR2209/PQ2200/PQ2201
GND GND GND GND
need mounted and PR2212 need /X. P_+VDDQ_PG1_10
P_+VDDQ_PG1_10 (23)

P_+VPPDDR_EN_10 (19,96)
P_+VPPDDR_EN_10

+VPPDDR_PGD_10 (17,96)
+VPPDDR_PGD_10

2
P_VDDQ_SIO_EN_10 (96)
P_VDDQ_SIO_EN_10 8.2KOhm
PR2221 P_VDDQ_COMP_10
mbs_r0603
PQ2207A

6
1
2 2N7002KDW
P_VDDQ_C1_10

1
1
3

3
D
PC2220
PR2222 10KOhm /NODDR4SEQ PQ2208 10PF/50V

2
2
11 H2N7002
(17,19,58,96) S_SLP_S4#
2 1 P_+VDDQ_B1_10 G /NODDR4SEQ PR2223 /X
S
2 0Ohm

2
+VPPDDR_PGD_C1_10
/DDR4SEQ

1
+5VSB_DUAL

1
PC2221 GND
0.1UF/16V GND
PL2001 /X

2
1 2

11031-0004F300
PCE2001
P_VDDQ_REGIN_S Irms,cin=Io(D(1-D))^0.5
FBN3560B-450

+12V PQ2011 GND


If HMOS is NXP/UBIQ,then PR2003=1Ohm and PR2001=1Ohm PQ2207B

560UF/6.3V

3
1
D PK616BA
If HMOS is ON,then PR2003=1Ohm and PR2001=0Ohm PR2224 10KOhm /NODDR4SEQ
5

PD2000 5% + 5 2N7002KDW
1 PR2001 1Ohm PC2001 +VPPDDR_PGD_10 2 1 +VPPDDR_PGD_R_10

4
3 4 1UF/16V PR2225 10KOhm
2

2 P_VDDQ_VCC_P_20 P_VDDQ_UGATE_M_20 G S mbs_c0603


mbs_r0603 P_VDDQ_SIO_EN_10 2 1

mbs_cpl560u6d3v6d3x9lfh_ms

mbs_cpl560u6d3v6d3x9lfh_ms

mbs_cpl560u6d3v6d3x9lfh_ms

1
BAT54CW /DDR4SEQ PC2222
1
2
3

PC2010 07005-A0540000 0.1UF/16V


1

VDDQ /X
If we use P_VDDQ_SIO_EN_10 from SIO to control

2
470PF/16V
VDDQ EN,then PR2225,PQ2209,PR2223,PR2221,PQ2207
2

11G233047101390 mbs_powpak_5p_203x242_share
1.2V need mounted.Otherwise,we s�ll use S_SLP_S4# and
2

PR2000 GND PL2012

11031V0002F500

11031V0002F500

11031V0002F500
2.2Ohm +VPPDDR_PGD_10 to control VDDQ EN.

PCE2012
1 2

PCE2011
GND GND

PCE2013
mbs_r0805 5%
1

1.2UH
1

09011-00060800
PC2003 PC2002
PR2003

560UF/4V

560UF/4V
4700PF/50V
P_VDDQ_SNB
2

560UF/4V
1

1
2 1 PQ2012 mbs_c0603
P_VDDQ_BOOT_R_20 + + +

1
1Ohm mbs_r0603
D PK616BA
5

0.1UF/16V mbs_c0603
5% PC2004
2

2
10UF/6.3V
1

2
4 PR2006 mbs_c0603
2

P_VDDQ_BOOT_20 G S 1Ohm /X
PU2011 PR2007 mbs_r1206 +5VSB_ATX VDDQ
20KOhm 5% /X
1
2
3

2
13 mbs_r0603 07005-A0540000
12
GND3 VDDQ Bleed circuit PR2004

1
GND2
1

11 PR2005
GND1 51Ohm
10 1 mbs_powpak_5p_203x242_share 8.2KOhm
0.01UF/16V

REFOUT BOOT GND GND


1 P_VDDQ_REFOUT_10
2 9 2 GND mbs_r0603
OFS UG

1
P_VDDQ_OFS_10 8 3 P_VDDQ_UGATE_20 GND

2
POK PH
PR2008 255Ohm P_+VDDQ_PG1_10 7 4 P_VDDQ_PHASE_20 GND
COMP/EN LG/OCS /X
1

PC2006 6 5 P_VDDQ_LGATE_20
FB VCC
GND PC2005 P_VDDQ_VCC_20 P_+VDDQ_S
0.022UF/16V UP1540PDDA PR2009 499Ohm PJP2001
2

2
/X 1 2 1 2 P_+VDDQ_G_10

3
D
mbs_dfn_10p_s118_p_2v_half
P_VDDQ_FB_10 P_VDDQ_FB_shortpin 3 PR2020

3
D
SHORTPIN PQ2016 SHORTPIN_0402
PC2008
2

PR2012 /X PQ2015 11 H2N7002


11
1

GND GND PR2010 PC2007 PR2011 2 1 1 2 H2N7002 G


P_VDDQ_COMP_10

1
1 2 2 1 PC2000 976OHM P_VDDQ_FB_C_10 (17,19,58,96) S_SLP_S4# G 2

2
S TEMP_M05_0040
P_VDDQ_FB_R_10 1UF/16V 10Ohm 2

2
0.068UF/16V /X
2

/X

1
32.4KOhm mbs_c0603
/X
1

1
3300PF/50V PR2013 7.87KOhm PC2015
PC2009 1 2 PC2014
P_+VDDQ_OV#_1_10 (57) 10PF/50V

2
2 1 P_+VDDQ_OV#_1_10 10PF/50V GND

2
GND GND /X
PR2019 2.61KOHM /X
10PF/50V
1 2 GND
P_+VDDQ_OV#_2_10 (57)
P_+VDDQ_OV#_2_10 GND GND
GND

P_+VDDQ_OV#_1_10 P_+VDDQ_OV#_2_10 VDDQ show value VDDQ design value

X X 1.2V 1.209V

0 X 1.25V 1.256V

X 0 1.35V 1.362V

0 0 1.40V 1.413V

<Variant Name>

Title : 1.2VDUAL

ASUSTek COMPUTER INC.


Engineer: RAY
Size Project Name Rev
R1.00
A1 SkyLake VC
Date: Monday, June 11, 2018 Sheet 17 of 113
VDDQ

2
PR2102
10KOhm

1
P_VTT_DDR_REFIN_10
VDDQ ===> VTT_DDR combine RT9040
Io:0.75A
+3V +3V

1
PR2103 PC2101
10KOhm 0.1UF/16V PR2100

1
PR2101

2
8.2KOhm 10Ohm

1
PU2101 5%
VDDQ VTT_DDR 13 mbs_r0603

2
GND4
12
GND3
11
GND2
GND 1 10
REFIN VCNTL
2 9 P_VTT_DDR_CTRL_10
VIN PGOOD
3 8
VOUT GND1

1
4 7
PGND EN
1

5 6 P_VTT_DDR_EN_10 PC2100
VSENSE REFOUT
1

1
PC2102 PC2103 PC2104 P_VTT_DDR_REOUT_10 4.7UF/6.3V

2
P_VTT_DDR_VOSNS_10
22UF/6.3V 22UF/6.3V 22UF/6.3V PC2106 PC2111 UP8815PDDA mbs_c0603
2

1
mbs_c0603 22UF/6.3V 22UF/6.3V s_dfn_10p_s118_colay2v_half PC2107
/X
2

2
0.1UF/16V

1
mbs_c0603 /X
PJP2100

2
GND SHORTPIN
GND GND GND GND GND /X GND

GND

2
GND

1
PC2108
0.1UF/16V

2
PR2105

GND 1 2

0Ohm
+5VSB_ATX
/X

2
PR2106
8.2KOhm P_VTT_DDR_EN_10
mbs_r0603

1
3

3
D

PQ2101
11 H2N7002
PR2107 P_DDR_VTT_C_10 G
S
1 2 2

2
(20,23,58,96) S_SLP_S3#
S_SLP_S3# DDR_VTT_CNTL_B_R_10
10KOhm /X

1
3 PC2110
PR2108 PR2109 C
10PF/50V GND

2
1 2 1 B
(35) H_DDR_VTT_CNTL PMBS3904
2 1 DDR_VTT_CNTL_B_10 /X
0Ohm 1KOhm E PQ2102
2
2

PR2110
20KOhm PC2109 GND
/X 0.1UF/16V
2

/X
1

GND GND
GND

<Variant Name>

Title : VPPDDR
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
R1.00
A2 SkyLake DEMO
Date: Monday, June 11, 2018 Sheet 18 of 113
If IC is NB671LB,then PR300's op�onal is N/A.

If IC is RT6220A,then PR3000's op�onal is /X.

PR3001

+5VSB 2 1 P_+1.0V_A_BST_R_20
P_+1.0V_A_BST_20
+5VSB +1.8VSB +3VSB 4.7Ohm
PL3001
1 2
P_+1.0A_L+5VSB_S
JA-300P05003
2

1
PC3001 PC3002 PC3003 PC3004

2
PR3002 PR3003 10UF/16V 10UF/16V 0.1UF/16V 0.1UF/16V

10
10KOhm PR3031 10KOhm PU3011

2
10KOhm

BOOT
/X 1 +1.0V_A
VIN
1

1
/X 8 PL3011
SW1
1

GND GND GND 9 1 2


SW2
13 15

1UF/6.3V
PC3005 P_+1.0V_A_SW_20
EN SW3
P_+1.0A_EN_10 +5VSB 16 1UH
PR3005 SW4
2

2
RT6220AGQUF 09016-00015900

1
PR3004 3 7 PR3006 PC3006 PC3007 PC3008 PC3009 PC3010
2

VBYP VOUT
10KOhm 1 2 P_+1.0V_A_LP#_10 1MOHM 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
5 12 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603
1

AGND1 FB

2
2.2Ohm 6 /X
AGND2
1

1
/X

AGND3

1
PGND
VCC
mbs_r0603 PJP3001

PG
GND GND PR3000 PR3007 SHORTPIN GND GND GND GND GND
200KOHM 1 2

11

14

2
P_+1.0V_A_FB_10 499Ohm P_+1.0V_A_FBR_10
mbs_r0603 PC3011

2
2 1

2
/X PC3012
GND 220PF/50V 220PF/50V

1
/X
/X
PR3008 6.8KOhm
1 2
(64) P_+1.0A_PG_10
P_+1.0A_PG_10 P_+1.0V_A_VOUT_10

1
PC3013

2
PR3010 0.1UF/16V
/X 100KOhm PR3011

2
mbs_r0603
10KOhm
2

GND

1
+1.0V_A_VCC_20

P_+1.0V_A_FB_R_10
(17) P_+1.0A_L+5VSB_S
1

PC3000
2.2UF/6.3V
2

mbs_c0603

GND GND GND PR3013


2 1
P_+1.0A_OV1_10 (57)
P_+1.0A_OV1_10
44.2KOHM

P_+1.0A_OV1_10 +1.0A Show value +1.0A Design value

1 1.00V 1.008V(deafault)

+5VSB_ATX
0 1.1V 1.1098V
2

PR3014
10KOhm P_+1.0A_EN_10
+1.8VSB +3VSB
1

mbs_r0603
2

PQ3004B PR3015 /X VCCST_VCCSFR


3

/X
PR3016 PR3033 +1.0V_A 1 2
10KOhm 10KOhm 5 2N7002KDW +5VSB_ATX
P_+1.0A_C_10 0Ohm
4

/X
1

mbs_r0603 mbs_r0603 PQ3002


1

/X /X
3 PC3018

S
D
C 3 2
10PF/50V

2
2

1 B

G
PMBS3904
P_+1.0A_B_10 /X

11
E PQ3003 AP2306GN

1
PC3016 /X 2 PR3023
GND
1

PR3019 8.2KOhm

1
PR3018 mbs_r0603
3.9KOHM GND PR3024
0.1UF/16V 8.2KOhm /X

2
2

mbs_r0603
2

/X P_+VPPDDR_EN_10 (17,96)
/X P_VCCST_VCCSFR_D1_10 2 1 P_+VPPDDR_EN_10
2
/X
0Ohm
PC3015

2
PQ3004A 5%

6
PR3017
GND GND GND 0.1UF/16V

1
2 2N7002KDW
(17,96) O_3VSBSW# /X
1 2 P_VCCST_VCCSFR_C1_10 /X

1
/X
PR3030 10KOhm
1

mbs_r0603 GND
mbs_r0603 PC3019
+5V
1 2 10PF/50V
2

10KOhm /X
3 /X
PR3025 C PQ3005
1 2 1 B PMBS3904
+3V
GND GND
E
2

1KOhm PC3017
PR3022 0.1UF/16V 2
/X
8.2KOhm /X /X
2

PR3020
1 2 /X
(17,58,96) S_SLP_S4#
1

10KOhm /X

GND GND GND

<Variant Name>

Title : +1.0A/+VCCST_VCCSFR

ASUSTek COMPUTER INC.


Engineer: Jun_Zhang
Size Project Name Rev
R1.00
A2 Coffeelake
Date: Monday, June 11, 2018 Sheet 19 of 113
+5VSB
If OVP protec�on circuit isn't mounted,then PC4001 and PC4002 aren't also mounted.
+5VSB
+12V +5V

NOTE:which power rail powerd to audio ic should be confirmed by EE. PQ4001


PK616BA

2
+5VSB_ATX 3

1
PR4001 2 5

D
40.2KOhm 1 PC4001
mbs_r0603 10UF/16V

2
1.Vin and Vout keep more than 30mils away. mbs_c0805

4
1
mbs_powpak_5p_203x242_share

2
2.Input cap and Output cap can't use same GND. 07005-A0540000
PR4000
Note: PC4001靠近PQ4002放置
3.P_5VSB_GATE_10 is away from Vin more than 15mils ,from Vout more than 30mils. 4.7KOhm
mbs_r0603 P_5VSB_GATE1_10
3
PR4002

1
C PQ4003
1 B PMBS3904
2 1 P_5VSB_Q2_10
E +5VSB_ATX GND
8.2KOhm 2

2
PQ4002

1
PR4003
PC4000 4.7KOHM EMB20P03A Note: +5VSB_ATX +5VSB_ATX
0.047UF/16V

2
P_5VSB_GATE_10 is about 15mil or more

D
S
1
GND distance apart from other power rail.

2
G
1
1

2
GND GND +5VSB_ATX
PC4002 PR4004
10UF/16V 10KOhm
2

1
mbs_c0805 E
PC4003 mbs_r0603 PMBS3906

1
2
0.068UF/16V P_+5VSB_ATX_OV_B_10 B 1

2
PR4005 C
8.2KOhm

1
PR4006 PQ4004
3
FOR O_PWROK mbs_r0603 PC4004
10KOhm
S0 GND mbs_r0603 100PF/50V

2
P_5VSB_GATE_10

1
1
P_+5VSB_ATX_OV_G_10
P_5VSB_GATE_10_1
0
3 P_5VSB_GATE_10 +5VSB
PR4007 C PQ4005
DS5/S5/S4/S3 DS5/S5/S4/S3
1 B PMBS3904

2
P_5VSB_Q1_10 P_5VSB_Q1_10 2 1 P_5VSB_Q3_10
E

2
PR4008
8.2KOhm 2
PR4010

1
3 4.7KOHM 3 2.94KOhm

3
D
3 PC4013 C PQ4008
3

1
PQ4007 10PF/50V B 1
PR4009

2
PQ4006 11 H2N7002 P_+5VSB_ATX_OV_REF_10
(96,101,105) O_DEEP_S5 E
11 H2N7002 G /X PMBS3904
(20,65,96,105,113) O_PWROK S 2
2 1 P_5VSB_B1_10 G 2 /EUP

2
S

1
2 GND
2

8.2KOhm
1

2
PC4016 GND GND
PC4015 10PF/50V PC4005 PR4011

2
2
10PF/50V 0.1UF/16V 4.7KOhm
2

/X /X mbs_r0603

1
/X P_5VSB_Q1_S_10 GND

1
P_+5VSB_ATX_OV_E_10
GND
3 PR4012 300OHM /X
3

D
GND 1 2
PQ4012 PR4026 +5VSB_ATX s_r0805_h24
1

11 H2N7002 SHORTPIN_0402
(23) S_SLP_S0#_IDLE
G PR4024 300OHM /X GND GND
2
S
/S0IX
FOR O_DEEP_S5
TEMP_M05_0040 1 2
2

/X s_r0805_h24
2
1

PC4034 DS5 PQ4009 PR4013 PR4014


0.1UF/16V 1 PR4025 300OHM /X PMBS3904 1 2 1 2
+3VSB_ATX
/X 1 2 P_+5VSB_ATX_OV_E_R_10

E
2
C
2

s_r0805_h24 P_5VSB_SHORT_10 499Ohm 499Ohm

2
0 /X PC4006

2
PR4015

1 B
GND GND S5/S4/S3/S0 S5/S4/S3/S0 8.2KOhm 0.1UF/16V

1
GND
Inrush circuit is available as matching UVP circuit.

1
GND GND

Inrush Circuit for USB Port default have Power or Flash Back Function
PR4516 2 1 1KOhm
P_5VSB_GATE_10 mbs_r0603

S5 ----> S0 S0 ----> S3 +5VSB_ATX ====>+3VSB_ATX Io:1.5A


PR4517 1 2 1KOhm
P_5VSB_USB_GATE_10 P_5VSB_GATE_10_1 mbs_r0603 P_5VSB_GATE_R_10 +5VSB_ATX PU4001
+3VSB_ATX
3 2

ADJ/GND
IN OUT

P_5VSB_USB_GATE_10_1 ( +3.38V )
+5VSB_ATX
AZ2185D-ADJTRG1

2
PR4020
S_SLP_A# PR4518 100kOhm
1 2 1.27KOhm
mbs_to252_share_lf3

mbs_r0603

1
S_SLP_S3# PQ4508
3

E
2
C

PD4500

1
1 PMBS3904
+5V 3 PC4011 P_+3VSB_ATX_ADJ_20 PC4022
1 B

ITE: 150 ms 2 10UF/16V 22UF/6.3V

2
NCT: 300

2
P_5VSB_GATE_D_10

ms BAT54AW P_5VSB_GATE_B1_10 PR4022


2

O_PWROK mbs_c0805 2.15KOhm


PR4519
1KOhm +5VSB

1
mbs_r0603
PR4520
1

+5V 100KOhm PC4509


1 2 2 1
P_5VSB_GATE_RC_10
(18,23,58,96) S_SLP_S3#
2

mbs_r0603 mbs_c0603 GND


0.01UF/16V
PR4521
8.2KOhm
2

PR4522 mbs_r0603 PC4510 2 1 0.22uF/16V /X


8.2KOhm /NOS0IX 3 mbs_c0603
PR4527
1

C PQ4509
1 B PMBS3904
1

P_SLPS3#_C1_10 2 1 P_5VSB_RC1_B_10 GND


3 8.2KOhm E
2
2

C PQ4510
1 B
1

PMBS3904 PR4523 PC4511


P_SLPS3#_R_10 8.2KOhm
E 0.1UF/16V
2

3 2
1

/X
3

D
1

PC4512 GND
PQ4511 0.1UF/16V
2

11 H2N7002 /X GND GND GND


(20,65,96,105,113) O_PWROK
G
S
2
2
1

GND
PC4513
0.1UF/16V
P_SLPS3#_C1_10 (21)
2

/X GND P_SLPS3#_C1_10

GND

don't need for Flash Back

<Variant Name>

Title : +5VSB/+3VSB_ATX/+1.8V_A

ASUSTek COMPUTER INC.


Engineer: Mandy_cao
Size Project Name
KabyLake DEMO Rev
R1.00
A0

Date: Monday, June 11, 2018 Sheet 20 of 113


If OVP protec�on circuit isn't mounted,then PC4501 isn't also mounted.

1.Vin and Vout keep more than 30mils away.

2.Input cap and Output cap can't use same GND.

3.P_5VSB_GATE_10 is away from Vin more than 15mils ,from Vout more than 30mils.
+5VSB_ATX
+5VSB_DUAL +5VSB_ATX
+12V +5V
+5VSB_DUAL

2
2016/06/30 modify +5VSB_ATX to +5VSB PQ4500
PR4501
PK616BA
10KOhm

2
+5VSB 3 mbs_r0603

S
PR4502 2 5 /5VSB_DUAL_OVP

D
2

1
40.2KOhm 1 E PQ4502
mbs_r0603 PMBS3906

G
P_+5VSB_DUAL_OV_B_10 B 1

4
1

2
mbs_powpak_5p_203x242_share C
/5VSB_DUAL_OVP
2

1
07005-A0540000 PR4503
3
PR4500 PC4501 10KOhm PC4502
4.7KOhm 10UF/16V mbs_r0603 100PF/50V

2
mbs_r0603 P_5V_USB_GATE_10 mbs_c0805 /5VSB_DUAL_OVP /5VSB_DUAL_OVP

1
3 /5VSB_DUAL_OVP
PR4505
1

C PQ4503 P_+5VSB_DUAL_OV_G_10
1 B PMBS3904
2 1 P_5V_USB_Q2_10
PC4501靠近PQ4501放置 P_5VSB_USB_GATE_10
E
2
+5VSB_ATX +5VSB_DUAL
8.2KOhm 2
PR4506

1
4.7KOHM
PQ4501

2
PC4500
EMB20P03A PR4508
0.047UF/16V
1

2
/5VSB_DUAL_OVP GND 2.94KOhm
3 /5VSB_DUAL_OVP

D
S
GND GND GND C PQ4506

1
B 1

G
P_+5VSB_DUAL_OV_REF_10

1
E

1
+5VSB_ATX PMBS3904
PC4503 2 /5VSB_DUAL_OVP
10UF/16V
Note:

2
mbs_c0805
PC4506 P_5VSB_USB_GATE_10 is about 15mil or PC4507 PR4509

2
/5VSB_DUAL_OVP

2
0.068UF/16V more distance apart from other power rail. 0.1UF/16V 4.7KOhm

2
PR4510 /5VSB_DUAL_OVP /X/5VSB_DUAL_OVP mbs_r0603

1
8.2KOhm /5VSB_DUAL_OVP

P_+5VSB_DUAL_OV_E_10

1
mbs_r0603
GND
1

P_5VSB_USB_GATE_10

GND GND
P_5VSB_USB_GATE_10_1
3
PR4511 C PQ4507 PR4512 PR4513
1 B PMBS3904 1 2 1 2
(105) P_5V_USB_Q1_10 +3VSB_ATX
2 1 P_5V_USB_Q3_10 P_+5VSB_DUAL_OV_E_R_10
E
2

499Ohm /5VSB_DUAL_OVP 499Ohm /5VSB_DUAL_OVP


8.2KOhm 2

2
PR4514 PC4517 PC4508

2
4.7KOHM 10PF/50V PR4515 0.1UF/16V
2

+5VSB_ATX 8.2KOhm /5VSB_DUAL_OVP

1
/X /5VSB_DUAL_OVP
1

1
GND
PR4526 300OHM GND GND
1 2
s_r0805_h24 PQ4512 GND GND
PR4528
/X 300OHM PMBS3904
1 2
3

E
2
C

s_r0805_h24 P_5VSB_DUAL_SHORT_10
/X PR4529 300OHM /X
1 2
1 B

s_r0805_h24 Modify:2017/01/22, 5VSB DUAL UVP circuit unmounted


/X

+5VSB_DUAL Inrush Circuit for USB Port default have Power

S5 ----> S0 S0 ----> S3

P_5VSB_USB_GATE_10
PR4600 4.7KOhm
P_5VSB_USB_GATE_10 mbs_r0603 2 1

P_5VSB_USB_GATE_10_1

S_SLP_A# PR4601 1 2 1KOhm


P_5VSB_USB_GATE_10_1 mbs_r0603 P_5VSB_DUAL_GATE_R_10

S_SLP_S3#

+5VSB_ATX

+5V
ITE: 150 ms PR4602 100kOhm
NCT: 300 1 2
ms
O_PWROK mbs_r0603 /USB_Inrush
PQ4600
3

E
2
C

PD4600
1 PMBS3904
3 /USB_Inrush
1 B

BAT54AW P_5VSB_DUAL_GATE_B1_10
2

/USB_Inrush
PR4603
1KOhm +5VSB_DUAL
mbs_r0603
PR4604 /USB_Inrush Modify:2017/01/22,0.047uf to 0.01uf
1

100KOhm
1 2 PC4600 2 1 0.01UF/16V
P_5VSB_DUAL_GATE_D_10 P_5VSB_DUAL_GATE_RC_10 X7R /USB_Inrush
mbs_r0603 mbs_c0603
/USB_Inrush

PC4601 2 1 0.22uF/16V /X/USB_Inrush


3 X7R mbs_c0603
PR4605 C PQ4601
1 B PMBS3904
(20) P_SLPS3#_C1_10
P_SLPS3#_C1_10 2 1 P_5VSB_DUAL_RC1_B_10 /USB_Inrush GND
8.2KOhm E
2
2

/USB_Inrush
1

PR4606 PC4602
8.2KOhm
0.1UF/16V
2

/USB_Inrush /X/USB_Inrush
<Variant Name>
1

GND

GND GND Title : +5VSB


ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
A2 Kabylake demo R1.00

Date: Monday, June 11, 2018 Sheet 21 of 113


+12V_CPU +5VSB PR5001 0Ohm /X
+5VSB_ATX 2 1
P_+12V/3V_EN_10 O_VCORE_EN_10
PR5002

1
PR5005 1 2

1
0402 P_+VCCIO_EN_10 (12,13,23)
13.3KOhm PR5003

1
PR5004 mbs_r0603 40.2KOhm /X
4.7KOhm /NOSIOSEQ mbs_r0603

2
O_VCORE_EN_10 (6,12)
mbs_r0603 3

3
D
/NOSIOSEQ

1
PQ5000B PQ5001

3
PC5001 P_+12V_EN_R1_10 11 H2N7002

1
5 2N7002KDW 0.1UF/16V PR5035 P_+12V/3V_EN_C1_10 G

1
S

2
P_VREN#_10 13.3KOhm PR5006 2

2
1
/NOSIOSEQ /X mbs_r0603 0Ohm
/NOSIOSEQ 3 PC5003

2
/X
PQ5000A PR5007 10KOhm C
0.1UF/16V

2
6

2
PR5000 1 2 1 B

/NOSIOSEQ
PMBS3904

10PF/50V
1 2 2 2N7002KDW P_+12V_EN_B1_10
/NOSIOSEQ /X

PC5000
(18,20,58,96) S_SLP_S3#

0.1UF/16V
P_VREN_10 /NOSIOSEQ E PQ5003
GND

PC5002
10KOhm P_+12V_EN_R2_10 2 /NOSIOSEQ
GND GND

1
P_VR_READY_10 (23,65)

2
/NOSIOSEQ
PR5008

2
3.9KOHM

1
/X /NOSIOSEQ

1
GND

GND PQ5004A

6
GND GND

P_+12V/3V_EN_C2_10
2 2N7002KDW
/NOSIOSEQ +3V

1
PR5009
10KOhm
GND /NOSIOSEQ

2
P_+VCCIO_EN_10 (12,13,23)

1
PQ5004B C

P_+3V_EN_R2_10
PR5010 10KOhm

3
PC5004 1 2 1 B

/NOSIOSEQ
0.1UF/16V
5 PMBS3904
2N7002KDW 0.1UF/16V P_+3V_EN_B2_10

PC5006
2
/NOSIOSEQ E PQ5006

4
/NOSIOSEQ /X 2 /NOSIOSEQ
1

2
PC5005

1
10PF/50V PR5011

1
2

5.6KOhm
/X GND /NOSIOSEQ

2
GND

GND GND
GND

PR5012

2 1
VDDQ
0Ohm
/SIOSEQ
5%

+3V +5VSB_ATX

2
PR5020
1KOhm

PR5019

1
2

PR5013
PR5014 1 2
1KOhm 8.2KOhm 0402
mbs_r0603 /X

P_+VDDQ_PG1_10
/NOSIOSEQ
1

+5VSB_ATX +3VSB
PQ5007
(23,65) P_VR_READY_10

2
3
3

D H2N7002
/NOSIOSEQ PR5018
1KOhm

2
11 /X
G P_VCORE_PG#_10 PR5017
S

1
2 10KOhm P_+VCCIO_EN_10 (12,13,23)
2

mbs_r0603 P_+VCCIO_EN_10
1

PC5007 PC5015 3 PQ5008

1
0.1UF/16V C PMBS3904 3
10PF/50V

3
D
2

/X B 1 /X
P_VRM_PGD_10 (6)
2

/X P_VRM_PGD_10 PQ5011
E
1

/NOSIOSEQ 11 H2N7002
2 PC5008 P_+VDDQ_PG_B2_10 G
GND S
1000PF/50V 3 2

2
2

1
/X PR5016 C
1 B /X
1 2 PC5011
(17) P_+VDDQ_PG1_10 PMBS3904
GND P_+VDDQ_PG_B1_10 10PF/50V

2
E PQ5010

1
GND GND GND 10KOhm
PC5010 2 /X
/X
10PF/50V /X

2
/X GND GND GND

GND

+5VSB

P_+VCCIO_PG_10 (6)
2

PR5015
8.2KOhm 3
3

D
mbs_r0603
PQ5016
1

P_VCCIO_PG_G2_10 11 H2N7002
G
S
2
2

3
PR5021 C
1

VCCIO 1 B
2 1 PMBS3904
P_VCCIO_PG_G1_10 PC5018
E PQ5015
1

8.2KOhm PC5009 10PF/50V


2

0.1UF/16V 2
/X /X
2

P_+VCCIO_PG_S0#_IDLE_10
GND PR5041
1

SHORTPIN_0402
3
3

D
GND GND TEMP_M05_0040
PQ5017 /X
2

11 H2N7002
(20) S_SLP_S0#_IDLE
1

PC5019 G
S
0.1UF/16V 2 /S0IX
2

/X
2

GND
<Variant Name>
GND GND

Title : POWER SEQUENCE


ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
R1.00
A2 coffeelake demo
Date: Monday, June 11, 2018 Sheet 23 of 113
whether 5V&3V dummy load need moun�ng,please confirm with EE.

+3V

2
PR5029 PR5030 PR5031 +5VSB_ATX +12V
100Ohm 100Ohm 100Ohm

2
s_r1206_h26 s_r1206_h26 s_r1206_h26

1
1

1
PR5027 PR5028
8.2KOhm 180Ohm
mbs_r0603 mbs_r2512_colay
/X /X

1
P_+12V_DUMMY_R1

PQ5013A

6
2 2N7002KDW
(55) O_+12V_DUMMYLOAD1
/X

1
1
GND PC5017
10PF/50V

2
/X
GND
GND

+12V
+5V

2
PR5039
2

180Ohm
PR5026 mbs_r2512_colay
200OHM /X

1
s_r1206_h26
/X P_+12V_DUMMY_R3
1

PQ5013B

3
5 2N7002KDW

4
/X

GND

+12V

2
PR5040
GND 180Ohm
mbs_r2512_colay
/X
1 P_+12V_DUMMY_R2
3
3
D

DUMMY LOAD
PQ5012
H2N7002
11
G /X
S
2
2

GND

<Variant Name>

Title : NA
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
R1.00
A3 KabyLake DEMO
Date: Monday, June 11, 2018 Sheet 25 of 113
4 Pin +12V Connector

0801

顏色: W
+12V_CPU

ATX12V

5
NP_NC
2 4
2 4
1 3
1 3

POWER_CON_4P

1
BC6
GND 0.1UF/16V

2
/X/PWR_CON

GND

<Variant Name>

Title : NA
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
A KabyLake DEMO R1.00

Date: Monday, June 11, 2018 Sheet 30 of 113


LGA1151C

B8 A5
(51) H_X16_SL1_RXP0 PEG_RXP[0] PEG_TXP[0] H_X16_SL1_TXP0 (51)
B7 A6
(51) H_X16_SL1_RXN0 PEG_RXN[0] PEG_TXN[0] H_X16_SL1_TXN0 (51)

C7 B4
(51) H_X16_SL1_RXP1 PEG_RXP[1] PEG_TXP[1] H_X16_SL1_TXP1 (51)
C6 B5
(51) H_X16_SL1_RXN1 PEG_RXN[1] PEG_TXN[1] H_X16_SL1_TXN1 (51)

D6 C3
(51) H_X16_SL1_RXP2 PEG_RXP[2] PEG_TXP[2] H_X16_SL1_TXP2 (51)
D5 C4
(51) H_X16_SL1_RXN2 PEG_RXN[2] PEG_TXN[2] H_X16_SL1_TXN2 (51)

E5 D2
(51) H_X16_SL1_RXP3 PEG_RXP[3] PEG_TXP[3] H_X16_SL1_TXP3 (51)
E4 D3
(51) H_X16_SL1_RXN3 PEG_RXN[3] PEG_TXN[3] H_X16_SL1_TXN3 (51)

F6 E1
(51) H_X16_SL1_RXP4 PEG_RXP[4] PEG_TXP[4] H_X16_SL1_TXP4 (51)
F5 E2
(51) H_X16_SL1_RXN4 PEG_RXN[4] PEG_TXN[4] H_X16_SL1_TXN4 (51)

G5 F2
(51) H_X16_SL1_RXP5 PEG_RXP[5] PEG_TXP[5] H_X16_SL1_TXP5 (51)
G4 F3
(51) H_X16_SL1_RXN5 PEG_RXN[5] PEG_TXN[5] H_X16_SL1_TXN5 (51)

H6 G1
(51) H_X16_SL1_RXP6 PEG_RXP[6] PEG_TXP[6] H_X16_SL1_TXP6 (51)
H5 G2
(51) H_X16_SL1_RXN6 PEG_RXN[6] PEG_TXN[6] H_X16_SL1_TXN6 (51)

J5 H2
(51) H_X16_SL1_RXP7 PEG_RXP[7] PEG_TXP[7] H_X16_SL1_TXP7 (51)
J4 H3
(51) H_X16_SL1_RXN7 PEG_RXN[7] PEG_TXN[7] H_X16_SL1_TXN7 (51)

K6 J1
(51) H_X16_SL1_RXP8 PEG_RXP[8] PEG_TXP[8] H_X16_SL1_TXP8 (51)
K5 J2
(51) H_X16_SL1_RXN8 PEG_RXN[8] PEG_TXN[8] H_X16_SL1_TXN8 (51)

L5 K2
(51) H_X16_SL1_RXP9 PEG_RXP[9] PEG_TXP[9] H_X16_SL1_TXP9 (51)
L4 K3
(51) H_X16_SL1_RXN9 PEG_RXN[9] PEG_TXN[9] H_X16_SL1_TXN9 (51)

M6 L1
(51) H_X16_SL1_RXP10 PEG_RXP[10] PEG_TXP[10] H_X16_SL1_TXP10 (51)
M5 L2
(51) H_X16_SL1_RXN10 PEG_RXN[10] PEG_TXN[10] H_X16_SL1_TXN10 (51)

N5 M2
(51) H_X16_SL1_RXP11 PEG_RXP[11] PEG_TXP[11] H_X16_SL1_TXP11 (51)
N4 M3
(51) H_X16_SL1_RXN11 PEG_RXN[11] PEG_TXN[11] H_X16_SL1_TXN11 (51)

P6 N1
(51) H_X16_SL1_RXP12 PEG_RXP[12] PEG_TXP[12] H_X16_SL1_TXP12 (51)
P5 N2
(51) H_X16_SL1_RXN12 PEG_RXN[12] PEG_TXN[12] H_X16_SL1_TXN12 (51)

R5 P2
(51) H_X16_SL1_RXP13 PEG_RXP[13] PEG_TXP[13] H_X16_SL1_TXP13 (51)
R4 P3
(51) H_X16_SL1_RXN13 PEG_RXN[13] PEG_TXN[13] H_X16_SL1_TXN13 (51)

T6 R2
(51) H_X16_SL1_RXP14 PEG_RXP[14] PEG_TXP[14] H_X16_SL1_TXP14 (51)
T5 R1
(51) H_X16_SL1_RXN14 PEG_RXN[14] PEG_TXN[14] H_X16_SL1_TXN14 (51)

U5 T2
(51) H_X16_SL1_RXP15 PEG_RXP[15] PEG_TXP[15] H_X16_SL1_TXP15 (51)
U4 T3
(51) H_X16_SL1_RXN15 PEG_RXN_15 PEG_TXN[15] H_X16_SL1_TXN15 (51)
VCCIO

HR1 1 2 L7
PEG_RCOMP
24.9Ohm H_PEG_RCOMP
PLACE Inside CPU Cavity
Trace W/S: 12/15 mils, Length: 400mils

Y3 AC2
(56) H_DMI_RXP0 DMI_RXP[0] DMI_TXP[0] H_DMI_TXP0 (56)
Y4 AC1
(56) H_DMI_RXN0 DMI_RXN[0] DMI_TXN[0] H_DMI_TXN0 (56)

AA4 AD3
(56) H_DMI_RXP1 DMI_RXP[1] DMI_TXP[1] H_DMI_TXP1 (56)
AA5 AD2
(56) H_DMI_RXN1 DMI_RXN[1] DMI_TXN[1] H_DMI_TXN1 (56)

AB4 AE2
(56) H_DMI_RXP2 DMI_RXP[2] DMI_TXP[2] H_DMI_TXP2 (56)
AB3 AE1
(56) H_DMI_RXN2 DMI_RXN[2] DMI_TXN[2] H_DMI_TXN2 (56)

AC4 AF2
(56) H_DMI_RXP3 DMI_RXP[3] DMI_TXP[3] H_DMI_TXP3 (56)
AC5 AF3
(56) H_DMI_RXN3 DMI_RXN[3] DMI_TXN[3] H_DMI_TXN3 (56)

SOCKET1151
12001V00180100

Title : LGA1151 (DMI/PEG)

ASUSTek Computer Inc.


Engineer: Jay_Tong
Size Project Name Rev
A3 CFL CHIPSET DEMO R1.00

Date: Monday, June 11, 2018 Sheet 31 of 113


LGA1151D

C21 E10 1 HT1


(44) H_DP_TXP0 DDI1_TXP[0] EDP_TXP[0]
D21 D10 1 HT2
(44) H_DP_TXN0 DDI1_TXN[0] EDP_TXN[0]
D22 D9 1 HT3
(44) H_DP_TXP1 DDI1_TXP[1] EDP_TXP[1]
E22 C9 1 HT4
DP (44) H_DP_TXN1 DDI1_TXN[1] EDP_TXN[1]
B23 H10
(44) H_DP_TXP2 DDI1_TXP[2] EDP_TXN[2] H_DP2VGA_TXN0 (48)
A23 G10
(44) H_DP_TXN2 DDI1_TXN[2] EDP_TXP[2] H_DP2VGA_TXP0 (48)
C23 G9
(44) H_DP_TXP3 DDI1_TXP[3] EDP_TXN[3] H_DP2VGA_TXN1 (48)
D23 F9
(44) H_DP_TXN3 DDI1_TXN[3] EDP_TXP[3] H_DP2VGA_TXP1 (48) DP to VGA IC
B13 D12
(44) H_DP_AUXP DDI1_AUXP EDP_AUXP H_DP2VGA_AUXP (48)
C13 E12
(44) H_DP_AUXN DDI1_AUXN EDP_AUXN H_DP2VGA_AUXN (48)

B18
(45) H_HDMI_TXDP2 DDI2_TXP[0]
A18
(45) H_HDMI_TXDN2 DDI2_TXN[0]
D18 D14 1 HT5 VCCIO
(45) H_HDMI_TXDP1 DDI2_TXP[1] EDP_DISP_UTIL
E18 H_EDP_DISP_UTIL
HDMI (45) H_HDMI_TXDN1 DDI2_TXN[1]
C19
(45) H_HDMI_TXDP0 DDI2_TXP[2]
D19 M9 HR2 1 2
(45) H_HDMI_TXDN0 DDI2_TXN[2] DISP_RCOMP
HDMI signals define TX2 as DP TX0 D20 H_DP_RCOMP 24.9Ohm
(45) H_HDMI_TXCP DDI2_TXP[3]
E20 Place Inside CPU Cavity
(45) H_HDMI_TXCN DDI2_TXN[3]
trace W/S:12/25, max lengtch 200mil
HT6 1 A12
DDI2_AUXP
HT7 1 B12
DDI2_AUXN

B14
(47) H_DVI_TXDP2 DDI3_TXP[0]
A14
(47) H_DVI_TXDN2 DDI3_TXN[0]
C15
(47) H_DVI_TXDP1 DDI3_TXP[1]
B15
DVI (47) H_DVI_TXDN1 DDI3_TXN[1]

teknisi indonesia
B16
(47) H_DVI_TXDP0 DDI3_TXP[2]
HDMI signals define TX2 as DP TX0 A16
(47) H_DVI_TXDN0 DDI3_TXN[2]
C17
(47) H_DVI_TXCP DDI3_TXP[3]
B17
(47) H_DVI_TXCN DDI3_TXN[3]
V3 I
PROC_AUDIO_CLK S_HDA_SCLK (58)
HT8 1 B11 V2 I
DDI3_AUXP PROC_AUDIO_SDI S_HDA_SDO_R (58)
HT9 1 C11 U1 O 1 2
DDI3_AUXN PROC_AUDIO_SDO H_HDA_SDI (58)
H_HDA_SDI_R HR3 20OHM
HR3 place close CPU
total lengtch <4,max=200
SOCKET1151
total lengtch >4,max=1000
12001V00180100
followCRB &PDG 341' SDO 20ohm,other 30 ohm

Title : LGA1150 (FDI/DISPLAY)


ASUSTek Computer Inc.
Engineer: Bing-jie_Wang
Size Project Name Rev
A3 SKYLAKE CHIPSET DEMO R1.02A

Date: Monday, June 11, 2018 Sheet 32 of 113


Channel A
4 Layer routing

(39) D4_DQ_A[0:63]

LGA1151A

AE38 AW18
DDR0_DQ[0] DDR0_CKP[0] D4_MA_CLK0 (39)
D4_DQ_A5 AE37 AV18
DDR0_DQ[1] DDR0_CKN[0] D4_MA_CLK#0 (39)
D4_DQ_A1 AG38 AW17
DDR0_DQ[2] DDR0_CKP[1] D4_MA_CLK1 (39)
D4_DQ_A2 AG37 AY17
DDR0_DQ[3] DDR0_CKN[1] D4_MA_CLK#1 (39)
D4_DQ_A3 AE39 AW16
DDR0_DQ[4] DDR0_CKP[2]
D4_DQ_A4 AE40 AV16
DDR0_DQ[5] DDR0_CKN[2]
D4_DQ_A0 AG39 AT16
DDR0_DQ[6] DDR0_CKP[3]
D4_DQ_A6 AG40 AU16
DDR0_DQ[7] DDR0_CKN[3]
D4_DQ_A7 AJ38
DDR0_DQ[8]
D4_DQ_A13 AJ37 AY24
DDR0_DQ[9] DDR0_CKE[0] D4_CKE_A0 (39)
D4_DQ_A9 AL38 AW24
DDR0_DQ[10] DDR0_CKE[1] D4_CKE_A1 (39)
D4_DQ_A10 AL37 AV24
DDR0_DQ[11] DDR0_CKE[2]
D4_DQ_A11 AJ40 AV25
DDR0_DQ[12] DDR0_CKE[3]
D4_DQ_A8 AJ39
DDR0_DQ[13]
D4_DQ_A12 AL39 AW12
DDR0_DQ[14] DDR0_CS#[0] D4_CS_A#0 (39)
D4_DQ_A14 AL40 AU11
DDR0_DQ[15] DDR0_CS#[1] D4_CS_A#1 (39)
D4_DQ_A15 AN38 AV13
DDR0_DQ[16]/DDR0_DQ[32] DDR0_CS#[2]
D4_DQ_A21 AN40 AV10
DDR0_DQ[17]/DDR0_DQ[33] DDR0_CS#[3]
D4_DQ_A16 AR38
DDR0_DQ[18]/DDR0_DQ[34]
D4_DQ_A18 AR37 AW11
DDR0_DQ[19]/DDR0_DQ[35] DDR0_ODT[0] D4_ODT_A0 (39)
D4_DQ_A19 AN39 AU14
DDR0_DQ[20]/DDR0_DQ[36] DDR0_ODT[1] D4_ODT_A1 (39)
D4_DQ_A20 AN37 AU12
DDR0_DQ[21]/DDR0_DQ[37] DDR0_ODT[2]
D4_DQ_A17 AR39 AY10
DDR0_DQ[22]/DDR0_DQ[38] DDR0_ODT[3]
D4_DQ_A22 AR40
DDR0_DQ[23]/DDR0_DQ[39]
D4_DQ_A23 AW37 AY13
DDR0_DQ[24]/DDR0_DQ[40] DDR0_BA[0] D4_BAA0 (39)
D4_DQ_A25 AU38 AV15
DDR0_DQ[25]/DDR0_DQ[41] DDR0_BA[1] D4_BAA1 (39)
D4_DQ_A28 AV35 AW23
DDR0_DQ[26]/DDR0_DQ[42] DDR0_BG[0] D4_BGA0 (39)
D4_DQ_A27 AW35
DDR0_DQ[27]/DDR0_DQ[43] D4_MAA[0:16] (39)
D4_DQ_A31 AU37 AW13
DDR0_DQ[28]/DDR0_DQ[44] DDR0_MA[16]
D4_DQ_A29 AV37 AV14 D4_MAA16
DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[14]
D4_DQ_A24 AT35 AY11 D4_MAA14
DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[15]
D4_DQ_A30 AU35 D4_MAA15
DDR0_DQ[31]/DDR0_DQ[47]
D4_DQ_A26 AY8 AW15
DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[0]
D4_DQ_A32 AW8 AU18 D4_MAA0
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]
D4_DQ_A36 AV6 AU17 D4_MAA1
DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[2]
D4_DQ_A34 AU6 AV19 D4_MAA2
DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3]
D4_DQ_A35 AU8 AT19 D4_MAA3
DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4]
D4_DQ_A33 AV8 AU20 D4_MAA4
DDR0_DQ[37]/DDR1_DQ[5] DDR0_MA[5]
D4_DQ_A37 AW6 AV20 D4_MAA5
DDR0_DQ[38]/DDR1_DQ[6] DDR0_MA[6]
D4_DQ_A39 AY6 AU21 D4_MAA6
DDR0_DQ[39]/DDR1_DQ[7] DDR0_MA[7]
D4_DQ_A38 AY4 AT20 D4_MAA7
DDR0_DQ[40]/DDR1_DQ[8] DDR0_MA[8]
D4_DQ_A44 AV4 AT22 D4_MAA8
DDR0_DQ[41]/DDR1_DQ[9] DDR0_MA[9]
D4_DQ_A40 AT1 AY14 D4_MAA9
DDR0_DQ[42]/DDR1_DQ[10] DDR0_MA[10]
D4_DQ_A47 AT2 AU22 D4_MAA10
DDR0_DQ[43]/DDR1_DQ[11] DDR0_MA[11]
D4_DQ_A43 AV3 AV22 D4_MAA11
DDR0_DQ[44]/DDR1_DQ[12] DDR0_MA[12]
D4_DQ_A41 AW4 AV12 D4_MAA12
DDR0_DQ[45]/DDR1_DQ[13] DDR0_MA[13]
D4_DQ_A45 AT4 AV23 D4_MAA13
DDR0_DQ[46]/DDR1_DQ[14] DDR0_BG[1] D4_BGA1 (39)
D4_DQ_A46 AT3 AU24
DDR0_DQ[47]/DDR1_DQ[15] DDR0_ACT# D4_A_ACT# (39)
D4_DQ_A42 AP2
DDR0_DQ[48]/DDR1_DQ[32]
D4_DQ_A49 AM4 AY15
DDR0_DQ[49]/DDR1_DQ[33] DDR0_PAR D4_A_PAR (39)
D4_DQ_A54 AP3 AT23
DDR0_DQ[50]/DDR1_DQ[34] DDR0_ALERT# D4_A_ALERT# (39)
D4_DQ_A53 AM3
DDR0_DQ[51]/DDR1_DQ[35]
D4_DQ_A50 AP4
DDR0_DQ[52]/DDR1_DQ[36]
D4_DQ_A52 AM2 AF39
DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[0] D4_DQS_A#0 (39)
D4_DQ_A51 AP1 AK39 D4_DQS_A#0
DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSN[1] D4_DQS_A#1 (39)
D4_DQ_A48 AM1 AP39 D4_DQS_A#1
DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[2]/DDR0_DQSN[4] D4_DQS_A#2 (39)
D4_DQ_A55 AK3 AU36 D4_DQS_A#2
DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSN[3]/DDR0_DQSN[5] D4_DQS_A#3 (39)
D4_DQ_A61 AH1 AW7 D4_DQS_A#3
DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[4]/DDR1_DQSN[0] D4_DQS_A#4 (39)
D4_DQ_A63 AK4 AU3 D4_DQS_A#4
DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSN[5]/DDR1_DQSN[1] D4_DQS_A#5 (39)
D4_DQ_A60 AH2 AN3 D4_DQS_A#5
DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQSN[6]/DDR1_DQSN[4] D4_DQS_A#6 (39)
D4_DQ_A59 AH4 AJ3 D4_DQS_A#6
DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQSN[7]/DDR1_DQSN[5] D4_DQS_A#7 (39)
D4_DQ_A62 AK2 D4_DQS_A#7
DDR0_DQ[61]/DDR1_DQ[45]
D4_DQ_A57 AH3 AF38
DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQSP[0] D4_DQS_A0 (39)
D4_DQ_A58 AK1 AK38 D4_DQS_A0
DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSP[1] D4_DQS_A1 (39)
D4_DQ_A56 AP38 D4_DQS_A1
DDR0_DQSP[2]/DDR0_DQSP[4] D4_DQS_A2 (39)
AU33 AV36 D4_DQS_A2
DDR0_ECC[0] DDR0_DQSP[3]/DDR0_DQSP[5] D4_DQS_A3 (39)
AT33 AV7 D4_DQS_A3
DDR0_ECC[1] DDR0_DQSP[4]/DDR1_DQSP[0] D4_DQS_A4 (39)
AW33 AU2 D4_DQS_A4
DDR0_ECC[2] DDR0_DQSP[5]/DDR1_DQSP[1] D4_DQS_A5 (39)
AV31 AN2 D4_DQS_A5
DDR0_ECC[3] DDR0_DQSP[6]/DDR1_DQSP[4] D4_DQS_A6 (39)
AU31 AJ2 D4_DQS_A6
DDR0_ECC[4] DDR0_DQSP[7]/DDR1_DQSP[5] D4_DQS_A7 (39)
AV33 D4_DQS_A7
DDR0_ECC[5]
AW31 AV32
DDR0_ECC[6] DDR0_DQSP[8]
AY31 AU32
DDR0_ECC[7] DDR0_DQSN[8]

SOCKET1151
12001V00180100

Title : LGA1151 (DDR4_A Control)


ASUSTek Computer Inc.
Engineer: Bing-jie_Wang
Size Project Name Rev
A3 SKYLAKE CHIPSET DEMO R1.00

Date: Monday, June 11, 2018 Sheet 33 of 113


Follow CRB

Channel B
4 Layer routing

(40) D4_DQ_B[0:63]

LGA1151B

AD34 AM20
DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKP[0] D4_MB_CLK0 (40)
D4_DQ_B4 AD35 AM21
DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[0] D4_MB_CLK#0 (40)
D4_DQ_B5 AG35 AP22
DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[1] D4_MB_CLK1 (40)
D4_DQ_B7 AH35 AP21
DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKN[1] D4_MB_CLK#1 (40)
D4_DQ_B3 AE35 AN20
DDR1_DQ[4]/DDR0_DQ[20] DDR1_CKP[2]
D4_DQ_B1 AE34 AN21
DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKN[2]
D4_DQ_B0 AG34 AP19
DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKP[3]
D4_DQ_B6 AH34 AP20
DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKN[3]
D4_DQ_B2 AK35
DDR1_DQ[8]/DDR0_DQ[24]
D4_DQ_B13 AL35 AY29
DDR1_DQ[9]/DDR0_DQ[25] DDR1_CKE[0] D4_CKE_B0 (40)
D4_DQ_B9 AK32 AV29
DDR1_DQ[10]/DDR0_DQ[26] DDR1_CKE[1] D4_CKE_B1 (40)
D4_DQ_B14 AL32 AW29
DDR1_DQ[11]/DDR0_DQ[27] DDR1_CKE[2]
D4_DQ_B15 AK34 AU29
DDR1_DQ[12]/DDR0_DQ[28] DDR1_CKE[3]
D4_DQ_B12 AL34
DDR1_DQ[13]/DDR0_DQ[29]
D4_DQ_B8 AK31 AP17
DDR1_DQ[14]/DDR0_DQ[30] DDR1_CS#_0 D4_CS_B#0 (40)
D4_DQ_B10 AL31 AN15
DDR1_DQ[15]/DDR0_DQ[31] DDR1_CS#_1 D4_CS_B#1 (40)
D4_DQ_B11 AP35 AN17
DDR1_DQ[16]/DDR0_DQ[48] DDR1_CS#_2
D4_DQ_B16 AN35 AM15
DDR1_DQ[17]/DDR0_DQ[49] DDR1_CS#_3
D4_DQ_B20 AN32
DDR1_DQ[18]/DDR0_DQ[50]
D4_DQ_B22 AP32 AM16
DDR1_DQ[19]/DDR0_DQ[51] DDR1_ODT[0] D4_ODT_B0 (40)
D4_DQ_B23 AN34 AL16
DDR1_DQ[20]/DDR0_DQ[52] DDR1_ODT[1] D4_ODT_B1 (40)
D4_DQ_B17 AP34 AP15
DDR1_DQ[21]/DDR0_DQ[53] DDR1_ODT[2]
D4_DQ_B21 AN31 AL15
DDR1_DQ[22]/DDR0_DQ[54] DDR1_ODT[3]
D4_DQ_B18 AP31
DDR1_DQ[23]/DDR0_DQ[55]
D4_DQ_B19 AL29 AN18
DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[16]
D4_DQ_B28 AM29 AL17 D4_MAB16
DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]
D4_DQ_B24 AP29 AP16 D4_MAB14
DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[15]
D4_DQ_B30 AR29 D4_MAB15
DDR1_DQ[27]/DDR0_DQ[59]
D4_DQ_B26 AM28 AL18
DDR1_DQ[28]/DDR0_DQ[60] DDR1_BA[0] D4_BAB0 (40)
D4_DQ_B25 AL28 AM18
DDR1_DQ[29]/DDR0_DQ[61] DDR1_BA[1] D4_BAB1 (40)
D4_DQ_B29 AR28 AW28
DDR1_DQ[30]/DDR0_DQ[62] DDR1_BG[0] D4_BGB0 (40)
D4_DQ_B27 AP28
DDR1_DQ[31]/DDR0_DQ[63] D4_MAB[0:16] (40)
D4_DQ_B31 AR12 AL19
DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[0]
D4_DQ_B32 AP12 AL22 D4_MAB0
DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[1]
D4_DQ_B33 AM13 AM22 D4_MAB1
DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[2]
D4_DQ_B38 AL13 AM23 D4_MAB2
DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[3]
D4_DQ_B34 AR13 AP23 D4_MAB3
DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[4]
D4_DQ_B36 AP13 AL23 D4_MAB4
DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[5]
D4_DQ_B37 AM12 AW26 D4_MAB5
DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[6]
D4_DQ_B39 AL12 AY26 D4_MAB6
DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[7]
D4_DQ_B35 AP10 AU26 D4_MAB7
DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[8]
D4_DQ_B44 AR10 AW27 D4_MAB8
DDR1_DQ[41]/DDR1_DQ[25] DDR1_MA[9]
D4_DQ_B45 AR7 AP18 D4_MAB9
DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[10]
D4_DQ_B46 AP7 AU27 D4_MAB10
DDR1_DQ[43]/DDR1_DQ[27] DDR1_MA[11]
D4_DQ_B42 AR9 AV27 D4_MAB11
DDR1_DQ[44]/DDR1_DQ[28] DDR1_MA[12]
D4_DQ_B41 AP9 AR15 D4_MAB12
DDR1_DQ[45]/DDR1_DQ[29] DDR1_MA[13]
D4_DQ_B40 AR6 AY28 D4_MAB13
DDR1_DQ[46]/DDR1_DQ[30] DDR1_BG[1] D4_BGB1 (40)
D4_DQ_B47 AP6 AU28
DDR1_DQ[47]/DDR1_DQ[31] DDR1_ACT# D4_B_ACT# (40)
D4_DQ_B43 AM10
DDR1_DQ[48]
D4_DQ_B52 AL10 AL20
DDR1_DQ[49] DDR1_PAR D4_B_PAR (40)
D4_DQ_B53 AM7 AY25
DDR1_DQ[50] DDR1_ALERT# D4_B_ALERT# (40)
D4_DQ_B55 AL7
DDR1_DQ[51]
D4_DQ_B51 AM9
DDR1_DQ[52]
D4_DQ_B48 AL9 AF34
DDR1_DQ[53] DDR1_DQSN[0]/DDR0_DQSN[2] D4_DQS_B#0 (40)
D4_DQ_B49 AM6 AK33
DDR1_DQ[54] DDR1_DQSN[1]/DDR0_DQSN[3] D4_DQS_B#1 (40)
D4_DQ_B54 AL6 AN33
DDR1_DQ[55] DDR1_DQSN[2]/DDR0_DQSN[6] D4_DQS_B#2 (40)
D4_DQ_B50 AJ6 AN29
DDR1_DQ[56] DDR1_DQSN[3]/DDR0_DQSN[7] D4_DQS_B#3 (40)
D4_DQ_B61 AJ7 AN13
DDR1_DQ[57] DDR1_DQSN[4]/DDR1_DQSN[2] D4_DQS_B#4 (40)
D4_DQ_B56 AE6 AR8
DDR1_DQ[58] DDR1_DQSN[5]/DDR1_DQSN[3] D4_DQS_B#5 (40)
D4_DQ_B63 AF7 AM8
DDR1_DQ[59] DDR1_DQSN[6] D4_DQS_B#6 (40)
D4_DQ_B58 AH7 AG6
DDR1_DQ[60] DDR1_DQSN[7] D4_DQS_B#7 (40)
D4_DQ_B60 AH6
DDR1_DQ[61]
D4_DQ_B57 AE7 AF35
DDR1_DQ[62] DDR1_DQSP[0]/DDR0_DQSP[2] D4_DQS_B0 (40)
D4_DQ_B59 AF6 AL33
DDR1_DQ[63] DDR1_DQSP[1]/DDR0_DQSP[3] D4_DQS_B1 (40)
D4_DQ_B62 AP33
DDR1_DQSP[2]/DDR0_DQSP[6] D4_DQS_B2 (40)
AR25 AN28
DDR1_ECC[0] DDR1_DQSP[3]/DDR0_DQSP[7] D4_DQS_B3 (40)
AR26 AN12
DDR1_ECC[1] DDR1_DQSP[4]/DDR1_DQSP[2] D4_DQS_B4 (40)
AM26 AP8
DDR1_ECC[2] DDR1_DQSP[5]/DDR1_DQSP[3] D4_DQS_B5 (40)
AM25 AL8
DDR1_ECC[3] DDR1_DQSP[6] D4_DQS_B6 (40)
AP26 AG7
DDR1_ECC[4] DDR1_DQSP[7] D4_DQS_B7 (40)
AP25
DDR1_ECC[5]
AL25 AN25
DDR1_ECC[6] DDR1_DQSP[8]
AL26 AN26
DDR1_ECC[7] DDR1_DQSN[8]

AB40
DDR_VREF_CA H_D4_VREFCA_A (43)
AC40 1 HT10
DDR0_VREF_DQ
AC39 TP_DIMM_DQ0
DDR1_VREF_DQ H_D4_VREFCA_B (43) /X/1151

SOCKET1151
12001V00180100
1

D4C1 D4C2 CRB & Z97


0.022UF/16V 0.022UF/16V High frequency
termination, can absorb
any high frequency
2

noise coming from


CPU/board crosstalk.
2

D4R13 D4R14
24.9Ohm 24.9Ohm

Title : LGA1151 (DDR4_B Control)


1

ASUSTek Computer Inc.


Engineer: CASPAR
GND GND
Size Project Name Rev
A3 SKYLAKE G R1.00

Date: Monday, June 11, 2018 Sheet 34 of 113


PLACE NEAR CPU
HR4 /X
1 1KOhm 2
VCCST_VCCSFR H_CFG0
HR10 /X
1 1KOhm 2
HC1 0.1UF/16V H_CFG1
1 2
/X LGA1151E HR5 /X
HC2 4.7UF/6.3V 1 1KOhm 2
1 2
/X mbs_c0603 I W5 H15 IPU H_CFG2
(54) CK_100M_CPUIP BCLKP CFG[0] H_CFG0 (38)
I W4 F15 IPU H_CFG0 HR6 /X
(54) CK_100M_CPUIN BCLKN CFG[1] H_CFG1 (38)
F16 IPU H_CFG1 1 1KOhm 2
CFG[2] H_CFG2 (38)
HR7 GND I W1 H16 IPU H_CFG2 HR8 H_CFG3
(54) CK_100M_PCIBCLKP PCI_BCLKP CFG[3] H_CFG3 (38)
I W2 F19 IPU H_CFG3
(54) CK_100M_PCIBCLKN PCI_BCLKN CFG[4] (38) XDP_PCUDEBUG
2 56.2Ohm 1 H_SVID_ALERT# H18 IPU H_CFG4 2 1
CFG[5] HR11
1 2 I K9 G21 IPU H_CFG5 /XDP 1KOhm
(54) CK_24M_NSCCCLKP CLK24P CFG[6]
HR9 H_SVID_DATA I J9 H20 IPU H_CFG6 1KOhm
(54) CK_24M_NSCCCLKN CLK24N CFG[7] H_CFG7 (38)
100Ohm G16 IPU H_CFG7 H_CFG4
if not 2
use eDP,unmount 1
it
CFG[8] H_CFG8 (38)
follow CRB E16 IPU H_CFG8 /VGA
CFG[9]
F17 IPU H_CFG9
CFG[10] H_CFG10 (38)
H17 IPU H_CFG10
CFG[11] H_CFG11 (38)
G20 IPU H_CFG11
CFG[12] H_CFG12 (38)
F20 IPU H_CFG12
CFG[13] H_CFG13 (38)
F21 IPU H_CFG13
CFG[14] H_CFG14 (38)
VCCST_VCCSFR HR13 I E39 H19 IPU H_CFG14
(6) H_SVID_ALERT# VIDALERT# CFG[15] H_CFG15 (38)
2 220Ohm 1 H_SVID_ALERT#_R OD E38 H_CFG15
(6) H_SVID_CLK VIDSCK
I/O E40 F14 IPU
(6) H_SVID_DATA VIDSOUT CFG[17] H_CFG17 (38)
HR15 1 2 H_SVID_DATA I/OD C39 E14 IPU H_CFG17
(6) P_VCORE_VRHOT#_R_4 PROCHOT# CFG[16] H_CFG16 (38)
HR16 51Ohm /X/XDP/MERG 499OHM H_PROCHOT#_R F18 IPU H_CFG16 HR17 /X
CFG[19] H_CFG19 (38)
2 1 H_PREQ# O AC36 G18 IPU H_CFG19 1 1KOhm 2
(18) H_DDR_VTT_CNTL DDR_VTT_CNTL CFG[18] H_CFG18 (38)
unstuff HR201 for merged XDP O AC38 H_CFG18 H_CFG7
(36,96) H_SKTOCC# SKTOCC#
D16 I/O IPU
BPM#[0] SKL_XDP_MBP_0 (38)
/X 1 D17 I/O IPU
BPM#[1] SKL_XDP_MBP_1 (38)
mbs_tpc26b_s4_85 G14 I/O IPU 1 HT13
AT3 BPM#[2]
2 1KOhm 1 HR18 P_VCORE_VRHOT#_R_4 I U2 H14 I/O IPU H_MBP#2 1 HT14
(65) S_VCCST_PWRGD VCCST_PWRGD BPM#[3]
O_VCCST_PWRGD H_MBP#3
I F8
(58) H_CPUPWRGD PROCPWRGD
2 1KOhm 1 HR19 H_THERMTRIP# H_CPUPWRGD I E7 H13 OD
O
(57) H_CPURST# RESET# PROC_TDO H_TDO (38)
/X H_CPURST# I E8 G12 I IPU H_TDO
(57) S_PM_SYNC PM_SYNC PROC_TDI H_TDI (38)
O D8 F13 I IPU
PM_DOWN PROC_TMS H_TMS (38)
ESDC1 1.5PF/50V /X H_PM_DOWN_R I/O G7 F11 I
(96) O_H_PECI PECI PROC_TCK H_TCK (38)
OD D11 H_TCK
(57) H_THERMTRIP# THERMTRIP#
1 2 H_CPUPWRGD H_THERMTRIP# F12 I
PROC_TRST# H_TRST# (38)
ESDC2 470PF/50V /X B9 I IPU
PROC_PREQ# H_PREQ# (38)
HT15 1 AB36 B10 OD H_PREQ#
PROC_SELECT# PROC_PRDY# H_PRDY# (38)
1 2 H_CPURST# H_SKL_CNL#_R
ESDC3 1.5PF/50V /X HT16 1 OD D13
CATERR#
H_CATERR# M11
CFG_RCOMP
1 2 H_PROCHOT#_R H_CFG_RCOMP
ESDC4 100PF/50V /X

1
HR20
1 2 O_VCCST_PWRGD 49.9Ohm

SOCKET1151

2
12001V00180100
GND
HR21
1 2
(57) H_PM_DOWN
20OHM H_PM_DOWN_R GND
2

HR20 PLACE INSIDE CAVITY


方框1 HT12 HR22 MAX trace lengtch 200mil
1 mbs_tpc26b_s4_85 1KOhm ALL CFG 1 = NO TERMAINATION ON BOARD DEFAULT HIGH
H_CFG6 /X /X ALL CFG 0 = PHYSICAL STRAP LOW ON BOARD
HT11 Skylake Strap Table Rev 0.85
1

1 mbs_tpc26b_s4_85 All Have Internal Pull-Ups +VCCIO


H_CFG5 /X
H22 place holder pull down only CFG H = 1 L = 0 Description
0 Normal STALL EAR GND
1 Reserved
@:如果Z390 且有switch 2 Normal Lane Reverse PCIEX16 Lane Reversal
GND
切X8,則用方框2,其餘都用方框1 3 Reserved
4 disable enable eDP
5 PCIE Config PCIE Config SEL[0]
6 PCIE Config PCIE Config SEL[1]
7 RESET# BIOS REQ H_TCK TERMINATION (HR127)
8-19 Reserved PLACE HR24 CLOSER TO CPU HR23 PLACE NEAR CPU WITHIN 1.1 INCH

‧ CFG[0]: Stall reset sequence after PCU PLL lock until VCCST_VCCSFR H_TCK
de-asserted:

1
- 1 = (Default) Normal Operation; No stall.
- 0 = Stall. HR23
‧ CFG[1]: Reserved configuration lane. 51Ohm

1
‧ CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
- 1 = Normal operation HR24 /XDP
- 0 = Lane numbers reversed. 100Ohm 5%

2
‧ CFG[3]: Reserved configuration lane.
‧ CFG[4]: eDP enable:
- 1 = Disabled. /XDP

2
- 0 = Enabled.
‧ CFG[6:5]: PCI Express* Bifurcation GND
- 00 = 1 x8, 2 x4 PCI Express* H_TDO
- 01 = reserved
- 10 = 2 x8 PCI Express*
- 11 = 1 x16 PCI Express*
H_CFG9 ‧ CFG[7]: PEG Training:
- 1 = (default) PEGTrain immediately following RESET#
de-assertion.
- 0 = PEG Wait for BIOS for training.
‧ CFG[19:8]: Reserved configuration lanes.
3
3

HQ1231
11 H2N7002
(62) S_CFG9
G /X
S
2
2

HR3065
1

8.2KOhm

/X
2

Title : LGA1151 (Control)


預留for SVID disable GND GND
ASUSTek Computer Inc.
Engineer: Morse_Peng
Size Project Name Rev
A3 SkyLake VC R1.00

Date: Monday, June 11, 2018 Sheet 35 of 113


XDP Card USB3 CON1 XDP Card USB3 CON4

CT1P1 1 +3VSB請從DIP電容跳線至XDP Card CON4 Pin1


H_CFG0 (35)

CT1P2 1
H_CFG1 (35)

CT1P3 1
H_CFG2 (35)

CT1P4 1
H_CFG3 (35)

Naming Rule:

CTxPy==>請跳線到XDP Card CONx connector的Piny


CT4P6 1
H_TCK (35)

CT1P8 1 CT4P7 1 Placement Rule:


H_CFG13 (35) H_TMS (35)

CT1P9 1 CT4P8 1 此頁面測點全部放置背面靠近輸出端,


H_CFG12 (35) C_CPU_XDP (54)

CT1P10 1 CT4P9 1 Layout會協助把Reference文字面開出,


H_CFG11 (35) C_CPU_XDP# (54)

CT1P11 1 CT4P10 1 若有需求初期PCB版本可洗背面文字,


H_CFG10 (35) H_TDO (35)

CT4P11 1 但低階機種PVT PCB版本請記得通知板廠不洗背面文字


S_JTAG_TDO (58)

CT1P13 1
H_CFG8 (35) +3VSB_ATX請從DIP電容跳線至XDP Card CON4 Pin19
CT1P14 1 Power Rework:
H_CFG7 (35)

CT1P15 1 +1.0V_A請從DIP電容跳線至XDP Card CON2 Pin19


H_TRST# (35)

+3VSB請從DIP電容跳線至XDP Card CON4 Pin1

XDP Card USB3 CON2 +VCCST請從DIP電容跳線至XDP Card CON3 Pin19


HR128

S_JTAGX (38,58) +VCCIO請從DIP電容跳線至XDP Card CON2 Pin1


+VCCIO請從DIP電容跳線至XDP Card CON2 Pin1 H_TCK 2 0Ohm 1
/X +3VSB_ATX請從DIP電容跳線至XDP Card CON4 Pin19
CT2P1 1
H_CFG14 (35)
GND請跳線至XDP Card CON2 Pin7
CT2P2 1
H_CFG15 (35)

CT2P3 1
H_CFG16 (35)

CT2P4 1
H_CFG17 (35)

GND請跳線至XDP Card CON2 Pin7


CT2P5 1
H_CFG18 (35)

CT2P6 1
H_CFG19 (35)
O_RSMRST# H_CFG4
CT2P7 1 SKL_XDP_MBP_1 (35)
O_IOPWRBTN# H_CFG5
CT2P8 1
SKL_XDP_MBP_0 (35)
O_RSTCON# H_CFG6
CT2P9 1
H_TDI (35)
H_CPUPWRGD H_CFG9
CT2P10 1
H_PRDY# (35)
S_SYSPWROK
CT2P11 1
H_PREQ# (35)
H_CPURST#
CT2P12 1
XDP_PCUDEBUG (35)
S_SMBCLK_MAIN
+1.0V_A請從DIP電容跳線至XDP Card CON2 Pin19
S_SMBDATA_MAIN

由於RD CT*test pin會被做 no


XDP Card USB3 CON3 test
處理,所以刪除這些需要有test
pin屬性,要layout額外加
CT3P1 1
S_XDP_PREQ# (61)

CT3P2 1
S_XDP_PRDY# (61)

CT3P5 1
S_ITP_PMODE (58)

讓VCCST在插入XDP制具時有電

CT311請跳線至CON3 Pin11
CT3P9 1
S_JTAG_TMS (58)

CT3P10 1
S_JTAG_TDI (58)

CT3P11 1
S_JTAG_TCK (58)

CT3P12 1
S_XDP_TRST# (61)
Title : LGA1150 (XDP)
CT3P13 1
S_JTAGX (38,58)
ASUSTek Computer Inc.
Engineer: Grace
+VCCST請從DIP電容跳線至XDP Card CON3 Pin19
Size Project Name Rev
A3 Z170 Series R1.02A

Date: Monday, June 11, 2018 Sheet 38 of 113


(33) D4_DQ_A[0:63]

(33) D4_MAA[0:16] DIMM_A1A


234 280
A17 DQ63
82 135 D4_DQ_A63 DIMM_A1_STAR
A16_RAS_N DQ62
D4_MAA16 86 273 D4_DQ_A62 1
A15_CAS_N DQ61 ASTERISK
D4_MAA15 228 128 D4_DQ_A61
A14_WE_N DQ60
D4_MAA14 232 282 D4_DQ_A60 ASTERISK
A13 DQ59
D4_MAA13 65 137 D4_DQ_A59
A12 DQ58 /X
D4_MAA12 210 275 D4_DQ_A58
A11 DQ57
D4_MAA11 225 130 D4_DQ_A57
A10 DQ56
D4_MAA10 66 269 D4_DQ_A56
A9 DQ55
D4_MAA9 68 124 D4_DQ_A55
A8 DQ54
D4_MAA8 211 262 D4_DQ_A54
A7 DQ53
D4_MAA7 69 117 D4_DQ_A53
A6 DQ52
D4_MAA6 213 271 D4_DQ_A52
A5 DQ51
D4_MAA5 214 126 D4_DQ_A51
A4 DQ50
D4_MAA4 71 264 D4_DQ_A50
A3 DQ49
D4_MAA3 216 119 D4_DQ_A49
A2 DQ48
D4_MAA2 72 258 D4_DQ_A48
A1 DQ47
D4_MAA1 79 113 D4_DQ_A47
A0 DQ46
D4_MAA0 251 D4_DQ_A46
DQ45
224 106 D4_DQ_A45
(33) D4_BAA1 BA1 DQ44
81 260 D4_DQ_A44
(33) D4_BAA0 BA0 DQ43
207 115 D4_DQ_A43
(33) D4_BGA1 BG1 DQ42
63 253 D4_DQ_A42
(33) D4_BGA0 BG0 DQ41
108 D4_DQ_A41
DQ40
218 247 D4_DQ_A40
(33) D4_MA_CLK1 CK1P DQ39
219 102 D4_DQ_A39
(33) D4_MA_CLK#1 CK1N DQ38
74 240 D4_DQ_A38
(33) D4_MA_CLK0 CK0P DQ37
75 95 D4_DQ_A37
(33) D4_MA_CLK#0 CK0N DQ36
249 D4_DQ_A36
DQ35
235 104 D4_DQ_A35
C2 DQ34
Chip ID 237 242 D4_DQ_A34
S3_N_C1 DQ33
93 97 D4_DQ_A33
S2_N_C0 DQ32
89 188 D4_DQ_A32
(33) D4_CS_A#1 S1_N DQ31
84 43 D4_DQ_A31
(33) D4_CS_A#0 S0_N DQ30
181 D4_DQ_A30
DQ29
203 36 D4_DQ_A29 +3V
(33) D4_CKE_A1 CKE1 DQ28
60 190 D4_DQ_A28
(33) D4_CKE_A0 CKE0 DQ27
45 D4_DQ_A27
DQ26
91 183 D4_DQ_A26
(33) D4_ODT_A1 ODT1 DQ25
87 38 D4_DQ_A25
(33) D4_ODT_A0 ODT0 DQ24
177 D4_DQ_A24
DQ23
32 D4_DQ_A23
DQ22

4
199 170 D4_DQ_A22
CB7 DQ21
54 25 D4_DQ_A21 D4D1
CB6 DQ20
VDDQ 192 179 D4_DQ_A20
CB5 DQ19 IP4220CZ6
47 34 D4_DQ_A19
CB4 DQ18 /X
201 172 D4_DQ_A18
CB3 DQ17
2

56 27 D4_DQ_A17
CB2 DQ16
D4R1 194 166 D4_DQ_A16 Placed close to DIMM
CB1 DQ15
240Ohm 49 21 D4_DQ_A15
CB0 DQ14
/X/DDR4 159 D4_DQ_A14 SMBus CAPs
DQ13
1% 222 14 D4_DQ_A13
(33) D4_A_PAR PAR DQ12
1

58 168 D4_DQ_A12
RESET_N DQ11
S_D4_RESET#_R 78 23 D4_DQ_A11
EVENT_N DQ10

3
CHA_DIMM0_TS_EVENT# 208 161 D4_DQ_A10
(33) D4_A_ALERT# ALERT_N DQ9
62 16 D4_DQ_A9
(33) D4_A_ACT# ACT_N DQ8 S_SMBCLK_DDR
155 D4_DQ_A8
DQ7
10 D4_DQ_A7
DQ6
Address A0 238 148 D4_DQ_A6 GND
SA2 DQ5
140 3 D4_DQ_A5
SA1 DQ4
139 157 D4_DQ_A4
SA0 DQ3
12 D4_DQ_A3
DQ2
150

1
D4_DQ_A2 S_SMBDATA_DDR D3C22 D3C24
DQ1
GND 5 D4_DQ_A1 10PF/50V 10PF/50V
DQ0
285 D4_DQ_A0 /X /X
(6,40,48,63) S_SMBDATA_DDR SDA

2
S_SMBDATA_DDR 141
(6,40,48,63) S_SMBCLK_DDR SCL
S_SMBCLK_DDR
144 GND GND
RFU2
227
RFU1
205
RFU0
1

D4C5 D4C6 230 VDDQ


SAVE_N_NC
330PF/50V 330PF/50V
/X/DDR4 /X/DDR4
2

197 51
DQS8P DQS17P
196 52
DQS8N DQS17N
278 132
(33) D4_DQS_A7 DQS7P DQS16P
GND GND 277 133
(33) D4_DQS_A#7 DQS7N DQS16N
267 121
(33) D4_DQS_A6 DQS6P DQS15P
266 122
(33) D4_DQS_A#6 DQS6N DQS15N
256 110
(33) D4_DQS_A5 DQS5P DQS14P
255 111
(33) D4_DQS_A#5 DQS5N DQS14N
245 99
(33) D4_DQS_A4 DQS4P DQS13P
244 100
(33) D4_DQS_A#4 DQS4N DQS13N
186 40
(33) D4_DQS_A3 DQS3P DQS12P
185 41
(33) D4_DQS_A#3 DQS3N DQS12N
175 29
(33) D4_DQS_A2 DQS2P DQS11P
174 30
(33) D4_DQS_A#2 DQS2N DQS11N
164 18
(33) D4_DQS_A1 DQS1P DQS10P
163 19
(33) D4_DQS_A#1 DQS1N DQS10N
153 7
(33) D4_DQS_A0 DQS0P DQS9P
152 8
(33) D4_DQS_A#0 DQS0N DQS9N

DDR4_DIMM_288P
12002-00078800
(40,58) S_D4_RESET#_R <Variant Name>
s_ddr4_dimm_288p_2hold_fxco S_D4_RESET#_R
1

D4C8
/X/DDR4 Title : DDR4 Channel A
0.1UF/16V
2

ASUS TeK Computer INC


Engineer: Morse_Peng
Put One Caps Per DIMM Slot
Size Project Name Rev
GND
A3 SkyLake VC R1.00

Date: Monday, June 11, 2018 Sheet 39 of 113


(34) D4_DQ_B[0:63]

(34) D4_MAB[0:16] DIMM_B1A

234 280 DIMM_B1_STAR


A17 DQ63
82 135 D4_DQ_B63 1
A16_RAS_N DQ62 ASTERISK
D4_MAB16 86 273 D4_DQ_B62
A15_CAS_N DQ61
D4_MAB15 228 128 D4_DQ_B61 ASTERISK
A14_WE_N DQ60
D4_MAB14 232 282 D4_DQ_B60
A13 DQ59 /X
D4_MAB13 65 137 D4_DQ_B59
A12 DQ58
D4_MAB12 210 275 D4_DQ_B58
A11 DQ57
D4_MAB11 225 130 D4_DQ_B57
A10 DQ56
D4_MAB10 66 269 D4_DQ_B56
A9 DQ55
D4_MAB9 68 124 D4_DQ_B55
A8 DQ54
D4_MAB8 211 262 D4_DQ_B54
A7 DQ53
D4_MAB7 69 117 D4_DQ_B53
A6 DQ52
D4_MAB6 213 271 D4_DQ_B52
A5 DQ51
D4_MAB5 214 126 D4_DQ_B51
A4 DQ50
D4_MAB4 71 264 D4_DQ_B50
A3 DQ49
D4_MAB3 216 119 D4_DQ_B49
A2 DQ48
D4_MAB2 72 258 D4_DQ_B48
A1 DQ47
D4_MAB1 79 113 D4_DQ_B47
A0 DQ46
D4_MAB0 251 D4_DQ_B46
DQ45
224 106 D4_DQ_B45
(34) D4_BAB1 BA1 DQ44
81 260 D4_DQ_B44
(34) D4_BAB0 BA0 DQ43
207 115 D4_DQ_B43
(34) D4_BGB1 BG1 DQ42
63 253 D4_DQ_B42
(34) D4_BGB0 BG0 DQ41
108 D4_DQ_B41
DQ40
218 247 D4_DQ_B40
(34) D4_MB_CLK1 CK1P DQ39
219 102 D4_DQ_B39
(34) D4_MB_CLK#1 CK1N DQ38
74 240 D4_DQ_B38
(34) D4_MB_CLK0 CK0P DQ37
75 95 D4_DQ_B37
(34) D4_MB_CLK#0 CK0N DQ36
249 D4_DQ_B36
DQ35
235 104 D4_DQ_B35
C2 DQ34
Chip ID 237 242 D4_DQ_B34
S3_N_C1 DQ33
93 97 D4_DQ_B33
S2_N_C0 DQ32
89 188 D4_DQ_B32
(34) D4_CS_B#1 S1_N DQ31
84 43 D4_DQ_B31
(34) D4_CS_B#0 S0_N DQ30
181 D4_DQ_B30
DQ29
203 36 D4_DQ_B29
(34) D4_CKE_B1 CKE1 DQ28
60 190 D4_DQ_B28
(34) D4_CKE_B0 CKE0 DQ27
45 D4_DQ_B27
DQ26
91 183 D4_DQ_B26
(34) D4_ODT_B1 ODT1 DQ25
87 38 D4_DQ_B25
(34) D4_ODT_B0 ODT0 DQ24
177 D4_DQ_B24
DQ23
32 D4_DQ_B23
DQ22
199 170 D4_DQ_B22
CB7 DQ21
54 25 D4_DQ_B21
CB6 DQ20
VDDQ 192 179 D4_DQ_B20
CB5 DQ19
47 34 D4_DQ_B19
CB4 DQ18
201 172 D4_DQ_B18
CB3 DQ17
2

56 27 D4_DQ_B17
CB2 DQ16
D4R3 194 166 D4_DQ_B16
CB1 DQ15
240Ohm 49 21 D4_DQ_B15
CB0 DQ14
/X/DDR4 159 D4_DQ_B14
DQ13
1% 222 14 D4_DQ_B13
(34) D4_B_PAR PAR DQ12
1

58 168 D4_DQ_B12
RESET_N DQ11
S_D4_RESET#_R 78 23 D4_DQ_B11
EVENT_N DQ10
CHB_DIMM0_TS_EVENT# 208 161 D4_DQ_B10
(34) D4_B_ALERT# ALERT_N DQ9
62 16 D4_DQ_B9
(34) D4_B_ACT# ACT_N DQ8
155 D4_DQ_B8
DQ7
VDDSPD 10 D4_DQ_B7
DQ6
Address A4 238 148 D4_DQ_B6
SA2 DQ5
140 3 D4_DQ_B5
SA1 DQ4
139 157 D4_DQ_B4
SA0 DQ3
12 D4_DQ_B3
DQ2
150 D4_DQ_B2
DQ1
GND 5 D4_DQ_B1
DQ0
285 D4_DQ_B0
(6,39,48,63) S_SMBDATA_DDR SDA
S_SMBDATA_DDR 141
(6,39,48,63) S_SMBCLK_DDR SCL
S_SMBCLK_DDR
144
RFU2
227
RFU1
205
RFU0
1

D4C9 D4C10 230 VDDQ


SAVE_N_NC
330PF/50V 330PF/50V
/X/DDR4 /X/DDR4
2

197 51
DQS8P DQS17P
196 52
DQS8N DQS17N
278 132
(34) D4_DQS_B7 DQS7P DQS16P
GND GND 277 133
(34) D4_DQS_B#7 DQS7N DQS16N
267 121
(34) D4_DQS_B6 DQS6P DQS15P
266 122
(34) D4_DQS_B#6 DQS6N DQS15N
256 110
(34) D4_DQS_B5 DQS5P DQS14P
255 111
(34) D4_DQS_B#5 DQS5N DQS14N
245 99
(34) D4_DQS_B4 DQS4P DQS13P
244 100
(34) D4_DQS_B#4 DQS4N DQS13N
186 40
(34) D4_DQS_B3 DQS3P DQS12P
185 41
(34) D4_DQS_B#3 DQS3N DQS12N
175 29
(34) D4_DQS_B2 DQS2P DQS11P
174 30
(34) D4_DQS_B#2 DQS2N DQS11N
164 18
(34) D4_DQS_B1 DQS1P DQS10P
163 19
(34) D4_DQS_B#1 DQS1N DQS10N
153 7
(34) D4_DQS_B0 DQS0P DQS9P
152 8
(34) D4_DQS_B#0 DQS0N DQS9N

DDR4_DIMM_288P

<Variant Name>
12002-00078800
(39,58) S_D4_RESET#_R
S_D4_RESET#_R
Title :
1

s_ddr4_dimm_288p_2hold_fxco D4C12
/X/DDR4
DDR4 Channel B
0.1UF/16V
ASUS TeK Computer INC
Engineer: Morse_Peng
2

Put One Caps Per DIMM Slot Size Project Name Rev
GND A3 SkyLake VC R1.00

Date: Monday, June 11, 2018 Sheet 40 of 113


VPPDDR VPPDDR
DIMM_A1B DIMM_B1B
142 1 142 1
VPP4 12V_1 VPP4 12V_1
143 145 143 145
VPP3 12V_0 VPP3 12V_0
288 288
VPP2 VPP2
286 286
VPP1 VPP1
287 VDDSPD VDDQ 287 VDDSPD VDDQ
VPP0 VPP0
VTT_DDR VTT_DDR

77 284 77 284
VTT1 VDDSPD VTT1 VDDSPD
221 221

1
VTT0 VTT0

1
VDDQ D4C13 D4R5 VDDQ D4C55 D4R7

1
/X/DDR4 1KOhm D4C37 /X/DDR4 1KOhm

1
59 0.1UF/16V 1% /DDR4 59 0.1UF/16V 1% D4C44
VDD25 VDD25

2
61 0.1UF/16V 61 /DDR4

2
VDD24 VDD24

2
64 64 0.1UF/16V
VDD23 VDD23

2
67 GND 67 GND
VDD22 VDD22
70 146 70 146
VDD21 VREFCA VDD21 VREFCA
73 H_D4A_VREFCA 73 H_D4B_VREFCA
VDD20 VDD20
76 76
VDD19 VDD19
80 80

1
VDD18 VDD18
83 D4R6 83 D4R8
VDD17 VDD17
85 1KOhm 85 1KOhm
VDD16 VDD16
88 1% 88 1%
VDD15 VDD15
90 90

2
VDD14 VDD14
92 92
VDD13 VDD13
204 204
VDD12 VDD12
206 289 206 289
VDD11 P_GND1 VDD11 P_GND1
209 290 GND 209 290 GND
VDD10 P_GND2 VDD10 P_GND2
212 212
VDD9 VDD9
215 215
VDD8 (43) D4_VREFCA_A VDD8 (43) D4_VREFCA_B
217 217
VDD7 VDD7
220 220
VDD6 VDD6
223 X7R D4C47 223 X7R X7R
VDD5 VDD5

1
226 D4C39 1UF/16V D4C48 226 D4C45 D4C46 D4C50
VDD4 VDD4
229 /X mbs_c0603 22UF/6.3V 229 /X 4.7UF/6.3V 22UF/6.3V
VDD3 VDD3
231 0.1UF/16V N/A mbs_c0603 231 0.1UF/16V mbs_c0603 mbs_c0603
VDD2 VDD2
2

2
233 233 /X
VDD1 /X VDD1
236 236
VDD0 VDD0

GND GND
2 147 2 147
VSS93 VSS46 VSS93 VSS46
4 149 4 149
VSS92 VSS45 VSS92 VSS45
6 151 6 151
VSS91 VSS44 VSS91 VSS44
9 154 9 154
VSS90 VSS43 VSS90 VSS43
11 156 11 156
VSS89 VSS42 VSS89 VSS42
13 158 13 158
VSS88 VSS41 VSS88 VSS41
15 160 15 160
VSS87 VSS40 VSS87 VSS40
17 162 17 162
VSS86 VSS39 VSS86 VSS39
20 165 20 165
VSS85 VSS38 VSS85 VSS38
22 167 22 167
VSS84 VSS37 VSS84 VSS37
24 169 24 169
VSS83 VSS36 VSS83 VSS36
26 171 26 171
VSS82 VSS35 VSS82 VSS35
28 173 28 173
VSS81 VSS34 VSS81 VSS34
31 176 31 176
VSS80 VSS33 VSS80 VSS33
33 178 33 178
VSS79 VSS32 VSS79 VSS32
35 180 35 180
VSS78 VSS31 VSS78 VSS31
37 182 37 182
VSS77 VSS30 VSS77 VSS30
39 184 39 184
VSS76 VSS29 VSS76 VSS29
42 187 42 187
VSS75 VSS28 VSS75 VSS28
44 189 44 189
VSS74 VSS27 VSS74 VSS27
46 191 46 191
VSS73 VSS26 VSS73 VSS26
48 193 48 193
VSS72 VSS25 VSS72 VSS25
50 195 50 195
VSS71 VSS24 VSS71 VSS24
53 198 53 198
VSS70 VSS23 VSS70 VSS23
55 200 55 200
VSS69 VSS22 VSS69 VSS22
57 202 57 202
VSS68 VSS21 VSS68 VSS21
94 239 94 239
VSS67 VSS20 VSS67 VSS20
96 241 96 241
VSS66 VSS19 VSS66 VSS19
98 243 98 243
VSS65 VSS18 VSS65 VSS18
101 246 101 246
VSS64 VSS17 VSS64 VSS17
103 248 103 248
VSS63 VSS16 VSS63 VSS16
105 250 105 250
VSS62 VSS15 VSS62 VSS15
107 252 107 252
VSS61 VSS14 VSS61 VSS14
109 254 109 254
VSS60 VSS13 VSS60 VSS13
112 257 112 257
VSS59 VSS12 VSS59 VSS12
114 259 114 259
VSS58 VSS11 VSS58 VSS11
116 261 116 261
VSS57 VSS10 VSS57 VSS10
118 263 118 263
VSS56 VSS9 VSS56 VSS9
120 265 120 265
VSS55 VSS8 VSS55 VSS8
123 268 123 268
VSS54 VSS7 VSS54 VSS7
125 270 125 270
VSS53 VSS6 VSS53 VSS6
127 272 127 272
VSS52 VSS5 VSS52 VSS5
129 274 129 274
VSS51 VSS4 VSS51 VSS4
131 276 131 276
VSS50 VSS3 VSS50 VSS3
134 279 134 279
VSS49 VSS2 VSS49 VSS2
136 281 136 281
VSS48 VSS1 VSS48 VSS1
138 283 138 283
VSS47 VSS0 VSS47 VSS0

DDR4_DIMM_288P DDR4_DIMM_288P
s_ddr4_dimm_288p_2hold_fxco s_ddr4_dimm_288p_2hold_fxco
12002-00078800 12002-00078800
GND GND GND GND

VDDSPD +3V_ATX

D3F501
1 2

1.75A/6V

<Variant Name>

Title : -12V
ASUS TeK Computer INC
Engineer: IAN
Size Project Name Rev
A2 Z87-PRO R1.02A

Date: Monday, June 11, 2018 Sheet 41 of 113


VDDQ

X5R X5R X5R X5R X5R X5R X5R X5R X5R

1
Layout to 0603 PCB1 PCB2 PCB3 PCB4 PCB5 PCB6 PCB7 PCB8 PCB45
22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V
/DDR4

2
mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603
Layout Layout Layout
/X /X /X

DIMM 附近
GND

VDDQ

Put near DIMM Slot DIMM_A1


1

1
X5R X5R X5R X5R PCB13 PCB14 PCB15 PCB16
PCB9 PCB10 PCB11 PCB12 /X /DDR4 /X /X
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
2

2
/X
/DDR4 /DDR4 /DDR4

GND

VDDQ

Put near DIMM Slot DIMM_B1


1

X5R X5R X5R X5R PCB29 PCB30 PCB31 PCB32


PCB25 PCB26 PCB27 PCB28 /X /X /X /X
1UF/6.3V 1UF/6.3V 1UF/6.3V 1UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
2

/X/DDR4 /DDR4 /DDR4 /DDR4

GND

VTT_DDR VTT_DDR VPPDDR VPPDDR

X5R X5R X5R


1

1
D4C15 D4C16 D4C18 D4C19 D4C21 X7R X7R X7R X7R X7R X7R X7R X7R
4.7UF/6.3V /X /DDR4 4.7UF/6.3V 4.7UF/6.3V D4C22 D4C29 D4C30 D4C31 D4C32 D4C33 D4C34 D4C35 D4C36
0.1UF/16V 0.1UF/16V 1UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
2

2
/DDR4 /X /X /DDR4 /X /X/DDR4 /X /X
/X/DDR4 /X/DDR4 /X/DDR4

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Put near DIMM Slot DIMM_A Put near DIMM Slot DIMM_B Put near DIMM Slot DIMM_A Put near DIMM Slot DIMM_B

<Variant Name>

Title : DDR4 (Power CAPs)


ASUSTek Computer Inc.
Engineer: Miles Liu
Size Project Name Rev
A3 X99_Deluxe 1.00

Date: Monday, June 11, 2018 Sheet 42 of 113


(6,39,40,48,63) S_SMBCLK_MAIN S_SMBCLK_DDR (6,39,40,48,63)
(6,39,40,48,63) S_SMBDATA_MAIN S_SMBDATA_DDR (6,39,40,48,63)

CPU DDR Vref

For CPU DDR Vref

D4R16 2Ohm 1%
1 2
(34) H_D4_VREFCA_A D4_VREFCA_A (41)

X7R

1
D4C54 D4C53

1
/X 1UF/16V D4C27
0.1UF/16V mbs_c0603 /X

2
X7R 0.1UF/16V

2
/X
To DIMM Slot

GND

Place close to DIMM pin

D4R17 2Ohm 1%
1 2
(34) H_D4_VREFCA_B D4_VREFCA_B (41)

D4C51

1
1UF/16V D4C42 D4C43
mbs_c0603 /X /X
2

X7R 0.1UF/16V 0.1UF/16V

2
/X

<Variant Name>

GND Title : DDR4 (SMBUS/SPD)


ASUSTeK Computer Inc.
Engineer: Payton_Lin
Size Project Name Rev
A3 X99 VC Rev1.00 1.00

Date: Monday, June 11, 2018 Sheet 43 of 113


delete it
for EMS +12V

+3V +3V_D_DP +3V_DP

1
GQ14C1 delete for PL only delete for PL/EL colay
0.1UF/16V

2
/X EL 820U:11V040827130

1
1
G
mbs_c0402_ns GF3 GL35 PL 560U:11031V0004F300
2 3 GND 1 2 1 2

3
N_3V_DP_L 0603

D
S

1
/X
1.1A/8V

1
GQ14 AP2306GN + GCE1
GC25 /DP++ GC26 560UF/6.3V
0.1UF/16V s_polyswitch_2p_0805_h31_ns 0.1UF/16V 11031V0004F300
/DP++

2
/X /X s_cpl_560u6d3vsha_lfh_ns
s_sot23_h49_ns mbs_c0402_ns /DP++
mbs_c0402_ns
GND GND for DP to VGA ,3V boost to 5V

GCE1:
Co-lay SYMBOL:mbs_cpl_560u6d3vsha_lfh_ms
NOMASK SYMBOL:s_cpl_560u6d3vsha_lfh_ns

GD106 GD105
1 9 1 9
Line-1 NC4 Line-1 NC4
2 8 2 8

DP
Line-2 NC3 Line-2 NC3
3 3
GND GND
4 7 4 7
Line-3 NC2 Line-3 NC2
5 6 5 6

DP D
Line-4 NC1 Line-4 NC1
GCXR1~8:
非蓋漆symbol:s_shortpin_r0402_jp_5mil AZ1045-04F AZ1045-04F
蓋漆symbol:mbs_r0402_ns
/X /X
GCX45 0.1UF/16V GCXR1 1 2 /X SHORTPIN_0402 GND GND
2 1 X7R mbs_r0402_ns s_dfn_10p_20_98x39_h26_ns s_dfn_10p_20_98x39_h26_ns
(32) H_DP_TXP0 H_DP_TXP0_R (46)
/DP++ H_DP_TXP0_C

1
mbs_c0402_ns SLX9 mbs_choke_4p_79x47_nm
GCX46 0.1UF/16V 90Ohm/100MHz
2 1 X7R /X

4
(32) H_DP_TXN0 H_DP_TXN0_R (46)
/DP++ H_DP_TXN0_C GCXR2 1 2 /X SHORTPIN_0402
mbs_c0402_ns mbs_r0402_ns

GCX47 0.1UF/16V GCXR3 1 2 /X SHORTPIN_0402


2 1 X7R mbs_r0402_ns
(32) H_DP_TXP1 /X H_DP_TXP1_R (46)
/DP++ H_DP_TXP1_C

1
SLX10 mbs_choke_4p_79x47_nm
mbs_c0402_ns
GCX48 0.1UF/16V 90Ohm/100MHz
2 1 X7R

4
(32) H_DP_TXN1 H_DP_TXN1_R (46)
/DP++ H_DP_TXN1_C GCXR4 1 2 /X SHORTPIN_0402
mbs_c0402_ns mbs_r0402_ns
GCX49 0.1UF/16V GCXR5 1 2 /X SHORTPIN_0402
2 1 X7R mbs_r0402_ns
(32) H_DP_TXP2 H_DP_TXP2_R (46)
/DP++ H_DP_TXP2_C

1
mbs_c0402_ns SLX11 mbs_choke_4p_79x47_nm
GCX50 0.1UF/16V 90Ohm/100MHz
2 1 X7R /X
3

4
(32) H_DP_TXN2 H_DP_TXN2_R (46)
/DP++ H_DP_TXN2_C GCXR6 1 2 /X SHORTPIN_0402
mbs_c0402_ns mbs_r0402_ns

GCX51 0.1UF/16V GCXR7 1 2 /X SHORTPIN_0402


2 1 X7R mbs_r0402_ns
(32) H_DP_TXP3 H_DP_TXP3_R (46)
3

4
/DP++ H_DP_TXP3_C
90Ohm/100MHz
mbs_c0402_ns
GCX52 0.1UF/16V SLX12 mbs_choke_4p_79x47_nm
2 1 X7R /X
(32) H_DP_TXN3 H_DP_TXN3_R (46)
2

/DP++ H_DP_TXN3_C GCXR8 1 2 /X SHORTPIN_0402


mbs_c0402_ns mbs_r0402_ns

+3V
2

GR1509

100KOhm
From CPU
/X/DP++
mbs_c0402_ns mbs_r0402_ns
1

+3V GCX20 0.1UF/16V


2 1 X7R
(32) H_DP_AUXN
/DP++ H_DP_B_AUXN_C
2 1
(32) H_DP_AUXP
X7R H_DP_B_AUXP_C
2

GCX22 0.1UF/16V GR1510


/DP++
(59) S_DP_DDC_DATA
mbs_c0402_ns 100KOhm
(59) S_DP_DDC_CLK
1

GC543 GC544 GC545 GC546 /X/DP++


10UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V mbs_r0402_ns
From PCH
1

mbs_c0603_ns /X/DP++ /X/DP++ /X/DP++


2

/DP++
mbs_c0402_ns mbs_c0402_ns mbs_c0402_ns

GND +3V_DP
+3V

+3V +5V GND


GND GC547

1
GR1345 1UF/16V

1
19
18
17
16
15
14
13
+3V DU1 mbs_c0603
0Ohm /X GR1506
1

GND3
GND2
GND1
SCLB
SDAB
P_AUX_DP+
P_AUX_DP-

2
GR1512 mbs_r0603_ns 100KOhm
/X
mbs_c0603_ns
/DP++
AUX Output
1KOhm

2
1
/DP++ GND mbs_r0402_ns
mbs_r0603_ns 1 12
2

SDAA C_AUX_DP- H_DP_AUXN_C (46)


DP_CTRL_DATA 2 11 H_DP_AUXN_C
1
1

SCLA C_AUX_DP+ H_DP_AUXP_C (46)


GR1513 GR1514 DP_CTRL_CLK 3 10 H_DP_AUXP_C
VCCB DP_PWR
2.2KOhm 2.2KOhm 4 9
EN DNG_DET HDMI_DP_DETECT (46)
/X/DP++ /X/DP++

1
mbs_r0402_ns mbs_r0402_ns GR1508
2
2

100KOhm GC541 GC542

C_HPD
P_HPD

VCCA
GND
/DP++ 470PF/50V 470PF/50V

2
DP_CTRL_DATA mbs_r0402_ns /X /X

2
DP_CTRL_CLK NCT3532Y +3V mbs_c0402_ns mbs_c0402_ns

5
6
7
8
06015-00250000
s_qfn_16p_s118_2via_h39_ns
/DP++ GND GND GND

S_DP_HPD_H

S_DP_HPD (59)

From PCH
+5V GND
S_DP_HPD_R (46)
S_DP_HPD_Q close to connector
2

3
3

D
/X GR1511 GD14
GQ43 0Ohm
11 H2N7002 /DP++ 1 6
G mbs_r0402_ns S_DP_HPD_R HDMI_DP_DETECT +3V
S
1

2 GR1503
2
2

GC540 +5V
s_sot23_h49_ns
1

GR1502 100KOhm
100KOhm GQ43C1 /DP++ 100PF/50V 2 5
/X 1.5PF/50V mbs_r0402_ns /X

1
2

mbs_r0603_ns mbs_c0402_ns GR1515


/X
1

1KOhm
mbs_c0402_ns GND GND /DP++
GND GND GND 3 4 vendor suggests

2
H_DP_AUXP_C H_DP_AUXN_C mbs_r0402_ns <Variant Name>

IP4220CZ6 Title : DP_MUX_PS8331


S_DP_HPD_H /X S_DP_HPD

HPD s_sot23_6p_ns ASUSTeK COMPUTER INC


Engineer: Morse_Peng
Size Project Name Rev
A2 SkyLake VC R1.00

Date: Monday, June 11, 2018 Sheet 44 of 113


delete it

delete this page for HDMI/DVI colay


for EMS

(32) H_HDMI_TXCN SW_HDMI_TXDP2_R (46)


H_HDMI_TXCN SW_HDMI_TXDP2_R
(32) H_HDMI_TXCP SW_HDMI_TXDN2_R (46)
+5V_DVI/HDMI H_HDMI_TXCP SW_HDMI_TXDN2_R
(32) H_HDMI_TXDN2 SW_HDMI_TXDP1_R (46)
H_HDMI_TXDN2 SW_HDMI_TXDP1_R
(32) H_HDMI_TXDP2 SW_HDMI_TXDN1_R (46)
H_HDMI_TXDP2 SW_HDMI_TXDN1_R
(32) H_HDMI_TXDN1 SW_HDMI_TXDP0_R (46)
H_HDMI_TXDN1 SW_HDMI_TXDP0_R
(32) H_HDMI_TXDP1 SW_HDMI_TXDN0_R (46)
H_HDMI_TXDP1 SW_HDMI_TXDN0_R
(32) H_HDMI_TXDN0 SW_HDMI_TXCP_R (46)

1
H_HDMI_TXDN0 SW_HDMI_TXCP_R
(32) H_HDMI_TXDP0 SW_HDMI_TXCN_R (46)
GC16 H_HDMI_TXDP0 SW_HDMI_TXCN_R
0.1UF/16V

2
X7R
SW_HDMI_DDC_CLK (46)
N/A SW_HDMI_DDC_CLK
SW_HDMI_DDC_DATA (46)
GND SW_HDMI_DDC_DATA
SW_HDMI_HPD (46)
SW_HDMI_HPD

/HDMI GCX9 0.1UF/16V mbs_c0402_ns mbs_r0402_ns GR1528 470Ohm /HDMI


2 1 X7R 1 2
H_HDMI_TXDP2 /HDMI GCX10 0.1UF/16V H_HDMI_TXDP2_C
mbs_c0402_ns mbs_r0402_ns GR1532 470Ohm /HDMI
2 1 X7R 1 2
H_HDMI_TXDN2 /HDMI GCX11 0.1UF/16V H_HDMI_TXDN2_C
mbs_c0402_ns mbs_r0402_ns GR1525 470Ohm /HDMI
2 1 X7R 1 2
H_HDMI_TXDP1 /HDMI GCX12 0.1UF/16V H_HDMI_TXDP1_C
mbs_c0402_ns mbs_r0402_ns GR1530 470Ohm /HDMI
2 1 X7R 1 2
H_HDMI_TXDN1 /HDMI GCX13 0.1UF/16V H_HDMI_TXDN1_C
mbs_c0402_ns mbs_r0402_ns GR1534 470Ohm /HDMI
2 1 X7R 1 2
H_HDMI_TXDP0 /HDMI GCX14 0.1UF/16V H_HDMI_TXDP0_C
mbs_c0402_ns mbs_r0402_ns GR1533 470Ohm /HDMI
2 1 X7R 1 2
H_HDMI_TXDN0 /HDMI GCX15 0.1UF/16V H_HDMI_TXDN0_C
mbs_c0402_ns mbs_r0402_ns GR1529 470Ohm /HDMI
2 1 X7R 1 2
H_HDMI_TXCP /HDMI GCX16 0.1UF/16V H_HDMI_TXCP_C
mbs_c0402_ns mbs_r0402_ns GR1531 470Ohm /HDMI
2 1 X7R 1 2
H_HDMI_TXCN H_HDMI_TXCN_C

+3V
+5V_DVI/HDMI
+3V

3
GR1537
0Ohm 5

2
/X GQ16B

1
GR1527 GR1526 mbs_r0402_ns 2N7002KDW

1
2.7KOhm 2.7KOhm /HDMI GQ16BC1
mbs_r0603_ns mbs_r0603_ns 1.5PF/50V

2
s_sot363_philips_ns

2
/HDMI /HDMI
/X

1
1 6
(59) S_HDMI_DDC_DATA
S_HDMI_DDC_DATA SW_HDMI_DDC_DATA mbs_c0402_ns

GQ17A
2N7002KDW GND
/HDMI

5
s_sot363_philips_ns
4 3
(59) S_HDMI_DDC_CLK
S_HDMI_DDC_CLK SW_HDMI_DDC_CLK
/HDMI GQ17B
+3V 2N7002KDW
+3V +3V
s_sot363_philips_ns
1

1
GQ17AC1 GQ17BC1 GR1536
1.5PF/50V 1.5PF/50V 1MOHM GQ16AC1
2

/X /X /HDMI 1.5PF/50V

2
mbs_c0402_ns mbs_c0402_ns
/X

1
mbs_r0402_ns
GND GND mbs_c0402_ns

2
1 6
(59) S_HDMI_HPD
S_HDMI_HPD SW_HDMI_HPD

GQ16A

1
2N7002KDW GR1535
/HDMI 20KOhm
/HDMI
s_sot363_philips_ns
mbs_r0402_ns

2
GND

GD103 GD104
1 9 1 9
Line-1 NC4 Line-1 NC4
2 8 2 8
Line-2 NC3 Line-2 NC3
3 3
GND GND
4 7 4 7
Line-3 NC2 Line-3 NC2
5 6 5 6
GCXR9~16: Line-4 NC1 Line-4 NC1
非蓋漆symbol:s_shortpin_r0402_jp_5mil
蓋漆symbol:mbs_r0402_ns AZ1045-04F AZ1045-04F

/X /X
GCXR9 1 2 /X GND GND
0402 s_dfn_10p_20_98x39_h26_ns s_dfn_10p_20_98x39_h26_ns
4

H_HDMI_TXDN2_C SW_HDMI_TXDN2_R
90Ohm/100MHz /X
SLX5 mbs_choke_4p_79x47_nm
1

H_HDMI_TXDP2_C GCXR10 1 2 /X SW_HDMI_TXDP2_R


0402

GCXR11 1 2 /X
0402
4

H_HDMI_TXDN1_C SW_HDMI_TXDN1_R
90Ohm/100MHz /X
SLX6 mbs_choke_4P_79x47_nm
1

H_HDMI_TXDP1_C GCXR12 1 2 /X SW_HDMI_TXDP1_R


0402

GCXR13 1 2 /X
0402
4

H_HDMI_TXDN0_C SW_HDMI_TXDN0_R
90Ohm/100MHz /X
SLX7 mbs_choke_4P_79x47_nm
1

H_HDMI_TXDP0_C GCXR14 1 2 /X SW_HDMI_TXDP0_R


0402

GCXR15 1 2 /X
0402
H_HDMI_TXCP_C SW_HDMI_TXCP_R
1

SLX8 mbs_choke_4P_79x47_nm
90Ohm/100MHz /X
4

H_HDMI_TXCN_C GCXR16 1 2 /X SW_HDMI_TXCN_R


0402

GD13

1 6
SW_HDMI_HPD

+5V_DVI/HDMI_Q

2 5

<Variant Name>
GND
3 4
SW_HDMI_DDC_DATA SW_HDMI_DDC_CLK Title : HDMI

ESD
IP4220CZ6 Engineer:
/X ASUSTek Computer Inc. alex_zhou
s_sot23_6p_ns Size Project Name Rev
A2 Standard Circuit 0.01A

Date: Monday, June 11, 2018 Sheet 45 of 113


2.2

(44) H_DP_TXP0_R

(44) H_DP_TXN0_R SW_HDMI_HPD (45)


SW_HDMI_DDC_CLK
(44) H_DP_TXP1_R

SW_HDMI_DDC_DATA
(44) H_DP_TXN1_R SW_HDMI_DDC_DATA (45)
(44) H_DP_TXP2_R SW_HDMI_DDC_CLK (45)
SW_HDMI_HPD

(44) H_DP_TXN2_R
(44) H_DP_TXP3_R SW_HDMI_TXCN_R (45)

1
SW_HDMI_TXCP_R (45)
GC10 GC11 GC9
(44) H_DP_TXN3_R
1.5PF/50V 1.5PF/50V 1.5PF/50V (44) HDMI_DP_DETECT SW_HDMI_TXDN0_R (45)

2
/X/HDMI /X/HDMI /X/HDMI SW_HDMI_TXDP0_R (45)
mbs_c0402_ns mbs_c0402_ns mbs_c0402_ns (44) H_DP_AUXP_C
SW_HDMI_TXDN1_R (45)
(44) H_DP_AUXN_C SW_HDMI_TXDP1_R (45)
GND GND GND (44) S_DP_HPD_R
SW_HDMI_TXDN2_R (45)
SW_HDMI_TXDP2_R (45)

+3V_DP

DP
22 HDMI
P_GND2
1 24 1 20
ML_LANE_0(P) P_GND4 1 P_GND1
H_DP_TXP0_R 2 SW_HDMI_TXDP2_R 2 22
GND1 2 P_GND3
3 3
ML_LANE_0(N) 3
H_DP_TXN0_R 4 SW_HDMI_TXDN2_R 4
ML_LANE_1(P) 4
H_DP_TXP1_R 5 SW_HDMI_TXDP1_R 5
GND2 5
6 6
ML_LANE_1(N) 6
H_DP_TXN1_R 7 SW_HDMI_TXDN1_R 7
ML_LANE_2(P) 7
H_DP_TXP2_R 8 SW_HDMI_TXDP0_R 8
GND3 8
9 9
ML_LANE_2(N) 9
H_DP_TXN2_R 10 SW_HDMI_TXDN0_R 10
ML_LANE_3(P) 10
H_DP_TXP3_R 11 SW_HDMI_TXCP_R 11
GND4 11
12 12
ML_LANE_3(N) 12
H_DP_TXN3_R 13 SW_HDMI_TXCN_R 13
CONFIG1 13
HDMI_DP_DETECT 14 +5V_DVI/HDMI 14
CONFIG2 14
15 15
AUX_CH_(P) 15
H_DP_AUXP_C 16 SW_HDMI_DDC_CLK 16
GND5 16
17 SW_HDMI_DDC_DATA 17
AUX_CH_(N) 17
H_DP_AUXN_C 18 18 23
HOT_PLUG_DETECT 18 P_GND4
S_DP_HPD_R 19 19 21
RETURN 19 P_GND2
20 23 SW_HDMI_HPD
DP_PWR P_GND3
21 HDMI_CON_19P
P_GND1
s_hdmi_19p_4hd_fxcn_lf3_ns
DISPLAYP_CON_20P
/HDMI
/DP++
GND GND
s_dp_con_20p_4hd_fox_lf3_ns

GND 12022-00025000

HDMI: 12022-00047500
DP: 12022-00025000

<Variant Name>

Title : BACK IO_VGA/DVI/HDMI/DP

ASUSTek COMPUTER INC.


Engineer: KENNY_CHEN
Size Project Name Rev
R1.02A
A2 Z87-PRO
Date: Monday, June 11, 2018 Sheet 46 of 113
delete it
for EMS
+5V

POWER for HDMI & DVI


+12V
GQ23
2 AP2306GN

2
S
G
1
1

1
D GQ23C1
3 0.1UF/16V

3
/X

2
+5V_DVI/HDMI
+3V
GND GR129 470Ohm /DVI
1 2
H_DVI_TXDN2_C GR130 470Ohm /DVI

2
1 2
GR70 GR69 H_DVI_TXDP2_C GR131 470Ohm /DVI
If only HDMI,this power must still need 2.7KOhm 2.7KOhm 1 2
mbs_r0603 mbs_r0603 H_DVI_TXDN1_C GR132 470Ohm /DVI

2
/DVI /DVI 1 2

1
1 6 H_DVI_TXDP1_C GR133 470Ohm /DVI
(59) S_DVI_DDC_DATA
SW_DVI_DDC_DATA 1 2
H_DVI_TXDN0_C GR134 470Ohm /DVI
GQ11A 1 2
+5V_DVI/HDMI_Q +5V_DVI/HDMI 2N7002KDW H_DVI_TXDP0_C GR135 470Ohm /DVI
/DVI 1 2

5
GF1 H_DVI_TXCN_C GR136 470Ohm /DVI
1 2 4 3 1 2
(59) S_DVI_DDC_CLK

1
GC5 2N7002KDW SW_DVI_DDC_CLK H_DVI_TXCP_C
1.75A 0.1UF/16V
GQ11B
mbs_polyswitch_2p_0805_h31 /X +3V /DVI +3V

2
+3V +3V

3
GND

2
GQ11AC1 GQ11BC1 GR42

1
1.5PF/50V 1.5PF/50V GR251 GQ12AC1 0Ohm 5
/X /X 1MOHM 1.5PF/50V /X/DVI

4
2

1
/X GQ12B GQ12BC1
/DVI

1
2N7002KDW 1.5PF/50V

1
/DVI /X

2
GND GND

2
1 6
(59) S_DVI_HPD
SW_DVI_HPD

GQ12A
GND

1
2N7002KDW GR151
/DVI 20KOhm

/DVI

2
GND

GD101 GD102
1 9 1 9
Line-1 NC4 Line-1 NC4
2 8 2 8
Line-2 NC3 Line-2 NC3
3 3
GND GND
4 7 4 7
Line-3 NC2 Line-3 NC2
5 6 5 6
Line-4 NC1 Line-4 NC1

AZ1045-04F AZ1045-04F

/X /X

GCX28 0.1UF/16V GCXR17 1 2 /X GND GND


2 1 0402
X7R
(32) H_DVI_TXDN2
H_DVI_TXDN2_C SW_DVI_TXDN2_R
1

/DVI 90Ohm/100MHz /X
GCX27 0.1UF/16V SLX1 mbs_choke_4p_79x47_nm
2 1 X7R
4

(32) H_DVI_TXDP2
H_DVI_TXDP2_C GCXR18 1 2 /X SW_DVI_TXDP2_R
0402
/DVI
GCX29 0.1UF/16V GCXR19 1 2 /X
2 1 0402
X7R
(32) H_DVI_TXDN1
H_DVI_TXDN1_C SW_DVI_TXDN1_R
DVI
1

/DVI
GCX30 0.1UF/16V
SLX2 mbs_choke_4p_79x47_nm
90Ohm/100MHz /X
DVI 1
1
2 1 X7R 9 SW_DVI_TXDN2_R
4

(32) H_DVI_TXDP1 9
H_DVI_TXDP1_C GCXR20 1 2 /X SW_DVI_TXDP1_R 17 SW_DVI_TXDN1_R
0402 17
/DVI 2 SW_DVI_TXDN0_R
2
GCX31 0.1UF/16V GCXR21 1 2 /X 10 SW_DVI_TXDP2_R
0402 10
2 1 X7R 18 SW_DVI_TXDP1_R
(32) H_DVI_TXDN0 18
H_DVI_TXDN0_C SW_DVI_TXDN0_R 3 SW_DVI_TXDP0_R
1

3
/DVI SLX3 mbs_choke_4p_79x47_nm 11
11
GCX32 0.1UF/16V 90Ohm/100MHz /X 25 19
P_GND1 19
2 1 X7R 26 4
4

(32) H_DVI_TXDP0 P_GND2 4


H_DVI_TXDP0_C GCXR22 1 2 /X SW_DVI_TXDP0_R 27 12
0402 P_GND3 12
/DVI 28 20
P_GND4 20
GCX33 0.1UF/16V GCXR23 1 2 /X 29 5 +5V_DVI/HDMI
0402 P_GND5 5
2 1 X7R 30 13
(32) H_DVI_TXCN P_GND6 13
H_DVI_TXCN_C SW_DVI_TXCN_R 31 21
1

NP_NC1 21
/DVI SLX4 mbs_choke_4p_79x47_nm 32 6
NP_NC2 6
GCX34 0.1UF/16V 90Ohm/100MHz /X 14 SW_DVI_DDC_CLK
14
2 1 X7R 22
4

(32) H_DVI_TXCP 22
H_DVI_TXCP_C GCXR24 1 2 /X SW_DVI_TXCP_R 7
0402 7
/DVI 15 SW_DVI_DDC_DATA
15
23
23
GND 8 SW_DVI_TXCP_R
8
16
16
24 SW_DVI_HPD
24
SW_DVI_TXCN_R
塑膠固定pin(NC) DVI_CON_24P
12010-00032500
/DVI
close to connector GND

SW_DVI_DDC_DATA SW_DVI_DDC_CLK SW_DVI_HPD


GD12

1
1 6 GC49 GC50 GC51
SW_DVI_HPD SW_DVI_DDC_CLK

2
100PF/50V 100PF/50V 100PF/50V
/X/EMI /X/EMI /X/EMI
+5V_DVI/HDMI_Q

2 5 GND GND GND

GND
3 4
SW_DVI_DDC_DATA

IP4220CZ6
/X

<Variant Name>

Title : DVI REDUCED LEV-SHIFT

ASUSTek COMPUTER INC.


Engineer: Morse_Peng
Size Project Name Rev
R1.00
A2 SkyLake VC
Date: Monday, June 11, 2018 Sheet 47 of 113
+3V +1.2VO_VGA +1.2V_VGA +3V +3V_VGAVCCA +3V +3V_VGADAC +3V +VCC_VGASYNC

GL3 GL1 GL2 GL4


1 2 1 2 1 2 1 2
0603 0603 0603
SHORTPIN_0603_NM /X /X /X
1

1
GU1C14 GU1C26 GU1C25 GU1C225 /X GU1C4 GU1C1 GU1C201 GU1C20 GU1C220 GU1C17 GU1C217
0.1UF/16V 0.1UF/16V 1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 4.7UF/6.3V 0.1UF/16V 10UF/6.3V 0.1UF/16V 4.7UF/6.3V
X7R X7R mbs_c0603 X7R X7R X7R mbs_c0603 X7R mbs_c0805 X7R mbs_c0603
2

2
/VGA /VGA X7R /X /VGA /X X5R /VGA X5R /VGA X5R
/VGA /VGA /VGA /X

GND GND GND GND GND GND GND GND GND

+3V

RTD2166 Slave Address :

1
GND GU1C29 GU1C30 GU1R28
0x64/0x65 and 0x68/0x69 1 2
10PF/50V 10PF/50V
/X /X DP2VGA_LOWPWR_EN#

2
4.7KOHM
N/A
(6,39,40,63) S_SMBDATA_MAIN
+1.2VO_VGA

(6,39,40,63) S_SMBCLK_MAIN
+3V +3V

(59) S_DP2VGA_HPD
GU1R27
GU1R32 1 2 100KOhm 1 2
/VGA DP2VGA_LDO_EN
4.7KOHM
/X
+3V_VGAVCCA GND

37
36
35
34
33

32

31

30

29

28

27

26

25
GU1
GU1R3 1 2 100KOhm +3V_VGADAC

GND6
GND5
GND4
GND3
GND2

HPD

SMB_SCL
EXT1.2V_CTRL

SMB_SDA

EXT_CLK_IN

LDO_RSTB

PVCC_33

VCCK_12
/X +3V_VGAVCCA
GU1R2 1 2 100KOhm
/X
+1.2V_VGA
GND 1 24
AVCC_33 GND1

GU1C2 2 1 0.1UF/16V 2 23
(32) H_DP2VGA_AUXP AUX_P RED_P VGA_RED (49)
X7R /VGA H_DP2VGA_AUXP_C
GU1C3 2 1 0.1UF/16V 3 22
(32) H_DP2VGA_AUXN AUX_N GREEN_P VGA_GREEN (49)
X7R /VGA H_DP2VGA_AUXN_C
4 21
AVCC_12 BLUE_P VGA_BLUE (49)
GU1C5 2 1 0.1UF/16V 5 20
(32) H_DP2VGA_TXP0 LANE0_P VDD_DAC_33
X7R /VGA H_DP2VGA_TXP0_C
GU1C6 2 1 0.1UF/16V 6 19
(32) H_DP2VGA_TXN0 LANE0_N HSYNC VGA_HSYNC (49)
X7R /VGA H_DP2VGA_TXN0_C
GU1C7 2 1 0.1UF/16V 7 18
(32) H_DP2VGA_TXP1 LANE1_P VSYNC VGA_VSYNC (49)
X7R /VGA H_DP2VGA_TXP1_C
GU1C8 2 1 0.1UF/16V 8 17
(32) H_DP2VGA_TXN1 LANE1_N HVSYNC_PWR
X7R /VGA H_DP2VGA_TXN1_C +VCC_VGASYNC

POL1/SPI_CEB

GPI1/SPI_CLK

GPI3/SPI_SO
GPI2/SPI_SI

VGA_SDA
VGA_SCL
VCC_33
GND

POL2
RTD2166-VAS-CG
9

10

11

12

13

14

15

16
/VGA +3V

VGA_DDC_DATA (49)

VGA_DDC_CLK (49)
DP2VGA_POL2

DP2VGA_POL1

2
+3V
GU1R12
4.7KOHM
GU1R9 1 2 4.7KOHM /VGA
/VGA

1
GU1R10 1 2 4.7KOHM
GP_DP2VGA_EEDID_EN (58)
/VGA

2
GU1R11 GP_DP2VGA_EEDID_EN GPIO select:
GND 4.7KOHM 1. could be GPI & GPO both, default GPI (no internal pull high resistor must)
/X 2. stand by power plane, 3V tolerance
3. Low level to disable RTD2166 Embedded EDID

1
4. High level to enable RTD2166 Embedded EDID
5. can't be High level under S3/S4/S5/Deep S4/Deep S5
GND

STANDARD CIRCUIT BOM need DP2VGA no DP2VGA

XUMB OTHER <Variant Name>


/VGA mount unmount

SZ_DP2VGA_1.0B
Title : RTD2166
/X unmount unmount
LOGO_HD_DEMO_OTHER ASUSTEK COMPUTER INC
Engineer: SZ Design IP
/X
Size Project Name Rev
A3
DP2VGA Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 48 of 113


D-Sub Connector Circuit for RTD2166
delete it for EMS
A. Choose D-Sub Connector Type by Project B. Modify Part Number of D-Sub Connector by Color
+5V +5V_D_VGA

GD4 GF6
1 2 1 2
+V_5V

1
SS14 1.1A/8V GC525
GL32 68NH /VGA /X/VGA /X/VGA 0.1UF/16V
1 2 X7R
(48) VGA_RED

2
VGA_RED_L /X
GL33 68NH /VGA
1 2 GND
(48) VGA_GREEN
VGA_GREEN_L
GL34 68NH /VGA
1 2 +5V_DVI/HDMI +5V_D_VGA
(48) VGA_BLUE
VGA_BLUE_L
GD15
2

2
GR1 0Ohm N/A

1
GR511 GR512 GR513 GC514 GC515 GC516 GC517 GC518 GC519 1 6 1 2 mbs_r0805
75Ohm 75Ohm 75Ohm 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V 10PF/50V
/VGA /VGA /VGA /VGA /VGA /VGA /VGA /VGA /VGA

2
1

2 5
D-Sub Power與HDMI/DVI Power共用
GND GND GND GND GND GND GND GND GND

GND
place near DP2VGA IC 3 4

IP4220CZ6
place near D-Sub Connector /VGA

+3V +3V +5V_D_VGA


GND

GQ34C1
2

2
GR500 1 2 GR503
2.7KOHM 0.1UF/16V 1.8KOhm
/X X7R /X mbs_r0603
1
1
G

/VGA GR521
1

1
2 3 1 2
2

(48) VGA_DDC_DATA
GQ34 H2N7002 VGA_DDC_DATA_Q VGA_DDC_DATA_R
D
S

/X 100Ohm

1
/VGA GC521
100PF/50V
+3V +3V +5V_D_VGA /X
A.2

2
for slew rate
GND

GQ35C1 control
2

2
GND
GR501
2.7KOHM
1 2
0.1UF/16V
GR502
1.8KOhm
High Rise D-Sub Connector
/X X7R /X mbs_r0603
1
1
G

/VGA GR522 +5V_D_VGA


1

2 3 1 2
2

(48) VGA_DDC_CLK
GQ35 H2N7002 VGA_DDC_CLK_Q VGA_DDC_CLK_R
D
S

/X 100Ohm

1
/VGA GC522
100PF/50V

16
/X VGA

2
GR505 1 2 /X
0402
GND 6
GR504 1 2 /X 1 11
0402 GD16 7
VGA_RED_L
2 12
1 6 VGA_GREEN_L 8 VGA_DDC_DATA_R
Level Shift 3 13
VGA_BLUE_L 9 VGA_HSYNC_R
4 14
10 VGA_VSYNC_R
2 5 5 15
VGA_DDC_CLK_R

GND D_SUB_15P

17
3 4 /VGA

place near DP2VGA IC


IP4220CZ6
/VGA 12010V00046300
GR524 1 2 33Ohm GND
(48) VGA_HSYNC
/VGA VGA_HSYNC_R
modify Part Number by color
GR523 1 2 33Ohm
(48) VGA_VSYNC
/VGA VGA_VSYNC_R
1

GC523 GC524 GC532 GC531


10PF/50V 4.7K Ohm 100PF/50V 22PF/50V
/X N/A /X N/A
2

10V212470210 <Variant Name>

for slew rate control


GND GND
place near D-Sub Connector GND GND
Title : RTD2166 D-Sub
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A3
DP2VGA Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 49 of 113


1.9

Support Gen3

+3VSB +3V_ATX +12V +12V +3V_ATX

PCIEX16

1
2
P_GND1
P_GND2
B1 A1
+12V_1 PRSNT1#
B2 A2
+12V_2 +12V_3
to SB SMBus(standby power) B3 A3
+12V_5 +12V_4
B4 A4
GND1 GND35
B5 A5
(63,69) S_SMBCLK_SLOT SMCLK JTAG2
B6 A6
(63,69) S_SMBDATA_SLOT SMDAT JTAG3
B7 A7
GND2 JTAG4
B8 A8
+3.3V_1 JTAG5
B9 A9
JTAG1 +3.3V_2
B10 A10
3.3Vaux +3.3V_3
B11 A11
WAKE# PWRGD
Pull-high at SB side

(58,69,72,89) S_WAKE#
O_X16_RST# (96)
B12 A12
RSVD2 GND36
XCX1 0.22UF/10V X5R B13 A13
GND3 REFCLK+ CK_100M_X16SL1P (54)

1
2 1 B14 A14
(31) H_X16_SL1_TXP0 HSOP0 REFCLK- CK_100M_X16SL1N (54)
2 1 H_X16_SL1_TXP0_C B15 A15 XC71
(31) H_X16_SL1_TXN0 HSON0 GND37
H_X16_SL1_TXN0_C B16 A16 1.5PF/50V
GND4 HSIP0 H_X16_SL1_RXP0 (31)

2
XCX2 0.22UF/10V X5R B17 A17
PRSNT2_1# HSIN0 H_X16_SL1_RXN0 (31) /X
B18 A18
GND5 GND38
GND
XCX3 0.22UF/10V X5R
2 1 B19 A19
(31) H_X16_SL1_TXP1 HSOP1 RSVD6
2 1 H_X16_SL1_TXP1_C B20 A20
(31) H_X16_SL1_TXN1 HSON1 GND39
H_X16_SL1_TXN1_C B21 A21
GND6 HSIP1 H_X16_SL1_RXP1 (31)
XCX5 0.22UF/10V X5R XCX4 0.22UF/10V X5R B22 A22
GND7 HSIN1 H_X16_SL1_RXN1 (31)
2 1 B23 A23
(31) H_X16_SL1_TXP2 HSOP2 GND40
2 1 H_X16_SL1_TXP2_C B24 A24
(31) H_X16_SL1_TXN2 HSON2 GND41
H_X16_SL1_TXN2_C B25 A25
GND8 HSIP2 H_X16_SL1_RXP2 (31)
XCX7 0.22UF/10V X5R XCX6 0.22UF/10V X5R B26 A26
GND9 HSIN2 H_X16_SL1_RXN2 (31)
2 1 B27 A27
(31) H_X16_SL1_TXP3 HSOP3 GND42
2 1 H_X16_SL1_TXP3_C B28 A28
(31) H_X16_SL1_TXN3 HSON3 GND43
H_X16_SL1_TXN3_C B29 A29
GND10 HSIP3 H_X16_SL1_RXP3 (31)
XCX8 0.22UF/10V X5R B30 A30
RSVD3 HSIN3 H_X16_SL1_RXN3 (31)
B31 A31
PRSNT2_2# GND44
B32 A32
GND11 RSVD7

XCX9 0.22UF/10V X5R


2 1 B33 A33
(31) H_X16_SL1_TXP4 HSOP4 RSVD8
2 1 H_X16_SL1_TXP4_C B34 A34
(31) H_X16_SL1_TXN4 HSON4 GND45
H_X16_SL1_TXN4_C B35 A35
GND12 HSIP4 H_X16_SL1_RXP4 (31)

www.teknisi-indonesia.com
XCX11 0.22UF/10V X5R XCX10 0.22UF/10V X5R B36 A36
GND13 HSIN4 H_X16_SL1_RXN4 (31)
2 1 B37 A37
(31) H_X16_SL1_TXP5 HSOP5 GND46
2 1 H_X16_SL1_TXP5_C B38 A38
(31) H_X16_SL1_TXN5 HSON5 GND47
H_X16_SL1_TXN5_C B39 A39
GND14 HSIP5 H_X16_SL1_RXP5 (31)
XCX13 0.22UF/10V X5R XCX12 0.22UF/10V X5R B40 A40
GND15 HSIN5 H_X16_SL1_RXN5 (31)
2 1 B41 A41
(31) H_X16_SL1_TXP6 HSOP6 GND48
2 1 H_X16_SL1_TXP6_C B42 A42
(31) H_X16_SL1_TXN6 HSON6 GND49
H_X16_SL1_TXN6_C B43 A43
GND16 HSIP6 H_X16_SL1_RXP6 (31)
XCX15 0.22UF/10V X5R XCX14 0.22UF/10V X5R B44 A44
GND17 HSIN6 H_X16_SL1_RXN6 (31)
2 1 B45 A45
(31) H_X16_SL1_TXP7 HSOP7 GND50
2 1 H_X16_SL1_TXP7_C B46 A46
(31) H_X16_SL1_TXN7 HSON7 GND51
H_X16_SL1_TXN7_C B47 A47
GND18 HSIP7 H_X16_SL1_RXP7 (31)
XCX16 0.22UF/10V X5R B48 A48
PRSNT2_3# HSIN7 H_X16_SL1_RXN7 (31)
X5R B49 A49
GND19 GND52
2 1 B50 A50
(31) H_X16_SL1_TXP8 HSOP8 RSVD9
2 1 H_X16_SL1_TXP8_C B51 A51
(31) H_X16_SL1_TXN8 HSON8 GND53
XCX17 0.22UF/10V H_X16_SL1_TXN8_C B52 A52
GND20 HSIP8 H_X16_SL1_RXP8 (31)
X5R XCX18 0.22UF/10V X5R B53 A53
GND21 HSIN8 H_X16_SL1_RXN8 (31)
2 1 B54 A54
(31) H_X16_SL1_TXP9 HSOP9 GND54
2 1 H_X16_SL1_TXP9_C B55 A55
(31) H_X16_SL1_TXN9 HSON9 GND55
XCX19 0.22UF/10V H_X16_SL1_TXN9_C B56 A56
GND22 HSIP9 H_X16_SL1_RXP9 (31)
X5R XCX20 0.22UF/10V X5R B57 A57
GND23 HSIN9 H_X16_SL1_RXN9 (31)
2 1 B58 A58
(31) H_X16_SL1_TXP10 HSOP10 GND56
2 1 H_X16_SL1_TXP10_C B59 A59
(31) H_X16_SL1_TXN10 HSON10 GND57
XCX21 0.22UF/10V H_X16_SL1_TXN10_C B60 A60
GND24 HSIP10 H_X16_SL1_RXP10 (31)
X5R XCX22 0.22UF/10V X5R B61 A61
GND25 HSIN10 H_X16_SL1_RXN10 (31)
2 1 B62 A62
(31) H_X16_SL1_TXP11 HSOP11 GND58
2 1 H_X16_SL1_TXP11_C B63 A63
(31) H_X16_SL1_TXN11 HSON11 GND59
XCX23 0.22UF/10V H_X16_SL1_TXN11_C B64 A64
GND26 HSIP11 H_X16_SL1_RXP11 (31)
X5RXCX24 0.22UF/10V X5R B65 A65
GND27 HSIN11 H_X16_SL1_RXN11 (31)
2 1 B66 A66
(31) H_X16_SL1_TXP12 HSOP12 GND60
2 1 H_X16_SL1_TXP12_C B67 A67
(31) H_X16_SL1_TXN12 HSON12 GND61
XCX25 0.22UF/10V H_X16_SL1_TXN12_C B68 A68
GND28 HSIP12 H_X16_SL1_RXP12 (31)
X5R XCX26 0.22UF/10V X5R B69 A69
GND29 HSIN12 H_X16_SL1_RXN12 (31)
2 1 B70 A70
(31) H_X16_SL1_TXP13 HSOP13 GND62
2 1 H_X16_SL1_TXP13_C B71 A71
(31) H_X16_SL1_TXN13 HSON13 GND63
XCX27 0.22UF/10V H_X16_SL1_TXN13_C
XCX28 0.22UF/10V X5R B72 A72
GND30 HSIP13 H_X16_SL1_RXP13 (31)
X5R B73 A73
GND31 HSIN13 H_X16_SL1_RXN13 (31)
2 1 B74 A74
(31) H_X16_SL1_TXP14 HSOP14 GND64
2 1 H_X16_SL1_TXP14_C B75 A75
(31) H_X16_SL1_TXN14 HSON14 GND65
XCX29 0.22UF/10V H_X16_SL1_TXN14_C B76 A76
GND32 HSIP14 H_X16_SL1_RXP14 (31)
X5R XCX30 0.22UF/10V X5R B77 A77
GND33 HSIN14 H_X16_SL1_RXN14 (31)
2 1 B78 A78
(31) H_X16_SL1_TXP15 HSOP15 GND66
2 1 H_X16_SL1_TXP15_C B79 A79
(31) H_X16_SL1_TXN15 HSON15 GND67
XCX31 0.22UF/10V H_X16_SL1_TXN15_C B80 A80
GND34 HSIP15 H_X16_SL1_RXP15 (31)
XCX32 0.22UF/10V X5R B81 A81
PRSNT2_4# HSIN15 H_X16_SL1_RXN15 (31)
B82 A82
RSVD4 GND68

CAP 在VCC 層不用挖空


SLOT_164P
12003-00036200
s_slot_pci_164p_2hd_fox_lf3

GND GND

B250M-A以下機種所使用的灰色側押尾料件料號12003-00036200,具體和SPM確認
(54) PCIEX16_SL1_PRSNT#

SLC1
2

0.1UF/16V
X7R
1

/X

GND

+12V
日製
XCE1
1

+ 270UF/16V

11031-0006F200
2

mbs_cpl270u16v_8x12_lfh_ms

GND
EL 470U: 11V040477330
PL 270U: 11031-0006F200

<Variant Name>

Title : PCIEX16_1(NAVY BLUE)

ASUSTek COMPUTER INC.


Engineer: IAN
Size Project Name Rev
R1.02A
A2 Z87-PRO
Date: Monday, June 11, 2018 Sheet 51 of 113
VCORE VCORE

LGA1151I
VCCSA VDDQ
LGA1151K A25 H32
VCC_A25 VCC_H32
A26 J21
VCC_A26 VCC_J21
AA6 AT18 A27 F32
VCCSA1 VDDQ_AT18 VCC_A27 VCC_F32
AA7 AT21 A28 F33
VCCSA2 VDDQ_AT21 VCC_A28 VCC_F33
AB6 AU13 A29 F34
VCCSA3 VDDQ_AU13 VCC_A29 VCC_F34
AB7 AU15 A30 G23
VCCSA4 VDDQ_AU15 VCC_A30 VCC_G23
AB8 AU19 B25 G24
VCCSA5 VDDQ_AU19 VCC_B25 VCC_G24
AC7 AU23 B27 G25
VCCSA6 VDDQ_AU23 VCC_B27 VCC_G25
AC8 AV11 B29 G26
VCCSA7 VDDQ_AV11 VCC_B29 VCC_G26
N7 AV17 B31 G27
VCCSA8 VDDQ_AV17 VCC_B31 VCC_G27
P7 AV21 B32 G28
VCCSA9 VDDQ_AV21 VCC_B32 VCC_G28
R7 AW10 B33 G29
VCCSA10 VDDQ_AW10 VCC_B33 VCC_G29
T7 AW14 B34 J22
VCCSA11 VDDQ_AW14 VCC_B34 VCC_J22
U7 AW25 B35 J23
VCCSA12 VDDQ_AW25 VCC_B35 VCC_J23
Y6 AY12 B36 J24
VCCSA15 VDDQ_AY12 VCC_B36 VCC_J24
Y7 AY16 VDDQ B37 J25
VCCSA16 VDDQ_AY16 VCC_B37 VCC_J25
Y8 AY18 C25 J26
VCCSA17 VDDQ_AY18 VCC_C25 VCC_J26
W7 AY23 C26 J27
VCCSA14 VDDQ_AY23 VCC_C26 VCC_J27
VCCIO V7 C27 J28
VCCSA13 VCC_C27 VCC_J28
AJ9 C28 J29
VCCPLL_OC VCC_C28 VCC_J29
+VCCSFR_OC_R C29 J30
VCC_C29 VCC_J30
AJ23 C30 J31
VCCIO1 HC3 放置在Top 層CPU 槽裡邊 VCC_C30 VCC_J31

1
AK11 HC3 C32 K16
VCCIO2 VCC_C32 VCC_K16
AK14 0.1UF/16V C34 K18
VCCIO3 Layout 注意:AJ9 pin 直接通過CPU VCC_C34 VCC_K18
AK24 mbs_c0603 C36 K20
VCCIO4 下方的VDDQ 給,不要繞很大的圈子 VCC_C36 VCC_K20

2
M8 X7R D25 K21
VCCIO5 VCC_D25 VCC_K21
P8 N/A D27 K23
VCCIO6 VCC_D27 VCC_K23
T8 D29 K25
VCCIO7 VCC_D29 VCC_K25
U8 GND D31 K27
VCCIO8 VCC_D31 VCC_K27
W8 D32 K29
VCCIO9 VCC_D32 VCC_K29
D33 K31
VCC_D33 VCC_K31
VCCST_VCCSFR D34 L14
VCC_D34 VCC_L14
D35 L15
VCC_D35 VCC_L15
V5 D36 L16
VCCST_V5 VCC_D36 VCC_L16
V6 E24 L17
VCCST_V6 VCC_E24 VCC_L17
E25 L18
VCC_E25 VCC_L18
V4 E26 L19
VCCPLL VCC_E26 VCC_L19
E27 L20
VCC_E27 VCC_L20
E28 L21
VCC_E28 VCC_L21
E29 L22
VCC_E29 VCC_L22
E30 L23
VCC_E30 VCC_L23
E32 L24
VCC_E32 VCC_L24
E34 L25
VCC_E34 VCC_L25
E36 L26
VCC_E36 VCC_L26
F23 L27
VCC_F23 VCC_L27
1 AD5 F24 L28
NP_NC1 VCCSA_SENSE H_VCCSA_VCC_SENSE (12) VCC_F24 VCC_L28
2 AF4 F25 L29
NP_NC2 VCCIO_SENSE H_VCCIO_VCC_SENSE (13) VCC_F25 VCC_L29
3 AE4 H_VCCIO_VCC_SENSE F27 L30
NP_NC3 VSS_SAIO_SENSE H_SAIO_VSS_SENSE (12,13) VCC_F27 VCC_L30
4 F29 M13
NP_NC4 VCC_F29 VCC_M13
5 F31 M14
NP_NC5 VCC_F31 VCC_M14
6 G30 M16
NP_NC6 VCC_G30 VCC_M16
7 G32 M18
NP_NC7 VCC_G32 VCC_M18
H22 M20
VCC_H22 VCC_M20
H23 M22
VCC_H23 VCC_M22
H25 M24
VCC_H25 VCC_M24
H27 M26
VCC_H27 VCC_M26
H29 M28
SOCKET1151 VCC_H29 VCC_M28
H31 M30
VCC_H31 VCC_M30
12001V00180100 AJ11 AJ12
VCC_AJ11 VCC_AJ12
AJ13 AJ14
VCC_AJ13 VCC_AJ14
LGA1151L AJ15 AJ16
VCC_AJ15 VCC_AJ16
AJ17 AJ18
VCC_AJ17 VCC_AJ18
HT24 1 J8 AC37 HR30 0Ohm AJ19 AJ20
RSVD_TP_J8 RSVD_AC37 VCC_AJ19 VCC_AJ20
HT25 1 J7 AB35 1 2 AJ21
RSVD_TP_J7 RSVD_AB35 H_SKTOCC# (35,96) VCC_AJ21
HT28 1 L8 AB37 H_SKTOCC#_R
IST_TRIG RSVD_AB37
HT29 1 K8 AB38 mbs_r0402 /KBLAKE M32 AJ29
RSVD_TP_K8 RSVD_AB38 VCC_M32 VCC_AJ29
AJ22 L31 AK21
RSVD_AJ22 VCC_L31 VCC_AK21
AV1 D15 K32 F35
RSVD_TP_AV1 RSVD_D15 VCC_K32 VCC_F35
AW2 K11 J33 F37 VCCSA
RSVD_TP_AW2 RSVD_K11 VCC_J33 VCC_F37
H33 G35
VCC_H33 VCC_G35
HT52 1 H8 G34 H34
RSVD_TP_H8/VSS VCC_G34 VCC_H34
AJ25 J35
VCC_AJ25 VCC_J35

1
K10 AJ26 K34 HC5
RSVD_K10 VCC_AJ26 VCC_K34
L10 AJ27 L33 HC4 10UF/6.3V
RSVD_L10 VCC_AJ27 VCC_L33
AJ28 1UF/6.3V mbs_c0603
VCC_AJ28

2
J17 /X /X
RSVD_J17
HT33 1 B39
RSVD_B39
HT34 1 C40 J15
RSVD_C40 RSVD_J15
J19 J14 GND
RSVD_J19 RSVD_J14
C38
VCC_SENSE H_VCC_SENSE (6)
G8 AU9 D38
VSS_G8 RSVD_AU9 VSS_SENSE H_VSS_SENSE (6)
AY3 AU10
VSS_AY3 RSVD_AU10

I D1 VCCST_VCCSFR VCCSA 放置在Top 層CPU 槽裡邊


HC12,HC13 VCCIO
(61) S_CPU_TRIGGER PROC_TRIGIN SOCKET1151
1 2 O B3 J13
(61) H_CPU_TRIGGER PROC_TRIGOUT RSVD_J13
HR25 20OHM
H_CPU_TRIGGER_R K13 12001V00180100
RSVD_K13
L12 J11
RSVD_L12 RSVD_J11
1

1
K12 HC9
RSVD_K12
HC6 HC7 HC8 10UF/6.3V HC13 HC10 HC11 HC12
22UF/6.3V 0.1UF/16V 0.1UF/16V mbs_c0603 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
2

2
/X /X /X /X /X /X /X
/X
1

HR26 mbs_c0603
Place at Socket Edge
SOCKET1151
560Ohm GND GND GND Place IN SOCKET CAVITY BOTTOM or TOP
12001V00180100 /X
GND Place IN SOCKET CAVITY BOTTOM
2

VDDQ

X5R X5R X5R


Title :
1

HC14 LGA1150 (POWER)


10UF/6.3V HC15 HC16 HC17 HC18 HC19 HC20 HC21
mbs_c0603 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 22UF/6.3V 0.1UF/16V 0.1UF/16V Engineer: IAN
2

ASUSTek Computer Inc.


N/A /X /X
/X /X /X /X /X
Size Project Name Rev
mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 mbs_c0603 GND
A3 Z87-PRO R1.02A
GND
Date: Monday, June 11, 2018 Sheet 36 of 113
VCCGT

LGA1151F LGA1151G LGA1151H


A11 AK29 AR24 C37 K39 AJ24 LGA1151J
VSS_A11 VSS_AK29 VSS_AR24 VSS_C37 VSS_K39 VSS_AJ24
A13 AK30 AR27 C5 K4 AJ30
VSS_A13 VSS_AK30 VSS_AR27 VSS_C5 VSS_K4 VSS_AJ30
A15 AK36 AR3 C8 K7 AK22 H_CPU_GND AA34
VSS_A15 VSS_AK36 VSS_AR3 VSS_C8 VSS_K7 VSS_AK22 VCCGT1
A17 AK37 AR30 C10 L13 AK27 AA35
VSS_A17 VSS_AK37 VSS_AR30 VSS_C10 VSS_L13 VSS_AK27 VCCGT2
A24 AK40 AR31 D24 L3 AR22 AA36
VSS_A24 VSS_AK40 VSS_AR31 VSS_D24 VSS_L3 VSS_AR22 VCCGT3
A7 AK5 AR32 D26 L32 AR23 AA37
VSS_A7 VSS_AK5 VSS_AR32 VSS_D26 VSS_L32 VSS_AR23 VCCGT4
AA3 AK6 AR33 D28 L6 AT15 AA38
VSS_AA3 VSS_AK6 VSS_AR33 VSS_D28 VSS_L6 VSS_AT15 VCCGT5
AA33 AK7 AR34 D30 L9 AU39 AB33
VSS_AA33 VSS_AK7 VSS_AR34 VSS_D30 VSS_L9 VSS_AU39 VCCGT6
AA8 AK8 AR35 D37 M1 AU40 AB34
VSS_AA8 VSS_AK8 VSS_AR35 VSS_D37 VSS_M1 VSS_AU40 VCCGT7
AB39 AK9 AR36 D39 M10 AV39 G36 H_CPU_GND
VSS_AB39 VSS_AK9 VSS_AR36 VSS_D39 VSS_M10 VSS_AV39 VCCGT8
AB5 AL1 AR4 D4 M12 AW38 G37
VSS_AB5 VSS_AL1 VSS_AR4 VSS_D4 VSS_M12 VSS_AW38 VCCGT9
AC3 AL11 AR5 D7 M15 F36 G38
VSS_AC3 VSS_AL11 VSS_AR5 VSS_D7 VSS_M15 VSS_F36 VCCGT10
AC33 AL14 AT10 E11 M17 H11 G39

1
VSS_AC33 VSS_AL14 VSS_AT10 VSS_E11 VSS_M17 VSS_H11 VCCGT11
AC34 AL2 AT11 E13 M19 H12 G40 HR29
VSS_AC34 VSS_AL2 VSS_AT11 VSS_E13 VSS_M19 VSS_H12 VCCGT12
AC35 AL21 AT12 E15 M21 H36 0Ohm
VSS_AC35 VSS_AL21 VSS_AT12 VSS_E15 VSS_M21 VCCGT13
AC6 AL24 AT13 E17 M23 H38
VSS_AC6 VSS_AL24 VSS_AT13 VSS_E17 VSS_M23 VCCGT14 mbs_r0603
AD1 AL27 AT14 E19 M25 H40

2
VSS_AD1 VSS_AL27 VSS_AT14 VSS_E19 VSS_M25 VCCGT15 /X
AD33 AL3 AT17 E21 M27 J36
VSS_AD33 VSS_AL3 VSS_AT17 VSS_E21 VSS_M27 VCCGT16
AD36 AL30 AT24 E23 M29 J37
VSS_AD36 VSS_AL30 VSS_AT24 VSS_E23 VSS_M29 VCCGT17
AD37 AL36 AT25 E3 M35 GND J38
VSS_AD37 VSS_AL36 VSS_AT25 VSS_E3 VSS_M35 VCCGT18
AD38 AL4 AT26 E31 M37 J39
VSS_AD38 VSS_AL4 VSS_AT26 VSS_E31 VSS_M37 VCCGT19
AD39 AL5 AT27 E33 M39 J40
VSS_AD39 VSS_AL5 VSS_AT27 VSS_E33 VSS_M39 VCCGT20
AD4 AM11 AT28 E35 M4 K36 GND
VSS_AD4 VSS_AM11 VSS_AT28 VSS_E35 VSS_M4 VCCGT21
AD40 AM14 AT29 E37 M7 K38
VSS_AD40 VSS_AM14 VSS_AT29 VSS_E37 VSS_M7 VCCGT22
AD6 AM17 AT30 E6 N3 K40
VSS_AD6 VSS_AM17 VSS_AT30 VSS_E6 VSS_N3 VCCGT23
AD7 AM19 AT31 E9 N33 L34
VSS_AD7 VSS_AM19 VSS_AT31 VSS_E9 VSS_N33 VCCGT24
AD8 AM24 AT32 F1 N6 L35
VSS_AD8 VSS_AM24 VSS_AT32 VSS_F1 VSS_N6 VCCGT25
AE3 AM27 AT34 F10 N8 L36
VSS_AE3 VSS_AM27 VSS_AT34 VSS_F10 VSS_N8 VCCGT26
AE33 AM30 AT36 F22 P1 L37
VSS_AE33 VSS_AM30 VSS_AT36 VSS_F22 VSS_P1 VCCGT27
AE36 AM31 AT37 F26 P35 L38
VSS_AE36 VSS_AM31 VSS_AT37 VSS_F26 VSS_P35 VCCGT28
AE5 AM32 AT38 F28 P37 L39
VSS_AE5 VSS_AM32 VSS_AT38 VSS_F28 VSS_P37 VCCGT29
AE8 AM33 AT39 F30 P39 L40
VSS_AE8 VSS_AM33 VSS_AT39 VSS_F30 VSS_P39 VCCGT30
AF1 AM34 AT40 F4 P4 M33
VSS_AF1 VSS_AM34 VSS_AT40 VSS_F4 VSS_P4 VCCGT31
AF33 AM35 AT5 F40 R3 M34
VSS_AF33 VSS_AM35 VSS_AT5 VSS_F40 VSS_R3 VCCGT32
AF36 AM36 AT6 F7 R33 M36
VSS_AF36 VSS_AM36 VSS_AT6 VSS_F7 VSS_R33 VCCGT33
AF37 AM37 AT7 G11 R6 M38
VSS_AF37 VSS_AM37 VSS_AT7 VSS_G11 VSS_R6 VCCGT34
AF40 AM38 AT8 G13 R8 M40
VSS_AF40 VSS_AM38 VSS_AT8 VSS_G13 VSS_R8 VCCGT35
AF5 AM39 AT9 G15 T1 N34
VSS_AF5 VSS_AM39 VSS_AT9 VSS_G15 VSS_T1 VCCGT36
AF8 AM40 AU1 G17 T35 N35
VSS_AF8 VSS_AM40 VSS_AU1 VSS_G17 VSS_T35 VCCGT37 P_CPU_GND_GT (6)
AG1 AM5 AU25 G19 T37 N36
VSS_AG1 VSS_AM5 VSS_AU25 VSS_G19 VSS_T37 VCCGT38
AG2 AN1 AU30 G22 T39 N37

1
VSS_AG2 VSS_AN1 VSS_AU30 VSS_G22 VSS_T39 VCCGT39
AG3 AN10 AU34 G3 T4 N38 HR27
VSS_AG3 VSS_AN10 VSS_AU34 VSS_G3 VSS_T4 VCCGT40
AG33 AN11 AU4 G31 U3 N39 0Ohm
VSS_AG33 VSS_AN11 VSS_AU4 VSS_G31 VSS_U3 VCCGT41
AG36 AN14 AU5 G33 U33 N40
VSS_AG36 VSS_AN14 VSS_AU5 VSS_G33 VSS_U33 VCCGT42 mbs_r0603
AG4 AN16 AU7 G6 U6 P33

2
VSS_AG4 VSS_AN16 VSS_AU7 VSS_G6 VSS_U6 VCCGT43 /X
AG5 AN19 AV2 H1 V1 P34
VSS_AG5 VSS_AN19 VSS_AV2 VSS_H1 VSS_V1 VCCGT44
AG8 AN22 AV26 H21 V35 P36
VSS_AG8 VSS_AN22 VSS_AV26 VSS_H21 VSS_V35 VCCGT45
AH33 AN23 AV28 H24 V37 P38
VSS_AH33 VSS_AN23 VSS_AV28 VSS_H24 VSS_V37 VCCGT46
AH36 AN24 AV30 H26 V39 P40 GND
VSS_AH36 VSS_AN24 VSS_AV30 VSS_H26 VSS_V39 VCCGT47
AH37 AN27 AV34 H28 P_CPU_GND_GT V8 R34
VSS_AH37 VSS_AN27 VSS_AV34 VSS_H28 VSS_V8 VCCGT48 P_CPU_GND_VCORE (6)
AH38 AN30 AV38 H30 W3 R35
VSS_AH38 VSS_AN30 VSS_AV38 VSS_H30 VSS_W3 VCCGT49
AH39 AN36 AV5 H35 W33 R36
VSS_AH39 VSS_AN36 VSS_AV5 VSS_H35 VSS_W33 VCCGT50
AH40 AN4 AV9 H37 W6 R37

1
VSS_AH40 VSS_AN4 VSS_AV9 VSS_H37 VSS_W6 VCCGT51
AH5 AN5 AW3 H39 Y35 R38 HR28
VSS_AH5 VSS_AN5 VSS_AW3 VSS_H39 VSS_Y35 VCCGT52
AH8 AN6 AW30 H4 Y37 R39 0Ohm
VSS_AH8 VSS_AN6 VSS_AW30 VSS_H4 VSS_Y37 VCCGT53
AJ1 AN7 AW32 H7 Y5 R40
VSS_AJ1 VSS_AN7 VSS_AW32 VSS_H7 VSS_Y5 VCCGT54 mbs_r0603
AJ31 AN8 AW34 H9 T33

2
VSS_AJ31 VSS_AN8 VSS_AW34 VSS_H9 VCCGT55 /X
AJ32 AN9 AW36 J10 T34
VSS_AJ32 VSS_AN9 VSS_AW36 VSS_J10 VCCGT56
AJ33 AP11 AW5 J12 A4 T36
VSS_AJ33 VSS_AP11 VSS_AW5 VSS_J12 VSS_NCTF_A4 VCCGT57
AJ34 AP14 AW9 L11 B38 T38
VSS_AJ34 VSS_AP14 VSS_AW9 VSS_L11 VSS_B38 VCCGT58
AJ35 AP24 AY27 J16 P_CPU_GND_VCORE C2 T40 GND
VSS_AJ35 VSS_AP24 VSS_AY27 VSS_J16 VSS_NCTF_C2 VCCGT59
AJ36 AP27 AY30 J18 D40 U34
VSS_AJ36 VSS_AP27 VSS_AY30 VSS_J18 VSS_NCTF_D40 VCCGT60
AJ4 AP30 AY5 J20 U35
VSS_AJ4 VSS_AP30 VSS_AY5 VSS_J20 VCCGT61
AJ5 AP36 AY7 J3 U36
VSS_AJ5 VSS_AP36 VSS_AY7 VSS_J3 SOCKET1151 VCCGT62
AJ8 AP37 AY9 J32 U37
VSS_AJ8 VSS_AP37 VSS_AY9 VSS_J32 12001V00180100 VCCGT63
AK10 AP40 B24 J34 U38
VSS_AK10 VSS_AP40 VSS_B24 VSS_J34 VCCGT64
AK12 AP5 B26 J6 GND U39
VSS_AK12 VSS_AP5 VSS_B26 VSS_J6 VCCGT65
AK13 AR1 B28 K1 U40
VSS_AK13 VSS_AR1 VSS_B28 VSS_K1 VCCGT66
AK15 AR11 B30 K14 V33
VSS_AK15 VSS_AR11 VSS_B30 VSS_K14 VCCGT67
AK16 AR14 B6 K15 V34
VSS_AK16 VSS_AR14 VSS_B6 VSS_K15 VCCGT68
AK17 AR16 C12 K17 V36
VSS_AK17 VSS_AR16 VSS_C12 VSS_K17 VCCGT69
AK18 AR17 C14 K19 V38
VSS_AK18 VSS_AR17 VSS_C14 VSS_K19 VCCGT70
AK19 AR18 C16 K22 V40
VSS_AK19 VSS_AR18 VSS_C16 VSS_K22 VCCGT71
AK20 AR19 C18 K24 W34
VSS_AK20 VSS_AR19 VSS_C18 VSS_K24 VCCGT72
AK23 AR2 C20 K26 W35
VSS_AK23 VSS_AR2 VSS_C20 VSS_K26 VCCGT73
AK25 AR20 C22 K28 W36
VSS_AK25 VSS_AR20 VSS_C22 VSS_K28 VCCGT74
AK26 AR21 C24 K30 W37
VSS_AK26 VSS_AR21 VSS_C24 VSS_K30 VCCGT75
AK28 C31 K33 W38 F39
VSS_AK28 VSS_C31 VSS_K33 VCCGT76 VCCGT_SENSE H_GT_VCC_SENSE (6)
C33 K35 Y33 F38
VSS_C33 VSS_K35 VCCGT77 VSSGT_SENSE H_GT_VSS_SENSE (6)
C35 K37 Y34
SOCKET1151 VSS_C35 VSS_K37 VCCGT78
Y36
12001V00180100 VCCGT79
Y38
SOCKET1151 VCCGT80
GND GND
12001V00180100

GND GND SOCKET1151


12001V00180100

ILM1 ILM2

Title : LGA1151 (GND)

ASUSTek Computer Inc.


Engineer: Morse_Peng
Size Project Name Rev
A3 SkyLake VC R1.00
ILM1 ILM2
13020-00760500 13020-00064200 Date: Monday, June 11, 2018 Sheet 37 of 113
SU1G
N BC17
GPP_A16/CLKOUT_48

G2 L2
(35) CK_24M_NSCCCLKP CLKOUT_CPUNSSC_P CLKOUT_ITPXDP_N C_CPU_XDP# (38)
CPU CK_24M_NSCCCLKP G1 L3 CK_100M_XDPN XDP
(35) CK_24M_NSCCCLKN CLKOUT_CPUNSSC_N CLKOUT_ITPXDP_P C_CPU_XDP (38)
CK_24M_NSCCCLKN J3 CK_100M_XDPP
CLKOUT_CPUPCIBCLK_N CK_100M_PCIBCLKN (35)
H1 J2 CK_100M_PCIBCLKN CPU
(35) CK_100M_CPUIP CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK_P CK_100M_PCIBCLKP (35)
CPU CK_100M_PCHOP H2 CK_100M_PCIBCLKP
(35) CK_100M_CPUIN CLKOUT_CPUBCLK_N
CK_100M_PCHON
+1.0V_A_XCLK_BIAS A5 P5
XTAL24_OUT CLKOUT_SRC_N0 CK_100M_X1SL2N (69)
S_24M_OUT E1 P7 CK_100M_X1SL2N
XTAL24_IN CLKOUT_SRC_P0 CK_100M_X1SL2P (69) PCIEX1_2
SR11 S_24M_IN CK_100M_X1SL2P
close to PCH 1 2 F1 M7
XCLK_BIASREF CLKOUT_SRC_N1
MAX trace lengtch 200mil 2.7KOhm S_XCLK_BIASREF M5
CLKOUT_SRC_P1 ASM 1142AE
BF7
RTCX1
S_RTCX1 BG7 H7
RTCX2 CLKOUT_SRC_N2
S_RTCX2 G7
CLKOUT_SRC_P2
I BE22
(69) PCIEX1_SL2_PRSNT# GPP_B5/SRCCLKREQ0#
/X/SPTH ST179 1 S_GPP_B5 I BA24 K7
GPP_B6/SRCCLKREQ1# CLKOUT_SRC_N3
S_GPP_B6 I BA19 K5
I BE23
GPP_B7/SRCCLKREQ2# CLKOUT_SRC_P3 Not use these 4 ports at better,
I BD22
GPP_B8/SRCCLKREQ3#
E3 they are easy to be
GPP_B9/SRCCLKREQ4# CLKOUT_SRC_N4
I BF23
GPP_B10/SRCCLKREQ5# CLKOUT_SRC_P4
E4 interfered
I AR29
(87) CLKREQ#_LAN1 GPP_H0/SRCCLKREQ6#
S_GPP_H0 I AU27 C5
(72) M.2_SSD_CLKREQ7# GPP_H1/SRCCLKREQ7# CLKOUT_SRC_N5
S_GPP_H1 I BG30 C6
GPP_H2/SRCCLKREQ8# CLKOUT_SRC_P5
I BF30
GPP_H3/SRCCLKREQ9#
/X/SPTH ST181 1 I BD29 T8
GPP_H4/SRCCLKREQ10# CLKOUT_SRC_N6 CK_100M_LAN1N (87)
S_GPP_H4 I BE31 T7 CK_100M_LAN1N
(51) PCIEX16_SL1_PRSNT# GPP_H5/SRCCLKREQ11# CLKOUT_SRC_P6 CK_100M_LAN1P (87) LAN
S_GPP_H5 I AY29 CK_100M_LAN1P
GPP_H6/SRCCLKREQ12#
I AV29 V5
GPP_H7/SRCCLKREQ13# CLKOUT_SRC_N7 CK_100M_M.2N (72)
I BD31 V7 CK_100M_M.2N
(69) PCIEX1_SL1_PRSNT# GPP_H8/SRCCLKREQ14# CLKOUT_SRC_P7 CK_100M_M.2P (72) M2_X4
S_GPP_H8 I BF31 CK_100M_M.2P
GPP_H9/SRCCLKREQ15#
Y10
CLKOUT_SRC_N8
T13 Y11
CLKOUT_SRC_N15 CLKOUT_SRC_P8
T11
CLKOUT_SRC_P15
M2
CLKOUT_SRC_N9
R3 M1
(69) CK_100M_X1SL1N CLKOUT_SRC_N14 CLKOUT_SRC_P9
CK_100M_X1SL1N R2
PCIEX1_1 (69) CK_100M_X1SL1P CLKOUT_SRC_P14
CK_100M_X1SL1P P3
CLKOUT_SRC_N10
Y7 P2
CLKOUT_SRC_N13 CLKOUT_SRC_P10
AA5
CLKOUT_SRC_P13
T2 if not used,delete the unused signal
CLKOUT_SRC_N11 CK_100M_X16SL1N (51)
U1 T3 CK_100M_X16SL1N
CLKOUT_SRC_N12 CLKOUT_SRC_P11 CK_100M_X16SL1P (51) PCIEX16_1 (X16,X8)
U2 CK_100M_X16SL1P
CLKOUT_SRC_P12

KABYLAKE_PCH
REV = <REV>
02001-00780000
to CPU 100MHz
+3V SC13 1.5PF/50V /X
CK_100M_PCHOP SC15 1 2 1.5PF/50V /X
@:各個案子不同,如果那麼多的CLK REQ
CK_100M_PCHON 1 2
function,則可以換成那個4pin的排阻:10V253820240
PCIE ref CLK to CPU 100MHz
SRP1A 5 1 SC1 1.5PF/50V /X
8.2KOHM
10 S_GPP_B5 CK_100M_PCIBCLKP SC2 1 2 1.5PF/50V /X
CK_100M_PCIBCLKN 1 2
SRP1B 5 2
8.2KOHM
10 S_GPP_H1
CLK from Crystal to CPU 24MHz
SC4 1.5PF/50V /X
SRP1C 5 3 CK_24M_NSCCCLKP SC5 1 2 1.5PF/50V /X
8.2KOHM
10 CK_24M_NSCCCLKN 1 2

SRP1D 5
8.2KOHM
4 close to PCH GND
10

SRP1E 5 6
PEG 100MHz
8.2KOHM
10 S_GPP_H5 SC17 1.5PF/50V /X
SRP1F 5 7 W/S:4/40 mils CK_100M_X16SL1N SC18 1 2 1.5PF/50V /X
8.2KOHM
10 S_GPP_H8 Routing on bottom side CK_100M_X16SL1P 1 2
SRP1G 5 8
8.2KOHM
10 S_GPP_H0
SRP1H 5 9 S_24M_IN
8.2KOHM
10 close to SLOT GND
SR801
15Ohm SR14 1MOHM
1 2 1 2 S_24M_OUT
SRC 100MHz
@:如果沒有CLK,
SX2
旁邊的電容需移除
2 1
S_24M_IN_R GND
1

3 24MHZ SC140 1.5PF/50V /X


SC8 SC9 CK_100M_X1SL1N SC139 1 2 1.5PF/50V /X
27PF/50V 27PF/50V CK_100M_X1SL1P 1 2
2

SC137 1.5PF/50V /X
CK_100M_X1SL2N SC138 1 2 1.5PF/50V /X
GND CK_100M_X1SL2P 1 2

SC111 1.5PF/50V /X
CK_100M_M.2N SC110 1 2 1.5PF/50V /X
S_RTCX1 CK_100M_M.2P 1 2
S_RTCX2
SR1607 10MOhm
SX1_1
mbs_r0603 2 1

3 SX1 close to SLOT


1 GND 2 JUMPER_WIRE GND
GND no symbol 0.5Φ 6.3*4*6.3
4 32.768KHZ
Title :
1

SC143 SC144 PCH (CLOCK)


15PF/50V 15PF/50V
Trace < 1.5 Engineer: Bing-jie_Wang
2

ASUSTek Computer Inc.


Size Project Name Rev
Custom Skylake Chipset DEMO R1.00

RTC (10 MOHM RES): DO NOT CHANGE TO 0402 PACK_TYPE Date: Monday, June 11, 2018 Sheet 54 of 113
+3VSB
This strap should sample LOW. There should NOT be any
on-board device driving it to opposite direction during
strap sampling.

8.2KOhm
SR1
2 1 N/A S_PME# +3VSB

SR180 1 /X 2 8.2KOhm
+3VSB follow CRB S_GPP_H12
SR181 1 /X 2 8.2KOhm

GND
SR200 1 2 SU1A
20KOhm /X S_SPI_MOSI SR5
SR201 2 1 N(I/OD) BF15 BD24 N(O) 1 2
GPP_A11/PME# GPP_B13/PLTRST# S_PLTRST# (87,96,108,113)
4.7KOHM /X S_PME# S_PLTRST#_R 22Ohm
BOOT HALT ENABLED IF LOW AH16
RSVD_18
PCH HAS INTERNAL WEAK PU AH14 T43 I follow CRB +3V
RSVD_19 GPP_G16/GSXCLK
AG17 AC39 I
RSVD_20 GPP_G12/GSXDOUT
GND AF17 Y36 I S_GPP_G12
RSVD_21 GPP_G13/GSXSLOAD
Y43 I SR28 /X 8.2KOhm
GPP_G14/GSXDIN
AU19 U44 I S_GPP_E3 2 1
TP2 GPP_G15/GSXSRESET#
AP17 SR15 /X 8.2KOhm
TP1
+3VSB S_GPP_B4 2 1
IPU BF27 AP41 I SR1734 /X 3.3KOHM
(67) S_SPI_MOSI SPI0_MOSI GPP_E3/CPU_GP0
S_SPI_MOSI IPU BE27 AK43 I S_GPP_E3 S_GPP_G12 2 1
(67) S_SPI_MISO SPI0_MISO GPP_E7/CPU_GP1
IPD BF28 BF21 I S_GPP_E7 SR78 /X 3.3KOHM
(67) S_SPI_CS0# SPI0_CS0# GPP_B3/CPU_GP2
IPD BE29 BF22 I S_GPP_E7 2 1
1

(67) S_SPI_CLK SPI0_CLK GPP_B4/CPU_GP3


SR1936 /X/SPTH ST224 1 IPD BA27 S_GPP_B4
SPI0_CS1#
8.2KOhm BF34 I follow Taipei Test Only +3V
GPP_H18/SML4ALERT#
IPU BF26 BF32 I S_GPP_H18
(67) S_SPI_IO2 SPI0_IO2 GPP_H17/SML4DATA
IPU BD27 BD36 I
2

(67) S_SPI_IO3 SPI0_IO3 GPP_H16/SML4CLK


AY27 BD33 I /X 8.2KOhm
SPI0_CS2# GPP_H15/SML3ALERT#
I AY39 AV31 I S_GPP_H15 H10-H18 Native function server only S_GPP_H15 SR1753 2 1
GPP_D1/SPI1_CLK GPP_H14/SML3DATA
1 2 I AV41 BE33 I S_GPP_H14 /X 8.2KOhm
(96,98) S_PLED GPP_D0/SPI1_CS# GPP_H13/SML3CLK S_M2/SATA2_SEL (71)
S_PLED SR1836 S_GPP_D0
I AV43 BF33 S_GPP_H13
I IPD S_GPP_H14 SR1758 2 1
GPP_D3/SPI1_MOSI GPP_H12/SML2ALERT#
mbs_r0402 /X 0Ohm I BB44 AU31 I S_GPP_H12 /X 8.2KOhm
GPP_D2/SPI1_MISO GPP_H11/SML2DATA
I AM42 BE32 I S_GPP_H13 SR1757 2 1
GPP_D22/SPI1_IO3 GPP_H10/SML2CLK
I AM44 BF9
GPP_D21/SPI1_IO2 INTRUDER#
S_INTRUDER#

1
+3V_BAT

KABYLAKE_PCH AT6
02001-00780000 /X SR87 1MOHM
mbs_tpc26b_s4_85 1 2
S_INTRUDER#

SC521 1.5PF/50V /X
S_INTRUDER# 1 2

GND

for DUMMY load control

+3VSB

O_+12V_DUMMYLOAD1 (25)

2
SR185 3

3
D
8.2KOhm SQ53
/X H2N7002
11 /X

1
S_GPP_H18 G
S

1
SQ53C1 2

2
2
1.5PF/50V
SR183 /X

2
8.2KOhm
/X GND
GND

1
GND

Title : SPTH (PCI/SPI)

ASUSTek Computer Inc.


Engineer: Morse_Peng
Size Project Name Rev
A3 SkyLake VC R1.02A

Date: Monday, June 11, 2018 Sheet 55 of 113


+3VSB

(19) P_+1.0A_OV1_10

2
SR1638
3 8.2KOhm

3
D
/X
SQ213

1
11 SU1C
H2N7002 G GPP_G0
S
2

2
AU2 G35
CL_CLK PCIE13_RXN/SATA0B_RXN S_SATA6_RXN1 (74)

1
N/A SR1637 SQ213C1 AU4 E35
CL_DATA PCIE13_RXP/SATA0B_RXP S_SATA6_RXP1 (74)
8.2KOhm 1.5PF/50V AW2 C36
CL_RST# PCIE13_TXN/SATA0B_TXN S_SATA6_TXN1 (74)
/X I B36
PCIE13_TXP/SATA0B_TXP S_SATA6_TXP1 (74)

2
I W44
GPP_G8/FAN_PWM_0

1
I Y44
GPP_G9/FAN_PWM_1 SATA 1&2
I AC35 E37
GPP_G10/FAN_PWM_2 PCIE14_RXN/SATA1B_RXN S_SATA6_SW_RXN2 (74)
GND GND AC41 G37
GPP_G11/FAN_PWM_3 PCIE14_RXP/SATA1B_RXP S_SATA6_SW_RXP2 (74)
I A37
PCIE14_TXN/SATA1B_TXN S_SATA6_SW_TXN2 (74)
I AA43 B37
GPP_G0/FAN_TACH_0 PCIE14_TXP/SATA1B_TXP S_SATA6_SW_TXP2 (74)
+3VSB G0-G11 native function server only GPP_G0 I AB44
GPP_G1/FAN_TACH_1 SATA 3&4
I AC36 E41
(17) P_+VDDQ_OV#_1_10 GPP_G2/FAN_TACH_2 PCIE15_RXN/SATA2_RXN S_SATA6_RXN3 (74)
GPP_G2 I T44 C42
GPP_G3/FAN_TACH_3 PCIE15_RXP/SATA2_RXP S_SATA6_RXP3 (74)
2

GPP_G3 I AC33 C38


GPP_G4/FAN_TACH_4 PCIE15_TXN/SATA2_TXN S_SATA6_TXN3 (74)
SR1746 I V43 B38
(87) L1_ISOLATE# GPP_G5/FAN_TACH_5 PCIE15_TXP/SATA2_TXP S_SATA6_TXP3 (74)
8.2KOhm I Y42
GPP_G6/FAN_TACH_6
6

AA44 D42
/X GPP_G7/FAN_TACH_7 PCIE16_RXN/SATA3_RXN S_SATA6_RXN4 (74)
SQ214A I E43
PCIE16_RXP/SATA3_RXP S_SATA6_RXP4 (74)
1

2N7002KDW 2 I AE30 B39


GPP_F10/SCLOCK PCIE16_TXN/SATA3_TXN S_SATA6_TXN4 (74)
GPP_G2 I AH35 A39
GPP_F11/SLOAD PCIE16_TXP/SATA3_TXP S_SATA6_TXP4 (74)
1

I AE43
N/A GPP_F13/SDATAOUT0
1

SR1745 SQ214AC1 AE44 J41


GPP_F12/SDATAOUT1 PCIE17_RXN/SATA4_RXN
8.2KOhm 1.5PF/50V K39
PCIE17_RXP/SATA4_RXP
N/A /X G31 E45
PCIE9_RXN/SATA0A_RXN PCIE17_TXN/SATA4_TXN
2

H31 F45
PCIE9_RXP/SATA0A_RXP PCIE17_TXP/SATA4_TXP
1

D31
PCIE9_TXN/SATA0A_TXN
C31 M39
PCIE9_TXP/SATA0A_TXP PCIE18_RXN/SATA5_RXN
GND GND M41
PCIE18_RXP/SATA5_RXP
G29 G45
PCIE10_RXN/SATA1A_RXN PCIE18_TXN/SATA5_TXN
E29 G44
PCIE10_RXP/SATA1A_RXP PCIE18_TXP/SATA5_TXP
B31 OD
PCIE10_TXN/SATA1A_TXN
A32 AJ44 IPU I
M.2 PCIE10_TXP/SATA1A_TXP GPP_E8/SATALED#
+3VSB AM36 IPU I S_SATALED#_R
GPP_E0/SATAXPCIE0/SATAGP0 M2_SSD_SATA_PE#_DET (72)
L31 AM35 IPU I
(17) P_+VDDQ_OV#_2_10 (71) S_M.2_SW_RXN1 PCIE11_RXN GPP_E1/SATAXPCIE1/SATAGP1
K31 AM38 IPU I If not 2 SATA EXPRESS,DEL these 2 signal
(71) S_M.2_SW_RXP1 PCIE11_RXP GPP_E2/SATAXPCIE2/SATAGP2
2

C32 AK36 IPU I


(71) S_M.2_SW_TXN1 PCIE11_TXN GPP_F0/SATAXPCIE3/SATAGP3
SR1747 B32 AK33 IPU I
(71) S_M.2_SW_TXP1 PCIE11_TXP GPP_F1/SATAXPCIE4/SATAGP4
8.2KOhm AK38 IPU I SATAXPCIE[7:0]
GPP_F2/SATAXPCIE5/SATAGP5
3

E33 AH43 IPU I Set 0 : PCIe


/X (72) S_M.2_RXN2 PCIE12_RXN GPP_F3/SATAXPCIE6/SATAGP6
SQ214B G33 AE42 Set 1 : SATA
(72) S_M.2_RXP2 PCIE12_RXP GPP_F4/SATAXPCIE7/SATAGP7
1

2N7002KDW 5 C33 I could change by ME


(72) S_M.2_TXN2 PCIE12_TXN
GPP_G3 B33 AE36 I
PCIE12_TXP GPP_F21/eDP_BKLTCTL
4

(72) S_M.2_TXP2
2

AE35 I
N/A GPP_F20/eDP_BKLTEN
1

SR1748 SQ214BC1 P39 AC42 SR40 follow CRB&PDG change 620ohm


PCIE19_RXN/SATA6_RXN GPP_F19/eDP_VDDEN
8.2KOhm 1.5PF/50V P41 I
PCIE19_RXP/SATA6_RXP
N/A /X H44 AH4 I/O 1 2
PCIE19_TXN/SATA6_TXN THRMTRIP#
2

H45 AK4 S_VCORE_SHDN#_4_R S_VCORE_SHDN#_4


620Ohm
PCIE19_TXP/SATA6_TXP PECI
1

P38 AH3 SR44 1 2 30Ohm


PCIE20_RXN/SATA7_RXN PM_SYNC S_PM_SYNC (35)
P36 AK3 S_PM_SYNC_R
PCIE20_RXP/SATA7_RXP PLTRST_PROC# H_CPURST# (35)
GND GND J43 AH2
PCIE20_TXN/SATA7_TXN PM_DOWN H_PM_DOWN (35)
J44
PCIE20_TXP/SATA7_TXP

VCCST_VCCSFR
KABYLAKE_PCH

2
REV = <REV>
02001-00780000

1
SC6 SR41
10PF/50V 1KOhm
SR1739 /X /X

2
1 2 8.2KOhm

1
+1.0V_A

SR1628
1 2 8.2KOhm
/X S_VCORE_SHDN#_4 GND

2 1 SD2
/X S_VCORE_SHDN#_4_R 1
(6) P_VCORE_VRSHDN_4
ESDC14 1000PF/50V 3
2 S_VCORE_SHDN#_4
(35) H_THERMTRIP#
GND
BAT54AW

Level Shift
+3V +3V
2

SRN201A SRN201D
8.2KOHM 8.2KOHM
1

SQ46C1
1.5PF/50V
/X
2
1 B

GND

HDLED- (98)
S_SATALED#_R
C
2
E

SQ46 PMBS3904

S_SATALED#_R (72)
Title SPTH
: (HOST/FAN/SATA)
1

SRD Solution for HDLED Engineer:


SC198
ASUSTek Computer Inc. Morse_Peng
0.1UF/16V Size Project Name Rev
2

/X
Custom SkyLake VC R1.00

GND Date: Monday, June 11, 2018 Sheet 57 of 113


+3VSB Strap

SR93
1 2 /X 7 8 SRN25D SU1D
22Ohm
4.7KOHM S_GPP_C5
SR94
2 1 /X 1 22Ohm 2 SR52 BB3 BD15 I
(90) S_HD_BITCLK HDA_BCLK GPP_A12/BMBUSY# /ISH_GP6/SX_EXIT_HOLDOFF#
20KOhm 1 2 SRN25A S_HD_BITCLK_R BC1 BA15 S_SX_EXIT_HOLDOFF#
N(I/OD)
(90) S_HD_RST# 22Ohm HDA_RST# GPP_A8/CLKRUN#
S_HD_RST#_R IPD BA2 S_CLKRUN#
(90) A_HD_SDIN0 HDA_SDI0
0 = LPC Is selected for EC. (Default) IPD BB1 BC11 N(O)
1 = eSPI Is selected for EC. HDA_SDI1 GPD11/LANPHYPC
GND
3 4 SRN25B IPD BC3 BA9 N(O)
(90) S_HD_SDOUT 22Ohm HDA_SDO GPD9/SLP_WLAN#
5 6 SRN25C S_HD_SDOUT_R IPD BG6
(90) S_HD_SYNC 22Ohm HDA_SYNC
Strap S_HD_SYNC_R BD10 OD
DRAM_RESET#
+3VSB SR34 BF1 BG21 I S_D4_RESET#
RSVD_2 GPP_B2/VRALERT#
1KOhm total lengtch <4,max=200;total lengtch >4,max=400 BG2 AV19 O S_VR_ALERT#
RSVD_1 GPP_B1
AY22 O
GPP_B0
1 2 S_GPP_C2 SR49 1 2 30Ohm IPD AM3 V42 I
(32) S_HDA_SDO_R DISPA_SDO GPP_G17/ADR_COMPLETE
SR35 S_HDA_SDO IPD AN2 AR17 O
(32) H_HDA_SDI DISPA_SDI GPP_B11
2 1 /X SR50 1 2 30Ohm AM2 AW3 I
(32) S_HDA_SCLK DISPA_BCLK SYS_PWROK S_SYSPWROK (65)
20KOhm S_HDA_SCLK_R
TLS Confidentiality I AU42 BE9 I/OD IPD
GPP_D8/I2S0_SCLK WAKE# S_WAKE# (51,69,72,89)
0 = Disable Intel ME Crypto Transport Layer I AV44 BE13 N(O) S_WAKE# 1 ST151 /X/SPTH
Security (TLS) cipher suite (no confidentiality). GPP_D7/I2S0_RXD GPD6/SLP_A#
GND I AU43 AV11 O S_SLP_A# 1 ST134 /X/SPTH
1 = Enable Intel ME Crypto Transport Layer GPP_D6/I2S0_TXD SLP_LAN#
Security (TLS) cipher suite (with confidentiality). I AP36 BE24 N(O) S_SLP_LAN# 1 ST113 /X/SPTH
GPP_D5/I2S0_SFRM GPP_B12/SLP_S0#
Must be pulled up to support IntelR AMT with I AM43 BA11 N(O) S_SLP_S0#
TLS and Intel SBA (Small Business Advantage) GPP_D20/DMIC_DATA0 GPD4/SLP_S3# S_SLP_S3# (18,20,23,96)
with TLS. S_GPP_D20 I AP38 BF13 N(O)
GPP_D19/DMIC_CLK0 GPD5/SLP_S4# S_SLP_S4# (17,19,96)
I AN43 BB7 N(O) 1 ST114 /X/SPTH SBA 所用test pin
(104) GP_CHAFAN_PWM_DC# GPP_D18/DMIC_DATA1 GPD10/SLP_S5#
SR58 1 N/AS_GPP_D18
2 0Ohm I AP42
(48) GP_DP2VGA_EEDID_EN GPP_D17/DMIC_CLK1
S_GPP_D17 AV13 N(O)
GPD8/SUSCLK S_SUSCLK (72)
BF11 N(I)
GPD0/BATLOW#
BD17 N IPU S_GP_D0
+3VSB GPP_A15/SUSACK# S_SUSACK# (64)
BE8 BF17 N(O) S_SUSACK#
LAN SMBUS RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK S_SUSWARN# (64)
S_RTCRST# BF8
SRTCRST#
S_SRTCRST#
I BE4 BE10 I IPD
(63,65) S_PWROK PCH_PWROK GPD2/LAN_WAKE#
SR167 499Ohm S_PWROK BG5 BD13 I L1_LAN_WAKE#
(64) S_RSMRST# RSMRST# GPD1/ACPRESENT
2 1 L1_SMBCLK S_RSMRST# BF10 O S_GP_D1 1 ST350 /X/1151
SLP_SUS#
SR166 499Ohm I BD4 BC5 I IPU SLP_SUS#
(64) S_DPWROK DSW_PWROK GPD3/PWRBTN# O_IOPWRBTN# (96)
2 1 L1_SMBDATA S_DPWROK O IPD BE41 AV3 I O_IOPWRBTN#
GPP_C2/SMBALERT# SYS_RESET# O_RSTCON# (96)
SC31 1 2 10PF/50V S_GPP_C2 N(I/OD) BE38 AU24 O IPD O_RSTCON#
H: enable top swap mode +3VSB
(63) S_SMBCLK_VSB GPP_C0/SMBCLK GPP_B14/SPKR S_SPKR (98)
/X N(I/OD) BC42 AL2 1 2
(63) S_SMBDATA_VSB GPP_C1/SMBDATA PROCPWRGD H_CPUPWRGD (35)
SC32 1 2 10PF/50V O IPD BC35 S_CPUPWRGD_R SR75 30Ohm
GPP_C5/SML0ALERT#
/X S_GPP_C5 N(I/OD) BE37 AR2
GPP_C3/SML0CLK ITP_PMODE S_ITP_PMODE (38)
L1_SMBCLK N(I/OD) BC33 AP3 S_ITP_PMODE follow CRB
GPP_C4/SML0DATA JTAGX S_JTAGX (38)
L1_SMBDATA O IPD BA22 AP4 S_JTAGX
GPP_B23/SML1ALERT#/PCHHOT# JTAG_TMS S_JTAG_TMS (38)
GND S_GPP_B23 I BC43 AN3 S_JTAG_TMS
GPP_C6/SML1CLK JTAG_TDO S_JTAG_TDO (38)
S_GPP_C6 I BF38 AP2 S_JTAG_TDO SRN28C
S_SX_EXIT_HOLDOFF# 6 8.2KOHM 5
GPP_C7/SML1DATA JTAG_TDI S_JTAG_TDI (38)
S_GPP_C7 AN1 S_JTAG_TDI follow CRB
JTAG_TCK S_JTAG_TCK (38)
S_JTAG_TCK
+3VSB
S_VR_ALERT# SRN28D 8 8.2KOHM 7
KABYLAKE_PCH
GPI PU REV = <REV>
02001-00780000
SR60

3 8.2KOHM 4 SRN211B S_WAKE# 2 1

5 8.2KOHM
1KOhm
6 SRN211C S_GPP_C6 VDDQ +3V

7 8.2KOHM 8 SRN211D S_GPP_C7 SR36 /X

2
+3VSB SR57 S_SYSPWROK 2 1KOhm 1
470Ohm
Strap (12) P_+VCCSA_OV#_1_10
1 8.2KOHM

2
+3VSB CRB mount SR56 S_CLKRUN# 2 SRN210A

1
SR1735 SR1749 1 2 /X SR1641 2 8.2KOhm 1 /X
0402 S_D4_RESET#_R (39,40)
3 8.2KOhm
3

1 2 /X S_D4_RESET#
D
4.7KOHM S_GPP_B23
/X
SR1736 SQ216

1
2 1 /X 11 GND
H2N7002

1
20KOhm G S_GPP_D20 SC14
S
2
2
1.5PF/50V
2

1
DCI ENABLE STRAP ENABLED IF SAMPLED HIGH N/A SR1750 SQ216C1 /X +3VSB_ADV

2
PCH HAS INTERNAL WEAK PD 1.5PF/50V
GND 8.2KOhm
N/A /X

2
+3VSB_ATX
1

GND GND GND


2

SR163 ME disable S_GP_D0


SRN28A
2 8.2KOHM 1
2KOHM SRN28B
/SPTH +3VSB S_GP_D1 4 8.2KOHM 3
BATTERY
1

for EMI close to PCH SR701 SR118 BATT_HOLDER


ESDC15 10PF/50V /X 1 2 1KOhm SR122

1
SR1829 1 2 N/A
S_HD_BITCLK 1 2 47KOhm +BAT_R 2 1 +BAT 1 2
BATTERY2 L1_LAN_WAKE# 4.7KOHM
1KOhm
ESDC13 10PF/50V /X mbs_r0603 Battery /X
Socket GND

2
1

KTS
S_SUSACK# 1 2 GND SR1623
/SPTH
LITHIUM BATT

ESDC6 10PF/50V /X SD1 +3V_BAT_RTC CR2032


3V/220mAh 1 2 /X
(62) ME_UNLOCK 0402
Clear RTC S_HD_SDOUT_R
S_SYSPWROK 1 2 +3V_BAT BAT54CW SR120 PLACE ALL ABOVE CLOSE TO PCH
ESDC7 10PF/50V /X SR119 1KOhm
3

1 2
S_PWROK 1 2 2 1 S_RTCRST#
1
1

ESDC8 10PF/50V /X 18.7KOhm SC59


1UF/6.3V
1

1 2 AT4
O_IOPWRBTN# CLRTC N/A
2

ESDC9 10PF/50V /X SD3 1 /X audio side IO power must be +3VSB


2 mbs_tpc26b_s4_85
O_RSTCON# 1 2 /X BAT54CW
ESDC10 10PF/50V /X +3V_BAT HEADER_1X2P
3

SR121 12006-00161200 GND SPTH (AUDIO/SMBUS/MISC)


S_RSMRST# 1 2 1 2 Title :
ESDC12 10PF/50V /X S_SRTCRST#
1
1

20KOhm SC60
ASUSTek Computer Inc.
Engineer: Morse_Peng
S_DPWROK 1 2 1UF/6.3V
AT5
PDG:RC time delay between 18ms~25ms must be met! N/A Size Project Name Rev
2

/X
A3 SkyLake VC R1.00
GND mbs_tpc26b_s4_85
GND Date: Monday, June 11, 2018 Sheet 58 of 113
SU1E

AW5
GPP_I5/DDPB_CTRLCLK S_DP_DDC_CLK (44)
AV7 O IPD S_DP_DDC_CLK
GPP_I6/DDPB_CTRLDATA S_DP_DDC_DATA (44)
AP7 AT5 S_DP_DDC_DATA
(44) S_DP_HPD GPP_I0/DDPB_HPD0 GPP_I7/DDPC_CTRLCLK S_HDMI_DDC_CLK (45)
AT8 BA6 O IPD S_HDMI_DDC_CLK
(45) S_HDMI_HPD GPP_I1/DDPC_HPD1 GPP_I8/DDPC_CTRLDATA S_HDMI_DDC_DATA (45)
AP8 AY1 S_HDMI_DDC_DATA
(47) S_DVI_HPD GPP_I2/DDPD_HPD2 GPP_I9/DDPD_CTRLCLK S_DVI_DDC_CLK (47)
AT7 AY2 O IPD S_DVI_DDC_CLK +3VSB
(48) S_DP2VGA_HPD GPP_I3/DDPE_HPD3 GPP_I10/DDPD_CTRLDATA S_DVI_DDC_DATA (47)
S_DVI_DDC_DATA
Check if it need to be used
AD44
GPP_F14
+3V SR1828 AE39
GPP_F23 8.2KOHM
BA1 AB45 S_GPP_H23 8 7
SRN214D
GPP_I4/EDP_HPD GPP_F22
eDP_HPD 1 2 S_GPP_I4
SRN204D 100KOhm R44
2.7KOHM GPP_G23
8 7 S_HDMI_DDC_CLK /NO-VGA R45 +3V
GPP_G22
SRN204C AC30
2.7KOHM GPP_G21
6 5 S_HDMI_DDC_DATA GND Y35 I
GPP_G20
if not use BG34
eDP ,need GPP_H23 8.2KOHM
SRN204B S_GPP_H23 S_SERIRQ 5 6 SRN210C
2.7KOHM mount
4 3 S_DVI_DDC_CLK
SRN204A
2.7KOHM 8.2KOHM
2 1 S_DVI_DDC_DATA O_KBRST# 7 8 SRN210D
KABYLAKE_PCH
REV = <REV> 8.2KOhm
2.7KOHM SR703 02001-00780000
/DP++ 1 2
mbs_r0402_ns S_DP_DDC_CLK S_GPP_G18 SR175 2 1 /X
2.7KOHM SR704 8.2KOhm
/DP++ 1 2
mbs_r0402_ns S_DP_DDC_DATA
S_GPP_G19 SR146 2 1 /X
8.2KOhm
S_DVI_HPD S_HDMI_HPD S_DP_HPD S_DP2VGA_HPD 1 2
SR243 /X
+3VSB

GND
follow CRB
1

1
SC133 SC134 SC135 SC136
1.5PF/50V 1.5PF/50V 1.5PF/50V 1.5PF/50V

3
/X /X /X /X
2

2
8.2KOHM
SRN210B

GND GND GND GND

4
SC141
S_LAD[3..0] (96,108)
SU1F
B7 AR15 IPU O_KBRST# 1 2
(79) S_U3RXDN1_R USB3_1_RXN GPP_A1/LAD0/ESPI_IO0
A7 AY15 IPU S_LAD0
(79) S_U3RXDP1_R USB3_1_RXP GPP_A2/LAD1/ESPI_IO1 1.5PF/50V
SC154 2 1 0.1UF/16V D13 AV17 IPU S_LAD1
(79) S_U3TXDN1_R USB3_1_TXN GPP_A3/LAD2/ESPI_IO2
X7R SC155 2 1 0.1UF/16V S_U3TXDN1_C C13 BE14 IPU S_LAD2 /X
(79) S_U3TXDP1_R USB3_1_TXP GPP_A4/LAD3/ESPI_IO3
N/A void X7R N/A S_U3TXDP1_C C8 S_LAD3 GND
(79) S_U3RXDN2_R USB3_2_SSIC_1_RXN
void B8
(79) S_U3RXDP2_R USB3_2_SSIC_1_RXP
SC157 2 1 0.1UF/16V B13 BF14
(79) S_U3TXDN2_R USB3_2_SSIC_1_TXN GPP_A5/LFRAME#/ESPI_CS0# S_LFRAME# (96,108)
X7R SC156 2 1 0.1UF/16V S_U3TXDN2_C A14 BC13
(79) S_U3TXDP2_R USB3_2_SSIC_1_TXP GPP_A6/SERIRQ/ESPI_CS1# S_SERIRQ (96,108)
N/A void X7R N/A S_U3TXDP2_C AY13
GPP_A7/PIRQA#/ESPI_ALERT0#
void B9 AU15 S_GPP_A7 +3V
(79) S_U3RXDN3_R USB3_3_SSIC_2_RXN GPP_A0/RCIN#/ESPI_ALERT1# O_KBRST# (96)
A9 BF16 2 0Ohm 1
(79) S_U3RXDP3_R USB3_3_SSIC_2_RXP GPP_A14/SUS_STAT#/ESPI_RESET# S_ESPI_RST# (96)
SC159 2 1 0.1UF/16V B14 S_PWRDWN# SR1885 /eSPI
(79) S_U3TXDN3_R USB3_3_SSIC_2_TXN
X7R SC158 2 1 0.1UF/16V S_U3TXDN3_C C14 BE15
(79) S_U3TXDP3_R USB3_3_SSIC_2_TXP GPP_A9/CLKOUT_LPC0/ESPI_CLK
void
X7R S_U3TXDP3_C AY17 CK_24M_SIO_R 8.2KOhm
GPP_A10/CLKOUT_LPC1
void E11 CK_24M_TPM_R SR192 /X
(79) S_U3RXDN4_R USB3_4_RXN CRB PU +3V for SMI#
G11 R43 S_GPP_E4 2 1
(79) S_U3RXDP4_R USB3_4_RXP GPP_G19/SMI#
SC161 2 1 0.1UF/16V B15 U45 S_GPP_G19
(79) S_U3TXDN4_R USB3_4_TXN GPP_G18/NMI#
X7R SC160 2 1 0.1UF/16V S_U3TXDN4_C C15 S_GPP_G18
(79) S_U3TXDP4_R void
USB3_4_TXP
X7R S_U3TXDP4_C
void E13 AK44 PU on SIO side(+3VSB)
USB3_5_RXN GPP_E6/DEVSLP2
G13 AL45
USB3_5_RXP GPP_E5/DEVSLP1
A16 AL44
USB3_5_TXN GPP_E4/DEVSLP0 M2/SE1_DEVSLP (72)
B16 AF45 S_GPP_E4
USB3_5_TXP GPP_F9/DEVSLP7
AH36 Check spec to determine whether to use these signal
GPP_F8/DEVSLP6
H15 AH39
USB3_6_RXN GPP_F7/DEVSLP5
K15 AG41
USB3_6_RXP GPP_F6/DEVSLP4
C17 AF44
USB3_6_TXN GPP_F5/DEVSLP3
D17
USB3_6_TXP

KABYLAKE_PCH
REV = <REV>
02001-00780000

1 22Ohm 2 SR3
CK_24M_SIO (96)
CK_24M_SIO_R

@:TPM 不上件,則SR125 也不用上件

1 22Ohm 2 SR125
CK_24M_TPM (108)
CK_24M_TPM_R /TPM
If not TPM,delete this Title : SPTH (DISPLAY/USB3)
close to PCH

ASUSTek Computer Inc.


Engineer: Morse_Peng
Size Project Name Rev
A3 SkyLake VC R1.00

Date: Monday, June 11, 2018 Sheet 59 of 113


+3VSB +1.0V_A +1.0V_A_VCCAMPHYPLL
+1.0V_A SR155
+3VSB_ADV
SU1H 2 1
AE16 0603
+3VSB /X SC78
VCCPRIM_1P0_1 SR72

1
AD17 BC24 s_short_r0603_nomask SC76 SC77 1UF/16V
VCCPRIM_1P0_2 VCCPDSW_3P3

2
AM22 BC31 1 2 10UF/6.3V 0.1UF/16V mbs_c0603
VCCPRIM_1P0_3 VCCPGPPA 0603
AA23 VCCPGPPA +3VSB SR70 mbs_c0603 /X /X
VCCPRIM_1P0_4

2
0603
1
AA25 BE40 SC205 /X s_short_r0603_nomask /X /X
VCCPRIM_1P0_5 VCCPGPPBCH_1
AB23 BF42 0.1UF/16V s_short_r0603_nomask **CRB 0805 47UF&0402 1UF**
VCCPRIM_1P0_6 VCCPGPPBCH_2
AB26 AK41 /X Place close to PCH Pin A43, B43,C44,C45
VCCPRIM_1P0_7 VCCPGPPEF_1

1
AB28 AM41 GND
VCCPRIM_1P0_8 VCCPGPPEF_2
+1V0_PCH_VCCDSW AD23 AE41
VCCPRIM_1P0_9 VCCPGPPG
AD26 +1.0V_A GND
VCCPRIM_1P0_10

1
BC29 AK21 SC187 SC85 SC184
DCPDSW_1P0 VCCPRIM_1p0_15
+1.0V_A AF23 0.1UF/16V 0.1UF/16V 0.1UF/16V +1.0V_A +1.0V_A_VCCAPLL
VCCPRIM_1P0_12
N17 AD28 /X /X /X SR154
VCCCLK1 VCCPRIM_1P0_11

2
T19 VCCATS +3VSB +3V_BAT /X
VCCCLK3
+1.0V_A_XCLK_BIAS V20 2 1
VCCCLK4 0603
T17 GND SC75
VCCCLK2_1

1
W17 AE13 GND s_short_r0603_nomask SC74 1UF/16V
VCCCLK2_2 VCCATS
K1 BC20 0.1UF/16V mbs_c0603
VCCCLK5_1 VCCRTCPRIM_3P3
K2 BC22 /X /X
VCCCLK5_2 VCCRTC

2
+1.0V_A BC27
DCPRTC
V21 VCC_RTCEXT_CAP X7R BOARD CAP SC3 FOR VCCRTCEXT **CRB 0805 47UF**
VCCMPHY_1P0_1
V23 SC3 Place close to PCH Pin AK5, AM5, AR19

2
VCCMPHY_1P0_2
V25 0.1UF/16V GND
VCCMPHY_1P0_3
V26

1
VCCMPHY_1P0_4
V28 PLACE 3-5MM FROM PACKAGE EDGE
VCCMPHY_1P0_5 PIN BA26
+1.0V_A_VCCAMPHYPLL V29 +1.0V_A +1.0V_A_XCLK_BIAS
VCCMPHY_1P0
B43 +3VSB GND SR153
VCCAMPHYPLL_1P0_1
+1.0V_A A43 BG41 +3VSB +3VSB
VCCAMPHYPLL_1P0_2 VCCSPI_1
W28 BG42 2 1
VCCAPLLEBB_1P0 VCCSPI_2 0603
+1.0V_A_VCCAPLL AK25 BG43 VCCPGPPD
VCCPRIM_1P0_17 VCCSPI_3

1
AK5 BE44 /X SC182 SC68
VCCUSB2PLL_1P0_1 VCCPGPPD_1
AM5 BD45 s_short_r0603_nomask 10UF/6.3V 0.1UF/16V
VCCUSB2PLL_1P0_2 VCCPGPPD_2
AR19 BE45 +1.0V_A_VCCAMPHYPLL mbs_c0603 N/A
VCCHDAPLL_1P0 VCCPGPPD_3

2
2

2
+1.0V_A /X
C44 SR71 SR1732
VCCPCIE3PLL_1P0_1

0603

0603
AK23 C45 /X /X **CRB 0805 47UF&0402 1UF**
VCCPRIM_1P0_16 VCCPCIE3PLL_1P0_2
AF26 s_short_r0603_nomask s_short_r0603_nomask Place close to PCH Pin K1, K2 GND
VCCPRIM_1P0_13
AK20
VCCPRIM_1P0_14

1
+3VSB_ADV
+3VSB_HDA BF3
VCCPRIM_3P3_1
BG4 VCCPFUSE_3P3 +1.0V_A +1.0V_A
VCCPRIM_3P3_2
BC15 BG3
VCCHDA VCCPRIM_3P3_3
Y16 AP5
VCCDSW_3P3 VCCPRIM_3P3_4
VCCPHVC_3P3 SC79

1
SC71 1UF/16V SC80
KABYLAKE_PCH

1
REV = <REV> SC87 SC190 SC181 SC69 SC70 0.1UF/16V SC72 SC73 SC179 SC180 10UF/6.3V
02001-00780000 0.1UF/16V 0.1UF/16V nF_nV_ntype_n% nF_nV_ntype_n% nF_nV_ntype_n% N/A nF_nV_ntype_n% nF_nV_ntype_n% nF_nV_ntype_n% nF_nV_ntype_n% mbs_c0603 mbs_c0603

2
+3VSB +3VSB_HDA +3VSB VCCPGPPD /X /X mbs_c0402_nomask /X /X

2
Place close to PCH pin AK21 mbs_c0402_nomask
mbs_c0402_nomask mbs_c0402_nomask
mbs_c0402_nomask
mbs_c0402_nomask mbs_c0402_nomask
SR67 SR7 /X /X /X /X /X /X
/X Place close to PCH pin V21
0603 0603 GND GND Place close to PCH pin AE16,N17,W28,AK23,V29
2 1 2 1
GND GND
/X /X
+3VSB
s_short_r0603_nomask s_short_r0603_nomask

SC88

1
SC84 SC86 1UF/16V SC185
0.1UF/16V 0.1UF/16V 0.1UF/16V
/X /X mbs_c0603 /X

2
/X
close to PCH pin BE40,BF42 Place close to PCH pin BC20

GND
GROUP D POWER
LPT-H : 3.3V (FOR INTERPOSER) CRB
+3V SPT-H : 1.8V
VCCATS
SR1731 注意PCH GPIO D Group power plane
+3VSB +3V_BAT VCCPGPPD +3VSB_HDA
2
0603
1
PCH-H SPEC : GPP A~G 1.8V or 3.3V
/X
s_short_r0603_nomask
PCH-H SPEC : GPP I only 3.3V

1
SC183 X5R
Deep Sleep Well Group (GPD) only 3.3V

1
0.1UF/16V SC191 SC81 SC177 SC178 SC66
/X 0.1UF/16V 1UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V

2
1

X5R SC89 X5R SC211 close to PCH pin BG42 /X /X /X /X /X

2
1UF/6.3V 1UF/6.3V
/X /X Place close to PCH pin BC22 Place close to PCH Pin BC15
2

Place close to PCH pin AE13

GND GND GND GND

GND +1.0V_A +1V0_PCH_VCCDSW +3VSB_ADV


SR331

1 2

0Ohm X5R X5R X5R

1
mbs_r0603 SC82 SC907 /X SC189
/X 1UF/6.3V 1UF/6.3V SC83 0.1UF/16V
N/A /X nF_nV_ntype_n% /X

2
Place close to PCH Pin BC29 mbs_c0402_nomask
Place close to PCH Pin Y16 Place close to PCH Pin BC24

GND GND

Title : SPTH (POWER)

ASUSTek Computer Inc.


Engineer: Morse_Peng
Size Project Name Rev
A3 SkyLake VC R1.00

Date: Monday, June 11, 2018 Sheet 60 of 113


SU1B
L27
(31) H_DMI_TXN0 DMI_RXN0
N27 AH5 IPD
(31) H_DMI_TXP0 DMI_RXP0 USB2N_1 S_U2DN1_R (79)
D27 AH7 IPD
(31) H_DMI_RXN0 DMI_TXN0 USB2P_1 S_U2DP1_R (79)
C27 AE5 IPD
(31) H_DMI_RXP0 DMI_TXP0 USB2N_2 S_U2DN2_R (79)
E24 AE7 IPD
(31) H_DMI_TXN1 DMI_RXN1 USB2P_2 S_U2DP2_R (79)
G24 AH8 IPD
(31) H_DMI_TXP1
B27
DMI_RXP1 USB2N_3
AH10 IPD
S_U2DN3_R (79) U3.0
(31) H_DMI_RXN1 DMI_TXN1 USB2P_3 S_U2DP3_R (79)
A28 AE2 IPD
(31) H_DMI_RXP1 DMI_TXP1 USB2N_4 S_U2DN4_R (79)
G27 AE3 IPD
(31) H_DMI_TXN2 DMI_RXN2 USB2P_4 S_U2DP4_R (79)
E26 AC2 IPD
(31) H_DMI_TXP2 DMI_RXP2 USB2N_5 S_USB_PN5_R (81)
B28 AC3 IPD
(31) H_DMI_RXN2 DMI_TXN2 USB2P_5 S_USB_PP5_R (81)
C28 AF2 IPD
(31) H_DMI_RXP2 DMI_TXP2 USB2N_6 S_USB_PN6_R (81)
L29 AF1 IPD
(31) H_DMI_TXN3 DMI_RXN3 USB2P_6 S_USB_PP6_R (81)
K29 AB2 IPD If not used as USB3.0,
(31) H_DMI_TXP3 DMI_RXP3 USB2N_7 S_USB_PN7_R (81) net name could be changed
C29 AB1 IPD
(31) H_DMI_RXN3 DMI_TXN3 USB2P_7 S_USB_PP7_R (81)
B29 AM8 IPD
(31) H_DMI_RXP3 DMI_TXP3 USB2N_8 S_USB_PN8_R (81)
AM7 IPD
USB2P_8 S_USB_PP8_R (81)
Trace Width:12-15 mils, Other:12 mils B10 Y3 IPD
PCIE_RCOMPN USB2N_9 S_USB_PN9_R (83)
SR18 1 100Ohm 2 S_PCIE_RCOMPN C10 Y2 IPD
PCIE_RCOMPP USB2P_9 S_USB_PP9_R (83)
S_PCIE_RCOMPP AK8 IPD
USB2N_10 S_USB_PN10_R (83)
AK7 IPD
USB2P_10 S_USB_PP10_R (83)
G15 W2 IPD
PCIE1_RXN/USB3_7_RXN USB2N_11
E15 W1 IPD
PCIE1_RXP/USB3_7_RXP USB2P_11
A18 AD3 IPD
PCIE1_TXN/USB3_7_TXN USB2N_12
B18 AD2 IPD
PCIE1_TXP/USB3_7_TXP USB2P_12
E17 V3 IPD
PCIE2_RXN/USB3_8_RXN USB2N_13
G17 V2 IPD
PCIE2_RXP/USB3_8_RXP USB2P_13
B19 AK11 IPD +3VSB
PCIE2_TXN/USB3_8_TXN USB2N_14
C19 AK13 IPD
PCIE2_TXP/USB3_8_TXP USB2P_14
L17
PCIE3_RXN/USB3_9_RXN
K17

1
PCIE3_RXP/USB3_9_RXP
B20 SR152
PCIE3_TXN/USB3_9_TXN
C20 AJ43 I IPD 8.2KOhm
PCIE3_TXP/USB3_9_TXP GPP_E9/USB2_OC0# S_USB3_OC#12 (78)
E19 AH44 I IPD
PCIE4_RXN/USB3_10_RXN GPP_E10/USB2_OC1# S_USB3_OC#34 (78)
G19 AM39 I IPD

2
PCIE4_RXP/USB3_10_RXP GPP_E11/USB2_OC2# S_USB_OC#56 (80)
B21 AK42 I IPD
PCIE4_TXN/USB3_10_TXN GPP_E12/USB2_OC3# S_USB_OC#78 (80)
A21 AD43 I If not used ,pu to +3VSB
PCIE4_TXP/USB3_10_TXP GPP_F15/USB2_OCB_4 S_USB_OC#910 (82)
K19 AC44 I
(69) S_X1_SL1_RXN PCIE5_RXN GPP_F16/USB2_OCB_5
L19 AH42 I S_USB2_OCB_567
(69) S_X1_SL1_RXP PCIE5_RXP GPP_F17/USB2_OCB_6
D22 AC43 S_USB2_OCB_567
(69) S_X1_SL1_TXN PCIE5_TXN GPP_F18/USB2_OCB_7
C22 S_USB2_OCB_567
(69) S_X1_SL1_TXP PCIE5_TXP Place Within 1000mil
G22
(69) S_X1_SL2_RXN PCIE6_RXN
E22 AG3 I SR22 1 2 113Ohm
(69) S_X1_SL2_RXP PCIE6_RXP USB2_COMP
B22 AE10 I S_USB2_COMP
(69) S_X1_SL2_TXN PCIE6_TXN USB2_VBUSSENSE
A23 AC13 1 ST47 2 /X/SPTH 1 SR9
(69) S_X1_SL2_TXP PCIE6_TXP RSVD_3
L22 AG2 IPU I GND
PCIE7_RXN USB2_ID 1KOhm
K22 2 1
PCIE7_RXP
C23 SR10
PCIE7_TXN 1KOhm
B23
PCIE7_TXP
K24 BG11 1 ST48 /X/SPTH GND
(87) S_X1_LAN1_RXN PCIE8_RXN GPD7/RSVD
L24 S_GP_D7
(87) S_X1_LAN1_RXP PCIE8_RXP
C24
(87) S_X1_LAN1_TXN PCIE8_TXN
B24
(87) S_X1_LAN1_TXP PCIE8_TXP

KABYLAKE_PCH 02001-00780000
REV = <REV>
SU1M
T39
PCIE_21_RXN
T41
PCIE_21_RXP
K43
@:Intel 200 系列 chipset LAN port优先 PCIE_21_TXN
K44
用PCIE Port 4/8/12/16/20,如spec PCIE_21_TXP
V35
限制無法用Port PCIE_22_RXN
V36
4/8/12/16/20,可選用其它Port,但是禁止接PCIE PCIE_22_RXP
L43
PCIE_22_TXN
Lane 1/5/9/13/17; L44
PCIE_22_TXP
V39
X16_3
PCIE_23_RXN
V41
@:PCIE port PCIE_23_RXP
N44
的選擇,需要根據chipset 和PES PCIE_23_TXN
N45
自己選擇搭配 PCIE_23_TXP
Y39
PCIE_24_RXN
PCIE_24_RXP
Y41 Title : SPTH (PCIE/DMI/USB)
P43
PCIE_24_TXN
PCIE_24_TXP
P44
ASUSTek Computer Inc.
Engineer: Morse_Peng
Size Project Name Rev
KABYLAKE_PCH
A4 SkyLake VC R1.00
REV = <REV>
02001-00780000
Date: Monday, June 11, 2018 Sheet 56 of 113
S_SATA6_RXP2 (57,71,74)
(57,71,74) S_SATA6_SW_RXP2 S_SATA6_RXN2 (57,71,74) SATA6G_2 (57,71,74) S_SATA6_SW_TXP2 S_SATA6_TXP2 (57,71,74) SATA6G_2
(57,71,74) S_SATA6_SW_RXN2 (57,71,74) S_SATA6_SW_TXN2 S_SATA6_TXN2 (57,71,74)

QSWU1B
PCH SATA2 33
PCH SATA2 QSWU1C 5
A_outa+
32 SW_SATA6_M.2_TXP2
28
H310M-K V2的案子注意: 6
A_in+ A_outa-
SW_SATA6_M.2_TXN2
H310M-K V2的案子注意:
10
A_outa+
27 SW_SATA6_M.2_RXP2 SATA NET與Switch斷開。 A_in-
7 SATA NET與Switch斷開。
H310M-K V2的案子注意: 11
A_in+ A_outa-
SW_SATA6_M.2_RXN2 非H310M-K V2的案子注意: A_outb+
8 非H310M-K V2的案子注意:
SATA NET與Switch斷開。 A_in-
12 把SATA NET連到Switch上。
A_outb-
把SATA NET連到Switch上。
非H310M-K V2的案子注意: A_outb+
13
H310M-K V2的案子注意: ASM1480
把SATA NET連到Switch上。
A_outb-
SATA NET與Switch斷開。
s_qfn_42p_20_354x138_pad_ns
ASM1480 非H310M-K V2的案子注意:
/M.2
s_qfn_42p_20_354x138_pad_ns 把SATA NET連到Switch上。
/M.2

QSWU1A
QSWU1D 37
A_outa+
24 1 36 SW_SATA6_M.2_TXN2
A_outa+ (72) S_M.2_TXN1 A_in+ A_outa-
14 23 SW_SATA6_M.2_RXN2 2 SW_SATA6_M.2_TXP2
(72) S_M.2_RXN1 A_in+ A_outa- (72) S_M.2_TXP1 A_in-
15 SW_SATA6_M.2_RXP2 3
(72) S_M.2_RXP1 A_in-
16
A_outb+
4
S_M.2_SW_TXN1 (57) PCH PCIE11
A_outb+
17
S_M.2_SW_RXN1 (57) PCH PCIE11 A_outb- S_M.2_SW_TXP1 (57)
A_outb- S_M.2_SW_RXP1 (57) M.2 LANE1 ASM1480
M.2 LANE1 ASM1480 s_qfn_42p_20_354x138_pad_ns
s_qfn_42p_20_354x138_pad_ns /M.2
/M.2

QSWU1E
30 18

LES
3.3V for 1440 new version X_QSW_SEL 20
1.8V for 1440 old version 9 22
+V_QSW 19 25
+V_QSW 21 29

DNG
26 35

CCV
+3V +V_QSW 31 40
34 42
39 38
QSWR8 41 43
1

1
1 2
0603 QSWC1 QSWC2 QSWC3 QSWC4 ASM1480
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V s_qfn_42p_20_354x138_pad_ns
2

2
1

/X mbs_c0402_ns mbs_c0402_ns mbs_c0402_ns mbs_c0402_ns GND


/M.2
QSWC20
10UF/6.3V /M.2 /X/M.2 /M.2 /X/M.2
2

/M.2 GND GND GND GND


mbs_c0603_ns
X_QSW_SEL Function

GND
L N_in to N_outa M.2 SATA Mode

H N_in to N_outb M.2 PCIE Mode


M.2 MODE SEL

0 M.2 SATA Mode


1 M.2 PCIE Mode
+3V
M.2 MODE SEL GPIO select:
1. could be GPI & GPO both, default GPI
2. stand by power plane, 3V tolerance
3. GPO HIGH to switch PCIE Mode
4. GPI to switch SATA mode

2
QSWR2
8.2KOhm
QSWQ5
/M.2
H2N7002 (57,71,74) S_SATA6_SW_TXP2 S_SATA6_TXP2 (57,71,74)
mbs_r0402_ns
(57,71,74) S_SATA6_SW_TXN2 S_SATA6_TXN2 (57,71,74)

1
2 3

D
(72) M2_CONFIG1/PE_SATA#_SEL (57,71,74) S_SATA6_SW_RXP2 S_SATA6_RXP2 (57,71,74)
2

3
X_QSW_SEL
(57,71,74) S_SATA6_SW_RXN2 S_SATA6_RXN2 (57,71,74)
G
1
+3V 1 /M.2
mbs_sot23_ns
2

+3VSB QSWR30
8.2KOhm
非H310M-K V2的案子注意:
/M.2 switch蓋漆處理,此方框要留;
mbs_r0402_ns 若switch上件,刪除此方框
1
2

QSWR3
8.2KOhm
/X
mbs_r0402_ns 3
3

D
1

QSWQ13
11
(55) S_M2/SATA2_SEL H2N7002 QSWQ5C1
1

G
S
2 10PF/50V
2

/M.2 /X
2
2

QSWQ13C1 mbs_sot23_ns mbs_c0402_ns


QSWR5 10PF/50V
8.2KOhm /X
2

/M.2 mbs_c0402_ns GND


mbs_r0402_ns GND
1

<Variant Name>
GND
Title :
ASUSTek Computer Inc.
Engineer:
GND
Size Project Name Rev

Date: Sheet 71 of 113


+3V_M2
+3V

XJP3 SHORTPIN_1206_NM /X
1 2

XJP4 SHORTPIN_1206_NM /X
1 2 +3V

2
XR54
8.2KOhm
/M.2
M.2(SOCKET3)
1

1
mbs_r0402_ns

1
XC10 XC11 XC12 XC13 XC14 XC15 XC16
10UF/6.3V 10UF/6.3V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V M2_CONFIG3/PRESENT#
M2_CONFIG3/PRESENT# (62) H310M-K V2的案子注意:刪除M.2 hold
非H310M-K V2的案子注意:
2

2
/X/M.2 /X/M.2 /M.2 /X/M.2 /M.2 /X/M.2 /X/M.2

S
D
M2_M_HOLD_42,M2_HOLD_60,M2_HOLD_80上M.2 ANCHOR: (57) S_SATALED#_R
3 2 M2_LED-

2
mbs_c0603_ns mbs_c0603_ns mbs_c0402_ns mbs_c0402_ns mbs_c0402_ns mbs_c0402_ns mbs_c0402_ns
s11387 s_hole_c146d146n_spe

G
M2_LED- XQ4
H310M-K V2的案子注意:XC2~XC5改蓋漆symbol

11
H2N7002
mbs_c0402_ns /M.2
非H310M-K V2的案子注意:XC2~XC5改不蓋漆symbol mbs_sot23_ns
GND mbs_c0402_iv
M2_CONFIG1/PE_SATA#_SEL
Selection 2 For Hole Only

1
XQ4C1
X5R 1.5PF/50V
/X
S_M.2_RXN2 (57)

2
mbs_c0402_ns
S_M.2_RXP2 (57)
mbs_c0402_ns
XC5 X5R 2 1 0.22UF/10V
S_M.2_TXN2 (57)
XR43 1 2 /X PE_M2_TXN2_C XC4 2 1 0.22UF/10V GND
(59) M2/SE1_DEVSLP 0402 void S_M.2_TXP2 (57)
M2_DEVSLP_R PE_M2_TXP2_C X5R
void mbs_c0402_ns
S_M.2_RXP1 (71)
S_M.2_RXN1 (71)
mbs_c0402_ns
/X XC3 X5R 2 1 0.22UF/10V +3V
S_M.2_TXN1 (71)
XR22 1 2 PE_M2_TXN1_C XC2 2 1 0.22UF/10V
(69,96) O_X1_RST# 0402 S_M.2_TXP1 (71)
XR44 1 2 M2_PE_RST#
/X PE_M2_TXP1_C void X5R +3V
(54) M.2_SSD_CLKREQ7# 0402

2
void mbs_c0402_ns
(51,58,69,89) S_WAKE# CK_100M_M.2N (54)
XR23
CK_100M_M.2P (54)
8.2KOhm
/X/M.2

2
mbs_r0402_ns

1
Require No Stub M.2_SSD_PEDET XR3 XR52
M2_DEVSLP_R 8.2KOhm 8.2KOhm

2
XR46 1 2 /M.2 /M.2
(58) S_SUSCLK
M2_M_SUSCLK
0 M.2 SATA Mode XR24 mbs_r0402_ns mbs_r0402_ns
M2_CONFIG1/PE_SATA#_SEL (71)

1
/X/M.2 33Ohm M2_CONFIG1/PE_SATA#_SEL 8.2KOhm
1 M.2 PCIe Mode
if only one M.2,change XR46 to 33ohm
mbs_r0402_ns /X/M.2
mbs_r0402_ns

1
MINI_PCI_75P GND
M2_CONFIG1/PE_SATA#_SEL
GND M2_CONFIG3/PRESENT#
XR1003 /X
12003-00072700
1 2
/M.2 0402 M2_SSD_SATA_PE#_DET (57)
M2_CONFIG1/PE_SATA#_SEL
s_minipci75p_rem8_4hd_lo_ns

M2_DEVSLP_R

SLC6
2

0.1UF/16V
X7R
1

/X
mbs_c0402_ns
H310M-K V2的案子注意:
GND
刪除M.2_9。
非H310M-K V2的案子注意:
留M.2_9。

P8Z77-V DELUXE R1.00

Title : M.2_X4

ASUSTeK COMPUTER INC


Engineer: Bing-jie_Wang
Size Project Name Rev
D SkyLake R1.00

Date: Monday, June 11, 2018 Sheet 72 of 113


note:台北和蘇州機種去掉電容直連后在QTC測試PASS,經leaders討論后決定去除電容變為直連

SATA6G_3
1 8 SATA6G_1
(57) S_SATA6_TXP3 GND1 NC1
S_SATA6_TXP3_C 2 1 8
A+ (57) S_SATA6_TXP1 GND1 NC1
3 S_SATA6_TXP1_C 2
(57) S_SATA6_TXN3 A- A+
S_SATA6_TXN3_C 4 3
GND2 (57) S_SATA6_TXN1 A-
5 S_SATA6_TXN1_C 4
(57) S_SATA6_RXN3 B- GND2
S_SATA6_RXN3_C 6 5
B+ (57) S_SATA6_RXN1 B-
7 9 S_SATA6_RXN1_C 6
(57) S_SATA6_RXP3 GND3 NC2 B+
S_SATA6_RXP3_C 7 9
(57) S_SATA6_RXP1 GND3 NC2
S_SATA6_RXP1_C
SATA_CON_7P
12015-00063500 SATA_CON_7P
GND 12015-00063500
GND

180度connector
180度connector
SATA6G_4
1 8 SATA6G_2
(57) S_SATA6_TXP4 GND1 NC1
S_SATA6_TXP4_C 2 1 8
A+ (57) S_SATA6_TXP2 GND1 NC1
3 S_SATA6_TXP2_C 2
(57) S_SATA6_TXN4 A- A+
S_SATA6_TXN4_C 4 3
GND2 (57) S_SATA6_TXN2 A-
5 S_SATA6_TXN2_C 4
(57) S_SATA6_RXN4 B- GND2
S_SATA6_RXN4_C 6 5
B+ (57) S_SATA6_RXN2 B-
7 9 S_SATA6_RXN2_C 6
(57) S_SATA6_RXP4 GND3 NC2 B+
S_SATA6_RXP4_C 7 9
(57) S_SATA6_RXP2 GND3 NC2
S_SATA6_RXP2_C
SATA_CON_7P
12015-00063500 SATA_CON_7P
GND 12015-00063500
GND
顏色: LIGHT GRAY

<Variant Name>

Title : SATA6G_123456(CHIPSET)

ASUSTek COMPUTER INC.


Engineer: KENNY_CHEN
Size Project Name Rev
R1.00
A2 Z87-PRO
Date: Monday, June 11, 2018 Sheet 74 of 113
OC# circuit for Intel
+5V_USB3_P12 +5V_USB3_P12
+5V_USB3_P12 +5VSB_DUAL +5V_USB3_P12
place near Chipset U31G1_12
UF31 1
Vbus1
1 2 2 19
(79) S_U3RXDN1 RX1- Vbus2
3 18
(79) S_U3RXDP1 RX1+ RX2- S_U3RXDN2 (79)

2
2.6A/8V 4 17
GND1 RX2+ S_U3RXDP2 (79)

1
UR167 mbs_polyswitch_2p_0805_h31 5 16
(79) S_U3TXDN1 TX1- GND4
UC21 4.7KOhm 6 15
(79) S_U3TXDP1 TX1+ TX2- S_U3TXDN2 (79)
0.1UF/16V N/A 7 14
GND2 TX2+ S_U3TXDP2 (79)

1
/X 8 13
(79) S_U2DN1 D1- GND3

1
ESDUC31 9 12
(79) S_U2DP1 D1+ D2- S_U2DN2 (79)
GND 0.1UF/16V 10 11
ID D2+ S_U2DP2 (79)

2
N/A
BOX_HD_2X10P_K20
UR168 mbs_box_hd_2x10p_79_k20_sp
1 2
(56) S_USB3_OC#12

8.2KOhm N/A GND


12007-00015700

GND
已換黑色料
GND GND
modify Part Number by color

+5V_USB3_P34 +5VSB_DUAL +5V_USB3_P34 +5V_USB3_P34 +5V_USB3_P34


place near Chipset U31G1_34
UF32 1 10
VBUS1 VBUS2
1 2 2 11
(79) S_U2DN4 D-1 D-2 S_U2DN3 (79)
3 12
(79) S_U2DP4 D+1 D+2 S_U2DP3 (79)
2.6A/8V 4 13
GND1 GND2
1

mbs_polyswitch_2p_0805_h31 5 14
(79) S_U3RXDN4 STDA_SSRX-1 STDA_SSRX-2 S_U3RXDN3 (79)
6

UC22 6 15
(79) S_U3RXDP4 STDA_SSRX+1 STDA_SSRX+2 S_U3RXDP3 (79)
0.1UF/16V URN161C 7 16
GND_DRAIN1 GND_DRAIN2
2

1
/X 4.7KOHM 8 17
(79) S_U3TXDN4 STDA_SSTX-1 STDA_SSTX-2 S_U3TXDN3 (79)
ESDUC32 9 18
(79) S_U3TXDP4 STDA_SSTX+1 SSTDA_STX+2 S_U3TXDP3 (79)
GND 0.1UF/16V

2
/X 19 20
P_GND1 P_GND2
5

21 22
P_GND3 P_GND4

5 6 URN162C USB_CON_18P
(56) S_USB3_OC#34 8.2KOHM
mbs_usb_18p_4hd_lf3
GND GND
GND GND

<Variant Name>

Title : USB3 Port


ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A3
Chipset USB Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 78 of 113


1

2
ULA31 mbs_choke_4P_79x47_nm 90Ohm/100MHz /X

Port 12
90Ohm/100MHz /X ULA33 mbs_choke_4P_79x47_nm

2
4

3
1

2
ULB31 mbs_choke_4P_79x47_nm 90Ohm/100MHz /X
90Ohm/100MHz /X ULB33 mbs_choke_4P_79x47_nm

2
Delete it for EMS (59) S_U3RXDN1_R
UR311 1
0402
2 /X
S_U3RXDN1 (78) (59) S_U3RXDN3_R
UR319 1
0402
2 /X
S_U3RXDN3 (78)
UR312 1 2 /X UR320 1 2 /X
(59) S_U3RXDP1_R 0402 S_U3RXDP1 (78) (59) S_U3RXDP3_R 0402 S_U3RXDP3 (78)
UR313 1 2 /X UR321 1 2 /X
ESD Diode (59)
(59)
S_U3TXDN1_R
S_U3TXDP1_R
UR314 1 0402
0402
2 /X
S_U3TXDN1
S_U3TXDP1
(78)
(78)
(59)
(59)
S_U3TXDN3_R
S_U3TXDP3_R
UR322 1 0402
0402
2 /X
S_U3TXDN3
S_U3TXDP3
(78)
(78)

3
1

2
ULA32 mbs_choke_4P_79x47_nm 90Ohm/100MHz /X
UD31 90Ohm/100MHz /X ULA34 mbs_choke_4P_79x47_nm
1 9

3
Line-1 NC4

2
S_U3TXDP1 2 8
Line-2 NC3

3
S_U3TXDN1 3

2
GND
4 7 ULB32 mbs_choke_4P_79x47_nm 90Ohm/100MHz /X
Line-3 NC2
S_U3TXDP2 5 6 90Ohm/100MHz /X ULB34 mbs_choke_4P_79x47_nm
Line-4 NC1
S_U3TXDN2

2
AZ1045-04F
N/A
GND UR315 1 2 /X UR323 1 2 /X
(59) S_U3RXDN2_R 0402 S_U3RXDN2 (78) (59) S_U3RXDN4_R 0402 S_U3RXDN4 (78)
UR316 1 2 /X UR324 1 2 /X
(59) S_U3RXDP2_R 0402 S_U3RXDP2 (78) (59) S_U3RXDP4_R 0402 S_U3RXDP4 (78)
UR317 1 2 /X UR325 1 2 /X
(59) S_U3TXDN2_R 0402 S_U3TXDN2 (78) (59) S_U3TXDN4_R 0402 S_U3TXDN4 (78)
UR318 1 2 /X UR326 1 2 /X
(59) S_U3TXDP2_R 0402 S_U3TXDP2 (78) (59) S_U3TXDP4_R 0402 S_U3TXDP4 (78)

UD32
1 9
Line-1 NC4
S_U3RXDP1 2 8
Line-2 NC3

3
S_U3RXDN1 3 must use protected 5VSB power +5VSB
GND
4 7 90Ohm/100MHz /X
Line-3 NC2
S_U3RXDP2 5 6 ULA21 mbs_choke_4P_79x47_nm /X must use protected 5VSB power +5VSB

2
Line-4 NC1
S_U3RXDN2 AZAW2110S.R7G ULA22 mbs_choke_4P_79x47_nm

2
AZ1045-04F 90Ohm/100MHz /X
A2 B2

3
N/A 4 3 UP24

3
90Ohm/100MHz /X GND VDD
GND 5 2 6 1
A1 B1 A1 B1
ULB21 mbs_choke_4P_79x47_nm 6 1 5 2

2
GND VDD
UP22 ULB22 mbs_choke_4P_79x47_nm 4 3
A2 B2

2
s_sot23_s6_national_ns 90Ohm/100MHz /X
/X AZAW2110S.R7G

3
UD21 UR211 1 2 /X GND AZAW2110S.R7G /X
(56) S_U2DP2_R 0402 S_U2DP2 (78)
UR212 1 2 /X S_U2DP2_Z
(56) S_U2DN2_R 0402 A2 B2 S_U2DN2 (78) s_sot23_s6_national_ns
1 6 UR213 1 2 /X S_U2DN2_Z 4 3 UR215 1 2 /X GND UP23
(56) S_U2DP1_R 0402 GND VDD S_U2DP1 (56)
(78) S_U2DP4_R 0402 S_U2DP4 (78)
S_U2DP2 S_U2DN2 UR214 1 2 /X S_U2DP1_Z 5 2 UR216 1 2 /X S_U2DP4_Z 6 1
(56) S_U2DN1_R 0402 A1 B1 S_U2DN1 (56)
(78) S_U2DN4_R 0402 A1 B1 S_U2DN4 (78)
S_U2DN1_Z 6 1 UR217 1 2 /X S_U2DN4_Z 5 2
(56) S_U2DP3_R 0402 GND VDD S_U2DP3 (78)
+5VSB UP21 UR218 1 2 /X S_U2DP3_Z 4 3
(56) S_U2DN3_R 0402 A2 B2 S_U2DN3 (78)
s_sot23_s6_national_ns S_U2DN3_Z
2 5 must use AZAW2110S.R7G
protected UR141 1 2 /X /X
5VSB power UR142 1 0402 2 /X
0402 s_sot23_s6_national_ns
GND UR143 1 2 /X UR145 1 2 /X
UR144 1 0402 2 /X UR146 1 0402 2 /X
3 4 0402 UR147 1 0402 2 /X
S_U2DP1 S_U2DN1 UR148 1 0402 2 /X
0402
IP4220CZ6
N/A UD121 UD122

1 6 1 6
S_U2DP1 S_U2DN1 S_U2DP3 S_U2DN3

+5VSB +5VSB

2 5 must use 2 5 must use


protected protected
5VSB power 5VSB power
GND GND

3 4 3 4
S_U2DP2 S_U2DN2 S_U2DP4 S_U2DN4

IP4220CZ6 IP4220CZ6
/U2_2nd_ESD_Front /U2_2nd_ESD_Back
Delete it for EMS

ESD Diode

1
UD22

6
Port 34
S_U2DP3 S_U2DN3
UD33 UD34
1 9 1 9 +5VSB
Line-1 NC4 Line-1 NC4
S_U3TXDN3 2 8 S_U3RXDN3 2 8
Line-2 NC3 Line-2 NC3
S_U3TXDP3 3 S_U3RXDP3 3 2 5 must use
GND GND
4 7 4 7 protected
Line-3 NC2 Line-3 NC2 5VSB power
S_U3TXDN4 5 6 S_U3RXDN4 5 6
Line-4 NC1 Line-4 NC1
S_U3TXDP4 S_U3RXDP4 GND
AZ1045-04F AZ1045-04F
N/A N/A 3 4
GND GND S_U2DP4 S_U2DN4

IP4220CZ6
N/A

<Variant Name>

Title : USB3 Port


ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A2
Chipset USB Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 79 of 113


OC# circuit for Intel

+5V_USB_P56 +5VSB_DUAL +5V_USB_P56


place near Chipset
UF3
1 2

1.75A

1
mbs_polyswitch_2p_0805_h31

4
UC13
(81,88) S_USB_PN5
0.1UF/16V URN161B
(81,88) S_USB_PP5
2

1
/X 4.7KOHM
ESDUC3
(81,88) S_USB_PN6
GND 0.1UF/16V
(81,88) S_USB_PP6

2
N/A

3
3 4 URN162B
(56) S_USB_OC#56 8.2KOHM

GND GND

+5V_USB_P78 +5VSB_DUAL +5V_USB_P78 +5V_USB_P78


place near Chipset
UF4
1 2

1.75A USB78
1

mbs_polyswitch_2p_0805_h31 2 1
(81) S_USB_PN7
2

UC14 4 3
(81) S_USB_PP7
0.1UF/16V URN161A S_USB_PN7 6 5 S_USB_PN8
2

1
/X 4.7KOHM S_USB_PP7 8 7 S_USB_PP8
(81) S_USB_PN8
ESDUC4 10
(81) S_USB_PP8
GND 0.1UF/16V

2
N/A HEADER_2X5P
1

mbs_hd_2x5p_100_k9_usb_lf3

1 2 URN162A
(56) S_USB_OC#78 8.2KOHM
12006-00026300
GND
GND GND
modify Part Number by color

<Variant Name>

Title : USB2 Port


ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A3
Chipset USB Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 80 of 113


Reserve USB Guard with short pin Delete it for EMS
Delete it for EMS

2nd ESD Diode


ESD Diode +5VSB

2
ULA3 mbs_choke_4P_79x47_nm must use protected 5VSB power
90Ohm/100MHz /X
UP6

3
6 1
A1 B1
5 2 UD13

2
GND VDD
UD3 ULB3 mbs_choke_4P_79x47_nm 4 3
A2 B2
90Ohm/100MHz /X 1 6
1 6 AZAW2110S.R7G S_USB_PP6 S_USB_PN6

3
S_USB_PP6 S_USB_PN6 /X
s_sot23_s6_national_ns +5VSB
+5VSB UR9 1 2 /X GND UP5
(56) S_USB_PP6_R 0402 S_USB_PP6 (88)
UR10 1 2 /X S_USB_PP6_Z 6 1 2 5 must use
(56) S_USB_PN6_R 0402 A1 B1 S_USB_PN6 (88)
2 5 must use UR11 1 2 /X S_USB_PN6_Z 5 2 protected
(56) S_USB_PP5_R 0402 GND VDD S_USB_PP5 (88) 5VSB power
protected UR12 1 2 /X S_USB_PP5_Z 4 3
5VSB power (56) S_USB_PN5_R 0402 A2 B2 S_USB_PN5 (88)
S_USB_PN5_Z GND
GND AZAW2110S.R7G
/X 3 4
3 4 S_USB_PP5 S_USB_PN5
s_sot23_s6_national_ns
S_USB_PP5 S_USB_PN5 UR109 1 2 /X
UR110 1 0402 2 /X IP4220CZ6
1 0402 2
IP4220CZ6 UR111 /X /U2_2nd_ESD_Back
1 0402 2
N/A UR112 /X
0402

3
+5VSB
90Ohm/100MHz /X must use protected 5VSB power
ULA4 mbs_choke_4P_79x47_nm /X
AZAW2110S.R7G

2
A2 B2

3
4 3 UD14
90Ohm/100MHz /X GND VDD
UD4 5 2
ULB4 mbs_choke_4P_79x47_nm A1 B1
6 1 1 6
1 6 UP8 S_USB_PP7 S_USB_PN7

2
S_USB_PP8 S_USB_PN8 s_sot23_s6_national_ns
/X +5VSB
+5VSB UR13 1 2 /X GND AZAW2110S.R7G
(56) S_USB_PP8_R 0402 S_USB_PP8 (80)
UR14 1 2 /X S_USB_PP8_Z 2 5 must use
(56) S_USB_PN8_R 0402 A2 B2 S_USB_PN8 (80)
2 5 must use UR15 1 2 /X S_USB_PN8_Z 4 3 protected
(56) S_USB_PP7_R 0402 GND VDD S_USB_PP7 (80) 5VSB power
protected UR16 1 2 /X S_USB_PP7_Z 5 2
5VSB power (56) S_USB_PN7_R 0402 A1 B1 S_USB_PN7 (80)
S_USB_PN7_Z 6 1 GND
GND UP7
s_sot23_s6_national_ns 3 4
3 4 S_USB_PP8 S_USB_PN8
S_USB_PP7 S_USB_PN7 UR113 1 2 /X
UR114 1 0402 2 /X IP4220CZ6
IP4220CZ6 UR115 1 0402 2 /X /U2_2nd_ESD_Front
1 0402 2
N/A UR116 /X
0402

<Variant Name>

Title : USB2 Port


ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A2
Chipset USB Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 81 of 113


OC# circuit for Intel
+5V_USB_P910 +5VSB_DUAL +5V_USB_P910 +5V_USB_P910
place near Chipset
UF5
1 2

1.75A USB910
(83) S_USB_PN10

1
mbs_polyswitch_2p_0805_h31 2 1
(83) S_USB_PP10

8
UC15 4 3
0.1UF/16V URN161D S_USB_PN9 6 5 S_USB_PN10
(83) S_USB_PN9

1
/X 4.7KOHM S_USB_PP9 8 7 S_USB_PP10
(83) S_USB_PP9
ESDUC5 10
GND 0.1UF/16V

2
N/A HEADER_2X5P

7
mbs_hd_2x5p_100_k9_usb_lf3

7 8 URN162D
(56) S_USB_OC#910 8.2KOHM
12006-00026300
GND
GND GND
modify Part Number by color

<Variant Name>

Title : USB2 Port


ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A3
Chipset USB Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 82 of 113


Delete it for EMS
Reserve USB Guard with short pin Delete it for EMS

3
+5VSB
ESD Diode 90Ohm/100MHz
ULA5
/X
mbs_choke_4P_79x47_nm
must use protected 5VSB power
/X
2nd ESD Diode
AZAW2110S.R7G

2
A2 B2

3
UD5 4 3 UD15
90Ohm/100MHz /X GND VDD
5 2
ULB5 mbs_choke_4P_79x47_nm A1 B1
1 6 6 1 1 6
S_USB_PP9 S_USB_PN9 UP10 S_USB_PP10 S_USB_PN10

2
s_sot23_s6_national_ns
+5VSB /X +5VSB
UR17 1 2 /X GND AZAW2110S.R7G
(56) S_USB_PP10_R 0402 S_USB_PP10 (82)
2 5 must use UR18 1 2 /X S_USB_PP10_Z 2 5 must use
(56) S_USB_PN10_R 0402 A2 B2 S_USB_PN10 (82)
protected UR19 1 2 /X S_USB_PN10_Z 4 3 protected
5VSB power (56) S_USB_PP9_R 0402 GND VDD S_USB_PP9 (82) 5VSB power
UR20 1 2 /X S_USB_PP9_Z 5 2
(56) S_USB_PN9_R 0402 A1 B1 S_USB_PN9 (82)
GND S_USB_PN9_Z 6 1 GND
UP9
3 4 s_sot23_s6_national_ns 3 4
S_USB_PP10 S_USB_PN10 S_USB_PP9 S_USB_PN9
UR117 1 2 /X
1 0402 2
IP4220CZ6 UR118 /X IP4220CZ6
1 0402 2
N/A UR119 /X /U2_2nd_ESD_Front
UR120 1 0402 2 /X
0402

<Variant Name>

Title : USB2 Port


ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A2
Chipset USB Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 83 of 113


+5VSB_DUAL current:
DIMM*4=7A, DIMM*2=5A, DIMM not generate from +5VSB_DUAL=0A N-MOS Max Current
USB 2.0=0.5A/port
USB 3.x=1A/port Power PAK MOS 4 mohm 15A
USB Type C=3A/port
if +5VSB_DUAL current (DIMM+USB 2.0 Port+USB 3.x Port) > 15A, add UQ706
Power PAK MOS 6 mohm 13A

DPAK MOS 9 mohm 10A

<Variant Name>

Title : N-MOS2
ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A3
Chipset USB Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 84 of 113


USB Power CAP recommend placement
if there no USB Port, UCE2
place near UCE1 or
remove

UCE2

UCE1
PL CAP & EL CAP co-lay PL CAP & EL CAP co-lay

+5VSB_DUAL +5VSB_DUAL

EL 820U: 11V040827130 EL 820U: 11V040827130


PL 560U: 11031V0004F300 PL 560U: 11031V0004F300
PL 100U: 11031-0001F400 PL 100U: 11031-0001F400
1

+ UCE1 + UCE5
560UF/6.3V 560UF/6.3V
11031-0001F400 11031-0001F400

UCE6
2

mbs_cpl_560u6d3vsha_lfh_ms mbs_cpl_560u6d3vsha_lfh_ms
N/A N/A

GND GND
UCE6 place near USB3.x Header,
remove UCE6 if no USB3.x Header

+5VSB_DUAL

EL 820U: 11V040827130
PL 560U: 11031V0004F300
PL 100U: 11031-0001F400
UCE5
1

+ UCE2
560UF/6.3V
11031-0001F400
2

mbs_cpl_560u6d3vsha_lfh_ms
/X

<Variant Name>

GND
Title : USB Power CAP
ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A3
Chipset USB Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 85 of 113


RTL8111H Circuit
1. If support Deep S4/S5 wake-up, rename S_WAKE# to S_WAKE#_LAN1
2. Modify PCIE Reset Signal Net Name by Project
3. Choose Crystal Type by Project
4. Check +3VSB_LAN1 Power Source by Project,
5. Delete CLKREQ#_LAN1 if not need
6. select block 1 or 2 according to if you support S0IX

pull high on Chipset Side L1U1A


L1C13 2 1 10PF/50V
/X
(54) CLKREQ#_LAN1
L1C12 2 1 10PF/50V
/X 12
CLKREQB
15
(54) CK_100M_LAN1P REFCLK_P
GND 16 10
(54) CK_100M_LAN1N REFCLK_N MDIN3 L1_MDI_N3 (88)
9
MDIP3 L1_MDI_P3 (88)
7
MDIN2 L1_MDI_N2 (88)
6
MDIP2 L1_MDI_P2 (88)
5
MDIN1 L1_MDI_N1 (88)
Place near Chipset 4
MDIP1 L1_MDI_P1 (88)
SL1C1 2 1 0.1UF/16V X7R 13 2
pls select pcie (56) S_X1_LAN1_TXP
SL1C2 2 1 0.1UF/16V X7R S_X1_LAN1_TXP_C 14
HSIP MDIN0
1
L1_MDI_N0 (88)
(56) S_X1_LAN1_TXN HSIN MDIP0 L1_MDI_P0 (88)
port which can be S_X1_LAN1_TXN_C

separate disabled L1C3 2 1 0.1UF/16V X7R 17


(56) S_X1_LAN1_RXP
L1C4 2 1 0.1UF/16V X7R S_X1_LAN1_RXP_C 18
HSOP
28
DIP Crystal
(56) S_X1_LAN1_RXN HSON CKXTAL1
S_X1_LAN1_RXN_C 29 L1_XIN
CKXTAL2
Place near LAN IC L1_XOUT L1X1
21 1 2
(89) S_WAKE#_LAN1 LANWAKEB
L1_XOUT GND L1_XIN
L1C14 2 1 0.01UF/16V 3 25Mhz

1
X7R /X 19 L1C10 mbs_xtal_2p_h145_lfh L1C11
(55,96,108,113) S_PLTRST# PERSTB
30PF/50V 30PF/50V
GND

2
+3V

L1R2 GND
1KOhm
L1R811 2
1

1 2 0Ohm 20
(57) L1_ISOLATE# ISOLATEB
/X L1_ISOLATE#_R 27
LED0 L1_ACTLEDN (88)
2

L1R3 26
LED1/GPO L1_LINK100# (88)
L1_ISOLATE# GPIO select: 15KOhm L1R5
1. could be GPI & GPO both, default GPI (no mbs_r0603 L1R1
LED2
25 1 2
L1_LINK1000# (88)
internal pull-down/pull-high resistor) 1 2 31
RSET
L1_LINK1000#_R
1

2. main power plane or stand by power L1_LREXT 300OHM


plane, 3V tolerance 2.49KOhm +3VSB_LAN1
3. GPI to enable Realtek LAN GND GND
4. GPO low to disable Realtek LAN L1R6
1 2
L1_ACTLEDP (88)

300OHM

+3VSB_LAN1 +3VSB_LAN1 to Pin 23


trace need 40 mils wide +L1_1.0V_VOUT trace need
60 mils wide +L1_1.0V
23
VDDREG
L1L24
11 24 1 2
AVDD33_1 REGOUT
32 +L1_1.0V_VOUT
AVDD33_2

1
L1U1C24 SHORTPIN_0603_NM
1

L1U1C211 L1U1C11 L1U1C232 L1U1C32 0.1UF/16V /X


4.7UF/6.3V 0.1UF/16V 4.7UF/6.3V 0.1UF/16V X7R

2
STANDARD CIRCUIT mbs_c0603 X7R mbs_c0603 X7R
2

/X /X
GND
XUMB LAN
near pin 11 near pin 32
GND 3
AVDD10_1
SZ_LAN_1.0E 8
AVDD10_2
30
AVDD10_3

1
LOGO_HD_DEMO_LAN 22 L1U1C222 L1U1C3 L1U1C8 L1U1C30
DVDD10
/X L1U1C22 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
1UF/16V X7R X7R X7R X7R

2
mbs_c0603
N/A

near pin 22 near pin 3/8/30


BOM

GND
N/A mount
L1U1B
34
GND2
/X unmount 35 <Variant Name>
GND3
36 33
GND4 GND1
GND5
37
Title : RTL8111H
RTL8111H-CG RTL8111H-CG
GND ASUSTEK COMPUTER INC
Engineer: SZ Design IP
06112-00030200 GND 06112-00030200
Size Project Name Rev
A3
LAN Demo Circuit
0.0
Date: Monday, June 11, 2018 Sheet 87 of 113
1. change LAN_USB12 name ,part, partnumber to what you want,copy from page24
2. change vcc source name
3. change usb signal name

4. del L1C96,L1C94,L1C95 according what lan you use

GLAN + USB2 *2 Connector


single LAN named LAN_USBxx
dual LAN named LAN1_USBxx
for Realtek LAN LAN_USB56

GND

29

27
28

30
L1_CTR +5V_USB_P56
ACTLEDP

LANGND29

LANGND27
LANGND28

LANGND30
22
ACTLEDN
L1_ACTLEDP 21
L1_ACTLEDN
LAN_GND

1
L1C94 L1C95 18
TD4- VCC1
L1C96 100PF/50V 120PF/50V 17 8
TD4+ VCC2
1UF/16V L1_MDI_N3 16 7
TD3- 2P-

2
mbs_c0603 L1_MDI_P3 15 6
TD3+ 1P- S_USB_PN6 (81)
/X L1_MDI_N2 14 5
TD2- 2P+ S_USB_PN5 (81)
L1_MDI_P2 13 4
TD2+ 1P+ S_USB_PP6 (81)
L1_MDI_N1 12 3
TD1- GND1 S_USB_PP5 (81)
L1_MDI_P1 11 2
TD1+ GND2
L1_MDI_N0 10 1
CTR
L1_MDI_P0 9
S_USB_PN(a+1)
GND L1_CTR S_USB_PN(a)
LILEDN

USBGND25

USBGND23
USBGND24

USBGND26
20 S_USB_PP(a+1)
LILEDP
L1_LINK1000# 19 S_USB_PP(a)
L1_LINK100#

USB_LAN_LED

25

23
24

26
L1C90 2 1 1000PF/50V mbs_lan_usbx2_ledx2_stc_lf3
(87) L1_ACTLEDP
X7R /X 12014-00672000

L1C91 2 1 1000PF/50V
(87) L1_ACTLEDN
X7R /X

L1C92 2 1 1000PF/50V
(87) L1_LINK1000# Surge 6KV/6KV : 12014-00061700
X7R /X Surge 15KV/6KV: 12014-00671400 GND

L1C93 2 1 1000PF/50V
(87) L1_LINK100#
X7R /X

Place near LAN Connector


GND

Delete it for EMS

L1D1

1 6
(87) L1_MDI_P0 L1_MDI_N0 (87)

+3VSB_LAN1

2 5

GND

3 4
(87) L1_MDI_P1 L1_MDI_N1 (87)

IP4220CZ6
/X

unmount L2D1, L2D2 when use Surge 15KV/6KV LAN Connector

L1D2

1 6
(87) L1_MDI_P2 L1_MDI_N2 (87)

+3VSB_LAN1

2 5

GND

3 4 <Variant Name>
(87) L1_MDI_P3 L1_MDI_N3 (87)

IP4220CZ6
Title : LAN Connector
/X
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A3
LAN Demo Circuit
0.0
Date: Monday, June 11, 2018 Sheet 88 of 113
LAN1 Deep S4/S5 Wake-up Circuit
1. Remove Short-Pin L1R88 in LAN1 IC Page

+3VSB +3VSB_LAN1 +3VSB_ATX

L1R88 L1R89
1 2 1 2

0Ohm 0Ohm
/NO_LAN1_ERP_WAKE /LAN1_ERP_WAKE
1

for Intel PHY

2. for Intel PHY LAN, L1_LAN_DISABLE# renamed L1_LAN_DISABLE#_R in LAN1 IC Page

3. for Intel PHY LAN, L1_LAN_WAKE# renamed L1_LAN_WAKE#_R in LAN1 IC Page

for PCIE LAN1


4. for PCIE LAN, S_WAKE# renamed S_WAKE#_LAN1 in LAN1 IC Page

5. for Intel PCIE LAN, make sure L1_DEV_OFF# choose +3VSB_ATX power plane GPIO

+3VSB_LAN1
1

L1R82
8.2KOhm
/LAN1_ERP_WAKE
from LAN
to Chipset
2

L1R81
1 2
(87) S_WAKE#_LAN1 S_WAKE# (51,58,69,72)

0Ohm
/NO_LAN1_ERP_WAKE

L1R84
1 2
LAN_SIO_WAKE# (96,97)
<Variant Name>
0Ohm
to SIO's support wake-up pin
/LAN1_ERP_WAKE
Title : Deep S4/S5 Wake
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A3
LAN Demo Circuit
0.0
Date: Monday, June 11, 2018 Sheet 89 of 113
ALC887-VD2 & ALC892 Circuit
1. Modify AU1 Part Number by Project 4. Delete A_SPDIFO_HEADER if not need 7. Delete CEN/LFE & Surround for Rear 3 Jacks

2. Modify IO Power by Project 5. Delete A_SPDIFO_OPTICAL if not need 8. Block 8,9, select one of them according if
support s0ix
3. Delete A_EAPD if not need 6. Delete Side Surround for Rear 3 Jacks or 5Jacks

AU1
AR11
S_HD_SDOUT_R 22 Ohm S_HD_SDOUT 1 2 8 23
(58) A_HD_SDIN0 SDATA-IN LINE1-L(PORT-C-L) A_LINE_L_C (92)
A_HD_SDIN0_R
S_HD_SYNC_R 22 Ohm S_HD_SYNC 22Ohm 5 24
(58) S_HD_SDOUT SDATA-OUT LINE1-R(PORT-C-R) A_LINE_R_C (92)
10
Chipset S_HD_RST#_R S_HD_RST#
(58) S_HD_SYNC
11
SYNC
+5VA_IN
22 Ohm (58) S_HD_RST# RESET#

S_HD_BITCLK_R 22 Ohm S_HD_BITCLK 6 29


(58) S_HD_BITCLK BCLK LDOVDD

1
AU1C29 AU1C229
/X 0.1UF/16V 10UF/6.3V
The Resistor & CAP design
X7R mbs_c0805
in Chipset Circuit and

2
35 /X X5R
place on Chipset side FRONT-L(PORT-D-L) A_LOUT_L_C (92)

36
FRONT-R(PORT-D-R) A_LOUT_R_C (92)
A_GND

12
BEEP

+3V

21
MIC1-L(PORT-B-L) A_MIC1_L_C (92)
1

1
AU1C201 AU1C1 22
MIC1-R(PORT-B-R) A_MIC1_R_C (92)
1UF/10V 0.1UF/16V
mbs_c0603 X7R
2

2
X5R 48 28
SPDIFO_1 MIC1-VREFO-L(PORT-B-VREFO-L) A_VREF_MIC1_L (92)
/X
18 32
CD-L MIC1-VREFO-R(PORT-B-VREFO-R) A_VREF_MIC1_R (92)
GND GND 19
CD-GND
20
CD-R

+3VSB
IO Power
1
DVDD
9
DVDD-IO
+5VA 45
SIDESURR-L(PORT-H-L)
1

AU1C209 AU1C9
1UF/10V 0.1UF/16V 38 46
AVDD2 SIDESURR-R(PORT-H-R)
mbs_c0603 X7R 25
AVDD1
2

X5R
/X

GND GND
2 33
SenseC

27
VREF
+A_VREF 43
CENTER(PORT-G-L)
1

AU1C227 AU1C27
0.1UF/16V 10UF/6.3V 44
LFE(PORT-G-R)
X7R mbs_c0805
2

/X X5R

A_GND

AR1 1 2 20KOhm 40
JDREF
AETCH1 A_JDREF 39
SURR-L(PORT-A-L)
1
SHORT_GND
A_GND 41
SURR-R(PORT-A-R)
Short_GND
/X
2
(93) A_SPDIFO_HEADER GPIO0/DMIC_CLK/SPDIFO_2
3
REGREF
+A_REGREF
1

AU1C3
10UF/6.3V
mbs_c0805
2

BOM X5R

N/A mount GND 14


LINE2-L(PORT-E-L) A_HPOUT_L_C (91)

15
LINE2-R(PORT-E-R) A_HPOUT_R_C (91)
/X unmount

+5VA
31
LINE2-VREFO(PORT-E-VREFO) A_VREF_FMIC2 (91)

STANDARD CIRCUIT
1

AU1C225 AU1C25 AU1C238 AU1C38 16


MIC2-L(PORT-F-L) A_FMIC1_L_C (91)
10UF/6.3V 0.1UF/16V 10UF/6.3V 0.1UF/16V
mbs_c0805 X7R mbs_c0805 X7R 17
MIC2-R(PORT-F-R) A_FMIC1_R_C (91)
2

XUMB Audio X5R X5R 37


PIN37-VREFO
/X

SZ_Audio_1.0F
A_GND 30
MIC2-VREFO(PORT-F-VREFO) A_VREF_FMIC1 (91)
HD_STANDARD_AUDIO
/X

47
EAPD/SPDIFI
GPIO1/DMIC_DATA

13
(92) A_SENSE_A SenseA
AVSS2

AVSS1
DVSS

34
(91) A_SENSE_B SenseB
1

AC48 AC49 ALC892-GR <Variant Name>


4
7

42

26

100PF/50V 100PF/50V 02G611007310


/X /X
Title : ALC887-VD2_ALC892
2

ALC887-VD2: 02G611007310
ALC892(Cu): 02G611230701 Engineer:
ASUSTEK COMPUTER INC SZ Design IP
A_GND GND A_GND
Size Project Name Rev
Custom
AUDIO Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 90 of 113


AAFP Circuit
1. Choose AAFP Header Circuit by Codec,and change AAFP part number by your request,block 6,7, or 8
2. Choose HP Circuit with or without AMP/De-POP/Switch by Project,block 1,2,3,4
AAFP
3. Modify ACE9, ACE10 Part Number by Project
4. IF you use 1220, AC13,AC14,AC15,AC16 option must change to N/A and change part number to varistor for ALC887-VD2/ALC892
5. Modify ARN202 value to 4.7k if you use 887,block 5 AAFP
1 2
6. For Gamer Project with ALC1150, AL13, AL14 change to 47Ohm A_FMIC1_L 3 4
A_FMIC1_R 5 6 AR8 1 2 20KOhm
7. change AC37,AC38 part number if you have AMP,block 6 A_HPOUT_R 7 A_JD_FMIC1
A_JD_FRONT 9 10 AR9 1 2 39.2KOhm
A_HPOUT_L A_JD_HPOUT
HEADER_2X5P_K8
mbs_hd_2x5p_k8_audio_lf3
12006-00025800 A_GND

AR10 1 2 47OHM
A_SENSE_B (90)

for ALC887-VD2/ALC892/ALC1150/ALC1220X

1
AC27
100PF/50V AC37 0.01UF/16V /X
6 A_FMIC1_L 1 2 11V232103370

2
AC38 0.01UF/16V /X
A_GND A_FMIC1_R 1 2 11V232103370

AC37, AC38
0.01UF without AMP: 11V232103370 A_GND
0.033UF with AMP : 11V232333370

ACE9 100UF/16V AL13 1 2 75Ohm


+

(90) A_HPOUT_L_C
1 2 11011-00024100 A_HPOUT_L_L mbs_r0603 10V213750010 A_HPOUT_L
ACE10 100UF/16V AL14 1 2 75Ohm
+

(90) A_HPOUT_R_C
1 2 11011-00024100 A_HPOUT_R_L mbs_r0603 10V213750010 A_HPOUT_R

AD2
3 2
1
2.7KOHM
2 ARN201A AC13
1 2
100PF/50V
A_VREF_FMIC2_L A_HPOUT_L_L A_HPOUT_L /X 11V232101630
(90) A_VREF_FMIC2 N/A
3 3 4 ARN201B AC14 100PF/50V
2.7KOHM
1 A_VREF_FMIC2_R A_HPOUT_R_L A_HPOUT_R /X 1 2 11V232101630
N/A
BAT54AW
N/A 4 A_GND

without AMP without De-POP & Switch

DIP CAP AL13, AL14 AC13, AC14


EL 100U : 11V040107321 75 Ohm: 10V213750010 100PF : 11V232101630
PL 100U : 11031V0001F000 47 Ohm: 10V213470010 Varistor: 07V200402020
Nichicon 100U: 11011-00026100
Elan 100U :11011-00025000

Taping DIP CAP Taping DIP CAP


Chemicon 100U T: 11011-00024100 PL 100U T:11031V0001F400

AC21 2 1 10UF/6.3V AL15 1 2 75Ohm


(90) A_FMIC1_L_C
X5R mbs_c0805 A_FMIC1_L_L mbs_r0603 A_FMIC1_L
AC22 2 1 10UF/6.3V AL16 1 2 75Ohm
(90) A_FMIC1_R_C
X5R mbs_c0805 A_FMIC1_R_L mbs_r0603 A_FMIC1_R
1

1
AC15 AC16
100PF/50V 100PF/50V
AD1 11V232101630 11V232101630
2

2
1 2 ARN202A /X /X
4.7KOHM
2 A_VREF_FMIC1_L
(90) A_VREF_FMIC1
3 3 4 ARN202B
4.7KOHM
1 A_VREF_FMIC1_R A_GND
BAT54AW 5 6 ARN202C
4.7KOHM
AC15, AC16
7 8 ARN202D
4.7KOHM 100PF : 11V232101630
Varistor: 07V200402020
5
ARN202 change to 4.7K Ohm for ALC887-VD2

<Variant Name>

Title : AAFP
ASUSTEK COMPUTER INC
Engineer: SZ Design IP

Delete it for EMS


Size Project Name Rev
A3
AUDIO Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 91 of 113


Rear 3Jacks Circuit
for ALC887-VD2/ALC892
1. Choose Jack Detect Circuit by Codec,block 1,2,3
2. Choose LOUT DIP CAP Type by Codec & Project,block 4,5,6 AR2 1 2 5.1KOhm
(90) A_SENSE_A
AR3 1 2 10KOhm A_JD_LOUT
3. Choose LOUT Circuit with or without De-POP/Switch by Project,block 7,8 AR4 1 2 20KOhm A_JD_LINE

4. Modify ACE1, ACE2 Part Number by Project 1 A_JD_MIC1

5. Choose Rear MIC VREF Circuit by Project ,block9,10


6. For Gamer/Gaming modity AC17, AC18 part by request
7 if you use 1220 ,Modify AC1,AC2,AC3, AC4, ,AC5,AC6, Part Number to varistor and Optional to N/A

Delete it for EMS

10UF
ACE1 10UF/10V
+

(90) A_LOUT_L_C
1 2 11011-00064100
ACE2 10UF/10V
+

4 (90) A_LOUT_R_C
1 2 11011-00064100

AL3 1 2 75Ohm
A_LOUT_L_L mbs_r0603 A_LOUT_L
AL4 1 2 75Ohm
A_LOUT_R_L mbs_r0603 A_LOUT_R

without AMP/De-POP/Switch
8 AC3
1 2
100PF/50V
A_LOUT_L /X 11V232101630
AC4 100PF/50V
A_LOUT_L_L A_LOUT_R /X 1 2 11V232101630 AUDIO
32
A_LOUT_R_L A_LINE_L 33
A_GND A_JD_LINE 34 PORT3
35
A_LINE_R 31 Light Blue
22
AC17 2 1 10UF/6.3V AL1 1 2 75Ohm A_LOUT_L 23
(90) A_LINE_L_C PORT2
X5R mbs_c0805 A_LINE_L_L mbs_r0603 A_LINE_L A_JD_LOUT 24
AC18 2 1 10UF/6.3V AL2 1 2 75Ohm 25
(90) A_LINE_R_C
X5R mbs_c0805 A_LINE_R_L mbs_r0603 A_LINE_R A_LOUT_R 21 Lime

1
AC1 AC2 2
100PF/50V 100PF/50V A_MIC1_L 3
11V232101630 11V232101630 A_JD_MIC1 4 PORT1

2
/X /X 5
A_MIC1_R 1 Pink
G1 P_GND1

teknisi indonesia
A_GND G2 P_GND2
G3 P_GND3
G4 P_GND4
A_CGND P1 NP_NC1

1
AC19 2 1 4.7UF/6.3V AL5 1 2 75Ohm AC24 AC23
(90) A_MIC1_L_C
X5R mbs_c0603 A_MIC1_L_L mbs_r0603 A_MIC1_L 0.1UF/16V 0.1UF/16V AUDIO_JACK_13P_5HOLD
AC20 2 1 4.7UF/6.3V AL6 1 2 75Ohm X7R X7R mbs_audio_jack_13p_5hd_lf3
(90) A_MIC1_R_C

2
X5R mbs_c0603 A_MIC1_R_L mbs_r0603 A_MIC1_R /X

1
AC5 AC6
100PF/50V 100PF/50V
11V232101630 11V232101630
Normal
2

2
/X /X A_GND

5 6 ARN201C
(90) A_VREF_MIC1_L 2.7KOHM
A_MIC1_L_L A_GND
Audio CAP using rule,pls change all dip
7 8 ARN201D caps partnumber according bellow rule
9 (90) A_VREF_MIC1_R 2.7KOHM
A_MIC1_R_L

Z390,B450 ROG / Strix series Nichicon

Z390,B450 PRIME / TUF Series ELNA

Intel H310,H310C,H110&AMD A320 series Chemicon

other chipsets except above series Nichicon


<Variant Name>
DIP CAP DIP CAP
EL 10U : 11G040822620 EL 100U : 11V040107321 AC1, AC2, AC3, AC4, AC5, AC6 Title : 3 Jacks
PL 10U : 11V090106207 PL 100U : 11031V0001F000 100PF : 11V232101630
Nichicon 10U: 11011-00066100 Nichicon 100U: 11011-00026100 Varistor: 07V200402020 Engineer:
Elan 10U:11011-00065000 Elan 100U :11011-00025000 ASUSTEK COMPUTER INC SZ Design IP
Size Project Name Rev
Taping DIP CAP
A3
AUDIO Demo Circuit
Taping DIP CAP Taping DIP CAP PL 100U T:11031V0001F400 0.0
Chemicon 10U T: 11011-00064100 Chemicon 100U T: 11011-00024100 Date: Monday, June 11, 2018 Sheet 92 of 113
1. select block 1,2, or 3 by project
SPDIF

SPDIF Header
+5V 3
SPDIF_OUT
1

3
A_SPDIFO_HEADER (90)
4
1

AC32 AC28
HEADER_1X4P_K2 0.1UF/16V 100PF/50V
mbs_hd_1x4p_100_k2_lf3 X7R /X <Variant Name>
2

12006-00152400 /X
Title : SPDIF
GND
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A
AUDIO Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 93 of 113


Audio GAP & Power Circuit

1. Choose Resistor & Capacitor over GAP Circuit by Project

2. Keep or delete Audio Power LDO Circuit by Project

3. Modify APCE4 Part Number by Project

40 mils Gap for XU


0402 & 0603 component over 40 mils Gap must mount

must use protected 5VSB power


+5VSB +5VA_IN

AGL1 1 2 0Ohm
mbs_r0603 N/A

AGC1 2 1 0.1UF/16V
X7R N/A
AGC2 2 1 0.1UF/16V
X7R /X
AGC3 2 1 0.1UF/16V
X7R N/A

A_GND GND

BOM Audio Power from 5VSB Audio Power from 12V LDO 5V

/AUDIO_PWR_5VSB mount unmount

/AUDIO_PWR_LDO unmount mount

<Variant Name>

Title : GAP_Power
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A3
AUDIO Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 94 of 113


AUDIO LED Circuit

1. Modify Audio LED part number by Project 3. Keep or delete Codec Cover LED by Project

2. Choose or delete Codec Cover by Project 4. Modify Codec Cover Part Number by Project

5. One 2N7002 support max 10 LEDs

+5VSB if ARN101 change to single resistor, if ARN102 change to single resistor,


use R0603(10V213300110) use R0603(10V213300110)
2

8
ARN101A ARN101B ARN101C ARN101D ARN102A ARN102B ARN102C ARN102D
300Ohm 300Ohm 300Ohm 300Ohm 300Ohm 300Ohm 300Ohm 300Ohm
/AUDIO_GAP_LED /AUDIO_GAP_LED /AUDIO_GAP_LED /AUDIO_GAP_LED /AUDIO_GAP_LED /AUDIO_GAP_LED /AUDIO_GAP_LED /AUDIO_GAP_LED
s_4r8p0603_ns s_4r8p0603_ns s_4r8p0603_ns s_4r8p0603_ns s_4r8p0603_ns s_4r8p0603_ns s_4r8p0603_ns s_4r8p0603_ns
1

7
1

1
AULED1 AULED2 AULED3 AULED4 AULED5 AULED6
+

+
YELLOW YELLOW YELLOW YELLOW YELLOW YELLOW
07014-00091400 07014-00091400 07014-00091400 07014-00091400 07014-00091400 07014-00091400
/AUDIO_GAP_LED /AUDIO_GAP_LED /AUDIO_GAP_LED /AUDIO_GAP_LED /AUDIO_GAP_LED /AUDIO_GAP_LED
s_led_2p_63x31_h16_ns s_led_2p_63x31_h16_ns s_led_2p_63x31_h16_ns s_led_2p_63x31_h16_ns s_led_2p_63x31_h16_ns s_led_2p_63x31_h16_ns
2

2
place on Bottom Side, place on Bottom Side,
close to Gap close to Gap

Audio LED
Yellow: 07014-00091400
Red : 07VA010R0000

AULED_GND1 Audio LED


White: 07014-00471000
3
3

AQ101
11 H2N7002
G /AUDIO_GAP_LED
S
2 mbs_sot23_ns
2
1

AQ101C1 One 2N7002 support max 10 LEDs


0.1UF/16V
X7R
2

/X GND
mbs_c0402_ns

GND

ATX normal 12 pcs LED, m-ATX normal 6 pcs LED


AUDIO_LED_PWM (96)

AUDIO_LED_PWM GPIO select:


1. could be GPI & GPO both, default GPI (no internal pull-down resistor)
2. could mapping to Fading PWM function
3. stand by power plane, 3V tolerance
4. GPI to turn on Audio LED
5. GPO low to turn off Audio LED
6. Fading PWM to be Breathing LED

<Variant Name>

Title : Cover_LED
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A3
AUDIO Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 95 of 113


NCT5582D Circuit
C E.2
A. Choose +3V_SIO Power Source Choose SIO Power Source +3V_SIO
could delete this block when LPC Bus Pin 48 used as CASEOPEN0#
Signal with Chipset side pull-high O1R70 8.2KOhm /X +3V_BAT
B. Check Pin 59 VTT Power should be CPU PECI Power +PVDD_SIO 1 2
A.2 O1R23 1 2 2MOHM N/A
O1R266 8.2KOhm +3V_SIO +3V
C. Delete LPC Bus Signal Pull High Resistor if don't need S_LAD3 1 2 /X
O_CASEOPEN# (98)
O1R265 8.2KOhm O_CASEOPEN#
S_LAD2 1 2 /X
D. Delete Pin 13 KBRST# Circuit if not connect KBRST# to Chipset O1R264 8.2KOhm
S_LAD1 1 2 /X Near monitor point
O1R263 8.2KOhm
E. Choose Pin 48 THERMTRIP#/CASEOPEN0# circuit by Project S_LAD0 1 2 /X VCORE
CPUJP9
OU1 +3V_BAT
F. Delete COM1 Port Signal if don't need, but keep Strapping Pin Signal 2 1 /X
+PVDD_SIO SHORTPIN

2
G. Choose NCT5582D DDR4 Power Sequence Circuit by Project O1R261 8.2KOhm
S_LFRAME# 1 2 /X LPC/eSPI O1R24 O1R30 1KOhm
4 Intruder 2MOHM 2 1
SMBUS AUDIO_LED_PWM DDR4 Power Seuqence (59) S_ESPI_RST# ESPI_RST#/LDRQ#
48 O_VCORE O_VCORE_IN
THERMTRIP#_1/CASEOPEN0#

1
GP32(GRN_LED) +3VSB 50
Not use Can use SKTOCC# H_SKTOCC# (35,36)
O1C30 1000PF/50V

1
GRN_LED(GP23 or GP84) O1R1 1 2 8.2KOhm 5 O1C12 1 2 /X
Use Can use (59,108) S_SERIRQ ESPI_ALERT#/SERIRQ
O_RSMRST# 12 KBMS 100PF/50V
(55,87,108,113) S_PLTRST# PLFLRST#/LRESET#
GP24(MLED) O1R2 1KOhm 24 O1R31 2 1 1KOhm
Use Can not use (59,108) S_LFRAME# MCLK/GP23/AUXFANOUT3 O_MS_CLK (100)

2
O1_IOPWRBTN#_R 1 2 N/A 11 25
(59,108) S_LAD[3..0] ESPI_CS#/LFRAME# MDAT/GP22/AUXFANIN3 O_MS_DATA (100)
+5VSB 9 26
ESPI_IO0/LAD0 KCLK/GP21/AUXFANOUT2/CIRRX O_KB_CLK (100)
O1C201 S_LAD0 8 27 GND GND
H. Modify FAN IN/PWM/GPP/GPL Signal by Project O1R201 1 2 4.7KOhm mbs_r0603 /X S_LAD1 7
ESPI_IO1/LAD1 KDAT/GP20/AUXFANIN2 O_KB_DATA (100)
ESPI_IO2/LAD2
1 2 S_LAD2 6 13 2 1 +3V_SIO +12V
ESPI_IO3/LAD3 KBRST# O_KBRST# (59)
O1R202 1 2 8.2KOhm /X 1UF/16V S_LAD3 3 O_KBRST#_R O1R25 300OHM /LPC O1R132 O1R32
I. Add SMBUS Circuit by Project mbs_c0603
(59) CK_24M_SIO ESPI_CLK/PCICLK
1 2 1 2
D

1
/X O1C1 O1R71 1 2 8.2KOhm /X O_12V_IN_H
GND GND 10PF/50V 5.49KOhm 5.49KOhm
J. If use COM Port RI# do Deep S4/S5 wake-up, modify Pin 21 net name to /X mbs_r0603 mbs_r0603
LAN_SIO_WAKE#

2
COM 10G213549113010 10G213549113010
14
CTSA#/GP80 O_COM1_CTS1# (97)
+3V_SIO GND 15
DSRA#/GP81 O_COM1_DSR1# (97)
16 O_12V_IN
K. Delete AUDIO_LED_PWM Signal if don't need O1R3 8.2KOhm
(2E_4E_SEL)RTSA#/GP82
17 O_COM1_RTS1#
O_COM1_RTS1# (97)

O1_RSTCON#_R 1 2
GP83/DTRA#(DDR4_EN)
GP84/SINA
18
19
O_COM1_DTR1#
O_COM1_DTR1#
O_COM1_RXD1
(97)
(97)
F 2 1
1 2
O1R33 1KOhm 1000PF/50V
L. If SIO Breathing LED is reserved, unmount AUDIO_LED_PWM pull high resistor +3VSB ACPI
GP85/SOUTA/SOUTA_P80(ESPI_EN)
20 O_COM1_TXD1
O_COM1_TXD1 (97)
O1C32
GP86/DCDA# O_COM1_DCD1# (97)
49 21 /X
(64) O_RSMRST# RSMRST# GP87/RIA# LAN_SIO_WAKE# (89,97)
O1R267 8.2KOhm O1R14 2 1 1KOhm 29 GND GND
M. AUDIO_LED_PWM use GRN_LED or MLED or YLW_LED /X 1 2
(98,113) PWRBTN#
O1R68 1 2 49.9Ohm O_PWRBTN#_R 28
PSIN#
(58)
(17,19,58)
O_IOPWRBTN#
S_SLP_S4#
O1R10
1 2
300OHM O1_IOPWRBTN#_R 42
31
PSOUT#
SLP_S5# J +5V
O_SLP_S4#_R 10V213402310
N. Other Flash/Breathing LED could use YLW_LED or MLED or GRN_LED, but not +3V_SIO
(99) O_PSON#_O1 PSON#
1 2
same with AUDIO_LED_PWM O_5V_IN O1R34 40.2KOhm
O1R4 1 2 1KOhm O1R12 1 2 33Ohm 40 Fan Control mbs_r0603
(20,65,105,113) O_PWROK PWROK/FDLED1
O_PWROK_R O_PWROK_R 35 62 2 1
(17,19) O_3VSBSW# 3VSBSW#/GP33 CPUFANOUT O_CPUFAN_PWM (103)
34 64 O1C34 1 2
1000PF/50V
O. Add COM Debug Signal by Project, use Pin 33 or 19 (20,101,105) O_DEEP_S5
O1R13 2 1 1KOhm 41
DEEP_S5_0/3VSBSW/PWROK/ATXPGDO SYSFANOUT O_CHAFAN_PWM (104)
O1R35 10KOhm /X
(98,113) O_RSTCON#_P RESETCONI#/GP30/OVT#_1 /SMI#_1/CIRRX
+3VSB_ATX O1R67 1 2 49.9Ohm O_RSTCON#_P_R 22 FANIN
(58) O_RSTCON# RESETCONO#/GP47/FDLED4
O1R11 300OHM O1_RSTCON#_R 32 61 GND GND
P. Add SMI#/BEEP Signal by Project, use GPIO mapping function O1R6 8.2KOhm
(18,20,23,58) S_SLP_S3#
1 2 O_SLP_S3#_R
SLP_S3# CPUFANIN
63
O_CPUFANIN (103) HW Monitor
SYSFANIN O_CHAFANIN1 (104)
PWRBTN# 1 2
O1R7 8.2KOhm
Q. If use Pin 41 as OVT#, should add external RSTCON# De-bounce Circuit O_RSTCON#_P 1 2 33
GP71/SOUTB_P80/CPUFANGPP O_COMDBG_P80 (106)
O1R8 8.2KOhm SMBUS 2
CPUFANGPL/GP03
O_3VSBSW# 1 2 /X 36
R. If use MS as FAN or GPIO, remove pull high resistor ORN404A/ORN404D, 1 2 AUDIO_LED_PWM 37
GP32/SCL/MSCL/AUXFANIN2
GP31/SDA/MSDA/AUXFANOUT2
but keep MS Signal default pull high with other resistor to main power (55,98) O_PLED
O_PLED OR100 O_GP31 TEMP.IN
mbs_r0402 N/A 0Ohm 56
K CPUTIN
CPUD-/AGND
58
57
GND
H_TR (102)

S. If need turn off Stand By Power LED, choose a SIO GPIO connect to RSTOUT
VIN9/SYSTIN O_TR_MB (102)

O_SBPWRLED; if the GPIO default output high, could unmount O1R207 +3VSB
(51) O_X16_RST#
1
33OHM
2 O1RN102A 39
RSTOUT1#/GP75
VIN
7 8 O1RN102D O_X16_RST#_R 38 54
(69,72) O_X1_RST# 33OHM RSTOUT2#/GP76/MLED/GPIOE# CPUVCORE
O1R287 8.2KOhm 5 6 O1RN102C O_X1_RST#_R O_VCORE_IN
(95) AUDIO_LED_PWM 33OHM
1 2 N/A 3 4 O1RN102B 51
T. If use SIO Anti Surge Function, mount O1C32, O1C34 33OHM VIN0
52 O_12V_IN
L PECI
VIN1
O_5V_IN

60 55
(35) O_H_PECI PECI VREF O_VREF_SIO (102)

NCT5582D FAN Header Pin Table for Intel 300 Series ESDO1C3 2 1 1000PF/50V
/X S_PLTRST#
HW MONITOR
+PVDD_SIO +3V_SIO, +3VSB or +1.8VSB by Project
+3V_SIO VCCST_VCCSFR +3V_SIO
SIO FAN FAN IN FAN PWM GPP GPL FAN Header 2 1 DDR4
ESDO1C4 100PF/50V
CPUFAN Pin 61 Pin 62 Pin 33 Pin 2 CPU_FAN /X O_SLP_S4#_R 46 POWER O1L10 0Ohm +1.8VSB

ESDO1C5 2 1 100PF/50V
O_VPP_PG
P_VDDQ_SIO_EN_10
44
43
VPP_PG/CIRRX/GP24/IRRX1
VDDQ_EN/GP56/AUXFANOUT2 3VCC
1
59
B +3VSB_ATX
2 1 /LPC
SYSFAN Pin 63 Pin 64 CHA_FAN/CHA_FAN1 O1L11 0Ohm +3VSB
VPP_EN/GP57/AUXFANIN2 VTT
/X O_SLP_S3#_R O_VPP_EN 10 2 1 /eSPI
PAD_VDD
AUXFAN2 Pin 36 or 43 or 27 Pin 37 or 44 or 26 CHA_FAN2 53 +3V_BAT O1L12 0Ohm
AVSB
23 2 1 /X
3VSB
AUXFAN3 Pin 25 Pin 24 AIO_PUMP GND 47
VBAT

30 GND
PAD_CAP
O_+1.8VA 45 OU1C59 OU1C10
Nuvoton SIO COM Port Strapping Pin pull down

2
VSS

1
OU1C30 OU1C230 0.1UF/16V 0.1UF/16V

FAN Net Name Table with 680 Ohm, pull high with 680 - 1K Ohm

2
0.1UF/16V 4.7UF/6.3V X7R X7R

1
X7R mbs_c0603

2
/X NCT5582D
FAN FAN IN FAN PWM FAN GPP with 3941 FAN GPP with 3949 FAN GPL with 3949
GND GND GND LOW HIGH
CPU_FAN O_CPUFANIN O_CPUFAN_PWM GP_CPUFAN_MODE_SEL GP_CPUFAN_EQM_EN#
GND O1R40 680Ohm N/A
CPU_OPT O_CPUOPTIN 2E 4E 1 2
O_COM1_RTS1#
CHA_FAN1 O_CHAFANIN1 O_CHAFAN_PWM GP_CHAFAN_PWM_DC# GP_CHAFAN_MODE_SEL GP_CHAFAN_EQM_EN#
DDR4 DDR4
CHA_FAN2 O_CHAFANIN2 O_CHAFAN_PWM2 GP_CHAFAN_PWM_DC#2 GP_CHAFAN_MODE_SEL2 GP_CHAFAN_EQM_EN#2 G Dis EN O1R42 1 2 680Ohm
/NODDR4SEQ
+3VSB_ATX
O_COM1_DTR1#
CHA_FAN3 O_CHAFANIN3 O_CHAFAN_PWM3 GP_CHAFAN_PWM_DC#3 GP_CHAFAN_MODE_SEL3 GP_CHAFAN_EQM_EN#3 +3V_SIO +3VSB_ATX +3VSB +3V_BAT
for use or reserve NCT5582D DDR4 Power Sequence
O1R44 O1R45
CHA_FAN4 O_CHAFANIN4 O_CHAFAN_PWM4 GP_CHAFAN_PWM_DC#4 GP_CHAFAN_MODE_SEL4 GP_CHAFAN_EQM_EN#4 LPC eSPI 1 2 1 2
O_VREF_SIO O_COM1_TXD1

1
AIO_PUMP O_AIO_PUMP_FANIN O_AIO_PUMP_PWM O_AIO_PUMP_MODE O1R187 0Ohm OU1C255 OU1C55 OU1C1 OU1C423 OU1C223 OU1C23 OU1C53 OU1C228 OU1C28 OU1C47 OU1C247 680Ohm 1KOhm

2
(17,19) P_+VPPDDR_EN_10
2 1 /DDR4SEQ O_VPP_EN 1UF/16V 0.1UF/16V 0.1UF/16V 10UF/6.3V 1UF/16V 0.1UF/16V 0.1UF/16V 10UF/6.3V 0.1UF/16V 0.1UF/16V 10UF/6.3V /LPC /eSPI
W_PUMP+1 O_PUMP_FANIN O_PUMP_PWM O_PUMP_MODE O1R188 0Ohm mbs_c0603 X7R X7R mbs_c0805 mbs_c0603 X7R X7R mbs_c0805 X7R X7R mbs_c0805

1
(17) +VPPDDR_PGD_10

2
2 1 /DDR4SEQ O_VPP_PG /X X5R /X X5R /X X5R GND
W_PUMP+2 O_PUMP2_FANIN O_PUMP2_PWM O_PUMP2_MODE +3VSB /X /X /X

M.2_FAN O_M2_FANIN O_M2_FAN_PWM GP_M2_FAN_MODE_SEL GP_M2_FAN_EQM_EN# O1R189 8.2KOhm GND GND GND GND GND
(17) P_VDDQ_SIO_EN_10
1 2 /DDR4SEQ

+3VSB_ATX

NCT5582D VIN Table NCT5582D TIN Table O_COM1_DTR1#


O1R43 1 2 1KOhm
/DDR4SEQ

SIO VIN CPUVCORE VIN0 VIN1 VIN9 SIO TIN CPUTIN SYSTIN
BOM use SIO DDR4 Sequence unuse SIO DDR4 Sequence BOM LPC Mode eSPI Mode BOM STANDARD CIRCUIT <Variant Name>

VIN IN VCORE +12V +5V TIN IN CPU MB Use SIO DDR4 Power Sequence, mount O1R187, O1R188,
O1R189, O1R43, unmount O1R42 XUMB Super I/O
Title : NCT5582D_Intel
/DDR4SEQ mount unmount /LPC mount unmount N/A mount
Engineer: SZ Design IP
Unuse SIO DDR4 Power Sequence, unmount O1R187, O1R188,
NCT5582D SMBUS Table
ASUSTEK COMPUTER INC
/NODDR4SEQ unmount mount /eSPI unmount mount /X unmount SZ_SIO_1.0F
O1R189, O1R43, mount O1R42 Size Project Name Rev
Custom
Super I/O Demo Circuit
/X 0.0
SMBUS Master to RGB LED EC
Date: Monday, June 11, 2018 Sheet 96 of 113
SIO SMBUS Pin 36, 37
COM Circuit
COM PORT
A. Choose COM Port Connector/Header Type

B. Choose use RI# to do Deep S4/S5 wake-up or not by Project

C. Modify Part Number of COM Connector/Header by Color

D. Modify O_RI# pill-high power by Project

D +3VSB
+12V -12V +5V

1
BU3C1 BU3C10 BU3C20
RING#

1
BRN101A 0.1UF/16V 0.1UF/16V 0.1UF/16V
8.2KOHM X7R X7R X7R

2
/COM/X /X /X /X

BRN101B
2 to Chipset
3 4
8.2KOHM
/COM/X O_RI# (62)
GND A.2
3
C BQ14
COM Header
BRN101C
5 6 1 B PMBS3904
8.2KOHM
LS_COM1_RI1# /COM/X
/COM/X E 3 4 BCN5B /COM COM
2 150PF/50V
LS_COM1_RXD1 7 8 BCN4D /COM 1 2
150PF/50V
8

LS_COM1_TXD1 1 2 BCN4A /COM LS_COM1_DCD1# 3 4 LS_COM1_RXD1


150PF/50V
1

BRN101D BQ14C1 LS_COM1_RI1# 3 4 BCN4B /COM LS_COM1_TXD1 5 6 LS_COM1_DTR1#


150PF/50V
8.2KOHM 0.1UF/16V LS_COM1_DTR1# 7 8 LS_COM1_DSR1#
/COM/X X7R 7 8 BCN5D /COM LS_COM1_RTS1# 9 LS_COM1_CTS1#
150PF/50V
2

/X LS_COM1_DCD1# 5 6 BCN4C /COM LS_COM1_RI1#


150PF/50V
LS_COM1_CTS1# 1 2 BCN5A /COM HEADER_2X5P_K10
150PF/50V
7

LS_COM1_RTS1# 5 6 BCN5C /COM GND /COM


150PF/50V
LS_COM1_DSR1# 12V602025BA0

GND
modify Part Number by color
GND

for use COM Port RI# to do Deep S4/S5 wake-up function for not use COM Port RI# to do Deep S4/S5 wake-up function
modify SIO RI# Pin net name to LAN_SIO_WAKE#

-12V +12V +5V


B.1
BU3
1 20
VDD VCC
2 19
RA1 RY1 O_COM1_DCD1# (96)
LS_COM1_DCD1# 3 18
RA2 RY2 O_COM1_DSR1# (96)
LS_COM1_DSR1# 4 17
RA3 RY3 O_COM1_RXD1 (96)
LS_COM1_RXD1 5 16
DY1 DA1 O_COM1_RTS1# (96)
LS_COM1_RTS1# 6 15
DY2 DA2 O_COM1_TXD1 (96)
LS_COM1_TXD1 7 14
RA4 RY4 O_COM1_CTS1# (96)
LS_COM1_CTS1# 8 13
DY3 DA3 O_COM1_DTR1# (96)
LS_COM1_DTR1# 9 12
RA5 RY5
LS_COM1_RI1# 10 11
VSS GND

GD75232PWR
/COM
GND
When mount /COM
O1R171 1 2 0Ohm
/NO_LAN1_ERP_WAKE LAN Deep S4/S5 wake-up O1R171 O1Q171 & O1D171 BOM need COM Port no COM Port

O1D171
O1Q171 support unmount mount /COM mount unmount
(89,96) LAN_SIO_WAKE#
2
S
D

3 3 2 O_COM1_RI1#_Q
3

1 H2N7002 not support mount unmount


G

BAT54CW /LAN1_ERP_WAKE
11

/LAN1_ERP_WAKE
+5V
When unmount /COM
<Variant Name>
1

O1Q171C1 LAN Deep S4/S5 wake-up O1R171 O1Q171 & O1D171


0.1UF/16V
X7R
Title : COM
2

/X support unmount unmount


ASUSTEK COMPUTER INC
Engineer: SZ Design IP
GND Size Project Name Rev
not support unmount unmount
A3
Super I/O Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 97 of 113


Panel Circuit
A. Choose PANEL/F_PANEL Signal ESD Solution by Project D.1
B. Choose PANEL/F_PANEL Circuit + Chassis Inturder Circuit by Project
If change to single resistor, use
C. Choose Chassis Inturder Signal connect to SIO or Chipset by Project 75 Ohm(10V213750010)

D. Choose SPEAKER Header Circuit + BUZZER Circuit by Project +5V

E. Choose PLED Circuit by Project ORN203B 3


33OHM
4
ORN203C

+5V_SPKO +5V_SPKO_R 6 5

F. Choose PLED control by SIO or Chipset 33OHM

ORN203A

G. If use Memory Power control PLED, check Memory Power Net Name SPKO
1
33OHM
2
SPKO-_R
ORN203D 7
33OHM
8

H. Modify Part Number of PANEL/F_PANEL/SPEAKER Header by Color 3


C
B 1
ORN201C
OC207 5 6

2
8.2KOHM S_SPKR (58)
0.1UF/16V S_SPKR_R
X7R E OQ202

1
/X 2 PMBS3904 OQ202C1

2
0.1UF/16V ORN201A

A.1
X7R 1 2

1
8.2KOHM
/X

GND GND

OD200

1 6
HDLED+ PLED+ PLED- HDLED- PWRBTN# O_RSTCON#_P PWRBTN#_PANEL O_RSTCON#_PR
2

1
ESDOC203 ESDOC201 ESDOC204 ESDOC205 OC206 OC202
2

0.1UF/16V 0.1UF/16V 0.1UF/16V /X 0.01UF/16V 0.1UF/16V


X7R X7R X7R X7R mbs_c0603 2 5
1

2
/X /X /X mbs_c0603 X7R
/X /X
1

GND GND GND GND GND GND


GND 3 4
HDLED-

for Intel Platform PLACE NEAR PANEL or FPANEL IP4220CZ6


N/A

OR202 1 2 33Ohm
(96,113) PWRBTN#
PWRBTN#_PANEL

OR204 1 2 33Ohm
(96,113) O_RSTCON#_P
O_RSTCON#_PR

(57) HDLED-

B.1
10 Pin F_PANEL + 4 Pin SPEAKER
F_PANEL SPEAKER
1 2 1
HDLED+ 3 4 PLED+ 2 +5V_SPKO
HDLED- 5 6 PLED- 3

E.1
7 8 PWRBTN#_PANEL 4
O_RSTCON#_PR 9 SPKO
+5V HEADER_1X4P
HEADER_2X5P_K10 /SPEAKER_4PIN
12006-00152600 GND
Power LED power source use +5VSB
+5V_FPANEL
1

OR200 12V602025BA0
0Ohm GND
mbs_r0603 +5V
/X
modify Part Number by color
2

5 6 ORN202C
1KOHM
HDLED+ 7 8 ORN202D
1KOHM
OC208
2

0.1UF/16V
X7R +5VSB
1

/X
1 2 ORN202A
1KOHM
GND BOM need SPEAKER no SPEAKER PLED+ 3 4 ORN202B
1KOHM

/SPEAKER_4PIN mount unmount


PLED- G
3 VDDQ

CHASSIS INTRUDER HEADER C


B 1
O_PLED_B
7
ORN201D

8.2KOHM
8

E OQ205 OQ205C1
BOM need BUZZER no BUZZER From

2
2 O_PLED (55,96)
+3V_BAT PMBS3904 0.1UF/16V
X7R
SIO
pull high 2M Ohm to +3V_BAT

1
AT88 on SIO side or Chipset side /BUZZER mount unmount /X
mbs_tpc26b_s4_85 1 O_PLED_E
OR211 /X 3 GND
2

1 2 C ORN201B
O_CASEOPEN# (96) B 1 3 4
From
OR210
+5VSB_ATX 2MOHM 1KOhm O_PLED_R
8.2KOHM S_PLED SB
(55,96)
E
1

/CHASSIS /X OC211 O_CASEOPEN# to SIO OQ203 OQ203C1

2
CHASSIS 3 100PF/50V S_INTRUDER# to Chipset 2 PMBS3904 0.1UF/16V
BOM need CHASSIS no CHASSIS
3

F
D
1

1 /CHASSIS X7R

1
2

OQ204 /X
3 11 /CHASSIS mount unmount GND
4 O_CASEOPEN G H2N7002 GND
S
/CHASSIS
1

OQ204C1 2 GND
2

C
HEADER_1X4P_K2 0.1UF/16V
/CHASSIS mbs_c0603 place near SIO
2

X7R or Chipset
/X
GND GND GND
O_PLED/S_PLED GPIO select:
1. GPIO with blink function, default GPI(no internal pull-down resistor)
2. stand by power plane, 3V tolerance
3. Porting Guide: default keep GPI, enable blink 0.5Hz or 1Hz function when enter S3, <Variant Name>
disable blink function and back to GPI when resume from S3
Title : PANEL
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
Custom
Super I/O Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 98 of 113


EATX Power Circuit
A. Choose EATX Power Circuit by Project

B. If choose EATX 24Pin Circuit, choose EATX Connector with 0 Ear, 1 Ear or 2 Ears by Project

C. If choose EATX 24Pin Circuit, choose +3V_ATX & +3V Circuit by Project

D. If support Intel S0ix, add SC945, SC946 & Off-Page Net O_PSON#_O1 change to ATX_PSON#

E. Modify Part Number of EATX Connector by Color

A.1

EATX 24 Pin
+5VSB_ATX
B.1
+5V +5V -5V +5VSB_ATX
0 Ear
+12V +3V_ATX +3V_ATX -12V

2
EATXR216
25

EATXPWR 20KOhm
1 13 mbs_r0603
+3V1 +3V4
2 14
NP_NC

+3V2 -12V

1
3 15 EATXR16
GND1 GND4
4 16 1 2
+5V1 PSON# O_PSON#_O1 (96)
5 17 ATX_PSON#_R
GND2 GND5
6 18 33Ohm
+5V2 GND6
7 19
GND3 GND7
8 20
PWR0K -5V
9 21
5VSB +5V3
1

10 22 EATXC16
+12V1 +5V4 EATXR16, EATXR216
11 23 1000PF/50V
+12V2 +5V5 place near EATX
12 24
+3V3 GND8
/X 24Pin
2

POWER_CON_24P
P_PWROK_PS

GND 12015-00035400 GND GND


1

EATXC8
1000PF/50V
/X
modify Part Number by color
2

GND

AMD: mount EMI CAP by model/by test,default /X


Intel: mount /Intel CAPs

+5V +12V +5VSB_ATX -12V -5V

ESDATC4 EATXC6 ESDATC10 ESDATC9 ESDATC14 EATXC15 EATXC20


2

0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V


X7R X7R X7R X7R X7R X7R X7R
1

/X/Intel /X N/A /X/Intel /X/Intel /X /X

GND GND GND GND GND

place near EATXPWR

C.1 C.2

for mount or reserve for no +3V OVP


+3V OVP Protect Circuit Protect Circuit

+3V +3V_ATX

ESDATC1 EATXC12
2

0.1UF/16V 0.1UF/16V
X7R X7R
1

/X/Intel /X
<Variant Name>

GND Title : EATX


ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
Custom
Super I/O Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 99 of 113


KBMS Circuit
A. Choose KBMS Power Source by Project
B. If KBMS share power with USB Port, modify Share Power Net Name by Project
C. Choose KBMS Port Connector by Project
D. If choose KBMS Connector, KBMS Signal to-GND Cap choose Single Capacitor or RES Cap by Project
E. If choose KB & USB 2.0 Connector, check USB 2.0 Port D+/D- Signal begin with 0 or 1, then modify
USB 2.0 Port D+/D- Signal Net Name by Project
F. If choose KB & USB 3.0 Connector, modify USB Port TX/RX/D+/D- Signal Net Name by Project
G. If choose KB & USB Connector, modify USB Port Power Net Name by Project
H. If choose KB & USB Connector, modify Connector Part Reference by Project
I. If choose KB & USB Connector, for ITE SIO, ORN404 could /X for cost down
A.2
C.2 Dedicated Power
KBMS
+5VSB_DUAL +5V_ZPS2

+5VSB_DUAL BF4
1 2
OR402 1 2 4.7KOhm mbs_r0603
OR403 1 2 4.7KOhm mbs_r0603
1.1A/8V

1
OR404 1 2 4.7KOhm mbs_r0603 ESDOC405
OR405 1 2 4.7KOhm mbs_r0603 mbs_polyswitch_2p_0805_h31 0.1UF/16V
X7R

2
N/A

OR406 1 2 33Ohm
O_KB_DATA (96)
O_KB_DATA_R mbs_r0603 GND
OR407 1 2 33Ohm
O_KB_CLK (96)
O_KB_CLK_R mbs_r0603
OR408 1 2 33Ohm
O_MS_DATA (96)
O_MS_DATA_R mbs_r0603
OR409 1 2 33Ohm
O_MS_CLK (96)
O_MS_CLK_R mbs_r0603

+5V_ZPS2

KBMS
16 SIDE_G16

4 VCC1 NC2 6
2 NC1
17 SIDE_G17

1 KDATA
O_KB_DATA_R 3 GND1 KCLK 5
15 SIDE_G15
O_KB_CLK_R

PS2 MOUSE
14 SIDE_G14

10 VCC2 NC4 12
8 NC3

7 MDATA
O_MS_DATA_R 9 GND2 MCLK 11
13 SIDE_G13 O_MS_CLK_R

MINI_DIN_6PX2
12V017121002
GND

OD400

1 6
O_KB_DATA_R O_MS_DATA_R

2 5

GND

3 4
O_KB_CLK_R O_MS_CLK_R

IP4220CZ6
N/A

D.1
RES Capacitor
OCN403A 1 2
150PF/50V
O_KB_DATA_R
OCN403B 3 4
150PF/50V
O_KB_CLK_R
OCN403C 5 6
150PF/50V
O_MS_DATA_R
OCN403D 7 8
150PF/50V
O_MS_CLK_R

GND

D.2 for SI
Single Capacitor

<Variant Name>

Title : KBMS
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A2
Super I/O Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 100 of 113


ERP Circuit (20,96,105) O_DEEP_S5
BOM no SIO ERP & SIO DSW SIO ERP SIO DSW

A. Choose ERP Circuit by Project /NO_EUP mount unmount unmount

1
ESDOC762
0.1UF/16V
X7R /EUP unmount mount mount
B. OR764, OR765 choose Short-Pin, Resistor or delete by Project

2
/X

/NO_SIODSW mount mount unmount


GND
Near SIO for ESD
/SIODSW unmount unmount mount

A.2 B.2

+3VSB_ATX OQ760 +3VSB


Resistor
EMB45P03P
/EUP +3VSB_ATX +3VSB
D
S

OR764 0Ohm /NO_EUP


3

1 2 mbs_r0805
G
1
2

OR765 0Ohm /NO_EUP


1

OR763 OC761 OR760 1 2 mbs_r0805


2.7KOHM 0.1UF/16V 33Ohm
/EUP mbs_c0603 /EUP
2

X7R
1

/EUP

OR769 OR762 OC760


1 2 1 2 2 1
O_DEEP_S5 O_DEEP_S5_CR O_DEEP_S5_C
2.7KOhm 2.7KOhm 0.1UF/16V
mbs_r0603 mbs_r0603 X7R
/EUP /EUP /EUP
10005-00487000 10005-00487000
-12V

OR761 OQ761
S
D

2 1 O_DEEP_S5_12V 3 2
3

1KOhm H2N7002 <Variant Name>


G

/EUP /EUP
11

Title : ERP
Normal ERP Circuit GND
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
Custom
Super I/O Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 101 of 113


Stand By LED & HW Monitor Circuit
HW Monitor
A. Choose Stand By LED Circuit by Project
(96) O_VREF_SIO
B. Keep or delete TR_PCH Circuit by Project

2
OR217 OR218
10KOhm 10KOhm
C. Keep or delete T_SENSOR Circuit by Project N/A N/A

1
D. Keep or delete VCORE Power Controller TEMP Detect Circuit by Project (96) H_TR O_TR_MB (96)

2
E. Keep or delete GFX Power Controller TEMP Detect Circuit by Project

1
HTC1 HTR1 OC217 OTR1 OTC1
0.1UF/16V 10KOHM 1UF/16V 10KOHM 0.1UF/16V
X7R N/A mbs_c0603 N/A X7R
F. Modify Part Number of T_SENSOR Header by Color

2
N/A X7R N/A

1
/X

Place Place Place Place Place


near in CPU near follow near
BOM no Stand By LED need Stand By LED without GPIO control need Stand By LED with GPIO control GND HTR1 Socket SIO Rule OTR1 GND

/StandByLED unmount mount mount

/StandByLED_without_GPIO unmount mount unmount If no CPU thermistor, unmount components HTR1, HTC1, OR217
/StandByLED_with_GPIO unmount unmount mount If no MB thermistor, unmount components OTR1, OTC1, OR218

BOM need TR_PCH no TR_PCH BOM need T_SENSOR no T_SENSOR


A.1
/TR_PCH mount unmount /T_SENSOR mount unmount
+5VSB_ATX

SB_PWR
LED

2
OR203
4.7KOhm
mbs_r0603
/StandByLED

1
SMD
0805 SB_LED+

Green SB_PWR
GREEN

/StandByLED

GND

<Variant Name>

Title : SBLED_HWM
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
Custom
Super I/O Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 102 of 113


CHA_FAN PWM Mode & DC Mode QFAN Circuit use Single Resistor
A. Choose QFAN Mode Type by Project C. If only one CHA_FAN, rename CHA_FAN1 to CHA_FAN
B. Remove the CHA_FAN which don't need D. Modify Part Number of CHA FAN Header by Color

A.1
4 Pin PWM Mode & DC Mode BJT Cap PWM Mode & DC Mode Power Solution
Chassis FAN 1NCT3941S-A Power
Chassis FAN 1 +3V +5V
OR312
+3V

1 2 GP_CHAFAN_PWM_DC# GPIO select:


GP_CHAFAN_PWM_DC# +12V CHAFANPWR +12V 1. could be GPI & GPO both, default GPI (no
internal pull-down/pull-high resistor must)

2
2.7KOHM
only one CHAFAN call OR315 O_CHAFAN_EN 2. stand by power plane, 3V tolerance
3. GPI to switch to PWM Mode
2

2
CHA_FAN, 8.2KOhm OU310R1 0Ohm
else call CHA_FAN1 CHAFANPWR OR311 OR313 OR314 O_CHAFAN_PWM OR318 mbs_r0805 1 2 /NO-3941S OU310 4. GPO low to switch to DC Mode
2.7KOHM 2.7KOhm 8.2KOhm 8.2KOhm 9VIA 18
9
10
11
12
13
14
15
16
17
GND10
GND11
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

1
mbs_r0603 /X O_CHAFAN_PWM_B mbs_r0603 1 8
VOUT NC3
/3941S 2 7

C
VIN NC2
1

1
O_CHAFAN_PWM_B O_CHAFAN_PWM_Q OU310R4 3 6
ENABLE(FON#) GND1
3

3
OQ310 1 2 4 5 OQ311
CHA_FAN

B 1
(96,104) O_CHAFAN_PWM VSET NC1 D

1
PMBS3904 OQ310C3 OQ310C1 OQ310C2 O_CHAFAN_VSET1 H2N7002
0.1UF/16V 0.1UF/16V 0.1UF/16V 100KOhm NCT3941S /3941S
NP_NC

2
5 X7R X7R X7R 11
4 O_CHAFAN_PWM (96,104) GP_CHAFAN_PWM_DC# (58)
PWM

1
4 O_CHAFAN_PWM_Q C /X /X /X OR319 OU310C1 OU310C4 OU310C2 06053-00180000 GND G
3

E
2
SENSE
3 S

1
3 2.7KOHM 10UF/16V 1UF/16V 1UF/16V 2 OQ311C1
+12V
2 /3941S

2
2 /3941S mbs_c0805 mbs_c0603 mbs_c0603 0.1UF/16V
GND
1 use NCT3941S-A

2
1

1 OC310 OC311 X5R X7R X7R X7R

2
WAFER_HD_4P 0.1UF/16V 0.1UF/16V GND /3941S /3941S /X /X
X7R X7R OR310
2

12008-00014000 GND /X /ITE SIO 1 2 GND GND GND GND GND GND
O_CHAFANIN1 (96)
O_CHAFANIN1_R
GND GND 2.7KOHM

<Variant Name>

Title : CHA_FAN
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
Custom
Super I/O Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 104 of 113


USBPWR_SW# Circuit for Chipset GPIO
USBPWR_SW# GPIO select:
1. could be GPI & GPO both, default GPI (no internal pull-down/pull-high resistor)
1. Choose USBPWR_SW# Circuit by Project 2. stand by power plane, 3V tolerance

2. Check PWROK Signal Net Name by Platform

+5VSB_DUAL default no power, reserve USB Inrush Circuit


for AMD Project +3VSB

P_5V_USB_Q1_10 (21)

2
UR731
1KOhm 3

3
D
/X UQ730
H2N7002
1

11 N/A
(20,65,96,113) O_PWROK
G
S

1
UQ730C1 2
for Intel Project

2
0.1UF/16V
X7R

2
/X

GND GND

+3VSB
2

UR733
8.2KOhm UQ731A

6
N/A 2N7002KDW

3
UQ731B N/A
1

5 2N7002KDW 2
(62) USBPWR_SW# O_DEEP_S5 (20,96,101)
N/A
4

1
2

1
UR735 UQ731C5 UQ731C2
1KOhm 0.1UF/16V 0.1UF/16V
/X X7R X7R
2

2
/X /X
1

GND GND GND GND GND

USBPWR_SW# GPIO porting:


1. GPI to force +5VSB_DUAL switch to +5V
2. GPO low to let +5VSB_DUAL switch to +5VSB_ATX under S3/S4/S5
for Chipset GPIO

<Variant Name>

Title : USB Power Control

ASUSTEK COMPUTER INC


Engineer: SZ Design IP
Size Project Name Rev
Custom 0.0

Date: Monday, June 11, 2018 Sheet 105 of 113


Debug Header Circuit
A. Choose Debug Header by Project

B. If choose COM Debug Header, take care Debug Signal Net Name is different by Project

C. If choose LPC Debug Header, modify Clock Signal Net Name by Project

A.2
Delete it for EMS

COM Debug Header


+3V

COM_DEBUG
1 2
(96) O_COMDBG_P80
4
5 6

B HEADER_2x3P_K3
mbs_hd_2x3p_100_k3_lf3

/COM_DEBUG
GND

COM Debug Signal from Nuvoton 128 Pin SIO SOUTB_P80 or SOUTC_P80 Signal

BOM need COM Debug Header no COM Debug Header BOM need LPC Debug Header no LPC Debug Header
<Variant Name>

/COM_DEBUG mount unmount /LPC_DEBUG mount unmount Title : Debug Header


ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
B
Super I/O Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 106 of 113


m-ATX Screw Hole Circuit
A. Connect H3 to GND or A_GND by Project

MB SCREW FOOTPRINT
Delete it for EMS m-ATX Screw Hole
MB_HOLE_160_T_LF3
H1 H4
1 9 1 9
GND1 NC GND1 NC
2 8 2 8
GND2 GND8 GND2 GND8
3 7 3 7
GND3 GND7 GND3 GND7
4 6 4 6
GND4 GND6 GND4 GND6
5 5
GND5 GND5

C280D160N C280D160N
GND s_hole_c280d160n_t_u_v8 GND GND s_hole_c280d160n_t_u_v8 GND MB_HOLE_160_T_U_LF3
/X /X
origin-xy:(1300.00, 9350.00) origin-xy:(6500.00, 9350.00)

MB_HOLE_160_T_R_LF3

MB_HOLE_160_T_UR_LF3

< 9.3 inch

H2 H5
1 9 1 9
GND1 NC GND1 NC
2 8 2 8
GND2 GND8 GND2 GND8
3 7 3 7
GND3 GND7 GND3 GND7
4 6 4 6
GND4 GND6 GND4 GND6
5 5
GND5 GND5

C280D160N C280D160N
GND s_hole_c280d160n_t_v8 GND GND s_hole_c280d160n_t_v8 GND
/X /X
origin-xy:(400.00, 3150.00) origin-xy:(6500.00, 3150.00)

H3 H20
1 9 1 9
GND1 NC GND1 NC
2 8 2 8
GND2 GND8 GND2 GND8
3 7 3 7
GND3 GND7 GND3 GND7
4 6 4 6
GND4 GND6 GND4 GND6
5 5
GND5

C280D160N
A GND5

C280D160N
s_hole_c280d160n_t_v8 A_GND GND s_hole_c280d160n_t_v8 GND
/X /X
origin-xy:(400.00, 1350.00) origin-xy:(6500.00, 1350.00)

(X,Y)=(0,0)

< 9.6 inch H22


1
1

C400_NOPAD
s_c400_nopad
/X
place on bottom side <Variant Name>
origin-xy:(6500.00, 2950.00)
Title : Screw Hole
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A3
Other Demo Circuit
1.0D

Date: Monday, June 11, 2018 Sheet 107 of 113


LPC TPM Circuit
A. Del LPC TPM Header if don't need

B. Modify LPC TPM Header Clock Net Name by Project

C. Modify Part Number of LPC TPM Header by Color

D. Del Onboard LPC TPM IC if don't need

E. Modify Onboard LPC TPM IC Clock Net Name by Project

F. Modify Onboard LPC TPM IC's Part Number by Project

G. Modify Optional of TMR13, TMR14, TMR15 by Onboard LPC TPM IC

H. Modify +3V to +3V_S0IX if support Intel S0ix

I. Choose TPM_CLKRUN# Circuit by Project

I.2
for no Intel S0ix

/X TMT1 1
TPM_CLKRUN#

BOM LPC TPM Header Onboard LPC TPM

N/A mount mount


A
/X unmount unmount
2x7 Pin LPC TPM Header H
+3V /LPC TPM HEADER mount unmount
+3VSB
TMC1 0.1UF/16V
X7R 1 2 /X /LPC TPM IC unmount mount
TPM
(59,96) S_LAD[3..0]
1
3
2
4
GND B
S_LAD0
S_LAD1 5 6
CK_24M_TPM (59)
S_LAD2 7 8
S_LAD3 9
(59,96) S_LFRAME#
11 12
(59,96) S_SERIRQ S_PLTRST# (55,87,96,113)
13 14
TPM_CLKRUN#
HEADER_2X7P_K10 TMC4 TMC3
2

+3VSB /LPC TPM HEADER 0.01UF/16V 10PF/50V


X7R /X
1

12006-00321200 GND /X
1

TMC2
0.1UF/16V
X7R
modify Part Number by color
2

/X
GND
GND <Variant Name>

Title : LPC TPM


ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A3
Other Demo Circuit
1.0D

Date: Monday, June 11, 2018 Sheet 108 of 113


Fiducial Mask Delete it for EMS
(光學點)

圓形光學點 LayoutRD會依空間大小,
擺放大顆或小顆光學點;
所以兩種光學點都需畫入線路中,
最後再做刪除.

大顆光學點

小顆光學點

Delete it for EMS

十字光學點 LayoutRD會依空間大小,
擺放大顆或小顆光學點;
所以兩種光學點都需畫入線路中,
最後再做刪除.

大顆光學點

小顆光學點

INDEX31 INDEX32 INDEX35 INDEX36 INDEX37 INDEX38


1 1 1 1 1 1
1 1 1 1 1 1

INDEX_PLUS INDEX_PLUS INDEX_PLUS INDEX_PLUS INDEX_PLUS INDEX_PLUS


/X/FIDUCIAL MASK /X/FIDUCIAL MASK /X/FIDUCIAL MASK /X/FIDUCIAL MASK /X/FIDUCIAL MASK /X/FIDUCIAL MASK

<Variant Name>

Title : Fiducial Mask


ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A3
Silkscreen Demo Circuit
1.0C

Date: Monday, June 11, 2018 Sheet 111 of 113


Intel Platform

You can only choose


8 pcs PCB Impedance point for your project

Priority 0 (must choose if use ASM1142/2142/3142)

ASMedia USB 3.1 TX/RX

80 Ohm +/- 10%

Priority 1, must choose if MB have these functions

1 2 3 4
LAN PCIE GEN2/3 DDR3 USB2.0
DATA&CTRL
IP1 IP3 IP5 IP7
1 1 1 1
1 1 1 1

IMPEDANCE_CONTROL IMPEDANCE_CONTROL IMPEDANCE_CONTROL IMPEDANCE_CONTROL


/X /X /X /X

IP2 IP4 IP8


1 1 1
1 1 1

IMPEDANCE_CONTROL IMPEDANCE_CONTROL IMPEDANCE_CONTROL


/X /X /X

*** You can only choose 1 function to place point per block ***

Priority 2, can choose if MB have Priority 3, can choose if MB have


these functions (by project) these functions (by project)

1 2 1 2
DP/DVI/HDMI USB3.0 DMI DDR3 CLK

IP9 IP11 IP13 IP15


1 1 1 1
1 1 1 1

IMPEDANCE_CONTROL IMPEDANCE_CONTROL IMPEDANCE_CONTROL IMPEDANCE_CONTROL


/X /X /X /X

IP10 IP12 IP14 IP16


1 1 1 1
1 1 1 1

IMPEDANCE_CONTROL IMPEDANCE_CONTROL IMPEDANCE_CONTROL IMPEDANCE_CONTROL


/X /X /X /X
<Variant Name>

Title : PCB Impedance Point

ASUSTEK COMPUTER INC


Engineer: SZ Design IP

Delete it for EMS Size

A3

Date:
Project Name

Monday, June 11, 2018


Silkscreen Demo Circuit
Sheet 112 of 113
Rev

1.0C
+5VSB_DUAL
1

1
EC201 EC202 EC203 EC204 EC205 EC206 EC207 EC208 EC209 EC210
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
/X/EMI /X/EMI /X/EMI /X/EMI /X/EMI /X/EMI /X/EMI /X/EMI /X/EMI /X/EMI
2

2
GND

+5VSB +5V
(96,99) O_PSON#_O1
O_PSON#_O1
Vcore 200mil Vcore 200mil O_RSTCON#_P

(96,98) PWRBTN#

1
EC501 PWRBTN#
1

1
EC801 EC802 EC301 EC302 EC303 0.1UF/16V
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V /X/EMI
(96,98) O_RSTCON#_P

2
/X N/A /X/EMI /X/EMI /X/EMI O_RSTCON#_P
2

2
(55,87,96,108) S_PLTRST#
GND S_PLTRST#

(20,65,96,105) O_PWROK
O_PWROK
GND GND

PWRBTN# S_PLTRST# O_PWROK


+12V

1
EC502 EC503 EC504
Vcore 200mil 0.1UF/16V 0.1UF/16V 0.1UF/16V
/X/EMI /X/EMI /X/EMI

2
1

EC604 EC605 EC606


0.1UF/16V 0.1UF/16V 0.1UF/16V
/X/EMI /X/EMI /X GND GND GND
2

GND

+3V

Vcore 200mil
1

EC401 EC402 EC403 EC404 EC405


0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V
/X/EMI /X/EMI /X/EMI /X/EMI /X/EMI
2

GND

Title
<Title>

Size Document Number Rev


A4 <Doc> <RevCode>

Date: Monday, June 11, 2018 Sheet 113 of


113
Selling Point
1. Selling Point 新增流程及窗口人員

SPM 提出申請 CIS Team 建立 Symbol CE Team 申請建立 Part


http://prm.asus.com.tw Navy Yao(姚鈞_華碩蘇州) Laura Zhang(張靜思_華碩蘇州)
類別: CIS課需求申請

2. 如何抓取 Selling Point Part, 如下圖

3. Example

<Variant Name>

Title : Selling Point


ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A3
Silkscreen Demo Circuit
1.0C

Date: Monday, June 11, 2018 Sheet 110 of 113


ASUS PCB Logo Circuit

A. Choose ASUS Logo by Project C. Keep or remove NEED_COMP_SILK by Project

B. Choose KCC Logo by Project

LOGO2 LOGO7
1 1
FCC PCB MADE IN CHINA
A FCC PCB_MADE_IN_CHINA
/X /X

LOGO3 LOGO9
1 1
RCM CAN ICES-3(B)/NMB-3(B)
RCM CAN_ICES_3B_NMB_3B
/X /X

LOGO1 LOGO8
1 1
EMI_D33005_H VCCI
EMI_D33005_H
/X VCCI
/X
LOGO5
1
WEEE_LOGO
WEEE_LOGO
/X

LOGO6
1
CE
CE
/X

LOGO11
1
SFIS LABEL

SFIS_LABEL
/X

B 10mm without Wifi


LOGO10
KCC Logo without Wifi
1
KC R-REM-MSQ-XXXXXXXXXXXXXX

KC_R_REM_LOGO
/X

KCC Logo with Wifi

<Variant Name>

Title : PCB Logo


ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
A3
Silkscreen Demo Circuit
1.0C

Date: Monday, June 11, 2018 Sheet 109 of 113


Note:
1.Symbol value is not dispaly in layout
2.Symbol part reference change by project,
modify layout delete it,that put M.2 name to this place

Title
<Title>

Size Document Number Rev


A3 <Doc> <RevCode>

Date: Monday, June 11, 2018 Sheet 77 of 113


<Variant Name>

TitleSPTH
: EUP Control

ASUSTeK COMPUTER INC


Engineer: Morse_Peng
Size Project Name Rev
A3 SkyLake VC R1.00

Date: Monday, June 11, 2018 Sheet 66 of 113


CHA_FAN Circuit use Single Resistor
A. Choose QFAN Mode Type by Project C. Remove CPU_OPT if don't need
E. Modify Part Number of CPU_FAN & CPU_OPT by Color
B. If choose PWM Mode, choose with FAN RGB Header or not by Project D. Choose O_PWROK or O_PWROK_SB by Platform for FAN Expert 3 and above Mode
A.1
PWM Mode B.1
CPU FAN
+3V +5V +3V
OR302
1 2

2.7KOHM

2
+12V OR301 OR303 OR304
PWM Mode 2.7KOHM 2.7KOhm 8.2KOhm O_CPUFAN_PWM
mbs_r0603 /X
O_CPUFAN_PWM_B
1

1
O_CPUFAN_PWM_B
OQ300 O_CPUFAN_PWM_Q

B 1
CPU_FAN PMBS3904

1
OQ300C3 OQ300C1 OQ300C2
NP_NC
5 0.1UF/16V 0.1UF/16V 0.1UF/16V
4 O_CPUFAN_PWM (96)
PWM
4 O_CPUFAN_PWM_Q X7R X7R X7R

C
3

E
2
SENSE
3

2
+12V 3 /X /X /X
2
GND 2
1
1

1 OC300 OC301
WAFER_HD_4P 0.1UF/16V 0.1UF/16V
X7R X7R OR300 GND
2

12008-00014000 GND /X /ITE SIO 1 2


O_CPUFANIN (96)
O_CPUFANIN_R
BLACK:12008-00014000 GND GND 2.7KOHM

<Variant Name>

Title : CPU_FAN
ASUSTEK COMPUTER INC
Engineer: SZ Design IP
Size Project Name Rev
Custom
Super I/O Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 103 of 113


Title
<Title>

Size Document Number Rev


D <Doc> <RevCode>

Date: Monday, June 11, 2018 Sheet 73 of 113


<Variant Name>

Title : DVI REDUCED LEV-SHIFT

ASUSTek COMPUTER INC.


Engineer: Morse_Peng
Size Project Name Rev
R1.00
A3 SkyLake VC
Date: Monday, June 11, 2018 Sheet 50 of 113
<Variant Name>

Title : DVI REDUCED LEV-SHIFT

ASUSTek COMPUTER INC.


Engineer: Morse_Peng
Size Project Name Rev
R1.00
A2 SkyLake VC
Date: Monday, June 11, 2018 Sheet 52 of 113
<Variant Name>

Title : PS_ON#
ASUSTEK COMPUTER INC
Engineer: Jay_Tong
Size Project Name Rev
A3
Chipset Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 70 of 113


<Variant Name>

Title : DVI REDUCED LEV-SHIFT

ASUSTek COMPUTER INC.


Engineer: Morse_Peng
Size Project Name Rev
R1.00
A2 SkyLake VC
Date: Monday, June 11, 2018 Sheet 53 of 113
<Variant Name>

Title : NA
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
A KabyLake DEMO R1.00

Date: Monday, June 11, 2018 Sheet 27 of 113


<Variant Name>

Title : NA
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
A KabyLake DEMO R1.00

Date: Monday, June 11, 2018 Sheet 28 of 113


<Variant Name>

Title : NA
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
A KabyLake DEMO R1.00

Date: Monday, June 11, 2018 Sheet 29 of 113


Title
<Title>

Size Document Number Rev


A <Doc> <RevCode>

Date: Monday, June 11, 2018 Sheet 8 of 113


Title
<Title>

Size Document Number Rev


A <Doc> <RevCode>

Date: Monday, June 11, 2018 Sheet 9 of 113


<Variant Name>

Title : USB3 Port


ASUSTEK COMPUTER INC
Engineer: Kell_Huang
Size Project Name Rev
A2
Chipset USB Demo Circuit
0.0

Date: Monday, June 11, 2018 Sheet 86 of 113


<Variant Name>

Title : NA
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
A KabyLake DEMO R1.00

Date: Monday, June 11, 2018 Sheet 14 of 113


<Variant Name>

Title : +3V_S0IX/+5V_S0IX/+12V_S0IX
ASUSTEK COMPUTER INC
Engineer: Mandy_Cao
Size Project Name Rev
A2 coffeelake demo 0.0

Date: Monday, June 11, 2018 Sheet 22 of 113


<Variant Name>

Title : NA
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
A KabyLake DEMO R1.00

Date: Monday, June 11, 2018 Sheet 15 of 113


Title : +5VSB_DUAL/+1.1VSB
ASUSTek Computer Inc.
Engineer:
Size Project Name Rev
A2 FM2 PLUS 1.00

Date: Monday, June 11, 2018 Sheet 24 of 113


<Variant Name>

Title : NA
ASUSTek COMPUTER INC.
Engineer: Mandy_cao
Size Project Name Rev
A KabyLake DEMO R1.00

Date: Monday, June 11, 2018 Sheet 26 of 113


<Variant Name>

Title : DVI REDUCED LEV-SHIFT

ASUSTek COMPUTER INC.


Engineer: Morse_Peng
Size Project Name Rev
R1.00
A1 SkyLake VC
Date: Monday, June 11, 2018 Sheet 68 of 113
<Variant Name>

Title :
ASUSTek COMPUTER INC.
Engineer:
Size Project Name Rev
A3 R1.00

Date: Monday, June 11, 2018 Sheet 4 of 113


Title
<Title>

Size Document Number Rev


A <Doc> <RevCode>

Date: Monday, June 11, 2018 Sheet 11 of 113


Title
<Title>

Size Document Number Rev


D <Doc> <RevCode>

Date: Monday, June 11, 2018 Sheet 75 of 113


Title
<Title>

Size Document Number Rev


A2 <Doc> <RevCode>

Date: Monday, June 11, 2018 Sheet 76 of 113

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