Tms 320 F 2803525

TMS320F28030, TMS320F28030-Q1, TMS320F28031, TMS320F28031-Q1, TMS320F28032
TMS320F28032-Q1, TMS320F28033, TMS320F28033-Q1, TMS320F28034, TMS320F28034-Q1

TMS320F28035, TMS320F28035-Q1
SPRS584Q – APRIL 2009 – REVISED JANUARY 2024
TMS320F2803x Real-Time Microcontrollers

• On-chip memory
1 Features
– Flash, SARAM, OTP, Boot ROM available
• High-efficiency 32-bit CPU (TMS320C28x) • Code-security module
– 60MHz (16.67ns cycle time) • 128-bit security key and lock
– 16 × 16 and 32 × 32 MAC operations – Protects secure memory blocks
– 16 × 16 dual MAC – Prevents firmware reverse engineering
– Harvard bus architecture • Serial port peripherals
– Atomic operations – One Serial Communications Interface (SCI)
– Fast interrupt response and processing Universal Asynchronous Receiver/Transmitter
– Unified memory programming model (UART) module
– Code-efficient (in C/C++ and Assembly) – Two Serial Peripheral Interface (SPI) modules
• Programmable Control Law Accelerator (CLA) – One Inter-Integrated-Circuit (I2C) module
– 32-bit floating-point math accelerator – One Local Interconnect Network (LIN) module
– Executes code independently of the main CPU – One Enhanced Controller Area Network
• Endianness: Little endian (eCAN) module
• JTAG boundary scan support • Enhanced control peripherals
– IEEE Standard 1149.1-1990 Standard Test – ePWM
Access Port and Boundary Scan Architecture – High-Resolution PWM (HRPWM)
• Low cost for both device and system: – Enhanced Capture (eCAP) module
– Single 3.3V supply – High-Resolution Input Capture (HRCAP)
– No power sequencing requirement module
– Integrated power-on reset and brown-out reset – Enhanced Quadrature Encoder Pulse (eQEP)
– Low power module
– No analog support pins – Analog-to-Digital Converter (ADC)
• Clocking: – On-chip temperature sensor
– Two internal zero-pin oscillators – Comparator
– On-chip crystal oscillator and external clock • Advanced emulation features
input – Analysis and breakpoint functions
– Watchdog timer module – Real-time debug through hardware
– Missing clock detection circuitry • Package options
• Up to 45 individually programmable, multiplexed – 56-Pin RSH Very Thin Quad Flatpack (No lead)
GPIO pins with input filtering (VQFN)
• Peripheral Interrupt Expansion (PIE) block that – 64-Pin PAG Thin Quad Flatpack (TQFP)
supports all peripheral interrupts – 80-Pin PN Low-Profile Quad Flatpack (LQFP)
• Three 32-bit CPU timers • Temperature options
• Independent 16-bit timer in each Enhanced Pulse – T: –40°C to 105°C
Width Modulator (ePWM) – S: –40°C to 125°C
– Q: –40°C to 125°C
(AEC Q100 qualification for automotive
applications)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F28035, TMS320F28035-Q1
SPRS584Q – APRIL 2009 – REVISED JANUARY 2024 www.ti.com
• Energy storage power conversion system (PCS)

2 Applications • Micro inverter
• Air conditioner outdoor unit • Solar power optimizer
• Door operator drive control • String inverter
• DC/DC converter • AC drive control module
• Inverter & motor control • Linear motor segment controller
• On-board (OBC) & wireless charger • Servo drive power stage module
• Automated sorting equipment • AC-input BLDC motor drive
• Textile machine • DC-input BLDC motor drive
• Welding machine • Industrial AC-DC
• AC charging (pile) station • Three phase UPS
• DC charging (pile) station • Merchant network & server PSU
• EV charging station power module • Merchant telecom rectifiers
• Wireless vehicle charging module
3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes
the Premium performance MCUs and the Entry performance MCUs.
The F2803x family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA)
coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with
previous C28x-based code, and also provides a high level of analog integration.
An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM
to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have
been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3V fixed
full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for
low overhead and latency.
To learn more about the C2000 MCUs, visit the C2000™ real-time control MCUs page.
2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: TMS320F28030 TMS320F28030-Q1 TMS320F28031 TMS320F28031-Q1 TMS320F28032 TMS320F28032-Q1

TMS320F28033 TMS320F28033-Q1 TMS320F28034 TMS320F28034-Q1 TMS320F28035 TMS320F28035-Q1
TMS320F28035, TMS320F28035-Q1
www.ti.com SPRS584Q – APRIL 2009 – REVISED JANUARY 2024
Device Information
PART NUMBER(1) PACKAGE BODY SIZE
TMS320F28035PN LQFP (80) 12.0mm × 12.0mm
TMS320F28034PN LQFP (80) 12.0mm × 12.0mm
TMS320F28033PN LQFP (80) 12.0mm × 12.0mm
TMS320F28032PN LQFP (80) 12.0mm × 12.0mm
TMS320F28031PN LQFP (80) 12.0mm × 12.0mm
TMS320F28030PN LQFP (80) 12.0mm × 12.0mm
TMS320F28035PAG TQFP (64) 10.0mm × 10.0mm
TMS320F28035RSH VQFN (56) 7.0mm × 7.0mm
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

TMS320F28035, TMS320F28035-Q1
3.1 Functional Block Diagram

The Functional Block Diagram shows the functional block diagram for the device.
M0
Memory Bus
SARAM 1K × 16 OTP 1K × 16
(0-wait) Secure
M1 SARAM
SARAM 1K × 16 4K/6K/8K × 16
(CLA Only on
(0-wait)
28033 and 28035)
(0-wait)
Secure Code FLASH
Security 16K/32K/64K × 16
Module Secure
Boot-ROM
8K × 16
(0-wait)
OTP/Flash
PSWD Wrapper
Memory Bus
CLA Bus
CLA
TRST
TCK
COMP1OUT
TDI
32-Bit Peripheral Bus
GPIO COMP2OUT C28x

TMS
(CLA-Accessible)
MUX COMP3OUT 32-Bit CPU

TDO GPIO
Mux
COMP1A
COMP
COMP1B
COMP2A
COMP2B PIE 3 External Interrupts
COMP3A
COMP3B
OSC1, XCLKIN
CPU Timer 0
OSC2, X1
AIO Ext, X2
MUX CPU Timer 1 LPM Wakeup
PLL,
LPM, XRS
CPU Timer 2 WD
ADC
A7:0
Memory Bus
POR/
VREG
B7:0 BOR
16-Bit Peripheral Bus 32-Bit Peripheral Bus 32-Bit Peripheral Bus

(CLA-Accessible)
ePWM eCAN
SCI SPI I2C
LIN eCAP eQEP (32-mail HRCAP
(4L FIFO) (4L FIFO) (4L FIFO)
HRPWM box)
EPWMSYNCO
EPWMSYNCI
SPISIMO x
SPISOMIx
EPW MxA
EPW MxB
SC IT XD x
SCIR XDx
SPIC LK x
C AN R Xx
EQ EPxA
EQ EPxB
SPISTEx
EQEPxS
CA N TXx
HRCAPx
L IN A RX
LINA T X
EQE PxI
ECA Px
SDA x
SC L x
TZx
From
COMP1OUT,
COMP2OUT,
COMP3OUT
GPIO MUX
A. Not all peripheral pins are available at the same time due to multiplexing.
Figure 3-1. Functional Block Diagram

TMS320F28035, TMS320F28035-Q1
Table of Contents
1 Features............................................................................1 7 Detailed Description......................................................40
2 Applications..................................................................... 2 7.1 Overview................................................................... 40
3 Description.......................................................................2 7.2 Memory Maps........................................................... 48
3.1 Functional Block Diagram........................................... 4 7.3 Register Maps...........................................................55
4 Device Comparison......................................................... 6 7.4 Device Emulation Registers......................................57
4.1 Related Products........................................................ 8 7.5 VREG/BOR/POR...................................................... 58
5 Pin Configuration and Functions...................................9 7.6 System Control......................................................... 60
5.1 Pin Diagrams.............................................................. 9 7.7 Low-power Modes Block...........................................68
5.2 Signal Descriptions................................................... 12 7.8 Interrupts...................................................................69
6 Specifications................................................................ 20 7.9 Peripherals................................................................74
6.1 Absolute Maximum Ratings...................................... 20 8 Applications, Implementation, and Layout............... 141
6.2 ESD Ratings – Automotive....................................... 20 8.1 TI Reference Design............................................... 141
6.3 ESD Ratings – Commercial...................................... 21 9 Device and Documentation Support..........................142
6.4 Recommended Operating Conditions.......................21 9.1 Device and Development Support Tool
6.5 Power Consumption Summary................................. 22 Nomenclature............................................................ 142
6.6 Electrical Characteristics...........................................26 9.2 Tools and Software................................................. 143
6.7 Thermal Resistance Characteristics......................... 27 9.3 Documentation Support.......................................... 144
6.8 Thermal Design Considerations................................29 9.4 Support Resources................................................. 145
6.9 JTAG Debug Probe Connection Without Signal 9.5 Trademarks............................................................. 145
Buffering for the MCU..................................................30 9.6 Electrostatic Discharge Caution..............................145
6.10 Parameter Information............................................ 31 9.7 Glossary..................................................................145
6.11 Test Load Circuit..................................................... 31 10 Revision History........................................................ 145
6.12 Power Sequencing..................................................32 11 Mechanical, Packaging, and Orderable
6.13 Clock Specifications................................................35 Information.................................................................. 147
6.14 Flash Timing............................................................38 11.1 Packaging Information.......................................... 147

TMS320F28035, TMS320F28035-Q1
4 Device Comparison
Table 4-1 lists the features of the TMS320F2803x devices.
Table 4-1. Device Comparison
28030 28031 28032 28033 28034 28035
TYPE
FEATURE (1) 28030-Q1 28031-Q1 28032-Q1 28033-Q1 28034-Q1 28035-Q1
(60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz)
80- 64- 56- 80- 64- 56- 80- 64- 56- 80- 64- 56- 80- 64- 56- 80- 64- 56-
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
Package Type
PN PAG RSH PN PAG RSH PN PAG RSH PN PAG RSH PN PAG RSH PN PAG RSH
LQFP TQFP VQFN LQFP TQFP VQFN LQFP TQFP VQFN LQFP TQFP VQFN LQFP TQFP VQFN LQFP TQFP VQFN
Instruction cycle – 16.67 ns 16.67 ns 16.67 ns 16.67 ns 16.67 ns 16.67 ns
Control Law Accelerator
0 No No No Yes No Yes
(CLA)
On-chip flash (16-bit word) – 16K 32K 32K 32K 64K 64K
On-chip SARAM (16-bit
– 6K 8K 10K 10K 10K 10K
word)
Code security for on-chip
– Yes Yes Yes Yes Yes Yes
flash/SARAM/OTP blocks
Boot ROM (8K x 16) – Yes Yes Yes Yes Yes Yes
One-time programmable
– 1K 1K 1K 1K 1K 1K
(OTP) ROM (16-bit word)
ePWM channels 1 14 12 8 14 12 8 14 12 8 14 12 8 14 12 8 14 12 8
eCAP inputs 0 1 1 1 1 1 1
eQEP modules 0 1 1 1 1 1 1
Watchdog timer – Yes Yes Yes Yes Yes Yes
MSPS 2.0 2.0 4.6 4.6 4.6 4.6
Conversion
500.00 ns 500.00 ns 216.67 ns 216.67 ns 216.67 ns 216.67 ns
Time
12-Bit Channels 16 14 13 16 14 13 16 14 13 16 14 13 16 14 13 16 14 13
3
ADC
Temperature
Yes Yes Yes Yes Yes Yes
Sensor
Dual Sample-
Yes Yes Yes Yes Yes Yes
and-Hold
32-Bit CPU timers – 3 3 3 3 3 3
High-resolution ePWM
1 – – 7 6 4 7 6 4 7 6 4 7 6 4
Channels
High-resolution Capture
0 – – 2 2 – 2 2 – 2 2 – 2 2 –
(HRCAP) Modules
Comparators with
0 3 3 3 3 3 3
Integrated DACs
Inter-integrated circuit
0 1 1 1 1 1 1
(I2C)
Enhanced Controller Area
0 1 1 1 1 1 1
Network (eCAN)
Local Interconnect
0 1 1 1 1 1 1
Network (LIN)
Serial Peripheral Interface
1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1 2 1 1
(SPI)
Serial Communications
Interface (SCI) (UART 0 1 1 1 1 1 1
Compatible)
I/O pins GPIO – 45 33 26 45 33 26 45 33 26 45 33 26 45 33 26 45 33 26

(shared) AIO – 6 6 6 6 6 6
External interrupts – 3 3 3 3 3 3
Supply voltage (nominal) – 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V

TMS320F28035, TMS320F28035-Q1
Table 4-1. Device Comparison (continued)

28030 28031 28032 28033 28034 28035
TYPE
FEATURE (1) 28030-Q1 28031-Q1 28032-Q1 28033-Q1 28034-Q1 28035-Q1
(60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz) (60 MHz)
80- 64- 56- 80- 64- 56- 80- 64- 56- 80- 64- 56- 80- 64- 56- 80- 64- 56-
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
Package Type
PN PAG RSH PN PAG RSH PN PAG RSH PN PAG RSH PN PAG RSH PN PAG RSH
LQFP TQFP VQFN LQFP TQFP VQFN LQFP TQFP VQFN LQFP TQFP VQFN LQFP TQFP VQFN LQFP TQFP VQFN
T: –40°C to
– 28030 28031 28032 28033 28034 28035
105°C
Temperat
S: –40°C to
ure – 28030 28031 28032 28033 28034 28035
125°C
options
Q: –40°C to
– 28030-Q1 – 28031-Q1 – 28032-Q1 – 28033-Q1 – 28034-Q1 – 28035-Q1 –
125°C(2)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 Real-Time Control Peripherals Reference Guide and in the TMS320F2803x Real-Time Microcontrollers Technical Reference
Manual.
(2) The letter Q refers to AEC Q100 qualification for automotive applications.

TMS320F28035, TMS320F28035-Q1
4.1 Related Products

For information about similar products, see the following links:
The F2802x series offers the lowest pin-count and Flash memory size options. InstaSPIN-FOC™ versions are
available.
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the
parallel control law accelerator (CLA) option.
The F2805x series is similar to the F2803x series but adds on-chip programmable gain amplifiers (PGAs).
InstaSPIN-FOC and InstaSPIN-MOTION™ versions are available.
The F2806x series is the first to include a floating-point unit (FPU). The F2806x series also increases the
pin-count, memory size options, and the quantity of peripherals. InstaSPIN-FOC™ and InstaSPIN-MOTION™
versions are available.
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.
The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements. The
F28004x series is the best roadmap option for those using the F2806x series. InstaSPIN-FOC and configurable
logic block (CLB) versions are available.

TMS320F28035, TMS320F28035-Q1
5 Pin Configuration and Functions

5.1 Pin Diagrams
Figure 5-1 shows the 56-pin RSH Very Thin Quad Flatpack (No Lead) (VQFN) pin assignments. Figure 5-2
shows the 64-pin PAG Thin Quad Flatpack (TQFP) pin assignments. Figure 5-3 shows the 80-pin PN Low-
Profile Quad Flatpack (LQFP) pin assignments.
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1
GPIO18/SPICLKA/LINTXA/XCLKOUT
GPIO7/EPWM4B/SCIRXDA
GPIO16/SPISIMOA/TZ2
GPIO17/SPISOMIA/TZ3
GPIO12/TZ1/SCITXDA
GPIO38/TCK/XCLKIN
GPIO37/TDO
GPIO35/TDI
VDD
VSS
X1
X2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GPIO36/TMS 43 28 GPIO28/SCIRXDA/SDAA/TZ2
GPIO5/EPWM3B/SPISIMOA/ECAP1 44 27 TEST2
GPIO4/EPWM3A 45 26 VDDIO
GPIO3/EPWM2B/SPISOMIA/COMP2OUT 46 25 VSS
GPIO2/EPWM2A 47 24 GPIO29/SCITXDA/SCLA/TZ3
GPIO1/EPWM1B/COMP1OUT 48 23 GPIO30/CANRXA
GPIO0/EPWM1A 49 22 GPIO31/CANTXA
VDDIO 50 21 ADCINB7
VSS 51 20 ADCINB6/COMP3B/AIO14
VDD 52 19 ADCINB4/COMP2B/AIO12
VREGENZ 53 18 ADCINB3
GPIO34/COMP2OUT/COMP3OUT 54 17 ADCINB2/COMP1B/AIO10
GPIO20/EQEP1A/COMP1OUT 55 16 ADCINB1
GPIO21/EQEP1B/COMP2OUT 56 15 VSSA/VREFLO
ADCINA7 7
XRS 5
ADCINA4/COMP2A/AIO4 9
GPIO23/EQEP1I/LINRXA 2
VDD 3
TRST 6
ADCINA1 12
ADCINA0/VREFHI 13
GPIO22/EQEP1S/LINTXA 1
ADCINA3 10
VSS 4
VDDA 14
A. This figure shows the top view of the 56-pin RSH package. Shading denotes that the terminals are actually on the bottom side of the
package. See Section 11 for the 56-pin RSH mechanical drawing.
B. Pin 13: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and their use is mutually exclusive to one another.
C. Pin 15: VREFLO is always connected to VSSA on the 56-pin RSH device.
Figure 5-1. 2803x 56-Pin RSH VQFN (Top View)

TMS320F28035, TMS320F28035-Q1
GPIO8/EPWM5A/ADCSOCAO
GPIO16/SPISIMOA/TZ2
GPIO17/SPISOMIA/TZ3
GPIO12/TZ1/SCITXDA
GPIO38/TCK/XCLKIN
GPIO36/TMS
GPIO37/TDO
GPIO35/TDI
VDD
VSS
X1
X2
41
42
44
40
34
48
47
46
43
39
38
37
36
33
45
35
GPIO11/EPWM6B/LINRXA/HRCAP2 49 32 GPIO28/SCIRXDA/SDAA/TZ2
GPIO5/EPWM3B/SPSIMOA/ECAP1 50 31 GPIO9/EPWM5B/LINTXA/HRCAP1
GPIO4/EPWM3A 51 30 TEST2
GPIO10/EPWM6A/ADCSOCBO 52 29 VDDIO
VDDIO 57 24 ADCINB7
VSS 58 23 ADCINB6/COMP3B/AIO14
GPIO21/EQEP1B/COMP2OUT 63 18 ADCINB0
GPIO24/ECAP1 64 17 VSSA/VREFLO
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
TRST
ADCINA0/VREFHI
XRS
VDD
ADCINA7
GPIO22/EQEP1S/LINTXA
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
VSS
ADCINA2/COMP1A/AIO2
ADCINA6/COMP3A/AIO6
ADCINA4/COMP2A/AIO4
ADCINA3
VDDA
GPIO23/EQEP1I/LINRXA
ADCINA1
A. Pin 15: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and their use is mutually exclusive to one another.
B. Pin 17: VREFLO is always connected to VSSA on the 64-pin PAG device.
Figure 5-2. 2803x 64-Pin PAG TQFP (Top View)

TMS320F28035, TMS320F28035-Q1
GPIO12/TZ1/SCITXDA/SPISIMOB
GPIO8/EPWM5A/ADCSOCAO
GPIO16/SPISIMOA/TZ2
GPIO17/SPISOMIA/TZ3
GPIO38/TCK/XCLKIN
GPIO25/SPISOMIB
GPIO41/EPWM7B
GPIO36/TMS
GPIO37/TDO
GPIO35/TDI
GPIO39
GPIO44
VDD
VSS
X1
X2
51
41
52
42
60
54
50
44
59
58
57
56
53
49
48
47
46
43
55
45
GPIO11/EPWM6B/LINRXA/HRCAP2 61 40 GPIO28/SCIRXDA/SDAA/TZ2
GPIO5/EPWM3B/SPISIMOA/ECAP1 62 39 GPIO9/EPWM5B/LINTXA/HRCAP1
GPIO4/EPWM3A 63 38 TEST2
GPIO40/EPWM7A 64 37 GPIO26/HRCAP1/SPICLKB
GPIO10/EPWM6A/ADCSOCBO 65 36 VDDIO
VDDIO 70 31 GPIO27/HRCAP2/SPISTEB
VSS 71 30 ADCINB7
GPIO15/TZ1/LINRXA/SPISTEB 75 26 ADCINB3
GPIO13/TZ2/SPISOMIB 76 25 ADCINB2/COMP1B/AIO10
GPIO14/TZ3/LINTXA/SPICLKB 77 24 ADCINB1
GPIO21/EQEP1B/COMP2OUT 79 22 VREFLO
GPIO24/ECAP1/SPISIMOB 80 21 VSSA
10
12
13
14
15
16
20
11
17
18
19
1
2
3
4
5
6
7
8
9
TRST
VDDA
XRS
VREFHI
GPIO22/EQEP1S/LINTXA
GPIO42/COMP1OUT
VDD
ADCINA7
ADCINA1
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
GPIO23/EQEP1I/LINRXA
VSS
ADCINA6/COMP3A/AIO6
ADCINA5
ADCINA4/COMP2A/AIO4
ADCINA3
ADCINA0
GPIO43/COMP2OUT
ADCINA2/COMP1A/AIO2
Figure 5-3. 2803x 80-Pin PN LQFP (Top View)

TMS320F28035, TMS320F28035-Q1
5.2 Signal Descriptions

Table 5-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at reset,
unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some
peripheral functions may not be available in all devices. See Table 4-1 for details. Inputs are not 5-V tolerant. All
GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled on a per-pin basis.
This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at reset. The pullups
on other GPIO pins are enabled upon reset. The AIO pins do not have an internal pullup.
Note
When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 pins
could glitch during power up. This potential glitch will finish before the boot mode pins are read and
will not affect boot behavior. If glitching is unacceptable in an application, 1.8 V could be supplied
externally. Alternatively, adding a current-limiting resistor (for example, 470 Ω) in series with these pins
and any external driver could be considered to limit the potential for degradation to the pin and/or
external circuitry. There is no power-sequencing requirement when using an external 1.8-V supply.
However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered before
the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin
during power up. To avoid this behavior, power the VDD pins before or with the VDDIO pins, ensuring
that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.
Table 5-1. Signal Descriptions

TERMINAL
PN PAG RSH I/O/Z(1) DESCRIPTION
NAME
PIN NO. PIN NO. PIN NO.
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan
system control of the operations of the device. If this signal is not connected or
driven low, the device operates in its functional mode, and the test reset signals
are ignored. NOTE: TRST is an active high test pin and must be maintained
low at all times during normal device operation. An external pulldown resistor is
TRST 10 8 6 I
required on this pin. The value of this resistor should be based on drive strength
of the debugger pods applicable to the design. A 2.2-kΩ resistor generally
offers adequate protection. Because this is application-specific, TI recommends
validating each target board for proper operation of the debugger and the
application. (↓)
TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup. (↑)
See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial
TMS See GPIO36 I
control input is clocked into the TAP controller on the rising edge of TCK. (↑)
See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into
TDI See GPIO35 I
the selected register (instruction or data) on a rising edge of TCK. (↑)
See GPIO37. JTAG scan out, test data output (TDO). The contents of the
TDO See GPIO37 O/Z selected register (instruction or data) are shifted out of TDO on the falling edge of
TCK. (8 mA drive)
FLASH
TEST2 38 30 27 I/O Test Pin. Reserved for TI. Must be left unconnected.

TMS320F28035, TMS320F28035-Q1
Table 5-1. Signal Descriptions (continued)

TERMINAL
NAME
CLOCK
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either
the same frequency, one-half the frequency, or one-fourth the frequency of
SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register.
XCLKOUT See GPIO18 – O/Z
At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off
by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to
XCLKOUT for this signal to propagate to the pin.
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is
controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default
selection. This pin feeds a clock from an external 3.3-V oscillator. In this case,
the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator
must be disabled through bit 14 in the CLKCTL register. If a crystal/resonator is
XCLKIN See GPIO19 and GPIO38 I used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register.
NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external
clock for normal device operation may need to incorporate some hooks to
disable this path during debug using the JTAG connector. This is to prevent
contention with the TCK signal, which is active during JTAG debug sessions. The
zero-pin internal oscillators may be used during this time to clock the device.
On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or
a ceramic resonator must be connected across X1 and X2. In this case, the
X1 52 41 36 I
XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not
used, it must be tied to GND. (I)
On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be
X2 51 40 35 O
connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out). These devices have a built-in
power-on reset (POR) and brown-out reset (BOR) circuitry. During a power-on or
brown-out condition, this pin is driven low by the device. An external circuit may
also drive this pin to assert a device reset. This pin is also driven low by the MCU
when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low
for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value
from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is
placed between XRS and VSS for noise filtering, it should be 100 nF or smaller.
XRS 9 7 5 I/O
These values will allow the watchdog to properly drive the XRS pin to VOL
within 512 OSCCLK cycles when the watchdog reset is asserted. Regardless
of the source, a device reset causes the device to terminate execution. The
program counter points to the address contained at the location 0x3F FFC0.
When reset is deactivated, execution begins at the location designated by the
program counter. The output buffer of this pin is an open-drain device with an
internal pullup. (↑) If this pin is driven by an external device, it should be done
using an open-drain device.
ADC, COMPARATOR, ANALOG I/O
ADCINA7 11 9 7 I ADC Group A, Channel 7 input
ADCINA6 I ADC Group A, Channel 6 input
COMP3A 12 10 8 I Comparator Input 3A
AIO6 I/O Digital AIO 6
ADCINA5 13 – – I ADC Group A, Channel 5 input

TMS320F28035, TMS320F28035-Q1

TERMINAL
NAME
ADC Group A, Channel 0 input.
NOTE: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and
ADCINA0 18 15 13 I their use is mutually exclusive to one another.
NOTE: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and
their use is mutually exclusive to one another.
ADC External Reference High – only used when in ADC external reference
mode. See Section 7.9.2.1, ADC.
NOTE: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and
VREFHI 19 15 13 I
NOTE: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and
ADCINB7 30 24 21 I ADC Group B, Channel 7 input
ADCINB6 I ADC Group B, Channel 6 input
COMP3B 29 23 20 I Comparator Input 3B
ADCINB5 28 – – I ADC Group B, Channel 5 input
AIO12 I/O Digital AIO12
ADCINB0 23 18 – I ADC Group B, Channel 0 input
ADC External Reference Low.
VREFLO 22 17 15 I NOTE: VREFLO is always connected to VSSA on the 64-pin PAG device and on
the 56-pin RSH device.
CPU AND I/O POWER
VDDA 20 16 14 Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.
Analog Ground Pin.
VSSA 21 17 15 NOTE: VREFLO is always connected to VSSA on the 64-pin PAG device and on
the 56-pin RSH device.
7 5 3
CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF
VDD 54 43 38 capacitor between each VDD pin and ground. Higher value capacitors may be
used.
72 59 52
36 29 26 Digital I/O Buffers and Flash Memory Power Pin. Single supply source when
VDDIO VREG is enabled. Place a decoupling capacitor on each pin. The exact value
70 57 50 should be determined by the system voltage regulation solution.
8 6 4
35 28 25
VSS Digital Ground Pins
53 42 37
71 58 51

TMS320F28035, TMS320F28035-Q1

TERMINAL
NAME
VOLTAGE REGULATOR CONTROL SIGNAL
Internal voltage regulator (VREG) enable with internal pulldown. Tie directly to
VREGENZ 73 60 53 I VSS (low) to enable the internal 1.8-V VREG. Tie directly to VDDIO (high) to
disable the VREG and use an external 1.8-V supply.
GPIO AND PERIPHERAL SIGNALS (2)
GPIO0 I/O/Z General-purpose input/output 0
EPWM1A O Enhanced PWM1 Output A and HRPWM channel
69 56 49
– – –
– – –
EPWM1B O Enhanced PWM1 Output B
68 55 48
– –
COMP1OUT O Direct output of Comparator 1
EPWM2A O Enhanced PWM2 Output A and HRPWM channel
67 54 47
– –
– –
EPWM2B O Enhanced PWM2 Output B
66 53 46
SPISOMIA I/O SPI-A slave out, master in
EPWM3A O Enhanced PWM3 output A and HRPWM channel
63 51 45
– –
– –
EPWM3B O Enhanced PWM3 output B
62 50 44
SPISIMOA I/O SPI-A slave in, master out
ECAP1 I/O Enhanced Capture input/output 1
50 39 34
EPWMSYNCI I External ePWM sync pulse input
EPWMSYNCO O External ePWM sync pulse output
49 38 33
SCIRXDA I SCI-A receive data
– –
43 35 –
– –
ADCSOCAO O ADC start-of-conversion A

TMS320F28035, TMS320F28035-Q1

TERMINAL
NAME
39 31 –
LINTXA O LIN transmit A
HRCAP1 I High-resolution input capture 1
65 52 –
– –
ADCSOCBO O ADC start-of-conversion B
61 49 –
LINRXA I LIN receive A
TZ1 I Trip Zone input 1
SCITXDA 47 37 32 O SCI-A transmit data
SPI-B slave in, master out.
SPISIMOB I/O
NOTE: SPI-B is available only in the PN package.
76 – –
– –
SPISOMIB I/O SPI-B slave out, master in
TZ3 I Trip zone input 3
77 – –
LINTXA O LIN transmit
SPICLKB I/O SPI-B clock input/output
75 – –
LINRXA I LIN receive
SPISTEB I/O SPI-B slave transmit enable input/output
SPISIMOA I/O SPI-A slave in, master out
46 36 31
– –
SPISOMIA I/O SPI-A slave out, master in
42 34 30
– –

TMS320F28035, TMS320F28035-Q1

TERMINAL
NAME
SPICLKA I/O SPI-A clock input/output
41 33 29 Output clock derived from SYSCLKOUT. XCLKOUT is either the same

frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT.
This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset,
XCLKOUT O/Z
XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting
XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT
for this signal to propagate to the pin.
External Oscillator Input. The path from this pin to the clock block is not gated
XCLKIN by the mux function of this pin. Care must be taken not to enable this path for
clocking if it is being used for the other peripheral functions
55 44 39
SPISTEA I/O SPI-A slave transmit enable input/output
EQEP1A I Enhanced QEP1 input A
78 62 55
– –
EQEP1B I Enhanced QEP1 input B
79 63 56
– –
EQEP1S I/O Enhanced QEP1 strobe
1 1 1
– –
EQEP1I I/O Enhanced QEP1 index
4 4 2
– –
GPIO24 – I/O/Z General-purpose input/output 24
See
GPIO5
and
80 64 GPIO19
– –
SPI-B slave in, master out.
SPISIMOB I/O
NOTE: SPI-B is available only in the PN and RSH packages.
– –
44 – –
– –
SPISOMIB I/O SPI-B slave out, master in

TMS320F28035, TMS320F28035-Q1

TERMINAL
NAME
37 – –
– –
SPICLKB I/O SPI-B clock input/output
31 – –
– –
SPISTEB I/O SPI-B slave transmit enable input/output
SCIRXDA I SCI receive data
40 32 28
SDAA I/OD I2C data open-drain bidirectional port
SCITXDA O SCI transmit data
34 27 24
SCLA I/OD I2C clock open-drain bidirectional port
CANRXA I CAN receive
33 26 23
– –
– –
CANTXA O CAN transmit
32 25 22
– –
– –
SDAA I/OD I2C data open-drain bidirectional port
2 2 –
EPWMSYNCI I Enhanced PWM external sync pulse input
ADCSOCAO O ADC start-of-conversion A
GPIO33 I/O/Z General-Purpose Input/Output 33
SCLA I/OD I2C clock open-drain bidirectional port
3 3 –
EPWMSYNCO O Enhanced PWM external synch pulse output
ADCSOCBO O ADC start-of-conversion B
74 61 54
– –
59 47 42 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
TDI I
register (instruction or data) on a rising edge of TCK
60 48 43 JTAG test-mode select (TMS) with internal pullup. This serial control input is
TMS I
clocked into the TAP controller on the rising edge of TCK.

TMS320F28035, TMS320F28035-Q1

TERMINAL
NAME
58 46 41 JTAG scan out, test data output (TDO). The contents of the selected register
TDO O/Z (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA
drive)
TCK I JTAG test clock with internal pullup
57 45 40 External Oscillator Input. The path from this pin to the clock block is not gated
XCLKIN I by the mux function of this pin. Care must be taken to not enable this path for
clocking if it is being used for the other functions.
– –
– –
56 – –
– –
– –
64 – –
– –
– –
48 – –
– –
– –
– –
5 – –
– –
– –
6 – –
– –
– –
45 – –
– –
– –
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown

(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate
functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output
path from the GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal.
See the System Control chapter in the TMS320F2803x Real-Time Microcontrollers Technical Reference Manual for details.

TMS320F28035, TMS320F28035-Q1
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VDDIO (I/O and Flash) with respect to VSS –0.3 4.6
Supply voltage V
VDD with respect to VSS –0.3 2.5
Analog voltage VDDA with respect to VSSA –0.3 4.6 V
VIN (3.3 V) –0.3 4.6
Input voltage V
VIN (X1) –0.3 2.5
Output voltage VO –0.3 4.6 V
Digital/analog input (per pin), IIK
–20 20
(VIN < VSS or VIN > VDDIO)(3)
Analog input (per pin), IIKANALOG
Input clamp current –20 20 mA
(VIN < VSSA or VIN > VDDA)
Total for all inputs, IIKTOTAL
–20 20
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)
Output clamp current IOK (VO < 0 or VO > VDDIO) –20 20 mA
Junction temperature(4) TJ –40 150 °C
Storage temperature(4) Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see Semiconductor and IC Package Thermal Metrics; Calculating Useful Lifetimes of Embedded
Processors; and Calculating FIT for a Mission Profile.
6.2 ESD Ratings – Automotive

VALUE UNIT
TMS320F2803x-Q1 in 80-pin PN package
Human body model (HBM), per AEC Q100-002(1) All pins ±2000
All pins except corner pins ±500
V(ESD) Electrostatic discharge V
Charged device model (CDM), per AEC Q100-011 Corner pins on 80-pin PN:
1, 20, 21, 40, 41, 60, 61, ±750
80
TMS320F2803x-Q1 in 64-pin PAG package
Human body model (HBM), per AEC Q100-002(1) All pins ±2000
All pins except corner pins ±500
V(ESD) Electrostatic discharge V
Charged device model (CDM), per AEC Q100-011 Corner pins on 64-pin
PAG: 1, 16, 17, 32, 33, ±750
48, 49, 64
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

TMS320F28035, TMS320F28035-Q1
6.3 ESD Ratings – Commercial

VALUE UNIT
TMS320F2803x in 80-pin PN package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 V
±500
or ANSI/ESDA/JEDEC JS-002(2)
TMS320F2803x in 64-pin PAG package
±500
TMS320F2803x in 56-pin RSH package
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions

MIN NOM MAX UNIT
Device supply voltage, I/O, VDDIO 2.97 3.3 3.63 V
Device supply voltage CPU, VDD (When internal VREG is
1.71 1.8 1.995 V
disabled and 1.8 V is supplied externally)
Supply ground, VSS 0 V
Analog supply voltage, VDDA 2.97 3.3 3.63 V
Analog ground, VSSA 0 V
Device clock frequency (system clock) 2 60 MHz
High-level input voltage, VIH (3.3 V) 2 VDDIO + 0.3 V
Low-level input voltage, VIL (3.3 V) VSS – 0.3 0.8 V
All GPIO/AIO pins –4 mA
High-level output source current, VOH = VOH(MIN) , IOH
Group 2(1) –8 mA
All GPIO/AIO pins 4 mA
Low-level output sink current, VOL = VOL(MAX), IOL
Group 2(1) 8 mA
T version –40 105
S version –40 125
Ambient temperature, TA °C
Q version
–40 125
(AEC Q100 qualification)
Junction temperature, TJ –40 150 °C
(1) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37

TMS320F28035, TMS320F28035-Q1
6.5 Power Consumption Summary

6.5.1 TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT
VREG ENABLED VREG DISABLED
MODE TEST CONDITIONS IDDIO (1) IDDA (2) IDD IDDIO (1) IDDA (2)
TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX TYP(3) MAX
The following peripheral clocks
are enabled:
• ePWM1/2/3/4/5/6/7
• eCAP1
• eQEP1
• eCAN
• LIN
• CLA
• HRPWM
• SCI-A
Operational
• SPI-A/B 114 mA(7) 135 mA(7) 14 mA 18 mA 101 mA(7) 120 mA(7) 14 mA 18 mA 14 mA 18 mA
(Flash)
• ADC
• I2C
• COMP1/2/3
• CPU-TIMER0/1/2
All PWM pins are toggled at

60 kHz.
All I/O pins are left
unconnected.(4) (6)
Code is running out of flash
with 2 wait states.
XCLKOUT is turned off.
Flash is powered down.
XCLKOUT is turned off.
IDLE 13 mA 23 mA 10 μA 15 μA 13 mA 24 mA 120 μA 400 μA 10 μA 15 μA
All peripheral clocks are turned
off.
STANDBY 4 mA 9 mA 10 μA 15 μA 4 mA 7 mA 120 μA 400 μA 10 μA 15 μA
Peripheral clocks are off.
HALT Peripheral clocks are off. 46 μA 10 μA 15 μA 30 μA 24 μA 10 μA 15 μA
Input clock is disabled.(5)
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) To realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to
the PCLKCR0 register.
(3) The TYP numbers are applicable over room temperature and nominal voltage.
(4) The following is done in a loop:
• Data is continuously transmitted out of SPI-A/B, SCI-A, eCAN, LIN, and I2C ports.
• The hardware multiplier is exercised.
• Watchdog is reset.
• ADC is performing continuous conversion.
• COMP1/2 are continuously switching voltages.
• GPIO17 is toggled.
(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
(6) CLA is continuously performing polynomial calculations.
(7) For F2803x devices that do not have CLA, subtract the IDD current number for CLA (see Table 6-1) from the IDD (VREG disabled)/IDDIO
(VREG enabled) current numbers shown in Section 6.5.1 for operational mode.

TMS320F28035, TMS320F28035-Q1
Note
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from
being used at the same time. This is because more than one peripheral function may share an I/O
pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such
a configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
6.5.2 Reducing Current Consumption

The 2803x devices incorporate a method to reduce the device current consumption. Because each peripheral
unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning
off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the
three low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-1
indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 6-1. Typical Current Consumption by Various Peripherals (at 60 MHz)
PERIPHERAL IDD CURRENT
MODULE(1) (3) REDUCTION (mA)
ADC 2(2)
I2C 3
ePWM 2
eCAP 2
eQEP 2
SCI 2
SPI 2
COMP/DAC 1
HRPWM 3
HRCAP 3
CPU-TIMER 1
Internal zero-pin oscillator 0.5
CAN 2.5
LIN 1.5
CLA 20
(1) All peripheral clocks (except CPU Timer clock) are disabled upon reset. Writing to/reading from
peripheral registers is possible only after the peripheral clocks are turned on.
(2) This number represents the current drawn by the digital portion of the ADC module. Turning off the
clock to the ADC module results in the elimination of the current drawn by the analog portion of the
ADC (IDDA) as well.
(3) For peripherals with multiple instances, the current quoted is per module. For example, the 2 mA
value quoted for ePWM is for one ePWM module.
Note
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
Note
The baseline IDD current (current when the core is executing a dummy loop with no peripherals
enabled) is 40 mA, typical. To arrive at the IDD current for a given application, the current-drawn by the
peripherals (enabled by that application) must be added to the baseline IDD current.

TMS320F28035, TMS320F28035-Q1
Following are other methods to reduce power consumption further:

• The flash module may be powered down if code is run off SARAM. This results in a current reduction of
18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail.
• Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.
• To realize the lowest VDDA current consumption in a low-power mode, see the respective analog chapter
of the TMS320F2803x Real-Time Microcontrollers Technical Reference Manual to ensure each module is
powered down as well.
6.5.3 Current Consumption Graphs (VREG Enabled)
Operational Current vs Frequency
140
120
Operational Current (mA)
100
80
60
40
20
0
0 10 20 30 40 50 60 70
SYSCLKOUT (MHz)
IDDIO IDDA
Figure 6-1. Typical Operational Current Versus Frequency (F2803x)

TMS320F28035, TMS320F28035-Q1
Operational Power vs Frequency
500
450
Operational Power (mW)
400
350
300
250
200
0 10 20 30 40 50 60 70
SYSCLKOUT (MHz)
Figure 6-2. Typical Operational Power Versus Frequency (F2803x)
Typical CLA operational current vs SYSCLKOUT
25
CLA operational IDDIO current (mA)
20
15
10
0
10 15 20 25 30 35 40 45 50 55 60
SYSCLKOUT (MHz)
Figure 6-3. Typical CLA Operational Current Versus SYSCLKOUT

TMS320F28035, TMS320F28035-Q1
6.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = IOH MAX 2.4
VOH High-level output voltage V
IOH = 50 μA VDDIO – 0.2
VOL Low-level output voltage IOL = IOL MAX 0.4 V
Pin with pullup All GPIO –80 –140 –205

VDDIO = 3.3 V, VIN = 0 V
Input current enabled XRS pin –230 –300 –375
IIL μA
(low level)
Pin with pulldown
VDDIO = 3.3 V, VIN = 0 V ±2
enabled
Pin with pullup
VDDIO = 3.3 V, VIN = VDDIO ±2
Input current enabled
IIH μA
(high level) Pin with pulldown
VDDIO = 3.3 V, VIN = VDDIO 28 50 80
enabled
Output current, pullup or pulldown
IOZ VO = VDDIO or 0 V ±2 μA
disabled
CI Input capacitance 2 pF
VDDIO BOR trip point Falling VDDIO 2.50 2.78 2.96 V
VDDIO BOR hysteresis 35 mV
Supervisor reset release delay Time after BOR/POR/OVR event is removed to XRS
400 800 μs
time release
VREG VDD output Internal VREG on 1.9 V
(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage
(VDD) go out of range.

TMS320F28035, TMS320F28035-Q1
6.7 Thermal Resistance Characteristics

6.7.1 PN Package
°C/W(1) AIR FLOW (lfm)(2)
RΘJC Junction-to-case thermal resistance 14.2 N/A
RΘJB Junction-to-board thermal resistance 21.9 N/A
49.9 0
RΘJA 38.3 150

Junction-to-free air thermal resistance
(High k PCB) 36.7 250
34.4 500
0.8 0
1.18 150
PsiJT Junction-to-package top
1.34 250
1.62 500
21.6 0
20.7 150
PsiJB Junction-to-board
20.5 250
20.1 500
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute

TMS320F28035, TMS320F28035-Q1
6.7.2 PAG Package

56.5 0
RΘJA 44.7 150

(High k PCB) 42.9 250
40.3 500
0.15 0
0.42 150
0.51 250
0.67 500
31.1 0
29.7 150
29.2 250
28.4 500

TMS320F28035, TMS320F28035-Q1
6.7.3 RSH Package

34.8 0
RΘJA 23.6 150

(High k PCB) 22.3 250
20.5 500
0.24 0
0.36 150
0.43 250
0.56 500
9.2 0
8.8 150
8.9 250
8.8 500
6.8 Thermal Design Considerations

Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems
that exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.

TMS320F28035, TMS320F28035-Q1
6.9 JTAG Debug Probe Connection Without Signal Buffering for the MCU
Figure 6-4 shows the connection between the MCU and JTAG header for a single-processor configuration. If
the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-4 shows the simpler,
no-buffering situation. For the pullup/pulldown resistor values, see Section 5.2, Signal Descriptions.
6 inches or less
VDDIO VDDIO
13 5
EMU0 PD
14
EMU1
2 4
TRST TRST GND
1 6
TMS TMS GND
3 8
TDI TDI GND
7 10
TDO TDO GND
11 12
TCK TCK GND
9
TCK_RET
MCU
JTAG Header
A. See Figure 7-44 for JTAG/GPIO multiplexing.
Figure 6-4. JTAG Debug Probe Connection Without Signal Buffering for the MCU
Note
The 2803x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header onboard,
the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7-kΩ (typical) resistor.

TMS320F28035, TMS320F28035-Q1
6.10 Parameter Information

6.10.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their Letters and symbols and their
meanings: meanings:
a access time H High
c cycle time (period) L Low
d delay time V Valid
f fall time X Unknown, changing, or don't care level
h hold time Z High impedance
r rise time
su setup time
t transition time
v valid time
w pulse duration (width)
6.10.2 General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
6.11 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics Data Sheet Timing Reference Point
42 W 3.5 nH Output
Transmission Line Under
(A)
Test
Z0 = 50 W
(B)
Device Pin
4.0 pF 1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 6-5. 3.3-V Test Load Circuit

TMS320F28035, TMS320F28035-Q1
6.12 Power Sequencing

There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to
prevent the I/Os from glitching during power up/down (GPIO19, GPIO34–38 do not have glitch-free I/Os). No
voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, this
value is 0.7 V above VDDA) before powering up the device. Voltages applied to pins on an unpowered device can
bias internal p-n junctions in unintended ways and produce unpredictable results.
VDDIO, VDDA
(3.3 V)
VDD (1.8 V)
INTOSC1
tINTOSCST
X1/X2
tOSCST (B)
(A)
XCLKOUT
User-code dependent
tw(RSL1)
(D)
XRS
Address/data valid, internal boot-ROM code execution phase
Address/Data/
Control
(Internal)
td(EX) User-code execution phase
th(boot-mode)(C) User-code dependent
Boot-Mode
GPIO pins as input
Pins
Peripheral/GPIO function
Boot-ROM execution starts
Based on boot code
(E)
I/O Pins GPIO pins as input (state depends on internal PU/PD)
User-code dependent
A. Upon power up, SYSCLKOUT is OSCCLK/4. Because the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0,
SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this phase.
B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. XCLKOUT will not be visible at the
pin until explicitly configured by user code.
C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.
E. The internal pullup/pulldown will take effect when BOR is driven high.
Figure 6-6. Power-on Reset

TMS320F28035, TMS320F28035-Q1
6.12.1 Reset ( XRS) Timing Requirements

MIN MAX UNIT
th(boot-mode) Hold time for boot-mode pins 1000tc(SCO) cycles
tw(RSL2) Pulse duration, XRS low on warm reset 32tc(OSCCLK) cycles
6.12.2 Reset ( XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tw(RSL1) Pulse duration, XRS driven by device 600 μs
Pulse duration, reset pulse generated by
tw(WDRS) 512tc(OSCCLK) cycles
watchdog
td(EX) Delay time, address/data valid after XRS high 32tc(OSCCLK) cycles
tINTOSCST Start-up time, internal zero-pin oscillator 3 μs
tOSCST (1) On-chip crystal-oscillator start-up time 1 10 ms
(1) Dependent on crystal/resonator and board design.
INTOSC1
X1/X2
XCLKOUT
User-Code Dependent
tw(RSL2)
XRS
User-Code Execution Phase
td(EX)
Address/Data/
Control User-Code Execution
(Internal)
Boot-ROM Execution Starts th(boot-mode)(A)

Boot-Mode
Peripheral/GPIO Function GPIO Pins as Input Peripheral/GPIO Function
Pins
User-Code Execution Starts
I/O Pins User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Figure 6-7. Warm Reset

TMS320F28035, TMS320F28035-Q1
Figure 6-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004
and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is
written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is
complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2 OSCCLK/2 OSCCLK * 4
(Current CPU (CPU frequency while PLL is stabilizing (Changed CPU frequency)
Frequency) with the desired frequency. This period
(PLL lock-up time tp) is 1 ms long.)
Figure 6-8. Example of Effect of Writing Into PLLCR Register

TMS320F28035, TMS320F28035-Q1
6.13 Clock Specifications

6.13.1 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 2803x MCUs. Section 6.13.1.1 lists the cycle times of various clocks.
6.13.1.1 2803x Clock Table and Nomenclature (60-MHz Devices)
MIN NOM MAX UNIT
tc(SCO), Cycle time 16.67 500 ns
SYSCLKOUT
Frequency 2 60 MHz
tc(LCO), Cycle time 16.67 66.67(2) ns
LSPCLK(1)
Frequency 15(2) 60 MHz
tc(ADCCLK), Cycle time 16.67 ns
ADC clock
Frequency 60 MHz
(1) Lower LSPCLK will reduce device power consumption.

(2) This is the default reset value if SYSCLKOUT = 60 MHz.
6.13.1.2 Device Clocking Requirements/Characteristics

MIN NOM MAX UNIT
On-chip oscillator (X1/X2 pins) tc(OSC), Cycle time 50 200 ns

(Crystal/Resonator) Frequency 5 20 MHz
External oscillator/clock source tc(CI), Cycle time (C8) 33.3 200 ns

(XCLKIN pin) — PLL Enabled Frequency 5 30 MHz
External oscillator/clock source tc(CI), Cycle time (C8) 33.33 250 ns

(XCLKIN pin) — PLL Disabled Frequency 4 30 MHz
Limp mode SYSCLKOUT
Frequency range 1 to 5 MHz
(with /2 enabled)
tc(XCO), Cycle time (C1) 66.67 2000 ns
XCLKOUT
Frequency 0.5 15 MHz
PLL lock time(1) tp 1 ms
(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are
used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).

TMS320F28035, TMS320F28035-Q1
6.13.1.3 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics

PARAMETER MIN TYP MAX UNIT
Internal zero-pin oscillator 1 (INTOSC1) at 30°C(1) (2) Frequency 10.000 MHz
Internal zero-pin oscillator 2 (INTOSC2) at 30°C(1) (2) Frequency 10.000 MHz
Step size (coarse trim) 55 kHz
Step size (fine trim) 14 kHz
Temperature drift(3) 3.03 4.85 kHz/°C
Voltage (VDD) drift(3) 175 Hz/mV
(1) Oscillator frequency will vary over temperature, see Figure 6-9. To compensate for oscillator temperature drift, see the Oscillator
Compensation Guide and C2000Ware.
(2) Frequency range ensured only when VREG is enabled, VREGENZ = VSS.
(3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For
example:
• Increase in temperature will cause the output frequency to increase per the temperature coefficient.
• Decrease in voltage (VDD) will cause the output frequency to decrease per the voltage coefficient.
Zero-Pin Oscillator Frequency Movement With Temperature
10.6
10.5
10.4
10.3
Output Frequency (MHz)
10.2
10.1
10
9.9
9.8
9.7
9.6
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
Typical Temperature (°C)

Max
Figure 6-9. Zero-Pin Oscillator Frequency Movement With Temperature

TMS320F28035, TMS320F28035-Q1
6.13.2 Clock Requirements and Characteristics

6.13.2.1 XCLKIN Timing Requirements – PLL Enabled
NO. MIN MAX UNIT
C9 tf(CI) Fall time, XCLKIN 6 ns
C10 tr(CI) Rise time, XCLKIN 6 ns
C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45% 55%
C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45% 55%
6.13.2.2 XCLKIN Timing Requirements – PLL Disabled

NO. MIN MAX UNIT
Up to 20 MHz 6
C9 tf(Cl) Fall time, XCLKIN ns
20 MHz to 30 MHz 2
Up to 20 MHz 6
C10 tr(CI) Rise time, XCLKIN ns
20 MHz to 30 MHz 2
Pulse duration, XCLKIN low as a percentage of
C11 tw(CIL) 45% 55%
tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of
C12 tw(CIH) 45% 55%
tc(OSCCLK)
The possible configuration modes are shown in Table 7-17.

6.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
over recommended operating conditions (unless otherwise noted)(1) (2)
NO. PARAMETER MIN MAX UNIT
C3 tf(XCO) Fall time, XCLKOUT 5 ns
C4 tr(XCO) Rise time, XCLKOUT 5 ns
C5 tw(XCOL) Pulse duration, XCLKOUT low H–2 H+2 ns
C6 tw(XCOH) Pulse duration, XCLKOUT high H–2 H+2 ns
(1) A load of 40 pF is assumed for these parameters.

(2) H = 0.5tc(XCO)
C10
C9
C8
XCLKIN(A)
C3 C6
C1
C4
C5
XCLKOUT(B)
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to
illustrate the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-10. Clock Timing

TMS320F28035, TMS320F28035-Q1
6.14 Flash Timing

6.14.1 Flash/OTP Endurance for T Temperature Material
ERASE/PROGRAM
MIN TYP MAX UNIT
TEMPERATURE(1)
Nf Flash endurance for the array (write/erase cycles) 0°C to 105°C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
6.14.2 Flash/OTP Endurance for S Temperature Material

ERASE/PROGRAM
MIN TYP MAX UNIT
TEMPERATURE(1)
Nf Flash endurance for the array (write/erase cycles) 0°C to 125°C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) 1 write
6.14.3 Flash/OTP Endurance for Q Temperature Material

ERASE/PROGRAM
MIN TYP MAX UNIT
TEMPERATURE(1)
Nf Flash endurance for the array (write/erase cycles) –40°C to 125°C (ambient) 20000 50000 cycles
NOTP OTP endurance for the array (write cycles) –40°C to 30°C (ambient) 1 write
6.14.4 Flash Parameters at 60-MHz SYSCLKOUT

TEST
CONDITIONS
Program Time(1) 8K Sector 250 2000(2) ms
4K Sector 125 2000(2) ms
16-Bit Word 50 μs
Erase Time(3) 8K Sector 2 12(2) s
4K Sector 2 12(2) s
IDDP (4) VDD current consumption during Erase/Program cycle VREG 80 mA
disabled
IDDIOP (4) VDDIO current consumption during Erase/Program cycle 60 mA
IDDIOP (4) VDDIO current consumption during Erase/Program cycle VREG 120 mA
enabled
(1) Program time is at the maximum device frequency. The programming time indicated in this table is applicable only when all the
required code/data is available in the device RAM, ready for programming. Program time includes overhead of the flash state machine
but does not include the time to transfer the following into RAM:
• the code that uses flash API to program the flash
• the Flash API itself
• Flash data to be programmed
(2) Maximum flash parameter mentioned are for the first 100 program and erase cycles.
(3) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(4) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain
a stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at
all times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board
(during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands
placed during the programming process.

TMS320F28035, TMS320F28035-Q1
6.14.5 Flash/OTP Access Timing

PARAMETER MIN MAX UNIT
ta(fp) Paged Flash access time 40 ns
ta(fr) Random Flash access time 40 ns
ta(OTP) OTP access time 60 ns
6.14.6 Flash Data Retention Duration

PARAMETER TEST CONDITIONS MIN MAX UNIT
tretention Data retention duration TJ = 55°C 15 years
Table 6-2. Minimum Required Flash/OTP Wait States at Different Frequencies

SYSCLKOUT SYSCLKOUT PAGE RANDOM OTP
(MHz) (ns) WAIT STATE(1) WAIT STATE(1) WAIT STATE
60 16.67 2 2 3
55 18.18 2 2 3
50 20 1 1 2
45 22.22 1 1 2
40 25 1 1 2
35 28.57 1 1 2
30 33.33 1 1 1
25 40 0 1 1
(1) Random wait state must be ≥ 1.
The equations to compute the Flash page wait state and random wait state in Table 6-2 are as follows:
éæ t a( f · p ) ö ù
Flash Page Wait State = êç ÷ - 1ú round up to the next highest integer
êëçè t c (SCO ) ÷ø úû
éæ t a(f ×r) ö ù
Flash Random Wait State = êç ÷ - 1ú round up to the next highest integer, or 1, whichever is larger
êëçè t c(SCO) ÷ø úû
The equation to compute the OTP wait state in Table 6-2 is as follows:
éæ t a(OTP) ö ù
OTP Wait State = êç ÷ - 1ú round up to the next highest integer, or 1, whichever is larger
ç ÷
ëêè t c(SCO) ø ûú

TMS320F28035, TMS320F28035-Q1
7 Detailed Description
7.1 Overview
7.1.1 CPU
The 2803x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x-based
controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very efficient C/C++
engine, enabling users to develop not only their system control software in a high-level language, but also
enabling development of math algorithms using C/C++. The device is as efficient at MCU math tasks as it is at
system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for
a second processor in many systems. The 32 × 32-bit MAC 64-bit processing capabilities enable the controller
to handle higher numerical resolution problems efficiently. Add to this the fast interrupt response with automatic
context save of critical registers, resulting in a device that is capable of servicing many asynchronous events
with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This
pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. Special
branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional
operations further improve performance.
7.1.2 Control Law Accelerator (CLA)
The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the capabilities of
the C28x CPU by adding parallel processing. The CLA is an independent processor with its own bus structure,
fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be specified. Each task is started
by software or a peripheral such as the ADC, an ePWM, or CPU Timer 0. The CLA executes one task at
a time to completion. When a task completes the main CPU is notified by an interrupt to the PIE and the
CLA automatically begins the next highest-priority pending task. The CLA can directly access the ADC Result
registers and the ePWM+HRPWM registers. Dedicated message RAMs provide a method to pass additional
data between the main CPU and the CLA.
7.1.3 Memory Bus (Harvard Bus Architecture)
As with many MCU-type devices, multiple buses are used to move data between the memories and peripherals
and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus.
The program read bus consists of 22 address lines and 32 data lines. The data read and write buses consist
of 32 address lines and 32 data lines each. The 32-bit-wide data buses enable single cycle 32-bit operations.
The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a
data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus
prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows:
Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur on the
memory bus.)
Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the
memory bus.)
7.1.4 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices
adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various
buses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16
or 32 data lines and associated control signals. Three versions of the peripheral bus are supported. One
version supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit
accesses (called peripheral frame 1). The third version supports CLA access and both 16- and 32-bit accesses
(called peripheral frame 3).

TMS320F28035, TMS320F28035-Q1
7.1.5 Real-Time JTAG and Analysis

The devices implement the standard IEEE 1149.1 (IEEE Standard 1149.1-1990 Standard Test Access Port
and Boundary Scan Architecture) JTAG interface for in-circuit based debug. Additionally, the devices support
real-time mode of operation allowing modification of the contents of memory, peripheral, and register locations
while the processor is running and executing code and servicing interrupts. The user can also single step
through non-time-critical code while enabling time-critical interrupts to be serviced without interference. The
device implements the real-time mode in hardware within the CPU. This is a feature unique to the 28x family of
devices, requiring no software monitor. Additionally, special analysis hardware is provided that allows setting of
hardware breakpoint or data/address watch-points and generating various user-selectable break events when a
match occurs.
7.1.6 Flash
The F28035/34 devices contain 64K × 16 of embedded flash memory, segregated into eight 8K × 16 sectors.
The F28033/32/31 devices contain 32K × 16 of embedded flash memory, segregated into eight 4K × 16 sectors.
The F28030 device contains 16K × 16 of embedded flash memory, segregated into four 4K × 16 sectors. All
devices also contain a single 1K × 16 of OTP memory at address range 0x3D 7800 to 0x3D 7BFF. The user can
individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not
possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors.
Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP
is mapped to both program and data space; therefore, it can be used to execute code or store data information.
Addresses 0x3F 7FF0 to 0x3F 7FF5 are reserved for data variables and should not contain program code.
Note
The Flash and OTP wait states can be configured by the application. This allows applications running
at slower frequencies to configure the flash to use fewer wait states.
Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options
register. With this mode enabled, effective performance of linear code execution will be much faster
than the raw performance indicated by the wait-state configuration alone. The exact performance gain
when using the Flash pipeline mode is application-dependent.
For more information on the Flash options, Flash wait state, and OTP wait-state registers, see
the System Control chapter in the TMS320F2803x Real-Time Microcontrollers Technical Reference
Manual.
7.1.7 M0, M1 SARAMs

All devices contain these two blocks of single access memory, each 1K × 16 in size. The stack pointer points
to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices,
are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data
variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the
programmer. This makes for easier programming in high-level languages.
7.1.8 L0 SARAM, and L1, L2, and L3 DPSARAMs
The device contains up to 8K × 16 of single-access RAM. To ascertain the exact size for a given device, see
the device-specific memory map figures in Section 7.2. This block is mapped to both program and data space.
Block L0 is 2K in size and is dual mapped to both program and data space. Blocks L1 and L2 are both 1K in size
and are shared with the CLA which can utilize these blocks for its data space. Block L3 is 4K (2K on the 28031
device) in size and is shared with the CLA which can utilize this block for its program space. DPSARAM refers to
the dual-port configuration of these blocks.

TMS320F28035, TMS320F28035-Q1
7.1.9 Boot ROM

The Boot ROM is factory-programmed with bootloader software. The Boot ROM uses the boot-mode-select
GPIO pins to determine what boot mode to use upon power up. The user can select to boot normally to
application code, to download new software from an external connection, or to select boot software that is
programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS
waveforms, for use in math-related algorithms. The boot-ROM content, and hence the checksum value, may
vary for different silicon revisions. For details, see the Boot ROM chapter in the TMS320F2803x Real-Time
Microcontrollers Technical Reference Manual.
Table 7-1. Boot Mode Selection
GPIO34/COMP2OUT/
MODE GPIO37/TDO TRST MODE
COMP3OUT
3 1 1 0 GetMode
2 1 0 0 Wait (see Section 7.1.10 for description)
1 0 1 0 SCI
0 0 0 0 Parallel IO
EMU x x 1 Emulation Boot
7.1.9.1 Emulation Boot

When the JTAG debug probe is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In
this case, the boot ROM detects that a JTAG debug probe is connected and uses the contents of two reserved
SARAM locations in the PIE vector table to determine the boot mode. If the content of either location is invalid,
then the Wait boot option is used. All boot mode options can be accessed in emulation boot.
7.1.9.2 GetMode
The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another boot
option by programming two locations in the OTP. If the content of either OTP location is invalid, then boot to flash
is used. One of the following loaders can be specified: SCI, SPI, I2C, CAN, or OTP.
7.1.9.3 Peripheral Pins Used by the Bootloader
Table 7-2 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table to see if
these conflict with any of the peripherals you would like to use in your application.
Table 7-2. Peripheral Bootload Pins
BOOTLOADER PERIPHERAL LOADER PINS
SCI SCIRXDA (GPIO28)
SCITXDA (GPIO29)
Parallel Boot Data (GPIO31,30,5:0)
28x Control (AIO6)
Host Control (AIO12)
SPI SPISIMOA (GPIO16)
SPISOMIA (GPIO17)
SPICLKA (GPIO18)
SPISTEA (GPIO19)
I2C SDAA (GPIO32)
SCLA (GPIO33)
CAN CANRXA (GPIO30)
CANTXA (GPIO31)

TMS320F28035, TMS320F28035-Q1
7.1.10 Security
The devices support high levels of security to protect the user firmware from being reverse engineered. The
security features a 128-bit password (hardcoded for 16 wait states), which the user programs into the flash.
One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security
feature prevents unauthorized users from examining the memory contents through the JTAG port or trying to
boot-load some undesirable software that would export the secure memory contents. To enable access to the
secure blocks, the user must write the correct 128-bit KEY value that matches the value stored in the password
locations within the Flash.
In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent unauthorized
users from stepping through secure code. Any code or data access to flash, user OTP, or Lx memory while
the JTAG debug probe is connected will trip the ECSL and break the debug probe connection. To allow debug
of secure code, while maintaining the CSM protection against secure memory reads, the user must write the
correct value into the lower 64 bits of the KEY register (KEY0–KEY3), which matches the value stored in
the lower 64 bits of the password locations (PWL0–PWL3) within the flash. Dummy reads of all 128 bits of
the password in the flash must still be performed. If the lower 64 bits of the password locations are all ones
(unprogrammed), then the KEY value does not need to match. During debug of secure code, operations like
single-stepping is possible. However, the actual contents of the secure memory cannot be seen in the CCS
window.
When power is applied to a secure device that is connected to a JTAG debug probe, the CPU will start executing
and may execute an instruction that performs an access to a protected area. If this happens, the ECSL will trip
and cause the JTAG circuitry to be deactivated. Under this condition, a host (such as a computer running CCS or
flash programing software) would not be able to establish connection with the device.
The solution is to use the Wait boot option. In this mode, code loops around a software breakpoint to allow a
JTAG debug probe to be connected without tripping security. The user can then exit this mode once the JTAG
debug probe is connected by using one of the emulation boot options as described in the Boot ROM chapter
in the TMS320F2803x Real-Time Microcontrollers Technical Reference Manual. These devices do not support a
hardware wait-in-reset mode.
If reprogramming of a secure device via JTAG is desired, it is important to put in the needed hooks in the board
design to be able to put the device in Wait boot mode upon power-up. Otherwise, ECSL may deactivate the
JTAG circuitry and prevent connection to the device, as mentioned earlier.
Note
• When the code-security passwords are programmed, all addresses from 0x3F7F80 to 0x3F7FF5
cannot be used as program code or data. These locations must be programmed to 0x0000.
• If reprogramming of a secure device via JTAG may be needed in future, it is important to design
the board in such a way that the device could be put in Wait boot mode upon power-up (when
reprogramming is warranted). Otherwise, ECSL may deactivate the JTAG circuitry and prevent
connection to the device, as mentioned earlier. If reconfiguring the device for Wait boot mode in
the field is not practical, some mechanism must be implemented in the firmware to detect when a
firmware update is warranted. Code could then branch to the desired bootloader in the bootROM. It
could also branch to the Wait bootmode, at which point the JTAG debug probe could be connected,
device unsecured and programming accomplished through JTAG itself.
• If the code security feature is not used, addresses 0x3F7F80 to 0x3F7FEF may be used for code
or data. Addresses 0x3F7FF0 to 0x3F7FF5 are reserved for data and should not contain program
code.
The 128-bit password (at 0x3F 7FF8 to 0x3F 7FFF) must not be programmed to zeros. Doing so
would permanently lock the device.

TMS320F28035, TMS320F28035-Q1
Code Security Module Disclaimer

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM
OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS
STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS
FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
7.1.11 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE
block can support up to 96 peripheral interrupts. On the F2803x, 56 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines
(INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that
can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes
8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to
interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can
be enabled/disabled within the PIE block.
7.1.12 External Interrupts (XINT1–XINT3)
The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be selected
for negative, positive, or both negative and positive edge triggering and can also be enabled/disabled. These
interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is
detected. This counter can be used to accurately time stamp the interrupt. There are no dedicated pins for the
external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from GPIO0–GPIO31 pins.
7.1.13 Internal Zero Pin Oscillators, Oscillator, and PLL
The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal
attached to the on-chip oscillator circuit . A PLL is provided supporting up to 12 input-clock-scaling ratios. The
PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower
power operation is desired. Refer to Section 6, Electrical Specifications, for timing details. The PLL block can be
set in bypass mode.
7.1.14 Watchdog
Each device contains two watchdogs: CPU watchdog that monitors the core and NMI watchdog that is a missing
clock-detect circuit. The user software must regularly reset the CPU watchdog counter within a certain time
frame; otherwise, the CPU watchdog generates a reset to the processor. The CPU watchdog can be disabled if
necessary. The NMI watchdog engages only in case of a clock failure and can either generate an interrupt or a
device reset.

TMS320F28035, TMS320F28035-Q1
7.1.15 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative
to the CPU clock.
7.1.16 Low-power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE: Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that must function during IDLE are left operating. An enabled interrupt
from an active peripheral or the watchdog timer will wake the processor from IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event
HALT: This mode basically shuts down the device and places it in the lowest possible power
consumption mode. If the internal zero-pin oscillators are used as the clock source, the
HALT mode turns them off, by default. To keep these oscillators from shutting down, the
INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin oscillators may thus
be used to clock the CPU watchdog in this mode. If the on-chip crystal oscillator is used
as the clock source, it is shut down in this mode. A reset or an external signal (through a
GPIO pin) or the CPU watchdog can wake the device from this mode.
The CPU clock (OSCCLK) and watchdog clock source should be from the same clock source before attempting
to put the device into HALT or STANDBY.

TMS320F28035, TMS320F28035-Q1
7.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)

The device segregates peripherals into four sections. The mapping of peripherals is as follows:
PF0: PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash: Flash Wait-State Registers
Timers: CPU-Timers 0, 1, 2 Registers
CSM: Code Security Module KEY Registers
ADC: ADC Result Registers
CLA Control Law Accelerator Registers and Message RAMs
PF1: GPIO: GPIO MUX Configuration and Control Registers
eCAN: Enhanced Control Area Network Configuration and Control Registers
LIN: Local Interconnect Network Configuration and Control Registers
eCAP: Enhanced Capture Module and Registers
eQEP: Enhanced Quadrature Encoder Pulse Module and Registers
HRCAP: High-Resolution Capture Module and Registers
PF2: SYS: System Control Registers
SCI: Serial Communications Interface (SCI) Control and RX/TX Registers
SPI: Serial Port Interface (SPI) Control and RX/TX Registers
ADC: ADC Status, Control, and Configuration Registers
I2C: Inter-Integrated Circuit Module and Registers
XINT: External Interrupt Registers
PF3: ePWM: Enhanced Pulse Width Modulator Module and Registers
HRPWM: High-Resolution Pulse-Width Modulator Registers
Comparators: Comparator Modules
7.1.18 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables
the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured
as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific
inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches.
The GPIO signals can also be used to bring the device out of specific low-power modes.
7.1.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling.
The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches
zero, it is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and can
be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. It is connected to INT14 of the CPU.
If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
• SYSCLKOUT (default)
• Internal zero-pin oscillator 1 (INTOSC1)
• Internal zero-pin oscillator 2 (INTOSC2)
• External clock source

TMS320F28035, TMS320F28035-Q1
7.1.20 Control Peripherals

The devices support the following peripherals that are used for embedded control and communication:
ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation,

adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip
mechanism. Some of the PWM pins support the HRPWM high resolution duty and
period features. The type 1 module found on 2803x devices also supports increased
dead-band resolution, enhanced SOC and interrupt generation, and advanced
triggering including trip functions based on comparator outputs.
eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
eQEP: The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit unit timer.
This peripheral has a watchdog timer to detect motor stall and input error detection logic
to identify simultaneous edge transition in QEP signals.
ADC: The ADC block is a 12-bit converter. It has up to 16 single-ended channels pinned
out, depending on the device. It contains two sample-and-hold units for simultaneous
sampling.
Comparator: Each comparator block consists of one analog comparator along with an internal 10-bit
reference for supplying one input of the comparator.
HRCAP: The high-resolution capture peripheral operates in normal capture mode through a
16-bit counter clocked off of the HCCAPCLK or in high-resolution capture mode by
utilizing built-in calibration logic in conjunction with a TI-supplied calibration library.
7.1.21 Serial Port Peripherals

The devices support the following serial communication peripherals:
SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream
of programmed length (1 to 16 bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between
the MCU and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multidevice communications are supported by the master/slave
operation of the SPI. The SPI contains a 4-level receive and transmit FIFO for reducing
interrupt servicing overhead.
SCI: The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. The SCI contains a 4-level receive and transmit FIFO for reducing
interrupt servicing overhead.
I2C: The inter-integrated circuit (I2C) module provides an interface between an MCU
and other devices compliant with Philips Semiconductors Inter-IC bus ( I2C-bus®)
specification version 2.1 and connected by way of an I2C-bus. External components
attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the MCU
through the I2C module. The I2C contains a 4-level receive and transmit FIFO for
reducing interrupt servicing overhead.
eCAN: This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is compliant with ISO11898-1 (CAN 2.0B).
LIN: LIN 1.3 or 2.0 compatible peripheral. Can also be configured as additional SCI port

TMS320F28035, TMS320F28035-Q1
7.2 Memory Maps

In Figure 7-1 through Figure 7-4, the following apply:
• Memory blocks are not to scale.
• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are
restricted to data memory only. A user program cannot access these memory maps in program space.
• Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order.
• Certain memory ranges are EALLOW protected against spurious writes after configuration.
• Locations 0x3D7C80 to 0x3D7CC0 contain the internal oscillator and ADC calibration routines. These
locations are not programmable by the user.

TMS320F28035, TMS320F28035-Q1
Data Space Prog Space

0x00 0000 M0 Vector RAM (Enabled if VMAP = 0)
0x00 0040 M0 SARAM (1K ´ 16, 0-Wait)
0x00 0400 M1 SARAM (1K ´ 16, 0-Wait)
0x00 0800 Peripheral Frame 0
0x00 0D00
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00 Peripheral Frame 0
0x00 1400 CLA Registers
0x00 1480 CLA-to-CPU Message RAM
0x00 1500 CPU-to-CLA Message RAM
0x00 2000 Reserved
(1K ´ 16, Protected)
(1.5K ´ 16, Protected)
Reserved
0x00 6A00 Peripheral Frame 1
0x00 8000 L0 SARAM (2K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual-Mapped)
0x00 8800 L1 DPSARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)
0x00 8C00 L2 DPSARAM (1K ´ 16)
0x00 9000 L3 DPSARAM (4K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Prog RAM)
0x00 A000 Reserved
0x3D 7800 User OTP (1K ´ 16, Secure Zone + ECSL)
0x3D 7C00
Reserved
0x3D 7C80
Calibration Data
0x3D 7CC0
Get_mode function
0x3D 7CE0
Reserved
0x3D 7E80
PARTID
Calibration Data
0x3D 7EB0
Reserved
0x3E 8000
FLASH
(64K ´ 16, 8 Sectors, Secure Zone + ECSL)
0x3F 7FF8 128-Bit Password
0x3F 8000
L0 SARAM (2K ´ 16)
0x3F 8800 Reserved
0x3F E000 Boot ROM (8K ´ 16, 0-Wait)
0x3F FFC0
Vector (32 Vectors, Enabled if VMAP = 1)
A. CLA-specific registers and RAM apply to the 28035 device only.

B. Memory locations 0x3D7E80-0x3D7EAF are reserved in TMX silicon.
Figure 7-1. 28034/28035 Memory Map

TMS320F28035, TMS320F28035-Q1

0x00 0040 M0 SARAM (1K ´ 16, 0-Wait)
0x00 0400 M1 SARAM (1K ´ 16, 0-Wait)
0x00 0D00
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 1400 CLA Registers
0x00 1480 CLA-to-CPU Message RAM
0x00 1500 CPU-to-CLA Message RAM
0x00 2000 Reserved
Reserved
0x00 8000 L0 SARAM (2K ´ 16)
0x00 8800 L1 DPSARAM (1K ´ 16)
0x00 8C00 L2 DPSARAM (1K ´ 16)
0x00 9000 L3 DPSARAM (4K ´ 16)
0x00 A000 Reserved
0x3D 7C00
Reserved
0x3D 7C80
Calibration Data
0x3D 7CC0
Get_mode function
0x3D 7CE0
Reserved
0x3D 7E80
PARTID
Calibration Data
0x3D 7EB0
Reserved
0x3F 0000
FLASH
0x3F 8000
L0 SARAM (2K ´ 16)
0x3F 8800 Reserved
0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1)
A. CLA-specific registers and RAM apply to the 28033 device only.

B. Memory locations 0x3D7E80-0x3D7EAF are reserved in TMX silicon.
Figure 7-2. 28032/28033 Memory Map

TMS320F28035, TMS320F28035-Q1

0x00 0040 M0 SARAM (1K ´ 16, 0-Wait)
0x00 0400 M1 SARAM (1K ´ 16, 0-Wait)
0x00 0D00
PIE Vector - RAM
(256 ´ 16)
(Enabled if Reserved
VMAP = 1,
ENPIE = 1)

0x00 2000 Reserved
Reserved
0x00 8000 L0 SARAM (2K ´ 16)
0x00 8800 L1 DPSARAM (1K ´ 16)
0x00 8C00 L2 DPSARAM (1K ´ 16)
0x00 9000 L3 DPSARAM (2K ´ 16)
0x00 9800 Reserved
0x3D 7C00
Reserved
0x3D 7C80
Calibration Data
0x3D 7CC0
Get_mode function
0x3D 7CE0
Reserved
0x3D 7E80
PARTID
Calibration Data
0x3D 7EB0
Reserved
0x3F 0000
FLASH
0x3F 8000
L0 SARAM (2K ´ 16)
0x3F 8800 Reserved
0x3F FFC0
A. Memory locations 0x3D7E80-0x3D7EAF are reserved in TMX silicon.
Figure 7-3. 28031 Memory Map

TMS320F28035, TMS320F28035-Q1

0x00 0040 M0 SARAM (1K ´ 16, 0-Wait)
0x00 0400 M1 SARAM (1K ´ 16, 0-Wait)
0x00 0D00
PIE Vector - RAM
(256 ´ 16)
(Enabled if Reserved
VMAP = 1,
ENPIE = 1)

0x00 2000 Reserved
Reserved
0x00 8000 L0 SARAM (2K ´ 16)
0x00 8800 L1 DPSARAM (1K ´ 16)
0x00 8C00 L2 DPSARAM (1K ´ 16)
0x00 9000
Reserved
0x00 A000 Reserved

0x3D 7C00
Reserved
0x3D 7C80
Calibration Data
0x3D 7CC0
Get_mode function
0x3D 7CE0
Reserved
0x3D 7E80
PARTID
Calibration Data
0x3D 7EB0
Reserved
0x3F 4000
FLASH
0x3F 8000
L0 SARAM (2K ´ 16)
0x3F 8800 Reserved
0x3F FFC0
A. Memory locations 0x3D7E80-0x3D7EAF are reserved in TMX silicon.
Figure 7-4. 28030 Memory Map

TMS320F28035, TMS320F28035-Q1
Table 7-3. Addresses of Flash Sectors in F28034/28035

ADDRESS RANGE PROGRAM AND DATA SPACE
0x3E 8000 to 0x3E 9FFF Sector H (8K × 16)
0x3E A000 to 0x3E BFFF Sector G (8K × 16)
0x3E C000 to 0x3E DFFF Sector F (8K × 16)
0x3E E000 to 0x3E FFFF Sector E (8K × 16)
0x3F 0000 to 0x3F 1FFF Sector D (8K × 16)
0x3F 2000 to 0x3F 3FFF Sector C (8K × 16)
0x3F 4000 to 0x3F 5FFF Sector B (8K × 16)
0x3F 6000 to 0x3F 7F7F Sector A (8K × 16)
Program to 0x0000 when using the
0x3F 7F80 to 0x3F 7FF5
Code Security Module
Boot-to-Flash Entry Point
0x3F 7FF6 to 0x3F 7FF7
(program branch instruction here)
Security Password (128-Bit)
0x3F 7FF8 to 0x3F 7FFF
(Do not program to all zeros)
Table 7-4. Addresses of Flash Sectors in F28031/28032/28033

0x3F 0000 to 0x3F 0FFF Sector H (4K × 16)
0x3F 1000 to 0x3F 1FFF Sector G (4K × 16)
0x3F 2000 to 0x3F 2FFF Sector F (4K × 16)
0x3F 3000 to 0x3F 3FFF Sector E (4K × 16)
Table 7-5. Addresses of Flash Sectors in F28030


TMS320F28035, TMS320F28035-Q1
Note
• When the code-security passwords are programmed, all addresses from 0x3F 7F80 to 0x3F 7FF5
cannot be used as program code or data. These locations must be programmed to 0x0000.
• If the code security feature is not used, addresses 0x3F 7F80 to 0x3F 7FEF may be used for code
or data. Addresses 0x3F 7FF0 to 0x3F 7FF5 are reserved for data and should not contain program
code.
Table 7-6 shows how to handle these memory locations.
Table 7-6. Impact of Using the Code Security Module

FLASH
ADDRESS
CODE SECURITY ENABLED CODE SECURITY DISABLED
0x3F 7F80 to 0x3F 7FEF Application code and data
Fill with 0x0000
0x3F 7FF0 to 0x3F 7FF5 Reserved for data only
Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks
to be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks
happen as written. Because of the pipeline, a write immediately followed by a read to different memory locations,
will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The CPU supports a block protection
mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles
are added to align the operations). This mode is programmable and by default, it protects the selected zones.
The wait states for the various spaces in the memory map area are listed in Table 7-7.
Table 7-7. Wait States
AREA WAIT STATES (CPU) COMMENTS
M0 and M1 SARAMs 0-wait Fixed
Peripheral Frame 0 0-wait
Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready.
2-wait (reads) Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
Peripheral Frame 2 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral.
2-wait (reads)
Peripheral Frame 3 0-wait (writes) Assumes no conflict between CPU and CLA.
2-wait (reads) Cycles can be extended by peripheral-generated ready.
L0 SARAM 0-wait data and program Assumes no CPU conflicts
OTP Programmable Programmed through the Flash registers.
1-wait minimum 1-wait is minimum number of wait states allowed.
FLASH Programmable Programmed through the Flash registers.
0-wait Paged min
1-wait Random min
Random ≥ Paged
FLASH Password 16-wait fixed Wait states of password locations are fixed.
Boot-ROM 0-wait

TMS320F28035, TMS320F28035-Q1
7.3 Register Maps

The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 7-8.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table
7-9.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table
7-10.
Peripheral Frame 3: These are peripherals that are mapped to the 32-bit peripheral bus and are
accessible by the CLA. See Table 7-11.
Table 7-8. Peripheral Frame 0 Registers
NAME(1) ADDRESS RANGE SIZE (×16) EALLOW PROTECTED(2)
Device Emulation Registers 0x00 0880 to 0x00 0984 261 Yes
System Power Control Registers 0x00 0985 to 0x00 0987 3 Yes
FLASH Registers(3) 0x00 0A80 to 0x00 0ADF 96 Yes
Code Security Module Registers 0x00 0AE0 to 0x00 0AEF 16 Yes
ADC registers (0 wait read only) 0x00 0B00 to 0x00 0B0F 16 No
CPU–TIMER0/1/2 Registers 0x00 0C00 to 0x00 0C3F 64 No
PIE Registers 0x00 0CE0 to 0x00 0CFF 32 No
PIE Vector Table 0x00 0D00 to 0x00 0DFF 256 No
CLA Registers 0x00 1400 to 0x00 147F 128 Yes
CLA to CPU Message RAM (CPU writes ignored) 0x00 1480 to 0x00 14FF 128 NA
CPU to CLA Message RAM (CLA writes ignored) 0x00 1500 to 0x00 157F 128 NA
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.

(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).

NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED
eCAN-A registers 0x00 6000 to 0x00 61FF 512 (1)
eCAP1 registers 0x00 6A00 to 0x00 6A1F 32 No

HRCAP1 registers 0x00 6AC0 to 0x00 6ADF 32 (1)
HRCAP2 registers 0x00 6AE0 to 0x00 6AFF 32 (1)
eQEP1 registers 0x00 6B00 to 0x00 6B3F 64 (1)
LIN-A registers 0x00 6C00 to 0x00 6C7F 128 (1)
GPIO registers 0x00 6F80 to 0x00 6FFF 128 (1)
(1) Some registers are EALLOW protected. For more information, see the TMS320F2803x Real-Time Microcontrollers Technical
Reference Manual.

TMS320F28035, TMS320F28035-Q1

System Control Registers 0x00 7010 to 0x00 702F 32 Yes
SPI-A Registers 0x00 7040 to 0x00 704F 16 No
SCI-A Registers 0x00 7050 to 0x00 705F 16 No
NMI Watchdog Interrupt Registers 0x00 7060 to 0x00 706F 16 Yes
External Interrupt Registers 0x00 7070 to 0x00 707F 16 Yes
ADC Registers 0x00 7100 to 0x00 717F 128 (1)
I2C-A Registers 0x00 7900 to 0x00 793F 64 (1)
SPI-B Registers 0x00 7740 to 0x00 774F 16 No
Reference Manual.

Comparator 1 registers 0x00 6400 to 0x00 641F 32 (1)
ePWM1 + HRPWM1 registers 0x00 6800 to 0x00 683F 64 (1)
ePWM3 + HRPWM3 registers 0x00 6880 to 0x00 68BF 64 (1)
ePWM4 + HRPWM4 registers 0x00 68C0 to 0x00 68FF 64 (1)
ePWM7 + HRPWM7 registers 0x00 6980 to 0x00 69BF 64 (1)
Reference Manual.

TMS320F28035, TMS320F28035-Q1
7.4 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 7-12 .
Table 7-12. Device Emulation Registers
ADDRESS EALLOW
NAME SIZE (x16) DESCRIPTION
RANGE PROTECTED
0x0880
DEVICECNF 2 Device Configuration Register Yes
0x0881
PARTID(1) 0x3D 7E80 1 Part ID Register TMS320F28035PN 0x00BF
TMS320F28035PAG 0x00BE
TMS320F28035RSH 0x00BD
TMS320F28034PN 0x00BB
TMS320F28034PAG 0x00BA
TMS320F28034RSH 0x00B9
TMS320F28033PN 0x00B7
TMS320F28033PAG 0x00B6
No
TMS320F28032PN 0x00B3
TMS320F28032PAG 0x00B2
TMS320F28031PN 0x00AF
TMS320F28031PAG 0x00AE
TMS320F28031RSH 0x00AD
TMS320F28030PN 0x00AB
TMS320F28030PAG 0x00AA
TMS320F28030RSH 0x00A9
CLASSID 0x0882 1 Class ID Register TMS320F28035 0x00BF
TMS320F28034 0x00BB
TMS320F28033 0x00B7
No
TMS320F28032 0x00B3
TMS320F28031 0x00AF
TMS320F28030 0x00AB
REVID 0x0883 1 Revision ID
0x0000 - Silicon Rev. 0 - TMS
Register No
0x0001 - Silicon Rev. A - TMS
(1) For TMS320F2803x devices, the PARTID register location differs from the TMS320F2802x devices' location of 0x3D7FFF.

TMS320F28035, TMS320F28035-Q1
7.5 VREG/BOR/POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage
regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and space of a
second external regulator on an application board. Additionally, internal power-on reset (POR) and brown-out
reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode.
7.5.1 On-chip Voltage Regulator (VREG)
A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors are
required on each V DD pin to stabilize the generated voltage, power need not be supplied to these pins to operate
the device. Conversely, the VREG can be disabled, should power or redundancy be the primary concern of the
application.
7.5.1.1 Using the On-chip VREG
To use the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended operating
voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic
will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum) capacitance for proper
regulation of the VREG. These capacitors should be located as close as possible to the VDD pins. Driving an
external load with the internal VREG is not supported.
7.5.1.2 Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the VDD
pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied high.

TMS320F28035, TMS320F28035-Q1
7.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the burden
of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is to create
a clean reset throughout the device during the entire power-up procedure. The trip point is a looser, lower trip
point than the BOR, which watches for dips in the VDD or VDDIO rail during device operation. The POR function
is present on both VDD and VDDIO rails at all times. After initial device power-up, the BOR function is present on
VDDIO at all times, and on VDD when the internal VREG is enabled ( VREGENZ pin is tied low). Both functions
tie the XRS pin low when one of the voltages is below their respective trip point. VDD BOR and overvoltage
trip points are outside of the recommended operating voltages. Proper device operation cannot be ensured. If
overvoltage or undervoltage conditions affecting the system is a concern for an application, an external voltage
supervisor should be added. Figure 7-5 shows the VREG, POR, and BOR. To disable both the VDD and VDDIO
BOR functions, a bit is provided in the BORCFG register. For details, see the System Control chapter in the
TMS320F2803x Real-Time Microcontrollers Technical Reference Manual.
In
I/O Pin
Out
(Force Hi-Z When High)
DIR (0 = Input, 1 = Output)
Internal SYSRS
Weak PU
Deglitch SYSCLKOUT
Filter
WDRST Sync RS
C28
Core
MCLKRS
JTAG
TCK
PLL Detect
XRS
+ Logic
Pin
Clocking
Logic
VREGHALT
(A)
WDRST
PBRS
(B) POR/BOR On-Chip
Generating Voltage
Module VREGENZ
Regulator
(VREG)
A. WDRST is the reset signal from the CPU watchdog.

B. PBRS is the reset signal from the POR/BOR module.
Figure 7-5. VREG + POR + BOR + Reset Signal Connectivity

TMS320F28035, TMS320F28035-Q1
7.6 System Control

This section describes the oscillator and clocking mechanisms, the watchdog function and the low-power modes.
Table 7-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME ADDRESS SIZE (x16) DESCRIPTION(1)
BORCFG 0x00 0985 1 BOR Configuration Register
XCLK 0x00 7010 1 XCLKOUT Control
PLLSTS 0x00 7011 1 PLL Status Register
CLKCTL 0x00 7012 1 Clock Control Register
PLLLOCKPRD 0x00 7013 1 PLL Lock Period
INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register
INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register
PCLKCR2 0x00 7019 1 Peripheral Clock Control Register 2
LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register
PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0
PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1
LPMCR0 0x00 701E 1 Low-Power Mode Control Register 0
PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3
PLLCR 0x00 7021 1 PLL Control Register
SCSR 0x00 7022 1 System Control and Status Register
WDCNTR 0x00 7023 1 Watchdog Counter Register
WDKEY 0x00 7025 1 Watchdog Reset Key Register
WDCR 0x00 7029 1 Watchdog Control Register
(1) All registers in this table are EALLOW protected.

TMS320F28035, TMS320F28035-Q1
Figure 7-6 shows the various clock domains that are discussed. Figure 7-7 shows the various clock sources
(both internal and external) that can provide a clock for device operation.
PCLKCR0/1/2/3 LOSPCP SYSCLKOUT

(System Ctrl Regs) (System Ctrl Regs) C28x Core CLKIN
Clock Enables LSPCLK
Peripheral
I/O SPI-A, SPI-B, SCI-A
Registers PF2
Clock Enables /2
Peripheral
I/O eCAN-A, LIN-A
Registers PF1
Clock Enables
GPIO Peripheral
I/O eCAP1, eQEP1, HRCAP1/2
Mux Registers PF1
Clock Enables
Peripheral
I/O ePWM1/.../7, HRPWM1/.../7
Registers PF3
Clock Enables
Peripheral
I/O I2C-A
Registers PF2
Clock Enables
ADC PF2
16 Ch 12-Bit ADC Registers
Analog PF0
GPIO
Mux Clock Enables
COMP
6 COMP1/2/3 Registers PF3
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT).
Figure 7-6. Clock and Reset Domains

TMS320F28035, TMS320F28035-Q1
A. Register loaded from TI OTP-based calibration function.

B. See Section 7.6.4 for details on missing clock detection.
Figure 7-7. Clock Tree

TMS320F28035, TMS320F28035-Q1
7.6.1 Internal Zero Pin Oscillators

The F2803x devices contain two independent internal zero pin oscillators. By default both oscillators are turned
on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused
oscillators may be powered down by the user. The center frequency of these oscillators is determined by their
respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See
Section 6, Electrical Specifications, for more information on these oscillators.
7.6.2 Crystal Oscillator Option
The on-chip crystal oscillator X1 and X2 pins are 1.8-V level signals and must never have 3.3-V level signals
applied to them. If a system 3.3-V external oscillator is to be used as a clock source, it should be connected to
the XCLKIN pin only. The X1 pin is not intended to be used as a single-ended clock input, it should be used with
X2 and a crystal.
The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in Table
7-14. Furthermore, ESR range = 30 to 150 Ω. For Table 7-14, Cshunt should be less than or equal to 5 pF.
Table 7-14. Typical Specifications for External Quartz Crystal
FREQUENCY (MHz) Rd (Ω) CL1 (pF) CL2 (pF)
5 2200 18 18
10 470 15 15
15 0 15 15
20 0 12 12
XCLKIN/GPIO19/38 X1 X2
Turn off Rd
XCLKIN path
in CLKCTL
register
CL1 Crystal CL2
Figure 7-8. Using the On-chip Crystal Oscillator
Note
1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the IC and
crystal. The value is usually approximately twice the value of the crystal's load capacitance.
2. The load capacitance of the crystal is described in the crystal specifications of the manufacturers.
3. TI recommends that customers have the resonator/crystal vendor characterize the operation of
their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise
to tune the tank circuit. The vendor can also advise the customer regarding the proper tank
component values that will produce proper start-up and stability over the entire operating range.

TMS320F28035, TMS320F28035-Q1
XCLKIN/GPIO19/38 X1 X2
External Clock Signal NC

(Toggling 0−VDDIO)
Figure 7-9. Using a 3.3-V External Oscillator
7.6.3 PLL-Based Clock Module

The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to
select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.
It can be re-enabled (if need be) after the PLL module has stabilized, which takes
1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL
(VCOCLK) is at least 50 MHz.
Table 7-15. PLL Settings
SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE(2) (3)
PLLSTS[DIVSEL] = 0 or 1(1) PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3
0000 (PLL bypass) OSCCLK/4 (Default)(2) OSCCLK/2 OSCCLK
0001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 (OSCCLK * 1)/1
(1) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
(2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic has no effect.
(3) This register is EALLOW protected. See the System Control chapter in the TMS320F2803x Real-Time Microcontrollers Technical
Reference Manual for more information.
Table 7-16. CLKIN Divide Options

PLLSTS [DIVSEL] CLKIN DIVIDE
0 /4
1 /4
2 /2
3 /1

TMS320F28035, TMS320F28035-Q1
The PLL-based clock module provides four modes of operation:

• INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide the clock
for the Watchdog block, core and CPU-Timer 2
• INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide the clock
for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be independently chosen
for the Watchdog block, core and CPU-Timer 2.
• Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/
resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2
pins. Some devices may not have the X1/X2 pins. See Table 5-1 for details.
• External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to be
bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin. The
XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as GPIO19 or
GPIO38 through the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables this clock input
(forced low). If the clock source is not used or the respective pins are used as GPIOs, the user should disable
at boot time.
Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock
source must be disabled (using the CLKCTL register) before switching clocks.
Table 7-17. Possible PLL Configuration Modes
CLKIN AND
PLL MODE REMARKS PLLSTS[DIVSEL]
SYSCLKOUT
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL
block is disabled in this mode. This can be useful to reduce system noise and for 0, 1 OSCCLK/4
PLL Off low-power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass) 2 OSCCLK/2
before entering this mode. The CPU clock (CLKIN) is derived directly from the 3 OSCCLK/1
input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass is the default PLL configuration upon power-up or after an external
0, 1 OSCCLK/4
reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000
PLL Bypass 2 OSCCLK/2
or while the PLL locks to a new frequency after the PLLCR register has been
3 OSCCLK/1
modified. In this mode, the PLL is bypassed but the PLL is not turned off.
0, 1 OSCCLK * n/4
Achieved by writing a nonzero value n into the PLLCR register. Upon writing to the
PLL Enable 2 OSCCLK * n/2
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
3 OSCCLK * n/1
7.6.4 Loss of Input Clock (NMI Watchdog Function)

The 2803x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1/INTOSC2), the
on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and
PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limp-mode clock at its output. This
limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–5 MHz.
When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.
Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately
or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the Missing Clock Status
(MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock failure and
initiate necessary corrective action such as switching over to an alternative clock source (if available) or initiate a
shut-down procedure for the system.
If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a
preprogrammed time interval. Figure 7-10 shows the interrupt mechanisms involved.

TMS320F28035, TMS320F28035-Q1
NMIFLG[NMINT]
NMIFLGCLR[NMINT] Clear
Latch
Set Clear
XRS
Generate NMIFLG[CLOCKFAIL]
Interrupt 1 0
Clear NMIFLGCLR[CLOCKFAIL]
NMINT Pulse
When 0 Latch CLOCKFAIL
SYNC?
Input = 1
Clear Set SYSCLKOUT
NMICFG[CLOCKFAIL]
NMIFLGFRC[CLOCKFAIL]
XRS
SYSCLKOUT
SYSRS
NMIWDPRD[15:0]
NMI Watchdog NMIRS See System
NMIWDCNT[15:0] Control Section
Figure 7-10. NMI Watchdog
7.6.5 CPU Watchdog Module

The CPU watchdog module on the 2803x device is similar to the one used on the 281x/280x/283xx devices.
This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up
counter has reached its maximum value. To prevent this, the user must disable the counter or the software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets the watchdog counter.
Figure 7-11 shows the various functional blocks within the watchdog module.
Normally, when the input clocks are present, the CPU watchdog counter decrements to initiate a CPU watchdog
reset or WDINT interrupt. However, when the external input clock fails, the CPU watchdog counter stops
decrementing (that is, the watchdog counter does not change with the limp-mode clock).
Note
The CPU watchdog is different from the NMI watchdog. It is the legacy watchdog that is present in all
28x devices.
Note
Applications in which the correct CPU operating frequency is absolutely critical should implement a
mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example,
an R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully
charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from
getting fully charged. Such a circuit would also help in detecting failure of the flash memory.

TMS320F28035, TMS320F28035-Q1
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 7-11. CPU Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the CPU watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can
wake the device from STANDBY (if enabled). See Section 7.7, Low-power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU out of
IDLE mode.
In HALT mode, the CPU watchdog can be used to wake up the device through a device reset.

TMS320F28035, TMS320F28035-Q1
7.7 Low-power Modes Block

Table 7-18 summarizes the various modes.
Table 7-18. Low-power Modes
MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT(1)
XRS, CPU watchdog interrupt, any
IDLE 00 On On On
enabled interrupt
On XRS, CPU watchdog interrupt, GPIO
STANDBY 01 Off Off
(CPU watchdog still running) Port A signal, debugger(2)
Off
(on-chip crystal oscillator and PLL
XRS, GPIO Port A signal, debugger(2),
HALT(3) 1X turned off, zero-pin oscillator and Off Off
CPU watchdog
CPU watchdog state dependent
on user code.)
(1) The EXIT column lists which signals or under what conditions the low-power mode is exited. A low signal, on any of the signals, exits
the low-power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the
low-power mode will not be exited and the device will go back into the indicated low-power mode.
(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.
(3) The WDCLK must be active for the device to go into HALT mode.
The various low-power modes operate as follows:

IDLE Mode: This mode is exited by any enabled interrupt that is recognized by the processor.
The LPM block performs no tasks during this mode as long as the LPMCR0(LPM)
bits are set to 0,0.
STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode.
The user must select which signal(s) will wake the device in the GPIOLPMSEL
register. The selected signal(s) are also qualified by the OSCCLK before waking
the device. The number of OSCCLKs is specified in the LPMCR0 register.
HALT Mode: CPU watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the
device from HALT mode. The user selects the signal in the GPIOLPMSEL
register.
Note
The low-power modes do not affect the state of the output pins (PWM pins included). They will be
in whatever state the code left them in when the IDLE instruction was executed. See the System
Control chapter in the TMS320F2803x Real-Time Microcontrollers Technical Reference Manual for
more details.

TMS320F28035, TMS320F28035-Q1
7.8 Interrupts
Figure 7-12 shows how the various interrupt sources are multiplexed.
Peripherals
2
(SPI, SCI, ePWM, I C, HRPWM, HRCAP,
eCAP, ADC, eQEP, CLA, LIN, eCAN)
WDINT
WAKEINT Watchdog
Sync LPMINT
Low Power Modes
SYSCLKOUT
XINT1
MUX
XINT1
Interrupt Control
XINT1CR(15:0)
Up to 96 Interrupts XINT1CTR(15:0)
GPIOXINT1SEL(4:0)
INT1 XINT2SOC
PIE
to ADC
INT12 XINT2
MUX
Interrupt Control XINT2
XINT2CR(15:0)
C28
Core XINT2CTR(15:0)
GPIOXINT2SEL(4:0)
GPIO0.int
XINT3
MUX
XINT3 GPIO
Interrupt Control
MUX
XINT3CR(15:0)
GPIO31.int
XINT3CTR(15:0)
GPIOXINT3SEL(4:0)
TINT0
CPU TIMER 0
INT13 TINT1
CPU TIMER 1
INT14 TINT2
CPU TIMER 2
CPUTMR2CLK
CLOCKFAIL System Control

NMI NMI interrupt with watchdog function
NMIRS (See the System
(See the NMI Watchdog section.)
Control section.)
Figure 7-12. External and PIE Interrupt Sources

TMS320F28035, TMS320F28035-Q1
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. Table 7-19 shows the interrupts used by 2803x devices.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding
to the vector specified. The TRAP #0 instruction attempts to transfer program control to the address pointed to
by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, the TRAP #0
instruction should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, the TRAP #1 to TRAP #12 instructions will transfer program control to the interrupt
service routine corresponding to the first vector within the PIE group. For example: the TRAP #1 instruction
fetches the vector from INT1.1, the TRAP #2 instruction fetches the vector from INT2.1, and so forth.
IFR[12:1] IER[12:1] INTM
INT1
INT2
1
MUX CPU
0
INT11
INT12 Global
(Flag) (Enable) Enable
INTx.1
INTx.2
INTx.3 From
INTx INTx.4 Peripherals
MUX INTx.5 or
External
INTx.6
Interrupts
INTx.7
PIEACKx INTx.8
(Enable) (Flag)
(Enable/Flag)
PIEIERx[8:1] PIEIFRx[8:1]
Figure 7-13. Multiplexing of Interrupts Using the PIE Block

TMS320F28035, TMS320F28035-Q1
In Table 7-19, out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for
future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level,
provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in
from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there
are two safe cases when the reserved interrupts could be used as software interrupts:
1. No peripheral within the group is asserting interrupts.
2. No peripheral interrupts are assigned to the group (for example, PIE group 7).
Table 7-19. PIE MUXed Peripheral Interrupt Vector Table
INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1
INT1.y WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1
(LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 – (ADC) (ADC)
0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40
INT2.y Reserved EPWM7_TZINT EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
– (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
INT3.y Reserved EPWM7_INT EPWM6_INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT
– (ePWM7) (ePWM6) (ePWM5) (ePWM4) (ePWM3) (ePWM2) (ePWM1)
INT4.y HRCAP2_INT HRCAP1_INT Reserved Reserved Reserved Reserved Reserved ECAP1_INT
(HRCAP2) (HRCAP1) – – – – – (eCAP1)
INT5.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved EQEP1_INT
– – – – – – – (eQEP1)
INT6.y Reserved Reserved Reserved Reserved SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA
– – – – (SPI-B) (SPI-B) (SPI-A) (SPI-A)
INT7.y Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
– – – – – – – –
0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0
INT8.y Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A
– – – – – – (I2C-A) (I2C-A)
0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0
INT9.y Reserved Reserved ECAN1_INTA ECAN0_INTA LIN1_INTA LIN0_INTA SCITXINTA SCIRXINTA
– – (CAN-A) (CAN-A) (LIN-A) (LIN-A) (SCI-A) (SCI-A)
0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0
INT10.y ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1
(ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC)
0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0
INT11.y CLA1_INT8 CLA1_INT7 CLA1_INT6 CLA1_INT5 CLA1_INT4 CLA1_INT3 CLA1_INT2 CLA1_INT1
(CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA) (CLA)
0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0
INT12.y LUF LVF Reserved Reserved Reserved Reserved Reserved XINT3
(CLA) (CLA) – – – – – Ext. Int. 3
0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0

TMS320F28035, TMS320F28035-Q1
Table 7-20. PIE Configuration and Control Registers

NAME ADDRESS SIZE (x16) DESCRIPTION(1)
PIECTRL 0x0CE0 1 PIE, Control Register
PIEACK 0x0CE1 1 PIE, Acknowledge Register
PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register
PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register
PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register
PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register
PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register
PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register
PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register
PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register
PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register
PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register
Reserved 0x0CFA – 6 Reserved
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector
table is protected.

TMS320F28035, TMS320F28035-Q1
7.8.1 External Interrupts

Table 7-21. External Interrupt Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
XINT1CR 0x00 7070 1 XINT1 configuration register
XINT1CTR 0x00 7078 1 XINT1 counter register
XINT2CTR 0x00 7079 1 XINT2 counter register
XINT3CTR 0x00 707A 1 XINT3 counter register
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the System Control chapter in the TMS320F2803x Real-Time
Microcontrollers Technical Reference Manual.
7.8.1.1 External Interrupt Electrical Data/Timing
7.8.1.1.1 External Interrupt Timing Requirements
MIN MAX UNIT

Synchronous 1tc(SCO) cycles
tw(INT) (1) (2) Pulse duration, INT input low/high
With qualifier 1tc(SCO) + tw(IQSW) cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.15.1.2.1.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
7.8.1.1.2 External Interrupt Switching Characteristics

td(INT) (1) Delay time, INT low/high to interrupt-vector fetch tw(IQSW) + 12tc(SCO) cycles
tw(INT)
XINT1, XINT2, XINT3
td(INT)
Address bus
Interrupt Vector
(internal)
Figure 7-14. External Interrupt Timing

TMS320F28035, TMS320F28035-Q1
7.9 Peripherals
7.9.1 Control Law Accelerator (CLA) Overview
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-critical
control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster
system response and higher frequency control loops. Utilizing the CLA for time-critical tasks frees up the main
CPU to perform other system and communication functions concurrently. The following is a list of major features
of the CLA.
• Clocked at the same rate as the main CPU (SYSCLKOUT).
• An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
• Program address bus and program data bus
• Data address bus, data read bus, and data write bus
– Independent eight-stage pipeline.
– 12-bit program counter (MPC)
– Four 32-bit result registers (MR0–MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
• Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load/store operations
• The CLA program code can consist of up to eight tasks or interrupt service routines.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the CLA program memory space.
– One task is serviced at a time through to completion. There is no nesting of tasks.
– Upon task completion, a task-specific interrupt is flagged within the PIE.
– When a task finishes, the next highest-priority pending task is automatically started.
• Task trigger mechanisms:
– C28x CPU through the IACK instruction
– Task1 to Task7: the corresponding ADC or ePWM module interrupt. For example:
• Task1: ADCINT1 or EPWM1_INT
– Task8: ADCINT8 or by CPU Timer 0.
• Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
– The CLA has direct access to the ADC Result registers, comparator registers, and the ePWM+HRPWM
registers.
For more information on the CLA, see the Control Law Accelerator (CLA) chapter in the TMS320F2803x
Real-Time Microcontrollers Technical Reference Manual.

TMS320F28035, TMS320F28035-Q1
IACK
Peripheral Interrupts
CLA Control
ADCINT1 to Registers
ADCINT8
EPWM1_INT to MIFR CLA_INT1 to CLA_INT8

INT11 Main
MPERINT1 MIOVF PIE
EPWM8_INT
INT 28x
to MICLR INT12
CPU
MPERINT8 MICLROVF
CPU Timer 0 MIFRC LVF
MIER LUF
MIRUN
Main CPU Read/Write Data Bus

MPISRCSEL1
MVECT1
MVECT2
CLA Program Address Bus MVECT3
CLA MVECT4
Program CLA Program Data Bus MVECT5
Memory MVECT6
MVECT7
MVECT8
CLA
Map to CLA or Map to CLA or
MMEMCFG Data
CPU Space CPU Space
Memory
Main CPU Bus

Main CPU BUS
MCTL
SYSCLKOUT CLA
CLAENCLK Shared
SYSRS Message
RAMs
CLA Data Bus

CLA Execution MEALLOW ADC
Registers Result
CLA Data Read Address Bus Registers
MPC(12) CLA Data Read Data Bus ePWM

MSTF(32) and
Main CPU Read Data Bus MR0(32) HRPWM
CLA Data Write Address Bus
MR1(32) Registers
MR2(32)
CLA Data Write Data Bus
MR3(32)
MAR0(32) Comparator
MAR1(32) Registers
Figure 7-15. CLA Block Diagram

TMS320F28035, TMS320F28035-Q1
Table 7-22. CLA Control Registers

CLA1 EALLOW
REGISTER NAME SIZE (x16) DESCRIPTION(1)
ADDRESS PROTECTED
MVECT1 0x1400 1 Yes CLA Interrupt/Task 1 Start Address
MCTL 0x1410 1 Yes CLA Control Register
MMEMCFG 0x1411 1 Yes CLA Memory Configure Register
MPISRCSEL1 0x1414 2 Yes Peripheral Interrupt Source Select Register 1
MIFR 0x1420 1 Yes Interrupt Flag Register
MIOVF 0x1421 1 Yes Interrupt Overflow Register
MIFRC 0x1422 1 Yes Interrupt Force Register
MICLR 0x1423 1 Yes Interrupt Clear Register
MICLROVF 0x1424 1 Yes Interrupt Overflow Clear Register
MIER 0x1425 1 Yes Interrupt Enable Register
MIRUN 0x1426 1 Yes Interrupt RUN Register
MIPCTL 0x1427 1 Yes Interrupt Priority Control Register
MPC(2) 0x1428 1 – CLA Program Counter
MAR0(2) 0x142A 1 – CLA Aux Register 0
MAR1(2) 0x142B 1 – CLA Aux Register 1
MSTF(2) 0x142E 2 – CLA STF Register
MR0(2) 0x1430 2 – CLA R0H Register
MR3(2) 0x143C 2 – CLA R3H Register
(1) All registers in this table are CSM protected

(2) The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes
to this register.
Table 7-23. CLA Message RAM

ADDRESS RANGE SIZE (x16) DESCRIPTION
0x1480 – 0x14FF 128 CLA to CPU Message RAM
0x1500 – 0x157F 128 CPU to CLA Message RAM

TMS320F28035, TMS320F28035-Q1
7.9.2 Analog Block

A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x. The
ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the timing
control of start of conversions. Figure 7-16 shows the interaction of the analog module with the rest of the
F2803x system.
For more information on the ADC, see the Analog-to-Digital Converter and Comparator chapter in the
56-Pin
80-Pin (3.3 V) VDDA
64-Pin
(Agnd) VSSA
VDDA VDDA VREFLO
VREFLO VSSA
Tied To Interface Reference
VSSA VREFLO Diff
VREFHI VREFHI
Tied To VREFHI
A0 A0 A0
B0
A1 A1
A1
A2 A2
B1
A3 A3
A2 COMP1OUT
A4 A4 AIO2 10-Bit Comp1
A5 AIO10 DAC
B2
Simultaneous Sampling Channels
A6 A6
A7 A7 A3 ADC
B3
B0 B0
B1 B1 A4 COMP2OUT
AIO4 10-Bit Comp2
B2 B2 AIO12 DAC
B3 B3 B4
B4 B4
B5 B5
B6 B6 Temperature Sensor
B7 B7 A5
Signal Pinout A6 COMP3OUT

AIO6 10-Bit Comp3
AIO14 DAC
B6
A7
B7
Figure 7-16. Analog Pin Configurations

TMS320F28035, TMS320F28035-Q1
7.9.2.1 Analog-to-Digital Converter (ADC)

7.9.2.1.1 Features
The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-
and-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to
16 analog input channels. The converter can be configured to run with an internal band-gap reference to
create true-voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to create
ratiometric-based conversions.
Contrary to previous ADC types, this ADC is not sequencer-based. It is easy for the user to create a series of
conversions from a single trigger. However, the basic principle of operation is centered around the configurations
of individual conversions, called SOCs, or Start-Of-Conversions.
Functions of the ADC module include:
• 12-bit ADC core with built-in dual sample-and-hold (S/H)
• Simultaneous sampling or sequential sampling modes
• Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input analog
voltage is derived by:
– Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or external
reference modes.)
Digital Value = 0, when input £ 0 V
Input Analog Voltage - VREFLO

Digital Value = 4096 ´ when 0 V < input < 3.3 V
3.3
Digital Value = 4095, when input ³ 3.3 V
– External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA when
using either internal or external reference modes.)
Digital Value = 0, when input £ 0 V
Input Analog Voltage - VREFLO

Digital Value = 4096 ´ when 0 V < input < VREFHI
VREFHI - VREFLO
Digital Value = 4095, when input ³ VREFHI
• Up to 16-channel, multiplexed inputs

• 16 SOCs, configurable for trigger, sample window, and channel
• 16 result registers (individually addressable) to store conversion values
• Multiple trigger sources
– S/W – software immediate start
– ePWM 1–7
– GPIO XINT2
– CPU Timers 0/1/2
– ADCINT1/2
• 9 flexible PIE interrupts, can configure interrupt request after any conversion

TMS320F28035, TMS320F28035-Q1
Table 7-24. ADC Configuration and Control Registers

SIZE EALLOW
REGISTER NAME ADDRESS DESCRIPTION
(x16) PROTECTED
ADCCTL1 0x7100 1 Yes Control 1 Register
ADCCTL2 0x7101 1 Yes Control 2 Register
ADCINTFLG 0x7104 1 No Interrupt Flag Register
ADCINTFLGCLR 0x7105 1 No Interrupt Flag Clear Register
ADCINTOVF 0x7106 1 No Interrupt Overflow Register
ADCINTOVFCLR 0x7107 1 No Interrupt Overflow Clear Register
INTSEL1N2 0x7108 1 Yes Interrupt 1 and 2 Selection Register
INTSEL3N4 0x7109 1 Yes Interrupt 3 and 4 Selection Register
INTSEL5N6 0x710A 1 Yes Interrupt 5 and 6 Selection Register
INTSEL7N8 0x710B 1 Yes Interrupt 7 and 8 Selection Register
INTSEL9N10 0x710C 1 Yes Interrupt 9 Selection Register (reserved Interrupt 10 Selection)
SOCPRICTL 0x7110 1 Yes SOC Priority Control Register
ADCSAMPLEMODE 0x7112 1 Yes Sampling Mode Register
ADCINTSOCSEL1 0x7114 1 Yes Interrupt SOC Selection 1 Register (for 8 channels)
ADCINTSOCSEL2 0x7115 1 Yes Interrupt SOC Selection 2 Register (for 8 channels)
ADCSOCFLG1 0x7118 1 No SOC Flag 1 Register (for 16 channels)
ADCSOCFRC1 0x711A 1 No SOC Force 1 Register (for 16 channels)
ADCSOCOVF1 0x711C 1 No SOC Overflow 1 Register (for 16 channels)
ADCSOCOVFCLR1 0x711E 1 No SOC Overflow Clear 1 Register (for 16 channels)
ADCSOC0CTL to 0x7120 – 1 Yes SOC0 Control Register to SOC15 Control Register
ADCSOC15CTL 0x712F
ADCREFTRIM 0x7140 1 Yes Reference Trim Register
ADCOFFTRIM 0x7141 1 Yes Offset Trim Register
COMPHYSTCTL 0x714C 1 Yes Comparator Hysteresis Control Register
ADCREV 0x714F 1 No Revision Register
Table 7-25. ADC Result Registers (Mapped to PF0)

SIZE EALLOW
REGISTER NAME ADDRESS DESCRIPTION
(x16) PROTECTED
ADCRESULT0 to ADCRESULT15 0xB00 to 0xB0F 1 No ADC Result 0 Register to ADC Result 15
Register

TMS320F28035, TMS320F28035-Q1
0-Wait
Result PF0 (CPU)
Registers
PF2 (CPU)
SYSCLKOUT
ADCENCLK
ADCINT 1
PIE
ADCINT 9
TINT 0
ADCTRIG 1 CPUTIMER 0
TINT 1
ADCTRIG 2 CPUTIMER 1
ADC TINT 2
AIO ADC ADCTRIG 3 CPUTIMER 2
Core
MUX Channels XINT 2SOC
12-Bit ADCTRIG 4 XINT 2
SOCA 1
ADCTRIG 5
SOCB 1 EPWM 1
ADCTRIG 6
SOCA 2
ADCTRIG 7
SOCB 2 EPWM 2
ADCTRIG 8
SOCA 3
ADCTRIG 9
SOCB 3 EPWM 3
ADCTRIG 10
SOCA 4
ADCTRIG 11
SOCB 4 EPWM 4
ADCTRIG 12
SOCA 5
ADCTRIG 13
SOCB 5 EPWM 5
ADCTRIG 14
SOCA 6
ADCTRIG 15
SOCB 6 EPWM 6
ADCTRIG 16
SOCA 7
ADCTRIG 17
SOCB 7 EPWM 7
ADCTRIG 18
Figure 7-17. ADC Connections
ADC Connections if the ADC is Not Used

TI recommends keeping the connections for the analog power pins, even if the ADC is not used. Following is a
summary of how the ADC pins should be connected, if the ADC is not used in an application:
• VDDA – Connect to VDDIO
• VSSA – Connect to VSS
• VREFLO – Connect to VSS
• ADCINAn, ADCINBn, VREFHI – Connect to VSSA
When the ADC module is used in an application, unused ADC input pins should be connected to analog ground
(VSSA).
Note
Unused ADCIN pins that are multiplexed with AIO function should not be directly connected to analog
ground. They should be grounded through a 1-kΩ resistor. This is to prevent an errant code from
configuring these pins as AIO outputs and driving grounded pins to a logic-high state.
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings.

TMS320F28035, TMS320F28035-Q1
7.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing

7.9.2.1.2.1 External ADC Start-of-Conversion Switching Characteristics
tw(ADCSOCL) Pulse duration, ADCSOCxO low 32tc(HCO) cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 7-18. ADCSOCAO or ADCSOCBO Timing

TMS320F28035, TMS320F28035-Q1
7.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing

7.9.2.1.3.1 ADC Electrical Characteristics

DC SPECIFICATIONS
Resolution 12 Bits
ADC clock 60-MHz device 0.001 60 MHz
Sample Window 28035/34/33/32 7 64 ADC
28031/30 24 64 Clocks
ACCURACY
INL (Integral nonlinearity) at ADC Clock ≤ 30 MHz(1) –4 4 LSB
DNL (Differential nonlinearity) at ADC Clock ≤ 30 MHz,
–1 1 LSB
no missing codes
Offset error (2) Executing a single self-
–20 0 20
recalibration(3)
LSB
Executing periodic self-
–4 0 4
recalibration(4)
Overall gain error with internal reference –60 60 LSB
Overall gain error with external reference –40 40 LSB
Channel-to-channel offset variation –4 4 LSB
Channel-to-channel gain variation –4 4 LSB
ADC temperature coefficient with internal reference –50 ppm/°C
ADC temperature coefficient with external reference –20 ppm/°C
VREFLO –100 µA
VREFHI 100 µA
ANALOG INPUT
Analog input voltage with internal reference 0 3.3 V
Analog input voltage with external reference VREFLO VREFHI V
VREFLO input voltage(5) VSSA 0.66 V
VREFHI input voltage(6) 2.64 VDDA
V
with VREFLO = VSSA 1.98 VDDA
Input capacitance 5 pF
Input leakage current ±2 μA
(1) INL will degrade when the ADC input voltage goes above VDDA.
(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
(3) For more details, see the TMS320F2803x Real-Time MCUs Silicon Errata.
(4) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be
performed as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset
Calibration" section of the Analog-to-Digital Converter and Comparator chapter in the TMS320F2803x Real-Time Microcontrollers
Technical Reference Manual.
(5) VREFLO is always connected to VSSA on the 64-pin PAG device.
(6) VREFHI must not exceed VDDA when using either internal or external reference modes. Because VREFHI is tied to ADCINA0 on the
64-pin PAG device, the input signal on ADCINA0 must not exceed VDDA.

TMS320F28035, TMS320F28035-Q1
7.9.2.1.3.2 ADC Power Modes
ADC OPERATING MODE CONDITIONS IDDA UNITS

ADC Clock Enabled
Band gap On (ADCBGPWD = 1)
Mode A – Operating Mode 13 mA
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 1)
ADC Clock Enabled
Mode B – Quick Wake Mode 4 mA
ADC Clock Enabled
Mode C – Comparator-Only Mode 1.5 mA
ADC Clock Enabled
Mode D – Off Mode 0.075 mA
7.9.2.1.3.3 Internal Temperature Sensor

7.9.2.1.3.3.1 Temperature Sensor Coefficient
PARAMETER(1) MIN TYP MAX UNIT

TSLOPE Degrees C of temperature movement per measured ADC LSB change
0.18(2) (3) °C/LSB
of the temperature sensor
TOFFSET ADC output at 0°C of the temperature sensor 1750 LSB
(1) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be
adjusted accordingly in external reference mode to the external reference voltage.
(2) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing
temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values
relative to an initial value.
(3) ADC temperature coefficient is accounted for in this specification
7.9.2.1.3.4 ADC Power-Up Control Bit Timing

7.9.2.1.3.4.1 ADC Power-Up Delays
PARAMETER(1) MIN MAX UNIT

td(PWD) Delay time for the ADC to be stable after power up 1 ms
(1) Timings maintain compatibility to the ADC module. The 2803x ADC supports driving all 3 bits at the same time td(PWD) ms before first
conversion.
ADCPWDN/
ADCBGPWD/
ADCREFPWD/
ADCENABLE td(PWD)
Request for ADC
Conversion
Figure 7-19. ADC Conversion Timing

TMS320F28035, TMS320F28035-Q1
Ron Switch
Rs ADCIN 3.4 kW
Source Cp Ch
ac
Signal 5 pF 1.6 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron): 3.4 k W

Sampling Capacitor (Ch): 1.6 pF
Parasitic Capacitance (Cp): 5 pF
Source Resistance (Rs): 50 W
Figure 7-20. ADC Input Impedance Model

TMS320F28035, TMS320F28035-Q1
7.9.2.1.3.5 ADC Sequential and Simultaneous Timings
Analog Input
SOC0 Sample SOC1 Sample SOC2 Sample
Window Window Window
0 2 9 15 22 24 37
ADCCLK
ADCCTL 1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core SOC0 SOC1 SOC2
ADCRESULT 0 2 ADCCLKs Result 0 Latched
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
ADCINTFLG .ADCINTx
Minimum Conversion 0
1 ADCCLK
7 ADCCLKs 13 ADC Clocks
6 Minimum Conversion 1
ADCCLKs 7 ADCCLKs 13 ADC Clocks
Figure 7-21. Timing Example for Sequential Mode / Late Interrupt Pulse

TMS320F28035, TMS320F28035-Q1
Analog Input
SOC0 Sample SOC1 Sample SOC2 Sample
Window Window Window
0 2 9 15 22 24 37
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core SOC0 SOC1 SOC2
ADCRESULT 0 Result 0 Latched
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG .ADCINTx
Minimum Conversion 0
2 ADCCLKs
7 ADCCLKs 13 ADC Clocks
6 Minimum Conversion 1
Figure 7-22. Timing Example for Sequential Mode / Early Interrupt Pulse

TMS320F28035, TMS320F28035-Q1
Analog Input A
SOC0 Sample SOC2 Sample
A Window A Window
Analog Input B
B Window B Window
0 2 9 22 24 37 50
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B)
ADCRESULT 0 2 ADCCLKs Result 0 (A) Latched
ADCRESULT 1 Result 0 (B) Latched
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse 1 ADCCLK
EOC2 Pulse
ADCINTFLG .ADCINTx
Minimum Conversion 0 (A) Conversion 0 (B)

2 ADCCLKs
7 ADCCLKs 13 ADC Clocks 13 ADC Clocks
19 Minimum Conversion 1 (A)

Figure 7-23. Timing Example for Simultaneous Mode / Late Interrupt Pulse

TMS320F28035, TMS320F28035-Q1
Analog Input A
A Window A Window
Analog Input B
B Window B Window
0 2 9 22 24 37 50
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B)
ADCRESULT 0 2 ADCCLKs Result 0 (A) Latched
ADCRESULT 1 Result 0 (B) Latched
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG.ADCINTx
Minimum Conversion 0 (A) Conversion 0 (B)

2 ADCCLKs
7 ADCCLKs 13 ADC Clocks 13 ADC Clocks
19 Minimum Conversion 1 (A)
Figure 7-24. Timing Example for Simultaneous Mode / Early Interrupt Pulse

TMS320F28035, TMS320F28035-Q1
7.9.2.2 ADC MUX
To COMPy A or B input
To ADC Channel X
Logic implemented in GPIO MUX block

AIOx Pin
AIOxIN SYSCLK
1
AIOxINE AIODAT Reg

SYNC (Read)
AIODAT Reg
(Latch)
AIOMUX 1 Reg
AIOSET,
0 = Output)
AIOCLEAR,
(1 = Input,
AIOxDIR
AIOTOGGLE
Regs
AIODIR Reg
1 (Latch)
(0 = Input, 1 = Output)
0 0
Figure 7-25. AIOx Pin Multiplexing
The ADC channel and Comparator functions are always available. The digital I/O function is available only when
the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects the actual pin
state.
The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode, reading
the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer is disabled to
prevent analog signals from generating noise.
On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO function
disabled for that pin.

TMS320F28035, TMS320F28035-Q1
7.9.2.3 Comparator Block

Figure 7-26 shows the interaction of the Comparator modules with the rest of the system.
COMP x A
+
COMP x B COMP
- GPIO TZ1/2/3
MUX
COMP x
+
DAC x ePWM
AIO Wrapper
MUX
COMPxOUT
DAC
Core
10-Bit
Figure 7-26. Comparator Block Diagram
Table 7-26. Comparator Control Registers

REGISTER COMP1 COMP2 COMP3 SIZE EALLOW
DESCRIPTION
NAME ADDRESS ADDRESS ADDRESS (x16) PROTECTED
COMPCTL 0x6400 0x6420 0x6440 1 Yes Comparator Control Register
COMPSTS 0x6402 0x6422 0x6442 1 No Comparator Status Register
DACCTL 0x6404 0x6424 0x6444 1 Yes DAC Control Register
DACVAL 0x6406 0x6426 0x6446 1 No DAC Value Register
RAMPMAXREF_ Ramp Generator Maximum Reference
0x6408 0x6428 0x6448 1 No
ACTIVE (Active) Register
RAMPMAXREF_ Ramp Generator Maximum Reference
0x640A 0x642A 0x644A 1 No
SHDW (Shadow) Register
RAMPDECVAL_ Ramp Generator Decrement Value
0x640C 0x642C 0x644C 1 No
ACTIVE (Active) Register
RAMPDECVAL_ Ramp Generator Decrement Value
0x640E 0x642E 0x644E 1 No
SHDW (Shadow) Register
RAMPSTS 0x6410 0x6430 0x6450 1 No Ramp Generator Status Register

TMS320F28035, TMS320F28035-Q1
7.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing

7.9.2.3.1.1 Electrical Characteristics of the Comparator/DAC
PARAMETER MIN TYP MAX UNITS

Comparator
Comparator Input Range VSSA – VDDA V
Comparator response time to PWM Trip Zone (Async) 30 ns
Input Offset ±5 mV
Input Hysteresis(1) 35 mV
DAC
DAC Output Range VSSA – VDDA V
DAC resolution 10 bits
DAC settling time See Figure 7-27
DAC Gain –1.5%
DAC Offset 10 mV
Monotonic Yes
INL ±3 LSB
(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback
resistance between the output of the comparator and the noninverting input of the comparator. There is an option to disable the
hysteresis and, with it, the feedback resistance; see the Analog-to-Digital Converter and Comparator chapter in the TMS320F2803x
Real-Time Microcontrollers Technical Reference Manual for more information on this option if needed in your system.
1100
1000
900
800
700
Settling Time (ns)
600
500
400
300
200
100
0
0 50 100 150 200 250 300 350 400 450 500
DAC Step Size (Codes)
DAC Accuracy 15 Codes 7 Codes 3 Codes 1 Code
Figure 7-27. DAC Settling Time

TMS320F28035, TMS320F28035-Q1
7.9.3 Detailed Descriptions

Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The
point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level
one-half LSB beyond the last code transition. The deviation is measured from the center of each particular code
to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A
differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code transitions and the ideal difference between first
and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(SINAD - 1.76)
N=
6.02 it is possible to get a measure of performance expressed as N, the effective number of
bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated
directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

TMS320F28035, TMS320F28035-Q1
7.9.4 Serial Peripheral Interface (SPI) Module

The device includes the four-pin serial peripheral interface (SPI) module. Up to two SPI modules are available.
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1
to 16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is
used for communications between the MCU and external peripherals or another processor. Typical applications
include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs.
Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
Note
All four pins can be used as GPIO if the SPI module is not used.
• Two operational modes: master and slave

Baud rate: 125 different programmable rates.
LSPCLK
Baud rate = when SPIBRR = 3 to 127
(SPIBRR + 1)
LSPCLK
Baud rate = when SPIBRR = 0, 1, 2
4
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive and transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
• Nine SPI module control registers: In control register frame beginning at address 7040h.
Note
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.

TMS320F28035, TMS320F28035-Q1
Enhanced feature:
• 4-level transmit/receive FIFO
• Delayed transmit control
• Bidirectional 3 wire SPI mode support
• Audio data receive support through SPISTE inversion
The SPI port operation is configured and controlled by the registers listed in Table 7-27 and Table 7-28.
Table 7-27. SPI-A Registers
NAME ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION(1)
SPICCR 0x7040 1 No SPI-A Configuration Control Register
SPICTL 0x7041 1 No SPI-A Operation Control Register
SPISTS 0x7042 1 No SPI-A Status Register
SPIBRR 0x7044 1 No SPI-A Baud Rate Register
SPIRXEMU 0x7046 1 No SPI-A Receive Emulation Buffer Register
SPIRXBUF 0x7047 1 No SPI-A Serial Input Buffer Register
SPITXBUF 0x7048 1 No SPI-A Serial Output Buffer Register
SPIDAT 0x7049 1 No SPI-A Serial Data Register
SPIFFTX 0x704A 1 No SPI-A FIFO Transmit Register
SPIFFRX 0x704B 1 No SPI-A FIFO Receive Register
SPIFFCT 0x704C 1 No SPI-A FIFO Control Register
SPIPRI 0x704F 1 No SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 7-28. SPI-B Registers

NAME ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION(1)
SPICCR 0x7740 1 No SPI-B Configuration Control Register
SPICTL 0x7741 1 No SPI-B Operation Control Register
SPISTS 0x7742 1 No SPI-B Status Register
SPIBRR 0x7744 1 No SPI-B Baud Rate Register
SPIRXEMU 0x7746 1 No SPI-B Receive Emulation Buffer Register
SPIRXBUF 0x7747 1 No SPI-B Serial Input Buffer Register
SPITXBUF 0x7748 1 No SPI-B Serial Output Buffer Register
SPIDAT 0x7749 1 No SPI-B Serial Data Register
SPIFFTX 0x774A 1 No SPI-B FIFO Transmit Register
SPIFFRX 0x774B 1 No SPI-B FIFO Receive Register
SPIFFCT 0x774C 1 No SPI-B FIFO Control Register
SPIPRI 0x774F 1 No SPI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
For more information on the SPI, see the Serial Peripheral Interface (SPI) chapter in the TMS320F2803x

TMS320F28035, TMS320F28035-Q1
Figure 7-28 is a block diagram of the SPI in slave mode.
SPIFFENA
Receiver Overrun
SPIFFTX.14 Overrun Flag INT ENA
RX FIFO Registers SPISTS.7

SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
----- SPIINT
RX FIFO Interrupt
RX FIFO _3 RX Interrupt
Logic
16
SPIRXBUF SPIFFOVF
Buffer Register FLAG
SPIFFRX.15 To CPU
TX FIFO Registers
SPITXBUF
TX FIFO _3 TX Interrupt
----- TX FIFO Interrupt Logic
TX FIFO _1
SPITX
TX FIFO _0
SPI INT
16 16 ENA
SPI INT FLAG
SPITXBUF SPISTS.6
Buffer Register
SPICTL.0
TRIWIRE
16 SPIPRI.0
M M
SPIDAT S TW
Data Register S SW1 SPISIMO
M TW
SPIDAT.15 - 0 M
TW
SPISOMI
S
STEINV
S SW2
Talk SPIPRI.1
SPICTL.1 STEINV
SPISTE
State Control
Master/Slave
SPI Char SPICCR.3 - 0 SPICTL.2

S
SW3
3 2 1 0
Clock Clock
M
SPI Bit Rate S Polarity Phase
LSPCLK SPIBRR.6 - 0 SPICCR.6 SPICTL.3 SPICLK

6 5 4 3 2 1 0 M
A. SPISTE is driven low by the master for a slave device.
Figure 7-28. SPI Module Block Diagram (Slave Mode)

TMS320F28035, TMS320F28035-Q1
7.9.4.1 SPI Master Mode Electrical Data/Timing

Section 7.9.4.1.1 lists the master mode timing (clock phase = 0) and Section 7.9.4.1.2 lists the master mode
timing (clock phase = 1). Figure 7-29 and Figure 7-30 show the timing waveforms.
7.9.4.1.1 SPI Master Mode External Timing (Clock Phase = 0)
BRR EVEN BRR ODD
NO. PARAMETER(1) (2) (3) (4) (5) UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LSPCLK) 128tc(LSPCLK) 5tc(LSPCLK) 127tc(LSPCLK) ns
Pulse duration, SPICLK first 0.5tc(SPC)M + 0.5tc(LSPCLK) 0.5tc(SPC)M +
2 tw(SPC1)M 0.5tc(SPC)M – 10 0.5tc(SPC)M + 10 ns
pulse – 10 0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second 0.5tc(SPC)M – 0.5tc(LSPCLK) 0.5tc(SPC)M –
pulse – 10 0.5tc(LSPCLK) + 10
Delay time, SPICLK to
4 td(SIMO)M 10 10 ns
SPISIMO valid
Valid time, SPISIMO valid after 0.5tc(SPC)M – 0.5tc(LSPCLK)
5 tv(SIMO)M 0.5tc(SPC)M – 10 ns
SPICLK – 10
Setup time, SPISOMI before
8 tsu(SOMI)M 26 26 ns
SPICLK
Hold time, SPISOMI valid after
9 th(SOMI)M 0 0 ns
SPICLK
Delay time, SPISTE active to 1.5tc(SPC)M – 1.5tc(SPC)M –
23 td(SPC)M ns
SPICLK 3tc(SYSCLK) – 10 3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE 0.5tc(SPC)M – 0.5tc(LSPCLK)
24 td(STE)M 0.5tc(SPC)M – 10 ns
inactive – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
SPICLK
(clock polarity = 0)
SPICLK
4
5
SPISIMO Master Out Data Is Valid
Master In Data
SPISOMI
Must Be Valid
23 24
SPISTE
Figure 7-29. SPI Master Mode External Timing (Clock Phase = 0)

TMS320F28035, TMS320F28035-Q1
7.9.4.1.2 SPI Master Mode External Timing (Clock Phase = 1)

BRR EVEN BRR ODD
NO. PARAMETER(1) (2) (3) (4) (5) UNIT
MIN MAX MIN MAX
1 tc(SPC)M Cycle time, SPICLK 4tc(LSPCLK) 128tc(LSPCLK) 5tc(LSPCLK) 127tc(LSPCLK) ns
Pulse duration, SPICLK first 0.5tc(SPC)M – 0.5tc(SPC)M –
pulse 0.5tc(LSPCLK) – 10 0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second 0.5tc(SPC)M + 0.5tc(SPC)M +
pulse 0.5tc(LSPCLK) – 10 0.5tc(LSPCLK) + 10
Delay time, SPISIMO valid to 0.5tc(SPC)M +
6 td(SIMO)M 0.5tc(SPC)M – 10 ns
SPICLK 0.5tc(LSPCLK) – 10
Valid time, SPISIMO valid after 0.5tc(SPC)M –
7 tv(SIMO)M 0.5tc(SPC)M – 10 ns
SPICLK 0.5tc(LSPCLK) – 10
Setup time, SPISOMI before
10 tsu(SOMI)M 26 26 ns
SPICLK
Hold time, SPISOMI valid after
11 th(SOMI)M 0 0 ns
SPICLK
Delay time, SPISTE active to 2tc(SPC)M – 2tc(SPC)M –
23 td(SPC)M ns
SPICLK 3tc(SYSCLK) – 10 3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE 0.5tc(SPC) –
24 td(STE)M 0.5tc(SPC) – 10 ns
inactive 0.5tc(LSPCLK) – 10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
2
SPICLK
6
7
SPISIMO Master Out Data Is Valid
10
11
SPISOMI Master In Data Must

Be Valid
24
23
SPISTE
Figure 7-30. SPI Master Mode External Timing (Clock Phase = 1)

TMS320F28035, TMS320F28035-Q1
7.9.4.2 SPI Slave Mode Electrical Data/Timing

Section 7.9.4.2.1 lists the slave mode timing (clock phase = 0) and Section 7.9.4.2.2 lists the slave mode timing
(clock phase = 1). Figure 7-31 and Figure 7-32 show the timing waveforms.
7.9.4.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
NO. PARAMETER(1) (2) (4) (3) (5) MIN MAX UNIT

12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
13 tw(SPC1)S Pulse duration, SPICLK first pulse 2tc(SYSCLK) – 1 ns
14 tw(SPC2)S Pulse duration, SPICLK second pulse 2tc(SYSCLK) – 1 ns
15 td(SOMI)S Delay time, SPICLK to SPISOMI valid 21 ns
16 tv(SOMI)S Valid time, SPISOMI data valid after SPICLK 0 ns
19 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns
20 th(SIMO)S Hold time, SPISIMO data valid after SPICLK 1.5tc(SYSCLK) ns
25 tsu(STE)S Setup time, SPISTE active before SPICLK 1.5tc(SYSCLK) ns
26 th(STE)S Hold time, SPISTE inactive after SPICLK 1.5tc(SYSCLK) ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
12
SPICLK
13
14
SPICLK
15
16
SPISOMI SPISOMI Data Is Valid
19
20
SPISIMO Data
SPISIMO
Must Be Valid
25 26
SPISTE
Figure 7-31. SPI Slave Mode External Timing (Clock Phase = 0)

TMS320F28035, TMS320F28035-Q1
7.9.4.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
NO. PARAMETER(1) (2) (3) (4) MIN MAX UNIT

12 tc(SPC)S Cycle time, SPICLK 4tc(SYSCLK) ns
13 tw(SPC1)S Pulse duration, SPICLK first pulse 2tc(SYSCLK) – 1 ns
14 tw(SPC2)S Pulse duration, SPICLK second pulse 2tc(SYSCLK) – 1 ns
17 td(SOMI)S Delay time, SPICLK to SPISOMI valid 21 ns
18 tv(SOMI)S Valid time, SPISOMI data valid after SPICLK 0 ns
21 tsu(SIMO)S Setup time, SPISIMO valid before SPICLK 1.5tc(SYSCLK) ns
22 th(SIMO)S Hold time, SPISIMO data valid after SPICLK 1.5tc(SYSCLK) ns
25 tsu(STE)S Setup time, SPISTE active before SPICLK 1.5tc(SYSCLK) ns
26 th(STE)S Hold time, SPISTE inactive after SPICLK 1.5tc(SYSCLK) ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
12
SPICLK
13 14
SPICLK
17
SPISOMI SPISOMI Data Is Valid Data Valid Data Valid
21 18
22
SPISIMO SPISIMO Data

Must Be Valid
25 26
SPISTE
Figure 7-32. SPI Slave Mode External Timing (Clock Phase = 1)

TMS320F28035, TMS320F28035-Q1
7.9.5 Serial Communications Interface (SCI) Module

The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
LSPCLK
Baud rate = when BRR ¹ 0
(BRR + 1) * 8
LSPCLK
Baud rate = when BRR = 0
16
• Data-word format
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– One or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ (nonreturn-to-zero) format
Note
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
Enhanced features:
• Auto baud-detect hardware logic
• 4-level transmit/receive FIFO

TMS320F28035, TMS320F28035-Q1
The SCI port operation is configured and controlled by the registers listed in Table 7-29.
Table 7-29. SCI-A Registers
EALLOW
NAME(1) ADDRESS SIZE (x16) DESCRIPTION
PROTECTED
SCICCRA 0x7050 1 No SCI-A Communications Control Register
SCICTL1A 0x7051 1 No SCI-A Control Register 1
SCIHBAUDA 0x7052 1 No SCI-A Baud Register, High Bits
SCILBAUDA 0x7053 1 No SCI-A Baud Register, Low Bits
SCICTL2A 0x7054 1 No SCI-A Control Register 2
SCIRXSTA 0x7055 1 No SCI-A Receive Status Register
SCIRXEMUA 0x7056 1 No SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA 0x7057 1 No SCI-A Receive Data Buffer Register
SCITXBUFA 0x7059 1 No SCI-A Transmit Data Buffer Register
SCIFFTXA(2) 0x705A 1 No SCI-A FIFO Transmit Register
SCIFFRXA(2) 0x705B 1 No SCI-A FIFO Receive Register
SCIFFCTA(2) 0x705C 1 No SCI-A FIFO Control Register
SCIPRIA 0x705F 1 No SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
For more information on the SCI, see the Serial Communications Interface (SCI) chapter in the TMS320F2803x
Figure 7-33 shows the SCI module block diagram.

TMS320F28035, TMS320F28035-Q1
TXENA
SCICTL1.1
TXSHF
SCITXD
Register
Frame 8
Format and Mode
Parity
Even/Odd TXEMPTY
0 1
SCICCR.6 8 SCICTL2.6
Enable
TX FIFO_0
TXINT
SCICCR.5 To CPU
TX FIFO_1 TX FIFO Interrupts TX Interrupt
88
Logic
TX FIFO_N
TXINTENA
TXRDY SCICTL2.0
8
TXWAKE 0 1 SCICTL2.7
SCICTL1.3
SCI TX Interrupt Select Logic
WUT 8
Transmit Data
Buffer Register
SCITXBUF.7-0 Auto Baud Detect Logic
RXENA
Baud Rate
MSB/LSB SCICTL1.0
LSPCLK Registers
RXSHF
SCIRXD
Register
SCIHBAUD.15-8
RXWAKE
SCILBAUD.7-0 8
SCIRXST.1
0 1
8
SCIFFENA
SCIFFTX.14 RX FIFO_0 RXINT
8 RX FIFO_1 To CPU
RX FIFO Interrupts RX Interrupt
Logic
RX FIFO_N
RXFFOVF
8 SCIFFRX.15
0 1
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6
RXENA BRKDT
RXERRINTENA
SCICTL1.0
SCIRXST.5 SCICTL1.6
SCI RX Interrupt Select Logic

8
SCIRXST.5-2
Receive Data BRKDT FE OE PE
Buffer Register
RXERROR
SCIRXBUF.7-0
SCIRXST.7
Figure 7-33. Serial Communications Interface (SCI) Module Block Diagram

TMS320F28035, TMS320F28035-Q1
7.9.6 Local Interconnect Network (LIN)

The device contains one LIN controller. The LIN standard is based on the SCI (UART) serial data link format.
The LIN module can be configured to work as a SCI as well.
The LIN module has the following features:
• Compatible to LIN 1.3 or 2.0 protocols
• Two external pins: LINRX and LINTX
• Multibuffered receive and transmit units
• Identification masks for message filtering
• Automatic master header generation
– Programmable sync break field
– Sync field
– Identifier field
• Slave automatic synchronization
– Sync break detection
– Optional baud rate update
– Synchronization validation
• 231 programmable transmission rates with 7 fractional bits
• Wakeup on LINRX dominant level from transceiver
• Automatic wakeup support
– Wakeup signal generation
– Expiration times on wakeup signals
• Automatic bus idle detection
• Error detection
– Bit error
– Bus error
– No-response error
– Checksum error
– Sync field error
– Parity error
• 2 Interrupt lines with priority encoding for:
– Receive
– Transmit
– ID, error and status
Note
The 2803x devices have passed LIN 2.0 conformance tests (master and slave). Contact TI for details.
For more information on the LIN, see the Local Interconnect Network (LIN) Module chapter in the

TMS320F28035, TMS320F28035-Q1
The registers in Table 7-30 configure and control the operation of the LIN module.
Table 7-30. LIN-A Registers
NAME(1) ADDRESS SIZE (x16) DESCRIPTION
SCIGCR0 0x6C00 2 Global Control Register 0
SCISETINT 0x6C06 2 Interrupt Enable Register
SCICLEARINT 0x6C08 2 Interrupt Disable Register
SCISETINTLVL 0x6C0A 2 Set Interrupt Level Register
SCICLEARINTLVL 0x6C0C 2 Clear Interrupt Level Register
SCIFLR 0x6C0E 2 Flag Register
SCIINTVECT0 0x6C10 2 Interrupt Vector Offset Register 0
SCIINTVECT1 0x6C12 2 Interrupt Vector Offset Register 1
SCIFORMAT 0x6C14 2 Length Control register
BRSR 0x6C16 2 Baud Rate Selection Register
SCIED 0x6C18 2 Emulation buffer register
SCIRD 0x6C1A 2 Receiver data buffer register
SCITD 0x6C1C 2 Transmit data buffer register
Reserved 0x6C1E 4 RSVD
SIPIO2 0x6C22 2 Pin control register 2
Reserved 0x6C24 10 RSVD
LINCOMP 0x6C30 2 Compare register
LINRD0 0x6C32 2 Receive data register 0
LINRD1 0x6C34 2 Receive data register 1
LINMASK 0x6C36 2 Acceptance mask register
Register containing ID- byte, ID-SlaveTask byte, and ID
LINID 0x6C38 2
received fields.
LINTD0 0x6C3A 2 Transmit Data Register 0
LINTD1 0x6C3C 2 Transmit Data Register 1
MBRSR 0x6C3E 2 Baud Rate Selection Register
Reserved 0x6C40 8 RSVD
IODFTCTRL 0x6C48 2 IODFT for BLIN
(1) Some registers and some bits in other registers are EALLOW-protected. For more details, see the Local Interconnect Network (LIN)
Module chapter in the TMS320F2803x Real-Time Microcontrollers Technical Reference Manual.

TMS320F28035, TMS320F28035-Q1
Figure 7-34 shows the LIN module block diagram.
READ DATA BUS
WRITE DATA BUS
ADDRESS BUS
CHECKSUM
CALCULATOR INTERFACE
ID PARTY
CHECKER
BIT
MONITOR
TXRX ERROR
DETECTOR (TED)
TIMEOUT
CONTROL
COUNTER
LINRX/
SCIRX COMPARE
LINTX/ MASK 8 RECEIVE

SCITX FSM
FILTER BUFFERS
8 TRANSMIT
SYNCHRONIZER
BUFFERS
Figure 7-34. LIN Block Diagram

TMS320F28035, TMS320F28035-Q1
7.9.7 Enhanced Controller Area Network (eCAN) Module

The CAN module (eCAN-A) has the following features:
• Fully compliant with ISO11898-1 (CAN 2.0B)
• Supports data rates up to 1 Mbps
• Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit time stamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
• Low-power mode
• Programmable wake-up on bus activity
• Automatic reply to a remote request message
• Automatic retransmission of a frame in case of loss of arbitration or error
• 32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
• Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby
eliminating the need for another node to provide the acknowledge bit.
Note
For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 4.6875 kbps.
The F2803x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and
exceptions.
For information on using the CAN module with the on-chip zero-pin oscillators, see MCU CAN Module Operation
Using the On-Chip Zero-Pin Oscillator.
For more information on the CAN, see the Controller Area Network (CAN) chapter in the TMS320F2803x

TMS320F28035, TMS320F28035-Q1
eCAN0INT eCAN1INT Controls Address Data
Enhanced CAN Controller 32
Message Controller
Mailbox RAM Memory Management

(512 Bytes) Unit eCAN Memory
(512 Bytes)
CPU Interface, Registers and
32-Message Mailbox Receive Control Unit, Message Objects Control
32 32
of 4 ´ 32-Bit Words Timer Management Unit
32
eCAN Protocol Kernel

Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 7-35. eCAN Block Diagram and Interface Circuit
Table 7-31. 3.3-V eCAN Transceivers

SUPPLY LOW-POWER SLOPE
PART NUMBER VREF OTHER TA
VOLTAGE MODE CONTROL
SN65HVD230 3.3 V Standby Adjustable Yes – –40°C to 85°C
SN65HVD230Q 3.3 V Standby Adjustable Yes – –40°C to 125°C
SN65HVD231 3.3 V Sleep Adjustable Yes – –40°C to 85°C
SN65HVD231Q 3.3 V Sleep Adjustable Yes – –40°C to 125°C
SN65HVD232 3.3 V None None None – –40°C to 85°C
SN65HVD232Q 3.3 V None None None – –40°C to 125°C
SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback –40°C to 125°C
SN65HVD234 3.3 V Standby and Sleep Adjustable None – –40°C to 125°C
SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback –40°C to 125°C
ISO1050 3–5.5 V None None None Built-in Isolation –55°C to 105°C
Low Prop Delay
Thermal Shutdown
Failsafe Operation
Dominant Time-Out

TMS320F28035, TMS320F28035-Q1
eCAN-A Control and Status Registers

Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
eCAN-A Memory (512 Bytes) Abort Acknowledge - CANAA
6000h Received Message Pending - CANRMP
Control and Status Registers
Received Message Lost - CANRML
603Fh
6040h Remote Frame Pending - CANRFP
Local Acceptance Masks (LAM)
(32 ´ 32-Bit RAM) Global Acceptance Mask - CANGAM
607Fh
6080h Master Control - CANMC
Message Object Time Stamps (MOTS)
(32 ´ 32-Bit RAM) Bit-Timing Configuration - CANBTC
60BFh
60C0h Error and Status - CANES
Message Object Time-Out (MOTO)
60FFh (32 ´ 32-Bit RAM) Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
eCAN-A Memory RAM (512 Bytes)
Mailbox Interrupt Mask - CANMIM
6100h-6107h Mailbox 0
Mailbox Interrupt Level - CANMIL
6108h-610Fh Mailbox 1
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
6118h-611Fh Mailbox 3
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h-61E7h Mailbox 28 Reserved

61E8h-61EFh Mailbox 29
61F0h-61F7h Mailbox 30
61F8h-61FFh Mailbox 31
Message Mailbox (16 Bytes)

61E8h-61E9h Message Identifier - MSGID
61EAh-61EBh Message Control - MSGCTRL
61ECh-61EDh Message Data Low - MDL
61EEh-61EFh Message Data High - MDH
Figure 7-36. eCAN-A Memory Map
Note
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for
this.

TMS320F28035, TMS320F28035-Q1
The CAN registers listed in Table 7-32 are used by the CPU to configure and control the CAN controller and
the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 7-32. CAN Register Map
eCAN-A
REGISTER NAME(1) SIZE (x32) DESCRIPTION
ADDRESS
CANME 0x6000 1 Mailbox enable
CANMD 0x6002 1 Mailbox direction
CANTRS 0x6004 1 Transmit request set
CANTRR 0x6006 1 Transmit request reset
CANTA 0x6008 1 Transmission acknowledge
CANAA 0x600A 1 Abort acknowledge
CANRMP 0x600C 1 Receive message pending
CANRML 0x600E 1 Receive message lost
CANRFP 0x6010 1 Remote frame pending
CANGAM 0x6012 1 Global acceptance mask
CANMC 0x6014 1 Master control
CANBTC 0x6016 1 Bit-timing configuration
CANES 0x6018 1 Error and status
CANTEC 0x601A 1 Transmit error counter
CANREC 0x601C 1 Receive error counter
CANGIF0 0x601E 1 Global interrupt flag 0
CANGIM 0x6020 1 Global interrupt mask
CANGIF1 0x6022 1 Global interrupt flag 1
CANMIM 0x6024 1 Mailbox interrupt mask
CANMIL 0x6026 1 Mailbox interrupt level
CANOPC 0x6028 1 Overwrite protection control
CANTIOC 0x602A 1 TX I/O control
CANRIOC 0x602C 1 RX I/O control
CANTSC 0x602E 1 Time stamp counter (Reserved in SCC mode)
CANTOC 0x6030 1 Time-out control (Reserved in SCC mode)
CANTOS 0x6032 1 Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.

TMS320F28035, TMS320F28035-Q1
7.9.8 Inter-Integrated Circuit (I2C)

The device contains one I2C Serial Port. Figure 7-37 shows how the I2C peripheral module interfaces within the
device.
The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 4-word receive FIFO and one 4-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode
For more information on the I2C, see the Inter-Integrated Circuit Module (I2C) chapter in the TMS320F2803x

TMS320F28035, TMS320F28035-Q1
I2C Module
I2CXSR I2CDXR
TX FIFO
SDA FIFO Interrupt to
CPU/PIE
RX FIFO
Peripheral Bus
I2CRSR I2CDRR
Control/Status
Registers CPU
Clock
SCL Synchronizer
Prescaler
Noise Filters
Interrupt to
I2C INT
CPU/PIE
Arbitrator
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the
SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low-power operation. Upon reset,
I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 7-37. I2C Peripheral Module Interfaces
The registers in Table 7-33 configure and control the I2C port operation.
Table 7-33. I2C-A Registers
EALLOW
NAME ADDRESS DESCRIPTION
PROTECTED
I2COAR 0x7900 No I2C own address register
I2CIER 0x7901 No I2C interrupt enable register
I2CSTR 0x7902 No I2C status register
I2CCLKL 0x7903 No I2C clock low-time divider register
I2CCLKH 0x7904 No I2C clock high-time divider register
I2CCNT 0x7905 No I2C data count register
I2CDRR 0x7906 No I2C data receive register
I2CSAR 0x7907 No I2C slave address register
I2CDXR 0x7908 No I2C data transmit register
I2CMDR 0x7909 No I2C mode register
I2CISRC 0x790A No I2C interrupt source register
I2CPSC 0x790C No I2C prescaler register
I2CFFTX 0x7920 No I2C FIFO transmit register
I2CFFRX 0x7921 No I2C FIFO receive register
I2CRSR – No I2C receive shift register (not accessible to the CPU)
I2CXSR – No I2C transmit shift register (not accessible to the CPU)

TMS320F28035, TMS320F28035-Q1
7.9.8.1 I2C Electrical Data/Timing

Section 7.9.8.1.1 shows the I2C timing requirements. Section 7.9.8.1.2 shows the I2C switching characteristics.
7.9.8.1.1 I2C Timing Requirements
MIN MAX UNIT

Hold time, START condition, SCL fall delay
th(SDA-SCL)START 0.6 µs
after SDA fall
Setup time, Repeated START, SCL rise
tsu(SCL-SDA)START 0.6 µs
before SDA fall delay
th(SCL-DAT) Hold time, data after SCL fall 0 µs
tsu(DAT-SCL) Setup time, data before SCL rise 100 ns
tr(SDA) Rise time, SDA Input tolerance 20 300 ns
tr(SCL) Rise time, SCL Input tolerance 20 300 ns
tf(SDA) Fall time, SDA Input tolerance 11.4 300 ns
tf(SCL) Fall time, SCL Input tolerance 11.4 300 ns
Setup time, STOP condition, SCL rise before
tsu(SCL-SDA)STOP 0.6 µs
SDA rise delay
7.9.8.1.2 I2C Switching Characteristics

I2C clock module frequency is from 7 MHz to
fSCL SCL clock frequency 12 MHz and I2C prescaler and clock divider 400 kHz
registers are configured appropriately.
Vil Low level input voltage 0.3 VDDIO V
Vih High level input voltage 0.7 VDDIO V
Vhys Input hysteresis 0.05 VDDIO V
Vol Low level output voltage 3-mA sink current 0 0.4 V
tLOW Low period of SCL clock 12 MHz and I2C prescaler and clock divider 1.3 μs
tHIGH High period of SCL clock 12 MHz and I2C prescaler and clock divider 0.6 μs
Input current with an input voltage from
lI –10 10 μA
0.1 VDDIO to 0.9 VDDIO MAX

TMS320F28035, TMS320F28035-Q1
7.9.9 Enhanced PWM Modules (ePWM1/2/3/4/5/6/7)

The devices contain up to seven enhanced PWM Modules (ePWM). Figure 7-38 shows a block diagram of
multiple ePWM modules. Figure 7-39 shows the signal interconnections with the ePWM. For more details,
see the Enhanced Pulse Width Modulator (ePWM) chapter in the TMS320F2803x Real-Time Microcontrollers
Technical Reference Manual.
Table 7-34 and Table 7-35 show the complete ePWM register set per module.
EPWMSYNCI
EPWM1SYNCI
EPWM1TZINT EPWM1B
EPWM1 TZ1 to TZ3
EPWM1INT
Module
(A)
EPWM2TZINT EQEP1ERR
TZ4
PIE EPWM2INT
CLOCKFAIL
TZ5
EPWMxTZINT
EMUSTOP
EPWMxINT TZ6
EPWM1ENCLK
TBCLKSYNC eCAPI
EPWM1SYNCO
EPWM1SYNCO
EPWM2SYNCI TZ1 to TZ3

COMPOUT1
COMPOUT2 EPWM2B
EPWM2
Module
COMP (A)
EQEP1ERR EPWM1A
TZ4
CLOCKFAIL H
TZ5 EPWM2A
R
EMUSTOP P
TZ6
EPWM2ENCLK W
EPWMxA
M
TBCLKSYNC G
EPWM2SYNCO P
I
Peripheral Bus
M
SOCA1 U
ADC
SOCB1 X
SOCA2
EPWMxSYNCI EPWMxB
SOCB2
SOCAx EPWMx TZ1 to TZ3
SOCBx Module (A)
EQEP1ERR EQEP1ERR
TZ4
CLOCKFAIL
TZ5
EMUSTOP
TZ6 eQEP1
EPWMxENCLK
TBCLKSYNC
System Control
C28x CPU
SOCA1
SOCA2 Pulse Stretch ADCSOCAO
SPCAx (32 SYSCLKOUT Cycles, Active-Low Output)
SOCB1
SOCB2 Pulse Stretch ADCSOCBO
SPCBx (32 SYSCLKOUT Cycles, Active-Low Output)
Copyright © 2017, Texas Instruments Incorporated
A. This signal exists only on devices with an eQEP1 module.
Figure 7-38. ePWM

TMS320F28035, TMS320F28035-Q1
Table 7-34. ePWM1–ePWM4 Control and Status Registers

SIZE (x16) /
NAME ePWM1 ePWM2 ePWM3 ePWM4 DESCRIPTION
#SHADOW
TBCTL 0x6800 0x6840 0x6880 0x68C0 1/0 Time Base Control Register
TBSTS 0x6801 0x6841 0x6881 0x68C1 1/0 Time Base Status Register
TBPHSHR 0x6802 0x6842 0x6882 0x68C2 1/0 Time Base Phase HRPWM Register
TBPHS 0x6803 0x6843 0x6883 0x68C3 1/0 Time Base Phase Register
TBCTR 0x6804 0x6844 0x6884 0x68C4 1/0 Time Base Counter Register
TBPRD 0x6805 0x6845 0x6885 0x68C5 1/1 Time Base Period Register Set
TBPRDHR 0x6806 0x6846 0x6886 0x68C6 1/1 Time Base Period High Resolution Register(1)
CMPCTL 0x6807 0x6847 0x6887 0x68C7 1/0 Counter Compare Control Register
CMPAHR 0x6808 0x6848 0x6888 0x68C8 1/1 Time Base Compare A HRPWM Register
CMPA 0x6809 0x6849 0x6889 0x68C9 1/1 Counter Compare A Register Set
CMPB 0x680A 0x684A 0x688A 0x68CA 1/1 Counter Compare B Register Set
AQCTLA 0x680B 0x684B 0x688B 0x68CB 1/0 Action Qualifier Control Register For Output A
AQCTLB 0x680C 0x684C 0x688C 0x68CC 1/0 Action Qualifier Control Register For Output B
AQSFRC 0x680D 0x684D 0x688D 0x68CD 1/0 Action Qualifier Software Force Register
Action Qualifier Continuous S/W Force
AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1/1
Register Set
DBCTL 0x680F 0x684F 0x688F 0x68CF 1/1 Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay
DBRED 0x6810 0x6850 0x6890 0x68D0 1/0
Count Register
Dead-Band Generator Falling Edge Delay
DBFED 0x6811 0x6851 0x6891 0x68D1 1/0
Count Register
TZSEL 0x6812 0x6852 0x6892 0x68D2 1/0 Trip Zone Select Register(1)
TZDCSEL 0x6813 0x6853 0x6893 0x98D3 1/0 Trip Zone Digital Compare Register
TZCTL 0x6814 0x6854 0x6894 0x68D4 1/0 Trip Zone Control Register(1)
TZEINT 0x6815 0x6855 0x6895 0x68D5 1/0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6816 0x6856 0x6896 0x68D6 1/0 Trip Zone Flag Register (1)
TZCLR 0x6817 0x6857 0x6897 0x68D7 1/0 Trip Zone Clear Register(1)
TZFRC 0x6818 0x6858 0x6898 0x68D8 1/0 Trip Zone Force Register(1)
ETSEL 0x6819 0x6859 0x6899 0x68D9 1/0 Event Trigger Selection Register
ETPS 0x681A 0x685A 0x689A 0x68DA 1/0 Event Trigger Prescale Register
ETFLG 0x681B 0x685B 0x689B 0x68DB 1/0 Event Trigger Flag Register
ETCLR 0x681C 0x685C 0x689C 0x68DC 1/0 Event Trigger Clear Register
ETFRC 0x681D 0x685D 0x689D 0x68DD 1/0 Event Trigger Force Register
PCCTL 0x681E 0x685E 0x689E 0x68DE 1/0 PWM Chopper Control Register
HRCNFG 0x6820 0x6860 0x68A0 0x68E0 1/0 HRPWM Configuration Register(1)
HRPWR 0x6821 - - - 1/0 HRPWM Power Register
HRMSTEP 0x6826 - - - 1/0 HRPWM MEP Step Register
HRPCTL 0x6828 0x6868 0x68A8 0x68E8 1/0 High resolution Period Control Register(1)
TBPRDHRM 0x682A 0x686A 0x68AA 0x68EA 1/ W(2) Time Base Period HRPWM Register Mirror
TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1/ W(2) Time Base Period Register Mirror
CMPAHRM 0x682C 0x686C 0x68AC 0x68EC 1 / W(2) Compare A HRPWM Register Mirror
CMPAM 0x682D 0x686D 0x68AD 0x68ED 1 / W(2) Compare A Register Mirror
DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1/0 Digital Compare Trip Select Register (1)
DCACTL 0x6831 0x6871 0x68B1 0x68F1 1/0 Digital Compare A Control Register(1)
DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1/0 Digital Compare B Control Register(1)

TMS320F28035, TMS320F28035-Q1
Table 7-34. ePWM1–ePWM4 Control and Status Registers (continued)

SIZE (x16) /
NAME ePWM1 ePWM2 ePWM3 ePWM4 DESCRIPTION
#SHADOW
DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1/0 Digital Compare Filter Control Register(1)
DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1/0 Digital Compare Capture Control Register(1)
DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1/1 Digital Compare Filter Offset Register
DCFOFFSETCN
0x6836 0x6876 0x68B6 0x68F6 1/0 Digital Compare Filter Offset Counter Register
T
DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1/0 Digital Compare Filter Window Register
DCFWINDOWCN Digital Compare Filter Window Counter
0x6838 0x6878 0x68B8 0x68F8 1/0
T Register
DCCAP 0x6839 0x6879 0x68B9 0x68F9 1/1 Digital Compare Counter Capture Register
(1) Registers that are EALLOW protected.

(2) W = Write to shadow register
Table 7-35. ePWM5–ePWM7 Control and Status Registers

SIZE (x16) /
NAME ePWM5 ePWM6 ePWM7 DESCRIPTION
#SHADOW
TBCTL 0x6900 0x6940 0x6980 1/0 Time Base Control Register
TBSTS 0x6901 0x6941 0x6981 1/0 Time Base Status Register
TBPHSHR 0x6902 0x6942 0x6982 1/0 Time Base Phase HRPWM Register
TBPHS 0x6903 0x6943 0x6983 1/0 Time Base Phase Register
TBCTR 0x6904 0x6944 0x6984 1/0 Time Base Counter Register
TBPRD 0x6905 0x6945 0x6985 1/1 Time Base Period Register Set
TBPRDHR 0x6906 0x6946 0x6986 1/1 Time Base Period High Resolution Register(1)
CMPCTL 0x6907 0x6947 0x6987 1/0 Counter Compare Control Register
CMPAHR 0x6908 0x6948 0x6988 1/1 Time Base Compare A HRPWM Register
CMPA 0x6909 0x6949 0x6989 1/1 Counter Compare A Register Set
CMPB 0x690A 0x694A 0x698A 1/1 Counter Compare B Register Set
AQCTLA 0x690B 0x694B 0x698B 1/0 Action Qualifier Control Register For Output A
AQCTLB 0x690C 0x694C 0x698C 1/0 Action Qualifier Control Register For Output B
AQSFRC 0x690D 0x694D 0x698D 1/0 Action Qualifier Software Force Register
AQCSFRC 0x690E 0x694E 0x698E 1/1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x690F 0x694F 0x698F 1/1 Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay Count
DBRED 0x6910 0x6950 0x6990 1/0
Register
Dead-Band Generator Falling Edge Delay Count
DBFED 0x6911 0x6951 0x6991 1/0
Register
TZSEL 0x6912 0x6952 0x6992 1/0 Trip Zone Select Register(1)
TZDCSEL 0x6913 0x6953 0x6993 1/0 Trip Zone Digital Compare Register
TZCTL 0x6914 0x6954 0x6994 1/0 Trip Zone Control Register(1)
TZEINT 0x6915 0x6955 0x6995 1/0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6916 0x6956 0x6996 1/0 Trip Zone Flag Register (1)
TZCLR 0x6917 0x6957 0x6997 1/0 Trip Zone Clear Register(1)
TZFRC 0x6918 0x6958 0x6998 1/0 Trip Zone Force Register(1)
ETSEL 0x6919 0x6959 0x6999 1/0 Event Trigger Selection Register
ETPS 0x691A 0x695A 0x699A 1/0 Event Trigger Prescale Register
ETFLG 0x691B 0x695B 0x699B 1/0 Event Trigger Flag Register
ETCLR 0x691C 0x695C 0x699C 1/0 Event Trigger Clear Register
ETFRC 0x691D 0x695D 0x699D 1/0 Event Trigger Force Register

TMS320F28035, TMS320F28035-Q1
Table 7-35. ePWM5–ePWM7 Control and Status Registers (continued)

SIZE (x16) /
NAME ePWM5 ePWM6 ePWM7 DESCRIPTION
#SHADOW
PCCTL 0x691E 0x695E 0x699E 1/0 PWM Chopper Control Register
HRCNFG 0x6920 0x6960 0x69A0 1/0 HRPWM Configuration Register(1)
HRPWR - - - 1/0 HRPWM Power Register
HRMSTEP - - - 1/0 HRPWM MEP Step Register
HRPCTL 0x6928 0x6968 0x69A8 1/0 High resolution Period Control Register(1)
TBPRDHRM 0x692A 0x696A 0x69AA 1 / W(2) Time Base Period HRPWM Register Mirror
TBPRDM 0x692B 0x696B 0x69AB 1/ W(2) Time Base Period Register Mirror
CMPAHRM 0x692C 0x696C 0x69AC 1 / W(2) Compare A HRPWM Register Mirror
CMPAM 0x692D 0x696D 0x69AD 1/ W(2) Compare A Register Mirror
DCTRIPSEL 0x6930 0x6970 0x69B0 1/0 Digital Compare Trip Select Register (1)
DCACTL 0x6931 0x6971 0x69B1 1/0 Digital Compare A Control Register(1)
DCBCTL 0x6932 0x6972 0x69B2 1/0 Digital Compare B Control Register(1)
DCFCTL 0x6933 0x6973 0x69B3 1/0 Digital Compare Filter Control Register(1)
DCCAPCT 0x6934 0x6974 0x69B4 1/0 Digital Compare Capture Control Register(1)
DCFOFFSET 0x6935 0x6975 0x69B5 1/1 Digital Compare Filter Offset Register
DCFOFFSETCNT 0x6936 0x6976 0x69B6 1/0 Digital Compare Filter Offset Counter Register
DCFWINDOW 0x6937 0x6977 0x69B7 1/0 Digital Compare Filter Window Register
DCFWINDOWCNT 0x6938 0x6978 0x69B8 1/0 Digital Compare Filter Window Counter Register
DCCAP 0x6939 0x6979 0x69B9 1/1 Digital Compare Counter Capture Register
(1) Registers that are EALLOW protected.

(2) W = Write to shadow register

TMS320F28035, TMS320F28035-Q1
Time-Base (TB)
CTR=ZERO Sync
TBPRD Shadow (24) In/Out
CTR=CMPB Select EPWMxSYNCO
TBPRDHR (8)
TBPRD Active (24) Disabled Mux
8
CTR=PRD
TBCTL[PHSEN] TBCTL[SYNCOSEL]
EPWMxSYNCI
Counter DCAEVT1.sync
Up/Down DCBEVT1.sync
TBCTL[SWFSYNC]
(16 Bit)
(Software Forced
CTR=ZERO Sync)
TCBNT
Active (16) CTR_Dir CTR=PRD
CTR=ZERO
TBPHSHR (8) CTR=PRD or ZERO EPWMxINT
16 8 CTR=CMPA Event
Trigger EPWMxSOCA
Phase CTR=CMPB
TBPHS Active (24) and
Control CTR_Dir EPWMxSOCB
Interrupt
(A) (ET)
DCAEVT1.soc EPWMxSOCA
(A) ADC
DCBEVT1.soc EPWMxSOCB
Action
Qualifier
CTR=CMPA (AQ)
CMPAHR (8)
16
High-resolution PWM (HRPWM)
CMPA Active (24)
CMPA Shadow (24) EPWMA EPWMxA
Dead PWM Trip

CTR=CMPB Chopper Zone
Band
(DB) (PC) (TZ)
16
EPWMB EPWMxB
CMPB Active (16) EPWMxTZINT
TZ1 to TZ3
CMPB Shadow (16)
EMUSTOP
CTR=ZERO CLOCKFAIL
(B)
DCAEVT1.inter EQEP1ERR
DCBEVT1.inter (A)
DCAEVT1.force
DCAEVT2.inter (A)
DCBEVT2.inter DCAEVT2.force
(A)
DCBEVT1.force
(A)
DCBEVT2.force
A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ
signals.
B. This signal exists only on devices with an eQEP1 module.
Figure 7-39. ePWM Submodules Showing Critical Internal Signal Interconnections

TMS320F28035, TMS320F28035-Q1
7.9.9.1 ePWM Electrical Data/Timing

PWM refers to PWM outputs on ePWM1–7. Section 7.9.9.1.1 shows the PWM timing requirements and Section
7.9.9.1.2, switching characteristics.
7.9.9.1.1 ePWM Timing Requirements
MIN MAX UNIT

Asynchronous 2tc(SCO) cycles
tw(SYCIN) (1) Sync input pulse width Synchronous 2tc(SCO) cycles
With input qualifier 1tc(SCO) + tw(IQSW) cycles
7.9.9.1.2 ePWM Switching Characteristics

tw(PWM) Pulse duration, PWMx output high/low 33.33 ns
tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles
Delay time, trip input active to PWM forced high
td(PWM)tza no pin load 25 ns
Delay time, trip input active to PWM forced low
td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns
7.9.9.2 Trip-Zone Input Timing

7.9.9.2.1 Trip-Zone Input Timing Requirements
MIN MAX UNIT

Asynchronous 2tc(TBCLK) cycles
tw(TZ) (1) Pulse duration, TZx input low Synchronous 2tc(TBCLK) cycles
With input qualifier 2tc(TBCLK) + tw(IQSW) cycles
SYSCLK
tw(TZ)
(A)
TZ
td(TZ-PWM)HZ
(B)
PWM
A. TZ - TZ1, TZ2, TZ3 , TZ4, TZ5, TZ6

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery
software.
Figure 7-40. PWM Hi-Z Characteristics

TMS320F28035, TMS320F28035-Q1
7.9.10 High-Resolution PWM (HRPWM)

This module combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module there is one HR delay line.
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A and
Phase registers of the ePWM module.
• HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an
ePWM module (that is, on the EPWMxA output). EPWMxB output has conventional PWM capabilities.
Note
The minimum SYSCLKOUT frequency allowed for HRPWM is 60 MHz.
Note
When dual-edge high-resolution is enabled (high-resolution period mode), the PWMxB output is not
available for use.
For more information on the HRPWM, see the High-Resolution Pulse Width Modulator (HRPWM) chapter in the
7.9.10.1 HRPWM Electrical Data/Timing
Section 7.9.10.1.1 shows the high-resolution PWM switching characteristics.
7.9.10.1.1 High-Resolution PWM Characteristics
PARAMETER(1) MIN TYP MAX UNIT

Micro Edge Positioning (MEP) step size(2) 150 310 ps
(1) The HRPWM operates at a minimum SYSCLKOUT frequency of 60 MHz.

(2) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.

TMS320F28035, TMS320F28035-Q1
7.9.11 Enhanced Capture Module (eCAP1)

The device contains an enhanced capture (eCAP) module. Figure 7-41 shows a functional block diagram of a
module.
CTRPHS
(phase register−32 bit) APWM mode
SYNC
SYNCIn
OVF CTR_OVF
TSCTR CTR [0−31]
SYNCOut PWM
(counter−32 bit) Delta−mode PRD [0−31] compare
RST
logic
CMP [0−31]
32
CTR [0−31] CTR=PRD

CTR=CMP
32
PRD [0−31]
eCAPx
MODE SELECT
32 CAP1 LD1 Polarity
LD
(APRD active) select
APRD 32
shadow CMP [0−31]
32
32 CAP2 LD2 Polarity

LD
(ACMP active) select
Event Event
32 ACMP
qualifier
shadow Prescale
32 Polarity
CAP3 LD3 select
LD
(APRD shadow)
32 CAP4 LD4
LD Polarity
(ACMP shadow) select
4
Capture events 4
CEVT[1:4]
Interrupt Continuous /
to PIE Trigger Oneshot
and CTR_OVF Capture Control
Flag
CTR=PRD
control
CTR=CMP
Figure 7-41. eCAP Functional Block Diagram
The eCAP module is clocked at the SYSCLKOUT rate.

The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for
low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.

TMS320F28035, TMS320F28035-Q1
Table 7-36. eCAP Control and Status Registers

NAME eCAP1 SIZE (x16) EALLOW PROTECTED DESCRIPTION
TSCTR 0x6A00 2 Time-Stamp Counter
CTRPHS 0x6A02 2 Counter Phase Offset Value Register
CAP1 0x6A04 2 Capture 1 Register
CAP4 0x6A0A 2 Capture 4 Register
Reserved 0x6A0C to 0x6A12 8 Reserved
ECCTL1 0x6A14 1 Capture Control Register 1
ECCTL2 0x6A15 1 Capture Control Register 2
ECEINT 0x6A16 1 Capture Interrupt Enable Register
ECFLG 0x6A17 1 Capture Interrupt Flag Register
ECCLR 0x6A18 1 Capture Interrupt Clear Register
ECFRC 0x6A19 1 Capture Interrupt Force Register
Reserved 0x6A1A to 0x6A1F 6 Reserved
For more information on the eCAP, see the Enhanced Capture (eCAP) Module chapter in the TMS320F2803x
7.9.11.1 eCAP Electrical Data/Timing
Section 7.9.11.1.1 shows the eCAP timing requirement and Section 7.9.11.1.2 shows the eCAP switching
characteristics.
7.9.11.1.1 Enhanced Capture (eCAP) Timing Requirement
MIN MAX UNIT

Asynchronous 2tc(SCO) cycles
tw(CAP) (1) Capture input pulse width Synchronous 2tc(SCO) cycles
With input qualifier 1tc(SCO) + tw(IQSW) cycles
7.9.11.1.2 eCAP Switching Characteristics

tw(APWM) Pulse duration, APWMx output high/low 20 ns

TMS320F28035, TMS320F28035-Q1
7.9.12 High-Resolution Capture (HRCAP) Module

The High-Resolution Capture (HRCAP) module measures the difference between external pulses with a typical
resolution of 300 ps.
Uses for the HRCAP include:
• Capactive touch applications
• High-resolution period and duty cycle measurements of pulse train cycles
• Instantaneous speed measurements
• Instantaneous frequency measurements
• Voltage measurements across an isolation boundary
• Distance/sonar measurement and scanning
The HRCAP module features include:
• Pulse width capture in either non-high-resolution or high-resolution modes
• Difference (Delta) mode pulse width capture
• Typical high-resolution capture on the order of 300 ps resolution on each edge
• Interrupt on either falling or rising edge
• Continuous mode capture of pulse widths in 2-deep buffer
• Calibration logic for precision high-resolution capture
• All of the above resources are dedicated to a single input pin
• HRCAP calibration software library supplied by TI is used for both calibration and calculating fractional pulse
widths
The HRCAP module includes one capture channel in addition to a high-resolution calibration block, which
connects internally to the last available ePWMxA HRPWM channel when calibrating (that is, if there are eight
ePWMs with HRPWM capability, it will be HRPWM8A).
Each HRCAP channel has the following independent key resources:
• Dedicated input capture pin
• 16-bit HRCAP clock which is either equal to the PLL output frequency (asynchronous to SYSCLK) or equal to
the SYSCLK frequency (synchronous to SYSCLK)
• High-resolution pulse width capture in a 2-deep buffer
HRCAP Calibration Logic
HRCAPxENCLK EPWMx EPWMxA HRPWM
SYSCLK
PLLCLK HRCAPx GPIO

Module HRCAP Calibration Signal (Internal) Mux
PIE
HRCAPxINTn
HRCAPx
Figure 7-42. HRCAP Functional Block Diagram

TMS320F28035, TMS320F28035-Q1
Table 7-37. HRCAP Registers

NAME HRCAP1 HRCAP2 SIZE (x16) DESCRIPTION
HCCTL 0x6AC0 0x6AE0 1 HRCAP Control Register(1)
HCIFR 0x6AC1 0x6AE1 1 HRCAP Interrupt Flag Register
HCICLR 0x6AC2 0x6AE2 1 HRCAP Interrupt Clear Register
HCIFRC 0x6AC3 0x6AE3 1 HRCAP Interrupt Force Register
HCCOUNTER 0x6AC4 0x6AE4 1 HRCAP 16-bit Counter Register
HCCAPCNTRISE0 0x6AD0 0x6AF0 1 HRCAP Capture Counter on Rising Edge 0 Register
HCCAPCNTFALL0 0x6AD2 0x6AF2 1 HRCAP Capture Counter on Falling Edge 0 Register
HCCAPCNTRISE1 0x6AD8 0x6AF8 1 HRCAP Capture Counter on Rising Edge 1 Register
HCCAPCNTFALL1 0x6ADA 0x6AFA 1 HRCAP Capture Counter on Falling Edge 1 Register
(1) Registers that are EALLOW-protected.
For more information on the HRCAP, see the High Resolution Capture (HRCAP) chapter in the TMS320F2803x
7.9.12.1 HRCAP Electrical Data/Timing
7.9.12.1.1 High-Resolution Capture (HRCAP) Timing Requirements
MIN NOM MAX UNIT

tc(HCCAPCLK) Cycle time, HRCAP capture clock 8.333 10.204 ns
tw(HRCAP) Pulse width, HRCAP capture 7tc(HCCAPCLK) (1) ns
HRCAP step size(2) 300 ps
(1) The listed minimum pulse width does not take into account the limitation that all relevant HCCAP registers must be read and RISE/
FALL event flags cleared within the pulse width to ensure valid capture data.
(2) HRCAP step size will increase with low voltage and high temperature and decrease with high voltage and low temperature.
Applications that use the HRCAP in high-resolution mode should use the HRCAP calibration functions to dynamically calibrate for
varying operating conditions.

TMS320F28035, TMS320F28035-Q1
7.9.13 Enhanced Quadrature Encoder Pulse (eQEP)

The device contains one enhanced quadrature encoder pulse (eQEP) module.
Table 7-38. eQEP Control and Status Registers
eQEP1
eQEP1
NAME SIZE(x16)/ REGISTER DESCRIPTION
ADDRESS
#SHADOW
QPOSCNT 0x6B00 2/0 eQEP Position Counter
QPOSINIT 0x6B02 2/0 eQEP Initialization Position Count
QPOSMAX 0x6B04 2/0 eQEP Maximum Position Count
QPOSCMP 0x6B06 2/1 eQEP Position-compare
QPOSILAT 0x6B08 2/0 eQEP Index Position Latch
QPOSSLAT 0x6B0A 2/0 eQEP Strobe Position Latch
QPOSLAT 0x6B0C 2/0 eQEP Position Latch
QUTMR 0x6B0E 2/0 eQEP Unit Timer
QUPRD 0x6B10 2/0 eQEP Unit Period Register
QWDTMR 0x6B12 1/0 eQEP Watchdog Timer
QWDPRD 0x6B13 1/0 eQEP Watchdog Period Register
QDECCTL 0x6B14 1/0 eQEP Decoder Control Register
QEPCTL 0x6B15 1/0 eQEP Control Register
QCAPCTL 0x6B16 1/0 eQEP Capture Control Register
QPOSCTL 0x6B17 1/0 eQEP Position-compare Control Register
QEINT 0x6B18 1/0 eQEP Interrupt Enable Register
QFLG 0x6B19 1/0 eQEP Interrupt Flag Register
QCLR 0x6B1A 1/0 eQEP Interrupt Clear Register
QFRC 0x6B1B 1/0 eQEP Interrupt Force Register
QEPSTS 0x6B1C 1/0 eQEP Status Register
QCTMR 0x6B1D 1/0 eQEP Capture Timer
QCPRD 0x6B1E 1/0 eQEP Capture Period Register
QCTMRLAT 0x6B1F 1/0 eQEP Capture Timer Latch
QCPRDLAT 0x6B20 1/0 eQEP Capture Period Latch
0x6B21 –
Reserved 31/0
0x6B3F
For more information on the eQEP, see the Enhanced QEP (eQEP) Module chapter in the TMS320F2803x

TMS320F28035, TMS320F28035-Q1
Figure 7-43 shows the eQEP functional block diagram.

System Control
Registers
To CPU
EQEPxENCLK
SYSCLKOUT
Data Bus
QCPRD
QCAPCTL QCTMR
16 16
16
Quadrature
Capture
QCTMRLAT Unit
(QCAP)
QCPRDLAT
Registers QUTMR QWDTMR

Used by QUPRD QWDPRD
Multiple Units
32 16
QEPCTL
QEPSTS UTOUT
UTIME QWDOG QDECCTL
QFLG
16
WDTOUT
EQEPxAIN
EQEPxINT QCLK EQEPxA/XCLK
PIE EQEPxBIN
QDIR
EQEPxIIN
16 Position Counter/ QI EQEPxB/XDIR
EQEPxIOUT
Control Unit QS Quadrature GPIO
(PCCU) Decoder EQEPxIOE
QPOSLAT PHE (QDU) MUX EQEPxI
EQEPxSIN
QPOSSLAT PCSOUT
EQEPxSOUT
QPOSILAT EQEPxS
EQEPxSOE
32 32 16
QPOSCNT QPOSCMP QEINT

QPOSINIT QFRC
QPOSMAX QCLR
QPOSCTL
eQEP Peripheral
Figure 7-43. eQEP Functional Block Diagram

TMS320F28035, TMS320F28035-Q1
7.9.13.1 eQEP Electrical Data/Timing

Section 7.9.13.1.1 shows the eQEP timing requirement and Section 7.9.13.1.2 shows the eQEP switching
characteristics.
7.9.13.1.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
MIN MAX UNIT

Asynchronous(1)/synchronous 2tc(SCO) cycles
tw(QEPP) QEP input period
With input qualifier(2) 2[1tc(SCO) + tw(IQSW)] cycles
tw(INDEXH) QEP Index Input High time
With input qualifier(2) 2tc(SCO) +tw(IQSW) cycles
tw(INDEXL) QEP Index Input Low time
With input qualifier(2) 2tc(SCO) + tw(IQSW) cycles
tw(STROBH) QEP Strobe High time
With input qualifier(2) 2tc(SCO) + tw(IQSW) cycles
tw(STROBL) QEP Strobe Input Low time
With input qualifier(2) 2tc(SCO) +tw(IQSW) cycles
(1) Refer to the TMS320F2803x Real-Time MCUs Silicon Errata for limitations in the asynchronous mode.
7.9.13.1.2 eQEP Switching Characteristics

td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles
Delay time, QEP input edge to position compare sync
td(PCS-OUT)QEP 6tc(SCO) cycles
output

TMS320F28035, TMS320F28035-Q1
7.9.14 JTAG Port

On the 2803x device, the JTAG port is reduced to 5 pins ( TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS
and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the pins
in Figure 7-44. During emulation/debug, the GPIO function of these pins are not available. If the GPIO38/TCK/
XCLKIN pin is used to provide an external clock, an alternate clock source should be used to clock the device
during emulation/debug because this pin will be needed for the TCK function.
Note
In 2803x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in the board
design to ensure that the circuitry connected to these pins do not affect the emulation capabilities of
the JTAG pin function. Any circuitry connected to these pins should not prevent the JTAG debug probe
from driving (or being driven by) the JTAG pins for successful debug.
TRST = 0: JTAG Disabled (GPIO Mode)

TRST = 1: JTAG Mode
TRST
TRST
XCLKIN
GPIO38_in
TCK
TCK/GPIO38
GPIO38_out
C28x
Core
GPIO37_in
TDO
TDO/GPIO37 1
0 GPIO37_out
GPIO36_in
1
TMS
TMS/GPIO36
GPIO36_out 1 0
GPIO35_in
1
TDI
TDI/GPIO35
GPIO35_out 1 0
Figure 7-44. JTAG/GPIO Multiplexing

TMS320F28035, TMS320F28035-Q1
7.9.15 General-Purpose Input/Output (GPIO) MUX

The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to
providing individual pin bit-banging I/O capability.
The device supports 45 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1
to enable 32-bit operations on the registers (along with 16-bit operations). Table 7-39 shows the GPIO register
mapping.
Table 7-39. GPIO Registers
NAME ADDRESS SIZE (x16) DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31)
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)
GPAPUD 0x6F8C 2 GPIO A Pullup Disable Register (GPIO0 to 31)
GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 44)
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 44)
GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 44)
GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 44)
GPBPUD 0x6F9C 2 GPIO B Pullup Disable Register (GPIO32 to 44)
AIOMUX1 0x6FB6 2 Analog, I/O mux 1 register (AIO0 to AIO15)
AIODIR 0x6FBA 2 Analog, I/O Direction Register (AIO0 to AIO15)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31)
GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 44)
GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 44)
GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 44)
GPBTOGGLE 0x6FCE 2 GPIO B Data Toggle Register (GPIO32 to 44)
AIODAT 0x6FD8 2 Analog I/O Data Register (AIO0 to AIO15)
AIOSET 0x6FDA 2 Analog I/O Data Set Register (AIO0 to AIO15)
AIOCLEAR 0x6FDC 2 Analog I/O Data Clear Register (AIO0 to AIO15)
AIOTOGGLE 0x6FDE 2 Analog I/O Data Toggle Register (AIO0 to AIO15)
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)
Note
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn and
GPxQSELn registers occurs to when the action is valid.

TMS320F28035, TMS320F28035-Q1
Table 7-40. GPIOA MUX

DEFAULT AT RESET
PERIPHERAL PERIPHERAL PERIPHERAL
PRIMARY I/O
SELECTION 1(1) (2) SELECTION 2(1) (2) SELECTION 3(1) (2)
FUNCTION
GPAMUX1 REGISTER
(GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01) (GPAMUX1 BITS = 10) (GPAMUX1 BITS = 11)
BITS
1-0 GPIO0 EPWM1A (O) Reserved Reserved
3-2 GPIO1 EPWM1B (O) Reserved COMP1OUT (O)
7-6 GPIO3 EPWM2B (O) SPISOMIA (I/O) COMP2OUT (O)
11-10 GPIO5 EPWM3B (O) SPISIMOA (I/O) ECAP1 (I/O)
13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O)
15-14 GPIO7 EPWM4B (O) SCIRXDA (I) Reserved
17-16 GPIO8 EPWM5A (O) Reserved ADCSOCAO (O)
19-18 GPIO9 EPWM5B (O) LINTXA (O) HRCAP1 (I)
21-20 GPIO10 EPWM6A (O) Reserved ADCSOCBO (O)
23-22 GPIO11 EPWM6B (O) LINRXA (I) HRCAP2 (I)
25-24 GPIO12 TZ1 (I) SCITXDA (O) SPISIMOB (I/O)
27-26 GPIO13(3) TZ2 (I) Reserved SPISOMIB (I/O)
29-28 GPIO14(3) TZ3 (I) LINTXA (O) SPICLKB (I/O)
31-30 GPIO15(3) TZ1 (I) LINRXA (I) SPISTEB (I/O)
GPAMUX2 REGISTER
(GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01) (GPAMUX2 BITS = 10) (GPAMUX2 BITS = 11)
BITS
1-0 GPIO16 SPISIMOA (I/O) Reserved TZ2 (I)
3-2 GPIO17 SPISOMIA (I/O) Reserved TZ3 (I)
5-4 GPIO18 SPICLKA (I/O) LINTXA (O) XCLKOUT (O)
7-6 GPIO19/XCLKIN SPISTEA (I/O) LINRXA (I) ECAP1 (I/O)
9-8 GPIO20 EQEP1A (I) Reserved COMP1OUT (O)
11-10 GPIO21 EQEP1B (I) Reserved COMP2OUT (O)
13-12 GPIO22 EQEP1S (I/O) Reserved LINTXA (O)
15-14 GPIO23 EQEP1I (I/O) Reserved LINRXA (I)
17-16 GPIO24 ECAP1 (I/O) Reserved SPISIMOB (I/O)
19-18 GPIO25(3) Reserved Reserved SPISOMIB (I/O)
21-20 GPIO26(3) HRCAP1 (I) Reserved SPICLKB (I/O)
23-22 GPIO27(3) HRCAP2 (I) Reserved SPISTEB (I/O)
25-24 GPIO28 SCIRXDA (I) SDAA (I/OD) TZ2 (I)
27-26 GPIO29 SCITXDA (O) SCLA (I/OD) TZ3 (I)
29-28 GPIO30 CANRXA (I) Reserved Reserved
31-30 GPIO31 CANTXA (O) Reserved Reserved
(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(2) I = Input, O = Output, OD = Open Drain
(3) These pins are not available in the 64-pin package.

TMS320F28035, TMS320F28035-Q1
Table 7-41. GPIOB MUX

DEFAULT AT RESET PERIPHERAL PERIPHERAL PERIPHERAL
PRIMARY I/O FUNCTION SELECTION 1(1) SELECTION 2(1) SELECTION 3(1)
GPBMUX1 REGISTER
(GPBMUX1 BITS = 00) (GPBMUX1 BITS = 01) (GPBMUX1 BITS = 10) (GPBMUX1 BITS = 11)
BITS
1-0 GPIO32 SDAA (I/OD) EPWMSYNCI (I) ADCSOCAO (O)
3-2 GPIO33 SCLA (I/OD) EPWMSYNCO (O) ADCSOCBO (O)
5-4 GPIO34 COMP2OUT (O) Reserved COMP3OUT (O)
7-6 GPIO35 (TDI) Reserved Reserved Reserved
9-8 GPIO36 (TMS) Reserved Reserved Reserved
11-10 GPIO37 (TDO) Reserved Reserved Reserved
13-12 GPIO38/XCLKIN (TCK) Reserved Reserved Reserved
15-14 GPIO39(2) Reserved Reserved Reserved
17-16 GPIO40(2) EPWM7A (O) Reserved Reserved
19-18 GPIO41(2) EPWM7B (O) Reserved Reserved
21-20 GPIO42(2) Reserved Reserved COMP1OUT (O)
23-22 GPIO43(2) Reserved Reserved COMP2OUT (O)
25-24 GPIO44(2) Reserved Reserved Reserved
27-26 Reserved Reserved Reserved Reserved
(1) I = Input, O = Output, OD = Open Drain

(2) These pins are not available in the 64-pin package.
Table 7-42. Analog MUX for 80-Pin PN Package

DEFAULT AT RESET
PERIPHERAL SELECTION 2 AND
AIOx AND PERIPHERAL SELECTION 1(1)
PERIPHERAL SELECTION 3(1)
AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x
1-0 ADCINA0 (I) ADCINA0 (I)
5-4 AIO2 (I/O) ADCINA2 (I), COMP1A (I)
17-16 ADCINB0 (I) ADCINB0 (I)
21-20 AIO10 (I/O) ADCINB2 (I), COMP1B (I)
(1) I = Input, O = Output

TMS320F28035, TMS320F28035-Q1
Table 7-43. Analog MUX for 56-Pin RSH and 64-Pin PAG Packages
DEFAULT AT RESET
PERIPHERAL SELECTION 2 AND
AIOx AND PERIPHERAL SELECTION 1(1)
PERIPHERAL SELECTION 3(1)
AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x
1-0 ADCINA0 (I), VREFHI (I) ADCINA0 (I), VREFHI (I)
11-10 – –
27-26 – –
(1) I = Input, O = Output
The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from
four choices:
• Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at
reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the
input is allowed to change.
• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling
window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the
same (all 0s or all 1s) as shown in Figure 7-47 (for 6 sample mode).
• No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not
required (synchronization is performed within the peripheral).
Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input
signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will
default to either a 0 or 1 state, depending on the peripheral.

TMS320F28035, TMS320F28035-Q1
GPIOXINT1SEL
GPIOLMPSEL GPIOXINT2SEL
LPMCR0 GPIOXINT3SEL
Low-Power External Interrupt PIE

Modes Block MUX
Asynchronous
path GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD 00 N/C
01 Peripheral 1 Input
Input
Internal
Qualification
Pullup 10 Peripheral 2 Input
11 Peripheral 3 Input
Asynchronous path GPxTOGGLE
GPIOx pin GPxCLEAR
GPxSET
00 GPxDAT (latch)
01 Peripheral 1 Output
High Impedance
Output Control
00 GPxDIR (latch)
0 = Input, 1 = Output 01 Peripheral 1 Output Enable
10 Peripheral 2 Output Enable
XRS
11 Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular
GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. For pin-specific variations, see the
System Control chapter in the TMS320F2803x Real-Time Microcontrollers Technical Reference Manual.
Figure 7-45. GPIO Multiplexing

TMS320F28035, TMS320F28035-Q1
7.9.15.1 GPIO Electrical Data/Timing

7.9.15.1.1 GPIO - Output Timing
7.9.15.1.1.1 General-Purpose Output Switching Characteristics
tr(GPO) Rise time, GPIO switching low to high All GPIOs 13(1) ns
tf(GPO) Fall time, GPIO switching high to low All GPIOs 13(1) ns
tfGPO Toggling frequency 15 MHz
(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Section 7.9.15.1.1.1 are applicable for a 40-pF load on
I/O pins.
GPIO
t r(GPO)
t f(GPO)
Figure 7-46. General-Purpose Output Timing

TMS320F28035, TMS320F28035-Q1
7.9.15.1.2 GPIO - Input Timing

7.9.15.1.2.1 General-Purpose Input Timing Requirements
MIN MAX UNIT

QUALPRD = 0 1tc(SCO) cycles
tw(SP) Sampling period
QUALPRD ≠ 0 2tc(SCO) * QUALPRD cycles
tw(IQSW) Input qualifier sampling window tw(SP) * (n(1) – 1) cycles
Synchronous mode 2tc(SCO) cycles
tw(GPI) (2) Pulse duration, GPIO low/high
With input qualifier tw(IQSW) + tw(SP) + 1tc(SCO) cycles
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal GPxQSELn = 1,0 (6 samples)
1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1
tw(SP) Sampling Period determined

(B)
by GPxCTRL[QUALPRD]
tw(IQSW)
(C)
Sampling Window [(SYSCLKOUT cycle * 2 * QUALPRD) * 5 ]
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in
2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to
occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 7-47. Sampling Mode

TMS320F28035, TMS320F28035-Q1
7.9.15.1.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 7-48. General-Purpose Input Timing
VDDIO
> 1 MS
2 pF
VSS VSS
Figure 7-49. Input Resistance Model for a GPIO Pin With an Internal Pullup

TMS320F28035, TMS320F28035-Q1
7.9.15.1.4 Low-Power Mode Wakeup Timing

Section 7.9.15.1.4.1 shows the timing requirements, Section 7.9.15.1.4.2 shows the switching characteristics,
and Figure 7-50 shows the timing diagram for IDLE mode.
7.9.15.1.4.1 IDLE Mode Timing Requirements
MIN MAX UNIT

Without input qualifier 2tc(SCO)
tw(WAKE-INT) Pulse duration, external wake-up signal cycles
With input qualifier(1) 5tc(SCO) + tw(IQSW)
7.9.15.1.4.2 IDLE Mode Switching Characteristics

Delay time, external wake signal to program execution resume (1) cycles
• Wake up from Flash Without input qualifier 20tc(SCO)
cycles
– Flash module in active state With input qualifier(2) 20tc(SCO) + tw(IQSW)
td(WAKE-IDLE) • Wake up from Flash Without input qualifier 1050tc(SCO)

1050tc(SCO) + cycles
– Flash module in sleep state With input qualifier(2)
tw(IQSW)
• Wake up from SARAM cycles
With input qualifier(2) 20tc(SCO) + tw(IQSW)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
td(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE−INT)
(A)(B)
WAKE INT
A. WAKE INT can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles
(minimum) is needed before the wake-up signal could be asserted.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 7-50. IDLE Entry and Exit Timing

TMS320F28035, TMS320F28035-Q1
7.9.15.1.4.3 STANDBY Mode Timing Requirements
MIN MAX UNIT
Pulse duration, external Without input qualification 3tc(OSCCLK)

tw(WAKE-INT) cycles
wake-up signal With input qualification(1) (2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
7.9.15.1.4.4 STANDBY Mode Switching Characteristics

Delay time, IDLE instruction
td(IDLE-XCOL) 32tc(SCO) 45tc(SCO) cycles
executed to XCLKOUT low
Delay time, external wake signal to program execution
cycles
resume(1)
• Wake up from flash Without input qualifier 100tc(SCO)
cycles
– Flash module in active state With input qualifier 100tc(SCO) + tw(WAKE-INT)
td(WAKE-STBY)
• Wake up from flash Without input qualifier 1125tc(SCO)
cycles
– Flash module in sleep state With input qualifier 1125tc(SCO) + tw(WAKE-INT)

• Wake up from SARAM cycles
With input qualifier 100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.

TMS320F28035, TMS320F28035-Q1
(A) (C) (F)

(B) (D)(E) (G)
Device STANDBY STANDBY Normal Execution

Status
Flushing Pipeline
Wake-up
(H)
Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/X2 or
XCLKIN
XCLKOUT
td(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.

B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off:
• 16 cycles, when DIVSEL = 00 or 01
• 32 cycles, when DIVSEL = 10
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the
device may not exit low-power mode for subsequent wake-up pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
Figure 7-51. STANDBY Entry and Exit Timing Diagram

TMS320F28035, TMS320F28035-Q1
7.9.15.1.4.5 HALT Mode Timing Requirements
MIN MAX UNIT

tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) cycles
tw(WAKE-XRS) Pulse duration, XRS wake-up signal toscst + 8tc(OSCCLK) cycles
7.9.15.1.4.6 HALT Mode Switching Characteristics

td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
tp PLL lock-up time 1 ms
Delay time, PLL lock to program execution resume
• Wake up from flash 1125tc(SCO) cycles
td(WAKE-HALT) – Flash module in sleep state
• Wake up from SARAM 35tc(SCO) cycles

TMS320F28035, TMS320F28035-Q1
(A) (C) (F) (H)

(B) (D)(E) (G)
Device
HALT HALT
Status
Flushing Pipeline PLL Lock-up Time Normal

Wake-up Latency Execution
(I)
GPIOn
td(WAKE−HALT )
tw(WAKE-GPIO)
tp
X1/X2 or
XCLKIN
Oscillator Start-up Time
XCLKOUT
td(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.

B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off
and the CLKIN to the core is stopped:
• 16 cycles, when DIVSEL = 00 or 01
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. It is possible
to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT mode. This is done by writing to
the appropriate bits in the CLKCTL register. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed
before the wake-up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up
sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean
clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure,
care should be taken to maintain a low noise environment prior to entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the
device may not exit low-power mode for subsequent wake-up pulses.
F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.
G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited.
H. Normal operation resumes.
I. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
Figure 7-52. HALT Mode Wakeup Using GPIOn

TMS320F28035, TMS320F28035-Q1
8 Applications, Implementation, and Layout

Note
Information in the following sections is not part of the TI component specification, and TI does not
warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of
components for their purposes. Customers should validate and test their design implementation to
confirm system functionality.
8.1 TI Reference Design

The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at the Select TI reference designs page.
Multiple Channels of High Density LED Control for Automotive Headlight Applications
This design, featuring the TMS320F2803x microcontroller, implements a high-efficiency, multichannel DC-DC
LED control system for typically automotive lighting systems. The design support up to six channels of LED
controls, each with a maximum of 1.2-A current driving capabilities. With a 2-stage power topology of boost
and buck, the system can be operated with a wide input DC voltage from 8 V to 20 V, which fits perfectly in
automotive applications.
Automotive Digitally Controlled Boost Power Supply
This TI reference design is an automotive voltage boost converter module. The purpose of this module is to
supply a steady voltage to vehicle electronics by boosting during voltage droop events such as engine crank.
The design is based on the C2000 Real-Time Microcontroller, and will provide up to 400 Watts of power from a
12-V automotive battery system. This solution supports continuous operational input voltage of 6 V to 16 V with
protection against 36-V load dump to provide a stable 12-V output supply with reverse battery protection.

TMS320F28035, TMS320F28035-Q1
9 Device and Documentation Support

9.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320 MCU commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS320F28032). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/
tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
TMP Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
TMS Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, PN) and temperature range (for example, T). Figure 9-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F2803x Real-Time
MCUs Silicon Errata.

TMS320F28035, TMS320F28035-Q1
A. For more information on peripheral, temperature, and package availability for a specific device, see Table 4-1.
Figure 9-1. Device Nomenclature
9.2 Tools and Software

TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
Code Composer Studio (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller
and Embedded Processors portfolio. CCS comprises a suite of tools used to develop and debug embedded
applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,
profiler, and many other features. The intuitive IDE provides a single user interface taking you through each
step of the application development flow. Familiar tools and interfaces allow users to get started faster than
ever before. CCS combines the advantages of the Eclipse software framework with advanced embedded debug
capabilities from TI resulting in a compelling feature-rich development environment for embedded developers.
Software Tools
powerSUITE - Digital Power Supply Design Software Tools for C2000™ MCUs
powerSUITE is a suite of digital power supply design software tools for Texas Instruments' C2000 real-time
microcontroller (MCU) family. powerSUITE helps power supply engineers drastically reduce development time
as they design digitally-controlled power supplies based on C2000 real-time control MCUs.
C2000Ware for C2000 MCUs
C2000Ware for C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.

TMS320F28035, TMS320F28035-Q1
C2000 Third-party search tool

TI has partnered with multiple companies to offer a wide range of solutions and services for TI C2000 devices.
These companies can accelerate your path to production using C2000 devices. Download this search tool to
quickly browse third-party details and find the right third-party to meet your needs.
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable
hands-on workshops provides an easy means for gaining a complete working knowledge of the C2000
microcontroller family. These training resources have been designed to decrease the learning curve, while
reducing development time, and accelerating product time to market. For more information on the various
training resources, visit the C2000™ real-time control MCUs – Support & training site.
Specific TMS320F2803x hands-on training resources can be found within C2000 Academy on TI Resource
Explorer.
9.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320F2803x Real-Time MCUs Silicon Errata describes known advisories on silicon and provides
workarounds.
Technical Reference Manual
TMS320F2803x Real-Time Microcontrollers Technical Reference Manual details the integration, the
environment, the functional description, and the programming models for each peripheral and subsystem in
the device.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and
the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also
describes emulation features available on these DSPs.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
digital signal processors (DSPs).
Tools Guides
TMS320C28x Assembly Language Tools v22.6.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v22.6.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.

TMS320F28035, TMS320F28035-Q1
Application Reports
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts their
application in perspective with respect to system-level junction temperature estimation.
Calculating FIT for a Mission Profile explains how use TI’s reliability de-rating tools to calculate a component
level FIT under power on conditions for a system mission profile.
Oscillator Compensation Guide describes a factory supplied method for compensating the internal oscillators for
frequency drift caused by temperature.
MCU CAN Module Operation Using the On-Chip Zero-Pin Oscillator.
The TMS320F2803x/TMS320F2805x/TMS320F2806x series of microcontrollers have an on-chip zero-pin
oscillator that needs no external components. This application report describes how to use the CAN module
with this oscillator to operate at the maximum bit rate and bus length without the added cost of an external clock
source.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TMS320C2000™, TMS320™, and TI E2E™ are trademarks of Texas Instruments.
I2C-bus® is a registered trademark of NXP B.V. Corporation.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

TMS320F28035, TMS320F28035-Q1
10 Revision History
Changes from June 12, 2021 to January 31, 2024 (from Revision P (June 2021) to Revision Q
(January 2024)) Page
• Device Comparison table: Updated SPI and SCI rows...................................................................................... 6
• Flash Parameters at 60-MHz SYSCLKOUT table: Updated Program Time and Erase Time units..................38
• Tools and Software section: Updated Training link.........................................................................................143

TMS320F28035, TMS320F28035-Q1
11 Mechanical, Packaging, and Orderable Information

11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 14-Sep-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TMS320F28030PAGQ ACTIVE TQFP PAG 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F28030PAGQ Samples
TMS320
TMS320F28030PAGS ACTIVE TQFP PAG 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F28030PAGS Samples
TMS320
TMS320F28030PAGT ACTIVE TQFP PAG 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 F28030PAGT Samples
TMS320
TMS320F28030PNQ ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F28030PNQ Samples
TMS320
TMS320F28030PNS ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F28030PNS Samples
TMS320
TMS320F28030PNT ACTIVE LQFP PN 80 119 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 F28030PNT Samples
TMS320
TMS320F28030RSHS ACTIVE VQFN RSH 56 260 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F28030RSHS Samples
S320 980
TMS320F28030RSHT ACTIVE VQFN RSH 56 260 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 F28030RSHT Samples
S320 980
TMS320
TMS320
TMS320
TMS320
TMS320
TMS320
S320 980
TMS320
Addendum-Page 1
(6)
TMS320
TMS320
TMS320
TMS320
TMS320
TMS320F28032PNTR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 F28032PNT Samples
TMS320
S320 980
S320 980
TMS320F28033P1PAGS ACTIVE TQFP PAG 64 160 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F28033PAGS Samples
TMS320
TMS320
TMS320
TMS320
TMS320
TMS320
TMS320
S320 980
TMS320
TMS320F28034PAGQR ACTIVE TQFP PAG 64 1500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F28034PAGQ Samples
TMS320
Addendum-Page 2
(6)
TMS320
TMS320
TMS320
TMS320
TMS320
TMS320
S320 980
S320 980
TMS320
TMS320
TMS320
TMS320F28035PAGTR ACTIVE TQFP PAG 64 1500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 F28035PAGT Samples
TMS320
TMS320
TMS320F28035PNQR ACTIVE LQFP PN 80 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 F28035PNQ Samples
TMS320
TMS320
TMS320
TMS320
Addendum-Page 3
(6)
S320 980
S320 980
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320F28030, TMS320F28030-Q1, TMS320F28031, TMS320F28031-Q1, TMS320F28032, TMS320F28032-Q1, TMS320F28033,
TMS320F28033-Q1, TMS320F28034, TMS320F28034-Q1, TMS320F28035, TMS320F28035-Q1 :
Addendum-Page 4
• Catalog : TMS320F28030, TMS320F28031, TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035

• Automotive : TMS320F28030-Q1, TMS320F28031-Q1, TMS320F28032-Q1, TMS320F28033-Q1, TMS320F28034-Q1, TMS320F28035-Q1
• Enhanced Product : TMS320F28035-EP, TMS320F28035-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Mar-2024
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMS320F28032PNTR LQFP PN 80 1000 330.0 24.4 16.0 16.0 2.0 24.0 24.0 Q2
TMS320F28034PAGQR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
TMS320F28035PAGTR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMS320F28032PNTR LQFP PN 80 1000 367.0 367.0 55.0
TMS320F28034PAGQR TQFP PAG 64 1500 367.0 367.0 55.0
TMS320F28035PAGTR TQFP PAG 64 1500 367.0 367.0 55.0
TRAY
L - Outer tray length without tabs KO -

Outer
tray
height
W-
Outer
tray
width
Text
P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.

Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW
Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
TMS320F28030PAGQ PAG TQFP 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13
TMS320F28030PAGS PAG TQFP 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13
TMS320F28030PAGT PAG TQFP 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13
TMS320F28030PNQ PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28030PNS PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28030PNT PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28030RSHS RSH VQFN 56 260 26 x 10 150 315 135.9 7620 11.8 10 10.35
TMS320F28030RSHT RSH VQFN 56 260 26 x 10 150 315 135.9 7620 11.8 10 10.35
TMS320F28031PNQ PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28031PNS PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28031PNT PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW

Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
TMS320F28032PNQ PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28032PNS PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28032PNT PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28033P1PAGS PAG TQFP 64 160 8 x 20 150 315 135.9 7620 15.2 13.1 13
TMS320F28033PNQ PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28033PNS PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28033PNT PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28034PNQ PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28034PNS PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28034PNT PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28035PNQ PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28035PNS PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
TMS320F28035PNT PN LQFP 80 119 7 X 17 150 315 135.9 7620 17.9 14.3 13.95
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK
0,27
0,50 0,08 M
0,17
48 33
49 32
64 17
0,13 NOM
1 16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20 0,25
SQ 0,05 MIN
11,80 0°– 7°
1,05
0,95 0,75
0,45
Seating Plane
1,20 MAX 0,08
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OUTLINE
PN0080A SCALE 1.250
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
12.2
PIN 1 ID B
11.8
80 61
A
1 60
12.2 14.2
TYP
11.8 13.8
20
41
21 40
76X 0.5 0.27

80X
4X 9.5 0.17
0.08 C A B
1.6 MAX
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25 (1.4)
GAGE PLANE
0.75 0.05 MIN

0 -7
0.45
DETAIL A
DETAIL A
SCALE: 14
TYPICAL
4215166/A 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PN0080A LQFP - 1.6 mm max height
SYMM
80 61
80X (1.5)
1
60
80X (0.3)
76X (0.5) SYMM

(13.4)
(R0.05) TYP
20 41
21 40
(13.4)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:6X
0.05 MAX
EXPOSED METAL ALL AROUND EXPOSED METAL 0.05 MIN
ALL AROUND
METAL SOLDER MASK SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
SOLDER MASK DETAILS
4215166/A 08/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PN0080A LQFP - 1.6 mm max height
SYMM
80 61
80X (1.5)
1
60
80X (0.3)
76X (0.5) SYMM
(13.4)
(R0.05) TYP
20 41
21 40
(13.4)
SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:6X
4215166/A 08/2022
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RSH0056D SCALE 2.000

VQFN - 1 mm max height
VQFN
7.15 A
B
6.85
PIN 1 INDEX AREA

7.15
6.85
C
1 MAX
SEATING PLANE
0.05
0.00
5.3 0.1 (0.2)

15 28
14 29
52X 0.4
4X
5.2
1 42
0.25
56X
PIN 1 ID 56 43 0.15
(OPTIONAL) 0.1 C A B
0.6
56X 0.05 C
0.4
4218794/A 07/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSH0056D VQFN - 1 mm max height

VQFN
(5.3)
SYMM 43
56
SEE DETAILS
56X (0.7)
56X (0.2)
1
42
52X (0.4) 6X
(1.12)
(1.28)
TYP
SYMM
(6.7)
14 29
( 0.2) TYP
VIA
15 28
(1.28) TYP 6X (1.12)
(6.7)
LAND PATTERN EXAMPLE

SCALE:10X
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
METAL SOLDERMASK
OPENING
SOLDERMASK METAL
OPENING
NON SOLDERMASK SOLDERMASK

DEFINED DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4218794/A 07/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSH0056D VQFN - 1 mm max height

VQFN
SYMM
METAL
TYP
(1.28) TYP
56 43
56X (0.7)
1
42
56X (0.2)
52X (0.4) (1.28)

TYP
SYMM
(6.7)
14 29
15 28
16X (1.08)
(6.7)
SOLDERPASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:12X
4218794/A 07/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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TMS320F28030, TMS320F28030-Q1, TMS320F28031, TMS320F28031-Q1, TMS320F28032

TMS320F28032-Q1, TMS320F28033, TMS320F28033-Q1, TMS320F28034, TMS320F28034-Q1

TMS320F2803x Real-Time Microcontrollers

• Energy storage power conversion system (PCS)

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3.1 Functional Block Diagram

GPIO COMP2OUT C28x

MUX COMP3OUT 32-Bit CPU

16-Bit Peripheral Bus 32-Bit Peripheral Bus 32-Bit Peripheral Bus

Figure 3-1. Functional Block Diagram

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I/O pins GPIO – 45 33 26 45 33 26 45 33 26 45 33 26 45 33 26 45 33 26

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Table 4-1. Device Comparison (continued)

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4.1 Related Products

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5 Pin Configuration and Functions

Figure 5-1. 2803x 56-Pin RSH VQFN (Top View)

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Figure 5-2. 2803x 64-Pin PAG TQFP (Top View)

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Figure 5-3. 2803x 80-Pin PN LQFP (Top View)

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5.2 Signal Descriptions

Table 5-1. Signal Descriptions

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Table 5-1. Signal Descriptions (continued)

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Table 5-1. Signal Descriptions (continued)

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Table 5-1. Signal Descriptions (continued)

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Table 5-1. Signal Descriptions (continued)

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Table 5-1. Signal Descriptions (continued)

41 33 29 Output clock derived from SYSCLKOUT. XCLKOUT is either the same

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Table 5-1. Signal Descriptions (continued)

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Table 5-1. Signal Descriptions (continued)

(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown

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6.2 ESD Ratings – Automotive

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6.3 ESD Ratings – Commercial

6.4 Recommended Operating Conditions