11th International Conference on Power Electronics-ECCE Asia

May 22 - 25, 2023 / ICC Jeju, Jeju, Korea

Design and Implementation of Asymmetric

Half-Bridge Flyback Converter for USB Power
Delivery Applications
Kai-Hung Cheng, Tsorng-Juu Liang, Huynh Kim Kien Nghiep, and Kai-Hui Chen
National Cheng Kung University, Taiwan

Abstract-- In this paper, a two-stage USB PD charger for A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

wide output voltage range of various electronics products is GND RX2+ RX2- VBUS SBU1 D- D+ CC VBUS TX1- TX1+ GND
implemented. The first stage is the boost power factor
corrector (PFC) to achieve high power factor. The GND TX2+ TX2- VBUS VCONN SBU2 VBUS RX1- RX1+ GND

asymmetrical half-bridge (AHB) flyback is used as the second B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
stage to provide electrical isolation. The energy is transferred
to the load by the resonance between the leakage inductance Fig. 1. USB Type-C plug interface
and resonant capacitor with soft switching. A 140 W
experimental prototype is implemented with input voltage of TABLE I
90 Vac ~ 264 Vac, rated output current of 5 A, and output USB TYPE-C RECEPTACLE INTERFACE PIN ASSIGNMENTS
voltage of 5/ 9/ 15/ 20/ 28 VDC. The experimental results reveal Signal Name Description
that the maximum efficiency and power factor of the boost
GND Ground return
PFC is 98.2% and 0.99, respectively. The maximum
efficiency of the AHB flyback converter is 91.8%. The Data transmission
Tx/Rx
maximum efficiency of the overall system is 90.2%. (Transport/Receive)
Vbus Bus Power
Index Terms-- Asymmetrical half-bridge flyback
Sideband Use. Audio
converter, PD charger, power factor correction. SUB1/SUB2
transmission channel
I. INTRODUCTION D+/D- Support for USB 2.0
Nowadays, adapters are widely adopted in many CC Configuration channel
portable devices such as notebooks, smartphones, and
Because rectifier and filter circuits are widely adopted
tablets. However, each electronic product corresponds to
for power electronic products, this will cause the distortion
one adapter, resulting in a great deal of wasted electronic
of the input AC current and result in low power factor. As
material currently. Given the balance between the rise of
a result, the power plant needs to provide more reactive
environmental awareness and the convenience of users, it
power causing transmission losses. Therefore, some
is extremely important to unify the specifications of the
international standards and regulations are also issued; for
chargers. Universal serial bus implementers forum (USB-
example, EN61000-3-2 for harmonic current. Normally,
IF) released a USB Type-C version 1.0 in 2014. Fig. 1 and
power factor correction function is required for non-
Table 1 show a front view of USB Type-C plug interface
lighting equipment above 75W [3]. The first stage uses a
and USB Type-C receptacle interface pin assignments,
boost PFC operated in boundary conduction mode (BCM)
respectively. The main advantages of Type-C are as
with good efficiency and high power factor correction
follows: 1) smaller size and being able to be inserted both
suitable for low-power applications [4]. The second stage
forwards and backwards; 2) bidirectional transmission
is constructed with an isolated dc-dc converter. The
without source and sink device limitations; 3) data, audio,
conventional flyback converter is suitable for low-power
and power can be transmitted; 4) faster transmission speed;
charger applications. However, the efficiency of the
and 5) four power transmission pins can enhance the power
flyback converter is low because of hard switching and the
transmission up to 20 V/5 A. In 2017, the USB-IF
effect of the leakage inductance [5]-[6]. The voltage stress
Association announced a programmable power supply
of the main power switches of the AHB flyback converter
(PPS) USB power delivery (PD) 3.0 to unify the
is low compared with the conventional flyback converter.
specifications of the current charging schemes. The PPS
In addition, the main switches can achieve zero-voltage
can provide suitable output according to load requirements
switching (ZVS) and the output switch can achieve zero-
through a communication protocol between PPS and the
current switching (ZCS) to improve the conversion
load. The output of USB PD 3.1 is further increased up to
efficiency [7]-[15].
28 V / 5A [2].
In this paper, a two-stage system diagram of USB PD
charger is shown in Fig. 2. The first stage is a boost PFC,
which has good efficiency and power factor performance.
The second stage is the AHB flyback converter.
Combining the characteristics of conventional flyback

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 vLb
converter and resonant converter, the reduction in voltage iLb iD5
stress on the power MOSFET and the ability of the AHB
iac D1 D3 Lb iSb D5
flyback converter to achieve primary side MOSFET ZVS
and output synchronous rectifier (SR) ZCS allow it to vac Cin Sb Cbus Ro Vbus
challenge the position of the conventional flyback
converter and become a strong candidate for USB PD D2 D4
application.
Boost PFC Asymmetrical Half-Bridge Fig. 4. Equivalent circuit of mode I of boost PFC
converter Flyback converter
Mode II [DpTp ~ Tp]: vgsb is low. Sb is off, and D5 is on.
Lb Db
iin(t)
D1 D3 S1 Input source vac provides energy to inductor Lb and the load.
vin(t) Cin Sb Cbus Vbus
Cr Llk NP:NS Inductor current iLb decreases. Fig. 5 shows the equivalent
D2 D4
S2 Lm Co RL Vo circuit for this mode. This mode ends when inductor
current iLb decreases to zero and vgsb becomes high at t=Tp.
Fig. 2. System diagram of USB PD charger iLb vLb iD5

iac D1 D3 Lb iSb D5
II. ANALYSES OF BOOST PFC CONVERTER
The topology and key waveforms of the boost PFC in vac Cin Sb Cbus Ro Vbus
BCM operation are shown in Fig. 2 (a) and (b),
respectively. In order to simplify the analyses of the boost D2 D4
converter, some assumptions are made.
1. The converter is operated in steady state. Fig. 5. Equivalent circuit of mode II of boost PFC
2. The converter is operated in BCM Fig. 6 shows the voltage and current waveforms of Lb
3. All components in the circuit are ideal, and the in BCM. When ωLt is near πL/2 and 3πL/2, the input voltage
antiparallel diode of MOSFET is included. variations become small so that inductor current iLb can be
4. Input AC voltage and current are defined as considered as under steady-state operation. Then, by volt-
vac=VmsinωLt, iac=ImsinωLt second balance of boost inductor Lb, (1) can be derived.
5. Output capacitance Cbus is large enough that Vbus can be
considered as a constant. Vm ⋅ Dp ⋅ Tp + (Vm − Vbus ) ⋅ 1 − Dp Tp =0( ) (1)
iLb iD5 Ibus From (1), Dp is derived as (2).
Vm
iac D1 D3 Lb iSb D5 ibus
Pbus DP = 1 − (2)
Vbus
vac Cin Sb Cbus Ro Vbus
From Fig. 3 (a), the magnitude of the input current (Im) can
D2 D4
vgsb be expressed as (3).
2 ⋅ Pbus 2 ⋅ Vbus ⋅ I bus
(a) Im = = (3)
vac
η ⋅ Vm η ⋅ Vm
vac=VmsinωLt
iac
iLb
iac=ImsinωLt Where Pbus is the output power and η is the efficiency of
Vm the boost PFC converter. According to Fig. 6, the peak
Im
t
inductor current (ILb,pk) can be expressed as (4).
0 πL
DpTp V (V -V )
vgsb
Tp
I Lb,pk = 2 ⋅ I m = m ⋅ Tp,on = bus m ⋅ Tp,off (4)
Lb Lb
t
vLb vLb
t Vm
t
Vm-Vbus
iSb iLb ILb,Pk
t
ILb,avg
iD5 t
t 0 DpTp Tp
0 DpTp Tp
Fig. 6. Voltage and current waveforms of Lb in BCM
(b)
Fig. 3. (a) Boost PFC converter (b) Key waveforms Where Tp,on is the on-time of the switching period, and Tp,off
is the off-time of the switching period. By substituting (3)
Mode I [0 ~ DpTp]: vgsb is high. Sb is on and D5 is off.
into (4), Tp,on and Tp,off can be derived as (5) and (6).
Input source vac provides energy to inductor Lb. Inductor 4 ⋅ Pbus ⋅ Lb
current iLb increases. Output capacitor Cbus provides energy Tp,on = (5)
to the load. Fig. 4 shows the equivalent circuit for this η ⋅ Vm 2
mode. This mode ends when vgsb becomes low at t= DpTp. 4 ⋅ Pbus ⋅ Lb
Tp,off = (6)
η ⋅ Vm ⋅ (Vbus -Vm )
With Tp = Tp,on+Tp,off, Tp can be derived as (7)

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 4 ⋅ Pbus ⋅ Vo ⋅ Lb Db1
Tp = (7)
η ⋅ Vm 2 ⋅ (Vbus -Vm ) S1 Cds1
S3
Then, BCM condition of boost inductor Lb,BCM is derived Cr Llk iLk is

η ⋅ Vm 2 ⋅ (Vbus -Vm ) Vbus

Lb,BCM = (8) vCr iLm Db3
4 ⋅ Pbus ⋅ Vbus ⋅ f p S2 Cds2 vLm Co RL Vo
Db2 Lm
III. ANALYSES OF AHB FLYBACK CONVERTER NP:NS
The topology and key waveforms are shown in Fig. 7
(a) and (b). In order to simplify the analysis, some Fig. 8. Equivalent circuit of mode I of AHB flyback converter
assumptions are made. Mode II [t1 ~ t2]: vgs1 is high and vgs2 is low. S1 is on,
1. The converter is operated in steady state. and S2 is off. iLk & iLm > 0 and iLk = iLm. The transformer is
2. All components in the circuit are ideal, except that the decoupled. Input source Vbus provides energy to inductors
output capacitance of MOSFETs and the leakage Llk and Lm. Output capacitor Co provides energy to the load.
inductance of the transformer are included. Fig. 9 shows the equivalent circuit of mode II. This mode
3. The secondary-side synchronous SR is regarded as its ends when gate signal vgs1 becomes low at t=t2.
ideal body diode.
4. Output capacitance Co is large enough that Vo can be Db1
S1 Cds1
considered as a constant. S3
5. The transformer turns ratio is defined as Np/Ns =n:1. Cr Llk iLk is
Vbus
Db1 vCr iLm Db3
S1 Cds1 S2 Cds2 vLm Co RL Vo
S3
vgs1 Cr Llk iLk is
Db2 Lm
Vbus
vab vCr iLm Db3 NP:NS
S2 Cds2 vLm Co RL Vo

vgs2 Db2 Lm Fig. 9. Equivalent circuit of mode II of AHB flyback converter

NP:NS
Mode III [t2 ~ t3]: vgs1 and vgs2 are low. S1 and S2 are off.
(a)
iLk & iLm > 0 and iLk = iLm. The transformer is decoupled.
DTs Ts Cds1 is charged and Cds2 is discharged. Output capacitor Co
vgs1 provides energy to the load. Fig. 10 shows the equivalent
circuit of mode III. This mode ends when Cds1 and Cds2 are
t fully charged and discharged, respectively at t=t3.
vgs2
Db1
t S1 Cds1
vds2 S3
vds1 Cr Llk iLk is
t Vbus
vCr iLm Db3
vLm
Vbus-vCr S2 vLm Co RL V o
t
-nV o Db2 Lm
iLm Ipk
NP:NS
iLk t
-ILo Fig. 10. Equivalent circuit of mode III of AHB flyback converter
is
Mode IV [t3 ~ t4]: vgs1 and vgs2 are low. S1 and S2 are
t
vCr off. iLk & iLm > 0 and iLk = iLm. The transformer is
decoupled. Db2 conducts to clamp vds2 at zero. Output
capacitor Co provides energy to the load. Fig. 11 shows the
t equivalent circuit of mode IV. This mode ends when vLm =
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 -nVo and Db3 conducts at t=t4.
(b)
Fig. 7. (a) AHB flyback converter (b) Key waveforms

Mode I [t0 ~ t1]: vgs1 is high and vgs2 is low. S1 is on, and
S2 is off. iLk & iLm < 0 and iLk = iLm. The transformer is
decoupled, and the output capacitor Co provides energy to
the load. Fig. 8 shows the equivalent circuit of mode I. This
mode ends when iLk = iLm = 0 at t = t1.

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 Db1
Db1 S1 Cds1
S1 S3
Cds1
S3 Cr Llk iLk is
Cr Llk iLk is Vbus
vCr iLm Db3
Vbus
vCr iLm Db3 S2 Cds2 vLm Co RL Vo
S2 Cds2 vLm Co RL Vo
Db2 Lm
Db2 Lm
NP:NS
NP:NS
Fig. 11. Equivalent circuit of mode IV of AHB flyback converter Fig. 14. Equivalent circuit of mode VII of AHB flyback converter

Mode V [t4 ~ t5]: vgs1 and vgs2 are low. S1 and S2 are off. Mode VIII [t7 ~ t8]: vgs1 and vgs2 are low. S1 and S2 are
iLk & iLm > 0 and iLk > iLm. The transformer is coupled. Cr off. iLk & iLm < 0 and iLk = iLm. The transformer is
resonates with Llk. Db2 conducts to clamp vds2 at zero, decoupled. Cds1 is discharged and Cds2 is charged. Fig. 15
which leads to ZVS. Lm provides energy to the load shows the equivalent circuit of mode VIII. This mode ends
through the transformer. Fig. 12 shows the equivalent when Cds1 and Cds2 are fully discharged and charged,
circuit of mode V. This mode ends when gate signal vgs2 respectively at t=t8.
becomes high at t=t5. Db1
S1 Cds1
Db1
S3
S1 Cds1 Cr Llk iLk is
S3 Vbus
Cr Llk iLk is vCr iLm Db3
Vbus S2 Cds2 vLm Co R L Vo
vCr iLm Db3
S2 Db2 Lm
Cds2 vLm Co RL Vo
Lm NP:NS
Db2
Fig. 15. Equivalent circuit of mode VIII of AHB flyback converter
NP:NS
Mode IX [t8 ~ t9]: vgs1 and vgs2 are low. S1 and S2 are
Fig. 12. Equivalent circuit of mode V of AHB flyback converter off. iLk&iLm < 0 and iLk = iLm. The transformer is decoupled.
Cr provides energy to Lm. Output capacitor Co provides
Mode VI [t5 ~ t6]: vgs2 is high and vgs1 is low. S2 is on, energy to the load. Fig. 16 shows the equivalent circuit of
and S1 is off. iLk < 0, iLm > 0 and iLm > iLk. The transformer mode IV. This mode ends when vgs1 becomes high at t=t9.
is coupled. iLm decreases linearly with a slope of -nVo. Cr
resonates with Llk. Inductor Lm and capacitor Cr provide Db1
energy to capacitor Co and the load. Fig. 13 shows the S1 Cds1
equivalent circuit of mode VI. This mode ends when S3
Cr Llk iLk is
secondary side current is = 0 at t=t6. Vbus
vCr iLm Db3
Db1 S2 Cds2 vLm Co RL Vo
S1 Cds1
S3 Db2 Lm
Cr Llk iLk is
NP:NS
Vbus Fig. 16. Equivalent circuit of mode IX of AHB flyback converter
vCr iLm Db3
S2 Cds2 vLm Co RL Vo In order to simplify the steady-state analyses of the
Db2 Lm AHB flyback converter, the key waveforms by ignoring
NP:NS
the effect of the dead times from t2 to t5 and from t7 to t9 is
shown in Fig. 17.
Fig. 13. Equivalent circuit of mode VI of AHB flyback converter

Mode VII [t6 ~ t7]: vgs2 is high and vgs1 is low. S2 is on,
and S1 is off. iLk & iLm < 0 and iLk = iLm. The transformer is
decoupled. Cr resonates with Llk and Lm. Lm and Llk
increase almost linearly with a slope of -vCr/(Lm+Llk).
Capacitor Co provides energy to the load. Fig. 14 shows
the equivalent circuit of mode VII. This mode ends when
gate signal vgs2 becomes low at t=t7.

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 DTs
Ts
vLm
vgs1 Vbus-VCr
t
t -nVo
vgs2

t iLm ILm,Pk
vLm
Vbus-VCr ILm,avg
t ∆ILm
-nVo ILm,Lo t
vab
0 DTs Ts
Vbus
t Fig. 18. Voltage and current waveforms of Lm in BCM
iLm ILm,Pk
iLk ∆ILm
ILm,avg IV. PARAMETERS DESIGN AND EXPERIMENTAL RESULTS
t
-ILm,Lo Table II shows the specifications of the USB PD
is charger system. The input voltage of the boost converter is
t 90~264 Vac. The output power of the first stage boost PFC
0 DTs Ts converter is set to 160 W by considering the conversion
Fig. 17. The equivalent circuit with the reflected output resistance Re efficiency. The output voltage range of the USB PD
and its signals
charger system is 5-28 V, with the maximum output
Cr is used as dc block capacitor, the average voltage current of 5 A. The rated output power Po,max is 140 W. The
across Cr is: key parameters and the components for the experimental
VCr = DVbus (9) prototype are listed in Table III.
By using volt-second balance of magnetizing inductance TABLE II
Lm and ignoring the effect of leakage inductance Llk, SPECIFICATIONS OF USB PD CHARGER SYSTEM
DT T
 (Vbus − VCr )dt +  (−nVo )dt =0
s s
(10) Circuit Parameters Value
0 DTs

(Vbus − DVbus ) ⋅ DTs + ( − nVo ) ⋅ (1 − D ) Ts =0 (11) Input RMS voltage(vac) 90 ~ 264 V

1 Bus voltage (Vbus) 400 V
Vo = ⋅ DVbus (12)
n Output power (Pbus) 160 W
According to Fig. 17, the maximum and minimum Input line frequency (fline) 60. Hz
magnetizing inductor current (ILm,Pk, ILm,Lo) are:
Minimum switching 30 kHz
∆I I nVo
I =I
Lm,Pk + Lm = o +
Lm,avg ⋅ (1 − D ) T (13)
s frequency (fPFC,min)
2 n 2 Lm
Output voltage (Vo) 5/9/15/20/28 V
∆I Lm I o nVo
− I Lm,Lo = I Lm,avg − = − ⋅ (1 − D ) Ts (14) Rated output current (Io,max) 5A
2 n 2 Lm
Rated output power (Po,max) 140 W
In order to ensure that power switches S1 and S2 can
achieve ZVS, the deadtime should sufficient enough for Switching frequency range 103-180 kHz
the magnetizing inductance of the transformer to charge
TABLE III
and discharge the output capacitors of the switches as (15) KEY PARAMETERS AND COMPONENTS OF THE PROTOTYPE
2 ⋅ Coss ⋅ Vbus (15)
I Lm,Lo ≥ Parameters Value
td
Input capacitance (Cin) 1 μF
In addition, the energy stored in the magnetizing
inductance should be large enough to charge and discharge Inductance (Lb) 400 μH
the output capacitors of two power switches. STF15NM65N (VDSS= 650
Power MOSFET (Sb)
1 1 (16) V, ID= 7.56 A)
Lm ⋅ I Lm,Lo 2 > ⋅ 2 ⋅ Coss ⋅Vbus 2
2 2 RURP1560 (VR= 600 V, IF=
Diode (Db)
Fig. 18 shows voltage and current waveforms of Lm in 15 A)
BCM. To ensure that magnetizing inductance Lm is Bus capacitance (Cbus) 120 μF
operated in DCM for achieving ZVS of main switch S1, the Turns ratio (Np：Ns) 13：1
key waveforms of the magnetizing inductance in BCM
Magnetizing inductance
operation is derived as (17). 120 μH
n2 ⋅Vo ⋅ (1 − D ) (Lm)
L =
(17)
m,BCM
2 ⋅ I o ⋅ fs Leakage inductance (Llk) 4.5 μH
Resonant capacitance (Cr) 82 nF
IPA65R190CF (VDSS= 650
Power MOSFET (S1, S2)
V, ID= 11 A, Coss= 86 pF)
IRFB3607PbF (VDSS= 75 V,
Power MOSFET (S3)
ID= 56 A, Rds,on= 9 mΩ)
Output capacitance (Co) 680 μF

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 Fig. 19 and Fig. 20 show the measured waveforms of
vac, iac, Vbus, vgsb, iLb under 160 W conditions at vac= 110 V, vac (500 V/div)
and vac= 220 V, respectively. The waveform of inductor
current iLb is in the boundary conduction mode.
vgsb(10 V/div)
vac (200 V/div)
iLb(2 A/div)

iac (5 A/div)
Time: 5 μs/div

vgsb(10 V/div)
(b)
Fig. 20. Measured PFC waveforms of (a) vac, iac, vgsb and Vbus (b) vac, vgsb
and iLb under vac =220 V and Pbus= 160 W
Vbus(500 V/div)
Time: 5 ms/div Fig. 21 (a) and (b) show the power factor and
efficiency curves of the boost PFC converter from 32 W to
160 W. The maximum efficiency is 96.9% and 98.2%
(a) under vac=110 V and 220 V, respectively. The efficiency is
higher at vac =220 V because of the lower conduction loss.
vac (200 V/div)
The maximum power factor is 0.99 and 0.98 under vac=110
V and 220 V, respectively.

vgsb(10 V/div)

iLb(2 A/div)
Time: 2 ms/div

vac (200 V/div)

(a)

vgsb(10 V/div)

iLb(2 A/div) Time: 5 μs/div

(b)
Fig. 19. Measured PFC waveforms of (a) vac, iac, vgsb and Vbus (b) vac, vgsb
and iLb under vac =110 V and Pbus= 160 W

vac (500 V/div)

(b)
Fig. 21. Boost PFC from 32 W to 160 W (a) measured power factor (b)
measured efficiency.
iac (2 A/div)

Fig. 22 (a) and Fig. 23 (a) show the waveforms of vgs1,

vgsb(10 V/div)
vgs2, iLk and is when output voltage Vo is 5 V and 28 V, and
the output current Io is 5 A. The switching frequency fsw of
Vbus(500 V/div) the converter is operated as 180 kHz and 103 kHz,
Time: 5 ms/div respectively. Fig. 22 (b) and Fig. 23 (b) show the
waveforms of vgs1, vgs2, is and vSR when output voltage Vo
(a) is 5 V and 28 V, and output current Io is 5 A; it shows the
switch S3 can achieve ZCS. Fig. 22 (c) and Fig. 23 (c) show
vac (500 V/div) the waveforms of vgs1, vds1, vgs2 and vds2 when output
voltage Vo is 5 V and 28 V, and output current Io is 5 A; it
shows the main switches S1 and S2 can achieve ZVS.
vgsb(10 V/div)

iLb(2 A/div) Time: 2 ms/div

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 (c)
(a) Fig. 23. Measured waveforms at output 28 V/ 5 A (a) vgs1, vgs2, iLk and is.
(b) vgs1, vgs2, is and vSR (c) vgs1, vds1, vgs2 and vds2, fsw = 103 kHz

Fig. 24 shows the efficiency curves of the AHB

flyback converter under different output voltages and
loads. The maximum efficiency is 91.6% when the output
voltage is 28 V under full load condition.

(b)

(a)

(c)
Fig. 22. Measured waveforms at output 5 V/ 5 A (a) vgs1, vgs2, iLk and is.
(b) vgs1, vgs2, is and vSR (c) vgs1, vds1, vgs2 and vds2, fsw = 180 kHz

(b)
Fig. 24. Measured efficiencies of AHB flyback converter (a) Various
load current and different output voltage (b) Various output voltage at
full load

V. CONCLUSIONS
In this paper, an experimental prototype for USB PD
(a) with ac input voltage of 90 Vac ~ 264 Vac, output voltage of
5/ 9/ 15/ 20/ 28 V, output current of 5 A, and rated power
of 140 W is implemented. The first stage of the system
uses a boost PFC circuit to achieve high power factor. The
second stage is an AHB flyback converter, and the power
devices of primary side and secondary side can achieve
zero voltage switching and zero current switching,
respectively. In addition, synchronous rectification
technology is used to improve efficiency on the secondary
side. Therefore, the conduction loss can be greatly
reduced. Finally, the experimental results reveal that the
(b)
maximum efficiency of the boost PFC converter is 98.2%
at an input voltage of 220 vac, and the maximum power
factor is 0.99 at an input voltage of 220 vac. The maximum
efficiency of the AHB flyback converter is 91.6% at an
output voltage of 28 V. The maximum efficiency of the
overall system is 90.2%.

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 ACKNOWLEDGMENT [20] J. F. Lazar and R. Martinelli “Analysis, design and
implementation of an active clamp flyback converter,” in
This paper was supported by the National Science and Proc. IEEE PEDS Conf., pp. 424-429, 2005.
Technology Council in Taiwan under project number [21] J. Zhang, X. huang, X. Wu, and Z. Qian, “A high efficiency
NSTC 110-2221-E-006 -123 -MY3. flyback converter with new active clamp technique,” IEEE
Trans. Power Electron., vol. 35, no. 7, pp. 1775-1785, Jul.
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