High-Accuracy Cmos Smart Temperature Sensors

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS
HIGH-ACCURACY
CMOS SMART
TEMPERATURE SENSORS
by
Anton Bakker
Philips Semiconductors
Tempe, AZ, U.S.A.
and
Johan Huijsing
Delft University of Technology
Delft, The Netherlands
Springer Science+Business Media, LLC

A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4419-4862-5 ISBN 978-1-4757-3190-3 (eBook)

DOI 10.1007/978-1-4757-3190-3
Printed on acid-free paper
All Rights Reserved

© 2000 Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers, Boston in 2000.
Softcover reprint of the hardcover 1st edition 2000
No part of the material protected by this copyright notice may be reproduced or
utilized in any form or by any means, electronic or mechanical,
including photocopying, recording or by any information storage and
retrieval system, without written permission from the copyright owner.
Table of contents
Preface
.
lX
1 Introduction 1
1.1 Temperature sensing .................................................. l
1.2 CMOS smart temperature sensors ............................. 3
1.3 Motivation and objectives ........................................ .4
1.4 Organization of the work ........................................... 5
References ................................................................. 7
2 Dynamic offset-cancellation
techniques
9
2.1 Introduction ............................................................... 9

2.1.1 Offset and noise in CMOS amplifiers ....................................... 10
2.1.2 Naming conventions and classification .................................... 13
2.2 Autozero techniques ................................................ 14
2.2.1 Principle .................................................................................... 14
2.2.2 Residual noise ........................................................................... 15
2.2.3 Self-calibrating opamp .............................................................. 16
2.2.4 Correlated double sampling ...................................................... 17
2.2.5 Ping-pong opamp ...................................................................... 17
2.2.6 Chopper-stabilization ................................................................ 18
2.2.7 Three-signal approach ............................................................... 19
2.3 Chopper techniques ................................................. 20
2.3.1 Principle .................................................................................... 20
2.3.2 Residual noise ........................................................................... 22
HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS v

Table of contents
2.3.3 Residual offset .......................................................................... 23

2.3.4 Gain accuracy ........................................................................... 25
2.3.5 Chopper opamp ......................................................................... 26
2.4 Nested chopper technique ....................................... 28
2.4.1 Principle .................................................................................... 28
2.4.2 Analysis .................................................................................... 29
2.4.3 Realization ................................................................................ 30
2.4.4 Measurement results ................................................................. 32
2.5 Conclusions ............................................................. 33
References ............................................................... 34
3 CMOS bandgap references 37

3.1 Introduction ............................................................. 37
3.2 Temperature curves of the bipolar transistor .......... 40
3.3 Design ..................................................................... 43
3.3.1 Non-idealities in practical CMOS bandgap references ............ 43
3.3.2 Curvature correction techniques ............................................... 45
3.4 Realization .............................................................. 48
3.4.1 Filtering of modulated offset .................................................... 48
3.4.2 Nested chopper technique ......................................................... 52
3.4.3 Piece-wise-linear circuit implementation ................................. 54
3.5 Conclusions ............................................................. 58
References ............................................................... 60
4 Design of CMOS Smart

Temperature Sensors
63
4.1 Introduction ............................................................. 63

4.1.1 Accuracy ................................................................................... 64
4.1.2 Power consumption .................................................................. 65
4.2 Analog-to-Digital conversion ................................. 66
4.2.1 Frequency conversion ............................................................... 67
4.2.2 Duty-cycle modulation ............................................................. 68
4.2.3 Sigma-delta A-to-D conversion ................................................ 69
VI HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS

Table of contents
4.3 Kelvin-to-Celsius conversion .................................. 71

4.4 Curvature correction ................................................ 73
4.5 Single transistor temperature sensors ...................... 74
4.6 Bus interfaces .......................................................... 77
References ............................................................... 78
5 Realizations of CMOS Smart

Temperature Sensors
79
5.1 Tyre monitoring system ........................................... 79

5.1.1 Motivation ................................................................................. 79
5.1.2 Specification ............................................................................. 82
5.1.3 Design of the tyre temperature sensor ...................................... 83
5.1.4 Detailed design of the tyre temperature sensor. ........................ 85
5.2 High-accuracy temperature sensor .......................... 93
5.2.1 Motivation ................................................................................. 93
5.2.2 Specification ............................................................................. 95
5.2.3 Design ....................................................................................... 98
5.2.4 Measurement results ............................................................... 105
5.3 Remote microprocessor temperature sensof. ......... 106
5.3.1 Motivation ............................................................................... 106
5.3.2 Specification ........................................................................... 108
5.3.3 Design of the single-transistor temperature sensor interface .. 110
5.3.4 Detailed design of the remote temperature sensOf. ................. 111
5.3.5 Measurement results ............................................................... 113
5.4 Conclusions ........................................................... 114
References ............................................................. 116
Appendix 117
Index 119
HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS VII

Preface
This book describes the theory and design of high-accuracy CMOS smart
temperature sensors. The major topic of the work is the realization of a smart
temperature sensor that has an accuracy that is so high that it can be applied
without any form of calibration. Integrated in a low-cost CMOS technology, this
yields at the publication date of this book one of the most inexpensive intelligent
general purpose temperature sensors in the world.
The first thermometers could only be read by the human eye. The industrial
revolution and the following computerization asked for more intelligent sensors,
which could easily communicate to digital computers. This led to· the
development of integrated temperature sensors that combine a bipolar
temperature sensor and an A-to-D converter on the same chip. The
implementation in CMOS technology reduces the processing costs to a minimum
while having the best-suited technology to increase the (digital) intelligence.
The accuracy of conventional CMOS smart temperature sensors is degraded by

the offset of the read-out electronics. Calibration of these errors is quite
expensive, however, dynamic offset-cancellation techniques can reduce the offset
of amplifiers by a factor 100 to 1000 and do not need trimming.
Chapter two gives an elaborate description of the different kinds of dynamic

offset-cancellation techniques. Also a new technique is introduced called the
nested chopper technique. An implementation of a CMOS nested-chopper
instrumentation amplifier shows a residual offset of less than lOOnV, which is the
best result reported to date.
Chapter three describes the most important part of a smart temperature sensor,
which is the bandgap voltage reference. It is shown that although this reference is
based on a bipolar transistor, it can be implemented in standard CMOS
technology by utilizing the (parasitic) substrate PNP transistor. This chapter also
describes different kinds of curvature correction techniques, which are very
important to further improve the accuracy.
HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS IX

Preface
Chapter four describes the general design of CMOS smart temperature sensors.
This includes Analog-to-Digital conversion, Kelvin-to-Celsius conversion,
curvature correction and bus interfaces. Also single-transistor temperature
sensors are discussed, which are very important nowadays for thermal
management in laptops.
The last chapter describes three different smart temperature sensors that have
been realized by the authors. The first one is an ultra-low power version for
application in a tyre monitoring system. The second is a high-accuracy
temperature sensor that meets the industry specifications without any form of
calibration. The last one is a remote microprocessor temperature sensor, which
can be found in all laptops.
The authors wish the reader a pleasant time in investigating the interesting aspects
of CMOS smart temperature sensor design.
Anton Bakker
lohan H. Huijsing
Sunnyvale, August 2000
x HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS

Introduction
This work describes the theory and design of high-accuracy CMOS smart
temperature sensors. The major topic of the work is the realization of a smart
temperature sensor that has an accuracy that is so high that it can be applied
without any form of calibration. Integrated in a low-cost CMOS technology, this
yields one of the most inexpensive intelligent general purpose temperature
sensors in the world. This chapter introduces the reader to the general aspects of
the design of CMOS smart temperature sensors. It explores the possibilities and
detect the bottle-necks. It ends with the motivation and the organization of the
book.
1.1 Temperature sensing

Even many centuries ago, people already had a great desire to know the
temperature. Reference points could be found, such as the freezing point of water
or the body temperature. However, to determine temperatures between those
fixed points a temperature meter or thermometer was needed. This led to the
invention of the mercury-in-glass thermometer, which is still widely used today.
Another issue was the definition of the scale. In 1714, Fahrenheit proposed a
scale that takes the minimal possible temperature he could imagine to appear in
Central Europe as OOf" (-18°C) and the body temperature as 960f". Celsius
proposed a few years later in 1742 a similar scale but he took the freezing point of
water as OOC and its boiling point as 100°C. Both scales are still in use, but the
Celsius scale is the most widely used scale. More than a century later, in 1851,
Kelvin proposed his law of thermodynamics in which he proved that the
HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS 1

A. Bakker et al., High-Accuracy CMOS Smart Temperature Sensors
© Springer Science+Business Media Dordrecht 2000
Introduction
Analog-to-Digital
digital
converter
Fig. 1-1 Communication between a temperature sensor and a

computer through an analog-to-digital converter.
theoretically minimal possible temperature is -273.l5°C. Since that time,
scientists have often used the Kelvin scale, which is a Celsius scale that is shifted
by -273.15 degrees.
The early function of thermometers was to literally read the temperature.

However, the industrial revolution asked for automatic temperature controllers.
These so-called thermostats were used in central heating systems, ovens and
engines. The thermometer needed to be adapted to control heaters, fuel valves or
other so-called actuators. We still use these thermometers with mechanical output
in thermostat taps and local temperature control in central heating systems.
In the second half of the 20th century, the temperature controllers became more
and more intelligent. Switching a heater or ventilator on and off was in many
applications not good enough anymore. For example, to reduce fuel consumption
in central heating systems, it is necessary to monitor temperature changes and
adapt the heating power to reduce unwanted temperature overshoots. The
electronic controller was introduced and the thermometers had to be adapted to
communicate with them. Thermometers needed to have an electrical output,
which resulted in the development of resistance thermometers. The most widely
used material for resistance thermometers nowadays is platinum because of its
stability and reproducible temperature characteristics. The Pt-100, which is a
platinum resistor with a nominal value of 100Q, is now the standard resistance
thermometer. Other widely used materials for resistance thermometers are
(lightly-doped) semiconductors, such as silicon. These resistance thermometers
are called thermistors and have the advantage of a much higher sensitivity than
metal-based resistance thermometers.
To communicate with a computer, the resistance changes have to be converted

into a digital signal. This is done with an analog-to-digital converter. Such a
system is shown in figure 1-1. These kind of temperature sensor systems are still
widely used. To reduce the cost of a system that consists of both a temperature
sensor and a computer interface, integration of the temperature sensor on the
2 HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS

1.2 CMOS smart temperature sensors
I~tat
VBE(l2) - - - - - _L - - - - - - - - - -
VBE(l1)
Fig. 1-2 Ie VBE characteristic of a bipolar transistor, which can be

used to make a temperature sensor that is almost perfectly
Proportional To Absolute Temperature (PTAT).
same chip as the A-to-D converter was attempted. This resulted in a whole new
family called integrated smart temperature sensors.
1.2 CMOS smart temperature sensors

The research on smart or integrated temperature sensors started in the mid-
seventies, together with the development of the Integrated Circuit (lC)
technology. It was also the time of the development of a new temperature sensing
device, the bipolar transistor. The bipolar transistor was completely compatible
with the (bipolar) technology and therefore much easier to integrate than a
platinum resistor. It was also much more accurate than a thermistor. Another great
advantage was that the bipolar transistor delivered a voltage as output signal
instead of a resistance variation, which is a much nicer signal for an A-to-D
converter. However, the biggest advantage sti11 is its extremely reproducible
exponential characteristic. This made it possible to make a temperature sensor
which has a very high intrinsic accuracy. This is explained by figure 1-2.
When a transistor is biased at a collector current of I}> it will have a base-emitter

voltage of
(1-1)

Introduction
where k is Boltzmann's constant (1.3807-lO- 23 J/K), T the absolute temperature

(in Kelvin), and q the electron charge (1.6022-lO- I9 C). Is is the saturation current
of the transistor, which is very much dependent on process parameters. Because
of the uncertainty in Is it is not possible to make an accurate temperature sensor
this way. However, if we take the difference of two base-emitter voltages of the
same transistor but biased at two different collector currents II and 12, we get
This equation shows that the voltage difference is, next to the constants k and q,
only dependent on T and the ratio of 12 and I I. This means that there are no longer
any parameters that are dependent on the process. The voltage difference is
therefore very accurately proportional to the absolute temperature T and is called
Vptat·
The PTAT voltage can easily be generated on chip and forms the base of the
family of smart temperature sensors. The first results were temperature sensors
with a current or voltage output [1.1]. At the end ofthe eighties these temperature
sensors were followed uo by a smart temperature sensor with a (semi-)digital
output [1.2]. A problem occurred during the beginning of the nineties, when the
bipolar technology started to become almost extinct in favour of CMOS
technology. CMOS technology was developed very fast because of the great
market demand for digital chips. CMOS, however, did not have a regular bipolar
transistor. Fortunately, a solution was found in a parasitic bipolar substrate
transistor. Although this transistor was not monitored nor wanted in the process, it
was found to be very usable as a temperature sensing device. This discovery was
made at the start of this work (1995) and during this work the whole world-wide
research on smart temperature sensors shifted from bipolar technology to CMOS
technology. Nowadays, most commercial smart temperature sensors are made in
CMOS technology.
1.3 Motivation and objectives

The main motivation of this book is definitely the fast growing demand for
smarter and cheaper temperature sensors. Smarter temperature sensors are
needed because the systems in which they are being applied are getting more and
more complex. This implies that the designers of such systems will have less
knowledge about subsystems such as temperature sensors. This lack of

1.4 Organization of the work
knowledge needs to be compensated by an increase of intelligence in the smart

temperature sensor.
Cheaper products are always needed when markets are growing. And markets are
already large when you consider that there are at least five temperature sensors
per car and two temperature sensors per PC. Cheaper temperature sensors will
also further increase the number of applications.
The main objectives of this work are therefore firstly to increase the intelligence
of the smart temperature sensor to such a level that it can be applied by, for
example, a digital engineer, who does not know anything about analog circuit
design nor physical temperature effects. The second objective is to reduce the
costs as much as possible. This is first done by an analysis of the costs, which
found that a major cost reduction can be achieved when it is possible to increase
the accuracy to such a level that calibration is not necessary for most of the
applications. This book will therefore focus on dedicated high-accuracy
electronics that are needed to design high-accuracy CMOS smart temperature
sensors.

The accuracy of CMOS smart temperature sensors is limited by the offset of the
read-out electronics. To increase the accuracy of CMOS smart temperature
sensors to the highest possible accuracy level, it is therefore best to first consider
techniques to reduce the offset of CMOS amplifiers. Chapter 2 describes the
theory and design of dynamic offset-cancellation techniques. These techniques
can reduce the offset by a factor of 100 to 1000 and do not need to be calibrated.
At the end of this chapter a new technique is introduced that even further reduces
the offset. A realization of this new technique and measurement results are
shown.
Another important part of the design of a CMOS smart temperature sensor is the
voltage reference. Such a reference is needed for the A-to-D converter. The
accuracy of the total sensor system can never be higher than the accuracy of its
reference. Chapter 3 therefore discusses the theory and design of CMOS bandgap
references. It will discuss available bipolar devices in CMOS technology, thermal
modelling of the bipolar transistor, and curvature correction techniques. Also the
design and implementation of a novel high-accuracy CMOS bandgap reference is
shown.

Introduction
Chapter 4 describes general design aspects of CMOS bandgap references. It

describes different kinds of analog-to-digital conversion, methods for Kelvin-to-
Celsius conversion, curvature correction and bus interfaces. Also, an electronic
interface for the read-out of a single remote bipolar transistor is proposed. The
design aspects that are considered most important are high uncalibrated accuracy
and low power consumption.
Chapter 5 describes the realizations of three different kinds of CMOS smart

temperature sensors that have been designed within the framework of this work.
The first realization finds its application in a tyre monitoring system, where it
watches the temperature of the tyre and compensates thermal cross-sensitivities
of a pressure sensor. The second realization is a general purpose ambient
temperature sensor, where special attention has been paid to high uncalibrated
accuracy. The last version can measure the temperature of a remote bipolar
transistor and has its application in microprocessor thermal management.

References
[1.1] National Semiconductor, "LM135 - Precision Temperature Sensor", http://
www.nationai.com. November 1999
[1.2] Smartec, "SMT160-30 Smart Temperature Sensor", http://
www.smartec.ni. November 1999

Dynamic offset-
cancellation
techniques
This chapter describes the theory and design of the different kinds of dynamic
offset-cancellation techniques. These techniques can reduce the offset of an
amplifier by a factor of 100 to 1000 and do not need trimming. Knowledge of
these techniques is necessary to improve the accuracy of CMOS smart
temperature sensors. Also in this chapter, a new technique is proposed that can
even further reduce the offset. This technique is called the "nested chopper
technique". An implementation of this new technique is shown and measurement
results are discussed.
2.1 Introduction
In many electronic systems, but especially in smart sensor interfaces, the overall
performance is usually limited by the offset and noise of the input amplifiers. This
problem has been growing in the past years, because of the shift from bipolar to
CMOS IC processes, which have inherently higher noise and offset. Especially in
low-frequency applications, like smart temperature sensors, the poor offset and
11/ noise performance of CMOS processes is a significant problem nowadays.
Laser trimming and other forms of calibration have been the most appropriate and
cheapest solution for many years to reduce the offset, but they could not solve the
11/ noise problem. And with the ongoing reduction of processing costs,
calibration is no longer an inexpensive solution.

Dynamic offset-cancellation techniques
A more fundamental approach to reduce offset and lIfnoise problems has already
been explored in the late forties and was called chopper-stabilization [2.1]. At that
time it was used to transport DC signals through vacuum tubes. Nowadays, all
commercially available low-offset CMOS operational amplifiers use a dynamic
offset-cancellation technique [2.2, 2.3, 2.4].
Comparing conventional trimming with dynamic offset-cancellation techniques,

the latter has the advantages of:
• Reduction of both offset and 1If noise

• Excellent long-term stability
• No additional costs at test level
Dynamic offset-cancellation techniques also have disadvantages. The first is the
higher complexity of the circuit and the corresponding increase of chip area. A
second, usually much more important disadvantage, is the unwanted mixing of
input signals and modulation signals. This can be explained as follows. All
dynamic offset-cancellation techniques perform a periodic sampling or switching
of the input signal. The frequency of this control signal is usually in the order of
100Hz to 100kHz. If the input signal has components that are close to the
frequency of the dynamic offset-cancellation control signals, a kind of aliasing
occurs. This implies that the original input signal is distorted and can not be
perfectly reconstructed anymore. The only good method to prevent this from
happening is limiting the bandwidth of your input signal to half the frequency at
which the dynamic offset-cancellation is performed.
In this chapter a systematic overview of all existing dynamic offset-cancellation

techniques will be given. But before that, we will first analyse and model the
offset and noise of CMOS amplifiers more accurately.
2.1.1 Offset and noise in CMOS amplifiers

If we perform a noise spectrum analysis on a standard CMOS operational
amplifier and calculate it back to the input voltage of that amplifier, we retrieve
an image as shown in figure 2-1.
We see that for high frequencies the input referred voltage noise is white. At these
frequencies the noise is dominated by shot noise and/or thermal noise. This area is
usually called the thermal noise floor. At lower frequencies, however, the noise is
not white but dependent on the frequency. In this part of the spectrum another

2.1 Introduction
lin (log[V'v(Hz)))
offset
lit noise . / ' / " ,-lit noise comer frequency
~:' thermal noise
'----------::+-------_+_, (log[Hz])
'knee
Fig. 2-1 Noise power spectrum of standard CMOS operational
amplifier
noise source is dominant over the thermal noise, which is usually called flicker
noise or 11/ noise. The reason for this latter name is that this noise decreases
linearly with frequency. The point where the thermal noise becomes dominant
over the lIf noise is called the 11/ noise comer frequency or/knee'
At very low frequencies close to DC, a third phenomenon appears that degrades
the performance of our amplifier which is called offset. Offset is assumed to be
time-invariant. However, offset changes due to aging or variations in temperature.
This implies that it has a certain bandwidth and can therefore be shown in the
same figure as the other noise sources. Another reason why we like to put it in the
same picture is that dynamic offset-cancellation techniques reduce both the offset
and the 11/ noise. It will appear to be much easier to explain these techniques if
we consider offset as a form of ultra-low-frequency 1I/noise.
-The three above determined parts of the noise spectrum (thermal noise floor, 11/
noise and offset) can be explained by the different noise sources in the CMOS
transistor. These noise sources are modelled in figure 2-2.

Dynamic otTset-canceUation techniques
o
I
G Vos Vn,f:
000: ~ In,th
s . . . . noiseless transistor
Fig. 2-2 Offset and noise modelling 0/ CMOS transistor
Assuming that the transistor is operated in weak inversion, which is usually the
case in low-power, low-noise applications, the following equations apply for the
different noise sources in a normalized 1 Hz bandwidth [2.5]
(2-1)
J4kTP (2-2)
~,J = /WL
~s, norm (2-3)

~s =
JWi
where n is the sub-threshold slope factor (n",,0.7 for NMOS and n""0.5 for PMOS),
P is a process-dependent parameter, and Vos,norm the offset voltage of a
normalized sized transistor.
The shot noise is modelled as a current source In.lh because this matches better
with its physical background. The flicker or 11/ noise V nj and offset Vos can be
modelled best as voltage sources [2.5].
For comparison reasons it is usually easier to also model the thermal noise as a
voltage instead of a current. If we do that and add it to the flicker noise, we get:
(2-4)

2.1 Introduction
Table 2-1 Classification of dynamic offset-cancellation techniques
autozeroing chopping
correlated double-sampling synchronous detection

ping-pong opamp chopper amplifier
chopper-stabilization chopper-stabi lization
self-calibrating opamp dynamic element matching
two or three-signal approach
From these equations we can conclude that for a given process, the only static
way to reduce offset and lIf noise is to increase the area (WL) of the transistor,
and the only way to reduce thermal noise is to increase the drain current ID'
2.1.2 Naming conventions and classification

Due to historical reasons some confusion has been arisen in the naming
conventions of the different dynamic offset-cancellation techniques. Nowadays, it
is generally accepted to distinguish two main groups: autozeroing and chopping
[2.6, 2.10, 2.16]. The fundamental difference between them is the handling of the
offset. While the autozero principle first measures the offset and subtracts it in a
next phase, chopping modulates the offset to higher frequencies, which will be
explained later.
In data books and literature you can find many derivatives of these two basic
offset-cancellation techniques like correlated double-sampling [2.6, 2.16], ping-
pong opamps [2.8, 2.11], self-calibrating opamps [2.7], synchronous detection,
the two- or three-signal approach [2.17] and dynamic element matching
(D.E.M.). The name chopper-stabilization is even used for both autozeroing and
chopping techniques [2.3, 2.6].
If we classify these techniques into the two main groups autozeroing and
chopping, we get a result as shown in table 2-1. The next paragraphs will discuss
the basics of these techniques. Practical applications will also be shown.

Fig. 2-3 Autozero principle
2.2 Autozero techniques
2.2.1 Principle
The basic principle of the autozero technique is shown in figure 2-3 and can be
explained as follows [2.6, 2.9]. The offset cancellation is done in two phases, a
sampling phase when <PI is high, and an amplification phase when <P2 is high. In
the sampling phase, the input signal V;n is disconnected from the
transconductance amplifier gm by switch S3' while the non-inverting input of gm
is connected to ground by S2. Switch SI is also closed and the offset Vas is
sampled on capacitor Caz . In the second or amplification phase, when <P2 is high,
ViII is connected to the amplifier gm. Switches S4 and Ss are also closed, which
results in an output voltage at Vaut of gmRl times V;w The offset Vas is in this
phase compensated by the sampled offset voltage on Caz . A disadvantage of this
circuit is that the output signal is not continuously available. This is solved by the
addition of the sample-and-hold circuit formed by Ss and Cl.
The residual offset of the autozero principle is determined by:
• Charge injection on Caz at the opening of switch S1

• Leakage on Caz during amplification phase ({J2
• Limited voltage gain of gm
This residual offset is minimized by choosing a large value of Caz and a high
voltage gain of gm. To reduce the influences of charge injection and leakage, low-
sensitivity inputs are often used. Examples of this are shown in sections 2.2.5 and

Vn (log[V"i(Hz)j)
offset
~
~
~
~
~
~
}If noise corner frequency
~~ ~
11f noise
~
-- '. X"
~
~
, I ,
~~I~ • thermal noise

Vn,th
'-----------t--------. f
- -- - - -- - - --- -- ~--
(log[Hz])
fs
Fig. 2-4 Noise power spectrum of autozeroed amplifier
2.2.6. With these low-sensitivity inputs, residual offsets of 1-IOJlV can be

achieved with capacitance values of 50pF.
2.2.2 Residual noise

As with all dynamic offset-cancellation techniques, autozeroing reduces the 1If
noise as well as the offset. This reduction depends on the sampling frequency and
is maximal when this sampling frequency is chosen higher than the 1If noise
comer frequency. A quantitative calculation of this reduction is rather
complicated, but has been done thoroughly by Enz et al [2.6]. In the framework of
this book it is, however, not necessary to understand all details of the residual 1If
noise in autozeroed amplifiers. We will therefore limit ourselves to a more
qualitative approach.
The voltage noise spectrum of an autozeroed amplifier is shown in figure 2-4. We

see that the 1If noise is removed at the cost of an increased thermal noise in the
signal band. This can be explained as follows: the capacitor Caz and the switch SI
in figure 2-3 act as a sample-and-hold filter. This sample-and-hold filter samples
the offset and noise of the amplifier gm' during the sampling phase (j>1' In the
amplification phase (j>2' the sampled offset and noise are extracted from the offset
and momentary noise of the amplifier. Because the sampling and extraction do
not occur at the same time but subsequently, only the slowly changing noise
components are cancelled. If we assume that the sampling frequency Is is higher
than the 1If noise comer frequency, all 1If noise frequency components are
removed.
A disadvantage ofthis method is that not only the low-frequency noise is sampled
on Caz' but the noise of the full bandwidth of the amplifier gm' This results in an

increased thermal or white noise component. This effect always occurs in

sampled systems and is often explained as folding of high-frequency components.
How much the white noise component will increase depends on the unity-gain
bandwidth of the amplifier fc. The higher the bandwidth, the more the thermal
noise will increase. In most practical cases, the increase in thermal noise is
approximately equal to the amplifier's original broadband thermal noise Vn th
multiplied by the ratio of the amplifier bandwidth fc and the sampling frequen~y
is [2.6]. This is shown in equation (2-5).
J;.
~, res = Is ~, th (2-5)
From equation (2-5) it can be seen that for optimal noise performance, the
bandwidth of the amplifier Ie should be as low as possible. However, this
bandwidth can not be chosen too small, because it needs enough speed to settle
during the sampling period. In practical situations./e is chosen at least three times
higher thanis, which results in a residual thermal noise that is at least three times
higher than the original wide-band thermal noise.
In the next paragraphs, several implementations of the autozero technique will be

discussed.
2.2.3 Self-calibrating oparnp

The principle of the self-calibrating opamp is shown in figure 2-5. This picture is
directly copied from the Texas Instruments TLC4501 data sheet [2.7]. It is a
genuine autozerocd opamp, but with the sample-and-hold circuit implemented by
an A-to-D converter, a register, and a D-to-A converter. An advantage of this
method is that there is no leakage on the sampling "capacitor" during the
amplification phase. A disadvantage is obviously the increased chip area.
Although it is possible to run this offset correction loop at a higher frequency,

which is done by Yu et al [2.8], Texas Instruments only performs an offset
correction at start-up. This has the advantage that the amplifier does not suffer
from spurious autozero-control signals in the signal band and does therefore not
need an anti-aliasing filter.
The disadvantage is that the 1/f noise is not reduced and that the offset drift after
start-up is not compensated for.

.ThxAs
INSIRUMENTS
IN+ ---"-ll----<>-~--<t---I
>-_ _ _ _---.--o--~+-'-l- OUT
IN- ---"-ll----<>-~--<~--I
Calibration Circuitry
r--------------
I
I
I
Voo --1
8 1---'1_ _--._-.5V
• GND
Fig. 2-5 Self-calibrating apamp (Courtesy afTexas Instruments)
2.2.4 Correlated double sampling

The correlated double sampling technique was originally introduced to reduce the
noise in charge-coupled devices (CCDs) [2.12, 2.13]. It can be described as an
autozero operation within a sample-and-hold circuit. Nowadays, it is widely used
in sampled-data systems and particularly in switched-capacitor (SC) circuits.
Many examples of high-accuracy SC sample-and-hold stages, voltage amplifiers,
integrators, and filters can be found in [2.6].
The effect of the correlated double sampling technique on the amplifier offset and
noise is equal to that of the autozero principle. However, because the input data is
already sampled the white noise is not increased as is the case by a continuous-
time input signal. This makes this technique widely used in sampled-data
systems.
2.2.5 Ping-pong opamp

Some applications require bandwidths that are higher than the sampling
frequency. In these cases a sample-and hold filter at the output can not be used.
This problem can be circumvented by duplicating the autozeroed amplifier and
using one amplifier in its amplification mode while the other is being autozeroed.
This time-sharing principle is called "ping pong" technique in literature [2.8,
2.11] and is shown in figure 2-6.
HIGH-ACCURACY CMOS SMART TEMPERA TURE SENSORS 17

CPt
Tc az2
Fig. 2-6 Ping-pong opamp principle
The circuit consists of two amplifiers Al and A 2. In the first phase, when <PI is
high, amplifier A 1 amplifies the input signal, while A2 is being autozeroed. In the
second phase, when <P2 is high, A2 amplifies the signal, while A I is being
autozeroed. The amplifiers have special low-sensitivity inverting inputs a-. This
has the advantage that the influence of charge injection on the autozeroing
capacitors Cazl and Caz2 is reduced and that the regular inverting input can be
used for feedback circuitry. In practical situations, the inputs a- have
approximately -40dB less sensitivity than the regular inverting inputs.
Disadvantages of this technique compared to regular autozeroing are the

increased chip area and power consumption and the glitches at the output when
switching the opamps. This latter problem can be reduced by the so-called
chopper-stabilization technique, which is described in the next paragraph.
2.2.6 Chopper-stabilization
The chopper-stabilization technique is the industry standard nowadays for ultra-
low offset CMOS opamps [2.2, 2.3, 2.4]. A better naming, however, would be
continuous-time autozeroed amplifier as proposed by Enz et al. [2.6].
The principle of the chopper-stabilized opamp is shown in figure 2-7. It consists

of a main opamp and a nulling opamp. The basic idea behind this circuit is to use
an offset-free nulling amplifier to sense the main amplifier's offset and generate a
correction voltage that is applied to the nulling input (a-, a low-sensitivity
inverting input) of the main amplifier to cancel its own offset. To make the

<PI
TC az1
Fig. 2-7 Chopper-stabilized opamp
nulling opamp offset-free, it is autozeroed during phase <PI, when switches Sl and
S2 are closed. In the second phase <P2' when switches S3 and S4 are closed, the
main opamp is made offset-free. During the next <PI phase, the main opamp
conserves its offset information on capacitor Caz2 .
The main difference compared to basic autozeroing and ping-pong techniques is

that the main opamp is not disconnected from the signal path, which reduces the
glitches at the output. Disadvantages are again the higher power and chip area
consumption.
2.2.7 Three-signal approach

In the previous paragraphs a number of different implementations and derivatives
of the autozero principle have been discussed. All these principles cancel the
offset and lIfnoiseat the amplifier level. A more system-level approach is found
in the two or three-signal approach [2.17]. In the two-signal approach, the offset
is sampled during the first phase, converted to a digital format by an A-to-D
converter, and stored in memory. In the second phase, the same is done with the
input signal. Afterwards, the two signals are subtracted by a microcontroller. To
also cancel amplification errors, the principle can be extended with a reference
signal and is then called the three-signal approach. This principle is shown in
figure 2-8.
In practical implementations [2.17], not a sampled but an integrating A-to-D

converter is used (duty-cycle or V-f converter). As a result, the noise performance
of the two and three-signal approach is not degraded by the sampling action. The
HIGH-ACCURACY CMOS SMART 'TEMPERATURE SENSORS 19

Analog
to Micro V in = V;- ~
Digital
Converter
Controller Vret ~- ~
111 = V;n + ""5

~ = Vref + ""5
\Ij = Vos
Fig. 2-8 Three-signal approach
noise will therefore not increase by at least a factor of five, but by a factor that is
dependent on the ratio of the offset (and reference voltage) measurement time and
the total time. For a two-signal approach with an offset measurement "duty cycle"
of 50%, the increase in thermal noise is approximately a factor of two.
In general it can be stated that the two and three-signal approach is a very low-
cost and easy offset and gain-cancellation technique if a microcontroller is
already available, which is usually the case in modem data-acquisition systems.
2.3 Chopper techniques
2.3.1 Principle
As already discussed in paragraph 2.1.2, the main difference between the
autozero technique and the chopper technique is the handling of the offset. While
in the autozeroing principle the offset is sampled, stored and subtracted in the
next phase, the chopping technique modulates the offset to higher frequencies and
therefore needs an additional low-pass filter to remove the high-frequency offset
components.
The chopping principle is shown in figure 2-9. The input signal Vin is multiplied
by a square wave signal at a frequency !chop. The modulated input signal is then
amplified by an amplifier with gain A and demodulated back to the baseband by a
second similar multiplier or chopper. The offset is, however, modulated only once
and appears as frequency components around the odd harmonics of Ichop. These
components need to be removed by a low-pass filter.
Next to the frequency domain, the chopping principle can also be explained in the
time domain. The input signal Vin is in that case periodically inverted by the first

+ <>---........ '-~~~
\{n \
LPF
\{wt
+
signal
..-noise
u......,.-.....,....-___ f
3 5 fchOP
signal
,I~ .
II ... nOise
:\ "
1IL...1~L._:__-~/\~'-_--_-_-,~·,_-___ f
fchOP
signal
L - - - - . . -_ _ _ f
T 2T
\fout
signal
A( V;n+ IIos}
A( V;n- Vas) L-~-~------f
T 2T T 2T
Fig. 2-9 Amplifier using the chopper technique. including signals

in the frequency and time domain

lfU1~--~----------------~
Vc/JoP
Fig. 2-10 AC-driven Wheatstone bridge
multiplier or chopper. After amplification, the inverted and amplified signal is

inverted again, while the non-inverted part of the signal is left alone. The offset is
periodically inverted only once and therefore appears as a square wave at the
output.
The chopping technique is older than the autozeroing technique and was already
applied with vacuum tubes in the late fifties. It is also called synchronous or
coherent detection. A well-known example is the AC-driven Wheatstone bridge,
which is shown in figure 2-10. The bias voltage on the bridge Vchop is inverted
periodically, thus modulating the output signal of the bridge. This output signal is
fed to the instrumentation amplifier. At the output of the amplifier the signal is
demodulated again, while the offset is modulated. Finally, a low-pass filter
removes the offset components.
Dynamic Element Matching (DEM) is an other derivative of the chopping

technique. This technique periodically interchanges a number of elements and
takes the average. The mismatch between the elements is cancelled this way.
Fundamentally, the chopping principle can be seen as a DEM with two elements,
for example the two input transistors which form the input stage of an amplifier.
A very nice application has been described by de Jong et al [2.18].
2.3.2 Residual noise

In contrast to the increased white noise component of autozeroed amplifiers, the
baseband white noise of chopped amplifiers is almost equal to the wideband
thermal noise, assuming that the chopping frequency is higher than the 11/ noise
corner frequency. The fundamental reason for this is that the input signal of a
chopper amplifier is not sampled, which makes it impossible for wideband

Vn (logIV/,J(Hz)])
offset
,,
,,
,
, ",1Ifnoise """, ..
.. './ 11f noise corner frequency
,,
,,
,, '
" ~' thermal noise
Vn,th
' - - - - - - - - - - - - - - - - - - . . f(logIHz])
Fig. 2-11 Noise power spectrum of chopper amplifier
thermal noise to fold back in the baseband. The typical noise power spectrum of a
chopped amplifier is shown in figure 2-11.
The superior noise performance of the continuous-time chopper technique over

the sampled autozero technique, makes it the best choice to realize low-noise
sensor interfaces. Since in low-bandwidth systems the power is mainly dictated
by the required signal-to-noise ratio and not by the power-bandwidth product, the
chopping principle is also the best choice to realize sensor interfaces with
minimal power.
2.3.3 Residual offset

The residual offset of the chopper amplifier as shown in figure 2-9 is determined
by the spikes of the input chopper [2.6, 2.10, 2.14]. This is schematically shown
in figure 2-12. The spikes are generated around the odd harmonics of the
modulating signal. They are demodulated to the baseband by the second
modulator. The residual offset equals the area under the spike. Given a time-
constant 't that is determined by the source impedance and the input capacitance,
the residual offset can be written as
O.5T
~s, res = O.ST

~pike f e
-tit d
t
(2-6)
o

~ut
+
\.4
+v_~ ~ ~.
(a)
-Vspik
\.'chop
V T
v= 2T
t(5)
v~f
T
c.
2T
t (5)
(b)
\?
+V:~---~---b--k--b . T 2T
t(5)
(c)
Fig. 2-12 Residual offset caused by spikes

(a) Spike signal (b) Demodulation signal
(c) Demodulated spike
for T » 't this can be written as
V
os, res = 2 ~PTike ""f e -1/. dt = 2't
T ~pike (2-7)
o
Since most of the spike energy appears at high frequencies, the influence of these
spikes on the residual offset can be reduced using a band- or low-pass filter
between the modulator and demodulator. This is implemented by Menolfi et al
[2.14, 2.15] and shown in figure 2-l3. Because of the tuning error between the
filter and the oscillator of 1%, the quality of the filter can not be set higher than
five. With this quality factor, the residual offset can be improved by
approximately a factor five. The analysis has been done very accurately by
Menolfi et al [2.14, 2.15]. They report a chopper amplifier with bandpass filter,

+.,...<""'----.;-t
!\
BPF
I asc I
I
I _ _ _ _ _ .J
Fig. 2-l3 Chopper amplifier with bandpass filter to improve

residual offset
having a 500nV offset at a source impedance of 20 kQ and a chopping frequency

of 5kHz.
2.3.4 Gain accuracy

The gain accuracy of the chopper amplifier principle, which is shown in figure
2-9, is limited by the bandwidth of the amplifier A. This is explained in figure
2-14. The output voltage for 'tc«T is given by:
(2-8)
Where 'tc is inversely proportional to the bandwidth of the amplifier Ic.
The gain error can be reduced by delaying the demodulation signal with 0.7'tc• see
figure 2-14 (d). The output signal is then given by:
2'tc)
~ut = ( 1 - T A "in (2-9)
If we consider an amplifier with a unity-gain bandwidth of 10Mhz and a dc-gain

of 100,fc is 100kHz. A chopping frequency of 5 kHz then already gives an error
of 10%, even if we reduce the gain error by delaying the demodulation signal! It
is shown from this example that for high gain accuracies, high bandwidth
amplifiers are needed. which imply high power consumption. A more power-
efficient solution can be found in the chopper opamp as discussed in the next
paragraph.

(a)
+AVpn (.
V(lI)
-A "'in
'c V~
f"j(b)
V(~
+1Y.:;fn-n -n -n -t
rv rv (e)
u
.t(5)
-A "'in
V(~
+1Y.:;~~-f"j(d)
Fig.2-14 Gain errors due to limited amplifier bandwidth
(a) Modulated input signal
(b) Amplified modulated input signal
(c) Output signal with in-phase demodulation signal
(d) Output signal with delayed demodulation signal
2.3.5 Chopper opamp

An interesting derivative of the chopper amplifier principle is the chopper opamp
as shown in figure 2-15. Amplifier Al is a regular opamp with high dc-gain.
Amplifier A2 has a limited gain and serves mainly to generate a single-ended
output.
In contrast to the above-mentioned chopper amplifier, the chopper opamp does

not modulate the input signal, but only the error signal. This implies that all errors
due to spikes and limited gain are independent of the input signal and thus do not
contribute to the gain error but to the residual offset.

I{,hoP U1J1
Rl
Fig.2-15 Chopper opamp
I{,hoP U1J1
Rl
Fig. 2-16 Chopper opamp with Miller pole-split
Another source for residual offset is caused by the limited gain of amplifier Al
and the second amplifiers offset Vos2 and is given by:
2fchop
Vos, res = to, A 1 ':;s2
(2-10)
Assuming that the first amplifier A 1 has a unity-gain bandwidth (fOA \) of

lOMHz, a chopping frequency of 5kHz and a second amplifier's offset of 5mV,
the residual offset caused by limited gain is 5p. V.
A method to increase the bandwidth of the first opamp is already reported by

Hsieh et al [2.16] in 1981. Their principle is shown in figure 2-16. By adding a
Miller capacitor across the second stage of the opamp, the pole of the first
amplifier is shifted to higher frequencies. Assuming that the tail current of the
input stage is already high for noise reasons, the bandwidth of the first stage can
be increased to frequencies up to 100MHz, without any increase of power

consumption! This makes it possible to neglect the contribution of the limited

gain to the residual offset as shown in equation (2-10).
The conclusion of this paragraph is that the chopper opamp with Miller split, as
shown in figure 2-16, is the best implementation of the chopping principle
regarding gain accuracy and power consumption. The offset performance is,
however, worse than the chopper amplifier with bandpass filter.
In the next paragraph we will present a new technique to improve the offset
performance of the chopper opamp, and bring it to a level that is higher than can
be achieved by chopper amplifiers with bandpass filter.
2.4 Nested chopper technique
2.4.1 Principle
At first glance, equation (2-7) on page 24 does not leave much room to improve
the residual offset of the chopper amplifier. The product 't times Vspike can hardly
be reduced because it is dictated by the source impedance and by process
parameters like the gate-drain overlap capacitance. Also the period T, which is
inversely proportional to the chopping frequency /chop' is dictated by the 1/j noise
corner frequency. This II/noise corner frequency can only be reduced at the cost
of higher thermal noise, or at the cost of larger input transistors, which are needed
for lower 11/ noise.
However, considering a chopper amplifier as a regular amplifier with a small

residual offset, but without lifnoise, we can reduce this offset by doing another
chopping action. This is shown in figure 2-17. The chopping frequency of this
outer chopping pair is now not dictated by the lI/noise corner frequency, but can
be chosen as low as possible, usually two times the bandwidth of the input signal.
Since the residual offset caused by spikes is linearly dependent on/chop according
to equation (2-7), the influence of these spikes on the residual offset can be
considerably reduced. If we look at a temperature sensor with a bandwidth of
10Hz for example, the outer chopper frequency can be as low as 20Hz, which is
the minimal frequency at which no aliasing occurs. With an inner chopper
frequency of 2 kHz, which is determined by the 11/ noise corner frequency, the
improvement can theoretically be a factor of 100.

Fig. 2-17 Nested chopper amplifier principle
V1
+v:":\-~ -~ -~ -~ -~ -~ -~ -~ -~ -~ -. 'I':")
+1
-1
r
V2
V
Jow
Thigh 2 Thigh 3 Thigh 4 Thigh 5 Thigh
•
(b)
t(S)
+v_~ ~ ~ ~~~ • 'I':C)

-v spike VV V VV
Fig. 2-18 Reduction of residual offset by nested chopper technique
(a) Spikes after first demodulator
(b)Low-frequency modulation signal
(c) Spikes after second demodulator
This short description of the nested chopper technique shows that a major
improvement over the conventional chopper technique can be obtained with a
rather simple extension. The extra chopper pair occupies negligible chip area and
does not consume power.
2.4.2 Analysis
An analysis of the nested chopper technique on the residual offset caused by
spikes is shown in figure 2-18. Figure2-18 (a) shows the result at the output of the
second high-frequency chopper CH2 , which is the same as for a conventional
chopper amplifier. Figure2-18 (c) shows the spikes at the output of the second
low-frequency chopper CL2 . The spikes are again modulated but now at a much

I bias
C'-2
2k Rl1 100kJ--------t-h---r-h,
R Vout
1--_2_0--11--_--11OOk~R~12:..----_ _rlII-o
~hOPIOW
Fig. 2-19 Nested chopper amplifier realization

lower frequency with a period T/oW" By this second modulation, the average value
of the spikes becomes zero and therefore they no longer contribute to the residual
offset. The extra spikes that are generated because of this low-frequency chopper
pair can be neglected if T low » Thigh .
In the figure it is suggested that the spikes are not influenced by the input low-
frequency chopper CLI' This is only true if the impedances of the input source at
both inputs of the amplifier are completely matched, which is in practice usually
not the case. This mismatch in source impedances will be the main source of
residual offset of the nested chopper technique. Nevertheless, the residual offset
of a nested chopper amplifier will be 10 to 50 times better than that of a
conventional chopper amplifier, depending on the mismatch of the source
impedances.
To examine the performance of the proposed nested chopper amplifier technique,

a realization has been designed and tested. The results will be shown in the next
paragraphs.
2.4.3 Realization
The realization of the nested chopper amplifier is shown in figure 2-19. A choice
has been made for an instrumentation amplifier to have a good matching of input

Fig. 2-20 Chip photograph of nested chopper instrumentation amplifier
impedances. The high-frequency choppers CH lI to CH 22 are configured as

chopper opamps with Miller pole-split as discussed in paragraph 2.3.5. The low-
frequency pair (CL I and CL2) modulates and demodulates the input signal as in a
regular chopper amplifier (see paragraph 2.3.1). The gain is determined by R l1 •
R12 and R20 and is set to 100. The ratio between the higher chopping frequency
and the lower chopping frequency is fixed and set to 128. The bandwidth of the
amplifier is around 4kHz. power consumption is 2001l A.
The choice for the input signal needs to be done very carefully. Applying an off-
chip input signal will give rise to unwanted thermocouple effects and the
protection diodes will add non-linearity and leakage currents. The best way is to
add a Wheatstone bridge or a Hall plate on chip. We made the choice for a
spinning-current Hall plate [2.19], because this directly shows an important
application. The offset of the nested chopper instrumentation amplifier can be
measured by switching off the bias current of the Hall plate.
The chip has been made in the in-house DIMES standard CMOS, 1.61lm, single
poly process. A chip photograph is shown in figure 2-20. The chip measures
6mm2 of which Imm2 is occupied by the instrumentation amplifier and another
1mm2 by the high-linearity metall-metal2 Miller capacitors.

Dynamic otTset-cancenation techniques
200
--chip 1
100 -+-chip 2
~chip 3
>
.:. ~chip 4
'Z 0 -+-chip 5
!II -+- chip 6
:::0
....... chip7
-100 ~chip8
-chip9
-200
0 2 3 4 5 6 7 8
chop high (kHz)
Fig. 2-21 Input referred offset versus chophigh frequency,
resolution of measurement is SOn V
2.4.4 Measurement results

Nine samples of the chip have been tested. The output of the amplifier is
connected to an external amplifier/filter. which has a 20-times amplification and a
3Hz bandwidth. For dc measurements. a multimeter with 500ms integration time
has been used.
The offset as a function of the higher chopping frequency is shown in figure 2-21.
It can be seen that the residual offset at a chophigh frequency of 2kHz is below
lOOnY for all samples. This offset becomes worse at higher frequencies. but stays
below 200nV at 8kHz. The other specifications are listed in table 2-2.
These results show that the nested chopper amplifier principle works. It gives an
improvement of 5 times over the best reported value so far by Menolfi [2.15].
Over regular chopper amplifiers it gives a 10 to 50 times improvement.
Given the fact that the charge injection is dependent on switch widths. even better
results are to be expected in up-to-date processes.

2.5 Conclusions
Table 2-2 Specifications of the nested chopper instrumentation

amplifier
Typ Unit
Supply voltage 5 V
Supply current 200 JlA
High chopping frequency 2 kHz

Low chopping frequency 16 Hz
Offset 100 nV
Offset temperature coefficient (20-50°C) 3 nV(JC
Noise (input referred) 27 nV/-V(Hz)

CMRR (0-3Hz) 140 dB
2.5 Conclusions
In this chapter it has been shown that, although many different names are being
used, basically only two different dynamic offset-cancellation techniques exist,
namely the autozeroing and the chopping technique. Autozeroing is a sampling
technique, while chopping is a modulating technique.
The main difference in performance is the residual noise in the signal band. The
chopping technique reduces the lIf noise to the minimal thermal noise floor,
while autozeroing has an increased thermal noise due to the sampling action.
An extension of the chopper technique is proposed, called the nested chopper

technique. This new technique can reduce the residual offset to values below
lOOnY, while keeping the noise at the minimal thermal noise floor. The
effectiveness of the nested chopper technique has been proved by a realization
and measurement results.
Based on the above-mentioned results, the nested chopper technique is the best
choice for realization of high-accuracy CMOS amplifiers and will therefore be
used as a starting point for the rest of the design and implementation of our high-
accuracy CMOS smart temperature sensor.

References
[2.1] AJ. Williams, RE. Tarpley and W.R Clark, "D-C amplifier stabilized for
zero and gain", Trans. AlEE, vo1.67, pp.47-57, 1948
[2.2] Maxim Integrated Products, "ICL7650, Chopper Stabilized Operational
Amplifier", http://www.maxim-ic.com. June 1999
[2.3] Linear Technology, "LTCI050, Precision chopper stabilized operational
amplifier with internal capacitors", http://www.linear.com. June 1999
[2.4] National Semiconductor, "LMC2001, High Precision, 6MHz Rail-To-Rail
Output Operational Amplifier", http://www.national.com. June 1999
[2.5] J.F. Franca and YP.Tsividis, "Design of VLSI Circuits for Tele-
communications and Signal Processing", Prentice Hall, 1991
[2.6] C.C. Enz and G.e. Ternes, "Circuit techniques for reducing the effects of
opamp imperfections: autozeroing, correlated double sampling and
chopper stabilization", Proc. of the IEEE, vol. 84, no.11, pp. 1584-1614,
november 1996
[2.7] Texas Instruments, "TLC45 0 1, Self-calibrating operational amplifier",
http://www.ti.com. May 1999
[2.8] C.G. Yu and RL. Geiger, "An automatic offset compensation scheme with
ping-pong control for CMOS operational amplifiers", IEEE Journal of
Solid-State Circuits, vol.29, pp.601-61O, May 1994
[2.9] M. Degrauwe, E.A Viuoz and I. Verbauwhede, "A micropower CMOS
Instrumentation amplifier", IEEE Journal of Solid-State Circuits, vol. 20,
pp.805-807, June 1985
[2.10] e.C. Enz, E.A Viuoz and F. Krummenacher, "A CMOS chopper
amplifier," IEEE Journal of Solid-State Circuits, vo1.22, pp.335-342, June
1987
[2.11] I.E. Opris and G.T.A Kovacs, "A rail-to-rail ping-pong opamp", IEEE
Journal of Solid-State Circuits, vo1.31, pp.1320-1324, September 1996
[2.12] K.H. White, D.R. Lampe, F.e. Blaha and LA Mack, "Characterization of
surface channel CCD image arrays at low light levels," IEEE Journal of
Solid-State Circuits, vo1.9, pp.1-14, February 1974
[2.13] RW. Brodersen and S.P. Emmons, "Noise in buried channel charge-
coupled devices", IEEE Journal of Solid-State Circuits, voLll, pp.147-
156, February 1976
[2.14] C. Menolfi and Q. Huang, "A low-noise CMOS instrumentation amplifier
for thermoelectric infrared detectors, IEEE Journal of Solid-State Circuits,
vo1.32, pp.968-976, July 1997
[2.15] C. Menolfi and Q. Huang, "A fully integrated CMOS instrumentation
amplifier with submicrovolt offset", IEEE Journal of Solid-State Circuits,
vo1.34, pp.415-420, March 1999

2.5 Conclusions
[2.16] K.C. Hsieh, P.R. Gray, D. Senderowicz and D.G. Messerschmitt, "A low-
noise chopper stabilized differential switched-capacitor filtering
technique, IEEE Journal of Solid-State Circuits, vol. 16, pp.708-715,
December 1981
[2.17] G.e.M. Meijer, "Concepts and focus point for intelligent sensor systems",
Sensors and Actuators, vol.41, pp.183-191, 1994
[2.18] P.e. de Jong, G.e.M. Meijer and A.H.M. van Roermund, "A 300°C
dynamic-feedback instrumentation amplifier", IEEE Journal of Solid-
State Circuits, vol.33, pp.1999-2009, December 1998
[2.19] A. Bakker and J.H.Huijsing, "Low-offset, low-noise 3.5mW CMOS
spinning-current Hall-effect sensor with integrated chopper amplifier",
Proc. Eurosensors XIII, The Hague, The Netherlands, pp. 1045-1048,
September 1999

CMOS bandgap
references
Voltage references are key elements in analog and mixed-mode circuits. They
determine the overall accuracy in many data-acquisition systems. The accuracy of
our smart temperature sensor is also mainly dependent on the quality of its
voltage reference.
This chapter describes bandgap voltage references with emphasis on CMOS

technology. It discusses available bipolar devices in CMOS technology, thermal
modelling of the bipolar transistor, and curvature correction techniques. Also the
design and implementation of a novel high-accuracy CMOS bandgap reference is
shown.
3.1 Introduction
Nowadays the bandgap reference is the most often used implementation of a
voltage reference. It was invented in the early seventies [3.1, 3.2], when people
started to explore integrated circuits. The popularity of the bandgap voltage
reference is based on its outstanding stability and reproducibility. It is called a
bandgap reference, because it exploits the bandgap voltage of the material it is
made of. Because silicon is the most widely used semiconductor material, many
commercial references have a value of approx.imately 1.2 V or a multiple of that.
A typical bandgap reference circuit and its behaviour over temperature are shown
in figure 3-1. It is explained as follows. The temperature coefficient of the base-

CMOS bandgap references
V(V)
IIcc
1.2
R2
\'Ptat
Vee ~-----3-'OO---"""::::'-:::'6'"T"OO. T(K)
~ (~
Fig. 3-1 Typical bandgap reference circuit (a) and temperature
curves (b)
emitter voltage VBE of a bipolar transistor is approximately -2 m V(lC. To obtain

the desired temperature-stable voltage, a signal with an equal but positive
temperature coefficient needs to be added. This voltage is derived by subtracting
the base-emitter voltages of two bipolar transistors (Q] and Q2) with different
emitter areas but biased at the same current. Assuming an emitter area ratio of n,
the voltage difference can be written as
kT
Vptat = -Inn
q (3-1)
where k is the Boltzmann's constant and q the electron charge. The ratio kT/q is
called the thermal voltage and equals approximately 26mV at room temperature
(T=300K). This voltage difference is called Vptat because it is proportional to the
absolute temperature T The temperature coefficient of the basic Vptat signal
yields approximately 200!!V(lC for n is 10. To obtain the necessary temperature
coefficient of 2 mV(lC, it needs to be amplified by approximately 10. This
amplification factor is set by the ratio of R2 and R].The bandgap reference circuit
described above, fitted perfectly in bipolar technology, which was the standard
technology of the seventies. When CMOS became the leading technology for
digital and mixed-mode circuits, a lot of effort was put into implementing the
bandgap reference principle in CMOS technology. The first description of a
CMOS-compatible bandgap reference was published in 1978 [3.3].
The choice for the best device in CMOS technology is less easy than it is in
bipolar technology. A conventional MOS transistor does not exhibit a very well
defined and reproducible temperature characteristic. It also suffers from large

3.1 Introduction
E B c
p-sub
Fig. 3-2 Substrate PNP transistor in n-well CMOS technology
mismatch and spread in Vt . MOS transistors operated in weak inversion have a

much better defined temperature dependence, which make them suitable for
generating flAT voltages, but the poor absolute accuracy remains. Vittoz et
al [3.4] did a lot of research on CMOS compatible lateral bipolar transistors,
which are available in all standard CMOS processes. These devices have the same
temperature characteristics as regular bipolar transistors and some bandgap
references have been reported using this device [3.4, 3.5]. However, the lateral
bipolar suffers from very large spread in current gain (l0-300) [3.4] and is very
poorly described and monitored by the process suppliers. This makes it very
difficult to make a commercial version of this type of CMOS bandgap reference.
The best device for implementation of a CMOS bandgap reference is by far the
parasitic substrate bipolar transistor. This device is available in every CMOS
process and is very well defined and highly reproducible. In addition, the
monitoring by the various suppliers is improving, since it is being used more
often. Most of the reported CMOS bandgap references are based on this substrate
bipolar transistor [3.6,3.7,3.8,3.9,3.10,3.11].
The substrate bipolar transistor is in a modern n-well CMOS process a pnp-type

which is formed by the p+ source-drain implant, the n-well and the p-substrate.
This is shown in figure 3-2. The main disadvantage, which becomes directly
clear, is that the collector is formed by the substrate. Consequently, some people
call it a diode. It is, however, a regular pnp-transistor of which the collector is
connected to substrate. An important advantage of this device is its high accuracy.
The base is rather large, which gives small spread in base-width. Compared to the
small base-width in general frequency-optimized bipolar processes, the bipolar
substrate transistor in CMOS technology has better absolute base-emitter voltage
accuracy and also the mismatch is smaller. This is also concluded in [3.12, 3.13].
In this paragraph we only discussed the basic principles of bandgap references

and possible implementations in CMOS technology. The next paragraph will
focus more deeply on the temperature modelling of the substrate bipolar transistor
and the error sources in CMOS bandgap references.

3.2 Temperature curves of the bipolar transistor

The temperature characteristics of the bipolar transistor are well known and show
almost no dependency on process parameters. Meijer [3.14] made a very useful
description of the bipolar transistor for application in temperature sensors, which
we will follow in this paragraph.
For a bipolar transistor with a zero base-collector voltage, the collector current Ie
as a function of the base-emitter voltage VBE can be written as
qVsE}
I
e = I S exp {-kT- (3-2)
where Is is the saturation current, q the electron charge, k Boltzmann's constant

and Tthe absolute temperature. Expressing VBE as a function of Ie, we get
kT Ie
v.-
BE
= -In-
q Is
(3-3)
This equation seems to imply that VBE increases with temperature, which is
however not true. The reason for this is that the saturation current Is is very
strongly dependent on temperature. Taking this into account, we can write
equation (3-3) as
kT Ie
'iJE = V + -In--
gO q CTTJ
(3-4)
where VgO is the extrapolated bandgap voltage at zero Kelvin and C and II are
constants. Because IdCTTJ <1, the value of the In function is negative, which
gives the VBE function a negative temperature coefficient.
Introducing a new constant VBE(Tr ), which is the base-emitter voltage at a chosen

reference temperature T,., equation (3-4) can be written as
(3-5)

3.2 Temperature curves of the bipolar transistor
This equation is derived in the appendix on page 117. In practice, Ie is usually not
constant over temperature, but for example flAT (proportional to absolute
temperature). This can be introduced by writing Ie as
(3-6)
A constant Ie is then represented by m=O and a flAT Ie by m=l. Equation (3-4)

then becomes
kT K]e
"h = V + -In _-c=-=_
gO q cr(l1 - m)
(3-7)
and equation (3-5) will change into
(3-8)
For further analysis and design, it is easier to write equation (3-8) as the sum of a
constant term (V~o), a linear term (AT), and higher-order terms (O(T2». Equation
(3-8) then becomes:
, 2
"BE(T) = ~O - AT + OCT ) (3-9)
where
(3-10)
(3-11)
(3-12)

V(V)
Vgo ,
Vg
!p=arctan A
Fig. 3-3 Plot of the base-emitter voltage VBpjT) versus temperature T
O. 0r--------=:::::::::~---~~:::::::::---_____,
-1 .0
~ -2.0
7;=500(;
·7,0
·8,0<--~-~-_-_~_~-~-~-~~-__l
·60 -40 ·20 0 20 40 60 80 100 120 140 160
Temp (OC)
Fig. 3-4 Plot of the non-linearity versus the temperature for

different values of T/-m
A plot of the base-emitter voltage VBE (T) versus temperature T according to

equation (3-9) is shown in figure 3-3. The non-linearity O(T2) is plotted in figure
3-4.
In the next paragraphs, design strategies for high-accuracy bandgap references are
presented. A realization and measurement results are also shown.

3.3 Design
p-1/lnn
~~~~__~____~Vss
Fig. 3-5 Traditional CMOS bandgap reference with non-idealities
3.3 Design
3.3.1 Non-idealities in practical CMOS bandgap references

A widely used practical CMOS bandgap reference is shown in figure 3-5. The
main difference of this circuit compared to the bipolar version, as shown in figure
3-1, is the presence of an operational amplifier. This opamp is needed because the
collector of the substrate transistor can not be connected. It is therefore not
possible to measure Ie. However, by means of the opamp the emitter-current IE
can be measured, which is a good alternative if the current-gain f3 is high or well
known. The output voltage Vbg yields:
(3-13)
The parameters p and n are chosen in such a way that the second term in
equation (3-13) exactly cancels the first-order temperature dependence of VBE,Ql'
According to equation (3-11) this yields:
k
p-Inn (3-14)
q
Practical values of nand p are 8 and 10 respectively. When the first-order

temperature dependence is completely cancelled, the bandgap voltage equals Via
at T,., which is approximately 1250 mV.

Table 3-1 Errors in CMOS bandgap references at room temperature
Error contribution when

Kind of Typical Error contribution for
applying dynamic offset-
error value typical value
cancellation
cr(Vos) O.4mV 4mV 0.33% O.4mV 0.03%
cr(Vos,Q) O.lmV ImV 0.08% ImV 0.08%
cr(~R) 0.1% 0.6mV 0.05% 0.6mV 0.05%
cr(~sh) 4% ImV 0.08% ImV 0.08%
cr(~ Vbe) 2mV 2mV 0.17% 2mV 0.17%
Total: 4.7mV 0.39% 2.5mV 0.21%
Errors ullcorrelated, Vbe = 600 mV, T = 300K, p=lO, 11=8
Looking at this CMOS bandgap reference, we can determine several non-

idealities. The major one is the offset of the opamp Vas' Other non-idealities are
the offset of the bipolar transistors Vas,Q' the mismatch of the resistors M, the
spread in the sheet resistance Msh and the spread in the base-emitter value ilVBE .
Taking these errors into account, equation (3-13) becomes:
(3-15)
The estimated values of the above-mentioned non-idealities and their

contributions to the total error of the bandgap voltage at room temperature are
shown in table 3-1. This table shows that a total typical error of 4.7mV or 0.39%
can be expected. The largest contributor to this error is by far the offset of the
opamp. This error can however be reduced by at least a factor of ten, if
appropriate dynamic offset-cancellation techniques are applied (see chapter 2).
Doing this, the total error in the bandgap reference can be reduced to typically
2.5 mV or 0.21 % as shown in table 3-1. This indicates that by removing the offset
of the opamp, the overall accuracy of the bandgap reference circuit will be
improved approximately two times. The largest contributor to the error then

3.3 Design
becomes the spread in Vbe. This error is however due to process variations and
can not be reduced by circuit techniques.
Considering errors not only at room temperature but also for a larger temperature
range, the non-linearity of VBE will also add to the total error. Figure 3-4 shows
that this can be up to 5mV or 0.4% over a temperature range from -50°C to
150°C. Comparing this to other error sources, this error will be the dominant one
over an extended temperature range. Although this problem was encountered
many years ago, techniques to solve this non-linearity problem are still being
developed.
An overview of these so-called curvature correction techniques is given in the

next paragraph. We will also propose a new class of techniques, which can be
very useful in situations where trimming is not possible.
3.3.2 Curvature correction techniques

To obtain a high-accuracy bandgap reference, it is not sufficient to consider
inaccuracies only at room temperature. Especially the non-linearity of the VBE-
curve over temperature needs more attention. Looking at figure 3-4 and
introducing values 11=4 ( [3.6, 3.14]), m=1 (PTAT bias current) and Tr=50oC, the
non-linearity can be up to 5 mVat -50°C and + 150°C. Comparing this to the total
error at room temperature of 2.5mV, it is obvious that the non-linearity is the
dominant error for temperatures below OOC and above 100°C.
To reduce the inaccuracy due to the non-linearity, several so-called curvature

correction techniques have been developed. The first ones appeared in the early
eighties for bipolar references [3.15, 3.16], followed a few years later by
CMOS [3.17]. Meijer describes a few of these early techniques in his Ph.D.
thesis [3.18]. They were based on the application of resistors with different
temperature coefficients. It was obvious that only poor accuracy could be
obtained, due to the matching problems of the different types of resistors.
Meijer himself proposed a new technique that is based on the so-called linearized
thermal behaviour of VBE. This principle is still the starting point for many
modern curvature correction techniques. Gunawan et al [3.19] adapted it for
lower supply voltages. The principle of this curvature correction technique is
shown in figure 3-6.
The non-linear correction voltage VIl1 is generated by the extraction of two base-
emitter voltages of which one (Q3) is biased at a PTAT current and the other (Q4)
at a temperature-constant current. This differential voltage is amplified by 11-1

Fig. 3-6 Curvature correction technique based on linearized VBE
and added to the conventional bandgap voltage. The emitter areas of Q3 and Q4
are chosen in such a way that at the chosen reference temperature Tr the
corresponding base-emitter voltages are equal.
The correction voltage yields:
(3-16)
Applying equation (3-9), this becomes:
VI
11
= (11 - 1) { -kT,
-
q
+ kT
- - -k[ T - Tr + Tln-
q q
TrJ}
T
(3-17)
The last term in this equation is exactly opposite to the non-linearity term shown
in equation (3-12). Equation (3-17) also shows a linear term (TJ-l)kTlq, which
makes it necessary to slightly adapt the parameter p, resulting in a p'. The
absolute value of the bandgap voltage is also decreased by a factor (TJ-l)kTrlq,
which makes it now exactly equal to Vgo.
A good implementation of the curvature correction circuit of figure 3-6 is not so

straightforward. Amplifier Aj has offset that is amplified by 11-1 and added to the
output voltage. Also the voltage VIII can both be positive and negative, which
requires a different method of adding it to the bandgap voltage. A solution in the
current domain, as proposed by Gunawan et al [3.19], requires multiple current
mirrors, which again add to the inaccuracy. Until now, all proposed curvature
correction techniques use calibration to obtain the required accuracy.
Because our objective is to disregard calibration to reduce costs, we will

introduce a new curvature correction technique that is based on a piece-wise-

3.3 Design
V(mV)
Vnl
+---....;:"....,.....:;~-- ..... T(OC)
50 150
Fig. 3-7 Piece-wise-linear curvature correction technique
linear (PWL) principle. This technique is proposed by Rincon-Mora et al in basic

form [3.20], but their implementation is still based on a non-linear approach.
The principle of the PWL curvature correction technique is shown in figure 3-7.
Just as in the linearized VBE technique, the PWL technique adds a correction
voltage Vnl to a regular bandgap voltage. The difference is that Vnl is now built
out of linear segments that follow the inverse curvature. These linear segments
are made out of the VBE signal and the amplified Vptat signal, which have large
opposite temperature coefficients of approximately 2mV/°C. It is therefore
unnecessary to amplify them, which would introduce offset problems. The main
advantage over the linearized VBE technique is therefore that the implementation
of the PWL technique is much easier. A designed and tested implementation
example is shown in paragraph 3.4.3
Another important advantage is that the PWL technique can not degrade but only
improve the accuracy, because the correction signal Vn1 only has a non-linearity
term, while in the linearized V BE technique V nl also has a significant constant and
linear term. The obvious disadvantage of PWL is the worse approximation of the
non-linearity curve. This makes PWL less suitable in ultra-high performance
references, where multi-point calibration is not an issue. However, because our
goal is only to reduce the error due to curvature below the next dominant error, an
improvement of a factor of five is sufficient This improvement can be obtained
with both linearized VBE and PWL techniques. A choice for PWL is then
justified, because it has an easier implementation.

3.4 Realization
3.4.1 Filtering of modulated offset

To dynamically cancel the offset of the opamp in our bandgap reference circuit, a
choice can be made between chopping and autozeroing. Because chopping has a
superior noise performance (see chapter 2), our choice will be the chopping
technique.
An important issue when using the chopping technique is the necessary filter to
remove offset that is modulated by the output chopper. To make the chopping
technique invisible to the outside world, we have to reduce the modulated offset
signal below the noise floor. Doing this, we have to be aware that when filtering
the output signal, the noise is also being filtered. Taking this into account, this
gives the following condition
(3-18)
where p is the amplification factor of the FrAT signal, Vos the initial offset
voltage, IH(fchop) I the filter attenuation at the chopping frequency, Vnoise the
output noise of the original bandgap reference circuit, and f3dB the -3dB
bandwidth of the filter. The relation between IH(fchop) I and f3dB for a first-order
passive filter is given by:
f-3dB
(3-19)
!chop
The required bandwidth for a first-order passive filter is then given by:
f -3dB <
-
(Vnoise!chop)2
pV (3-20)
os
Filling in practical values p=JO, Vos=lmV,fchop=lOkHz and V'lOise=lJ.LVN(Hz),

f-3dB needs to be smaller than 1 Hz. It is obvious that such a frequency requires
large RC-constants, which consume a huge amount of chip area. Also the start-up
time will become very large. A better approach is to use a second-order low-pass

3.4 Realization
Fig. 3-8 Filtering of modulated offset at output by a second-order

continuous-time filter
filter, which is shown in figure 3-8. The relation between IHlfchop) I andf3dB for a
second-order passive filter is given by:
L3dB) 2 (3-21)
IH(fchop)1 = ( ~
Jchop
and the corresponding bandwidth:
2
2 "3
f -3dB <- [Vnoise
pV
fChoP) (3-22)
os
This relaxes the requirements for the filter bandwidth to approximately 500Hz,
which is possible to make but still requires large RC-constants.
An interesting different approach is to use a discrete-time filter, instead of a

continuous-time one. Such an SC-filter implementation is shown in figure 3-9. It
is explained as follows. The modulated offset of amplifier A I appears at the
output of amplifier A2 as a square wave, with an amplitude of pVos and an average
value of the desired Vbg . The switches Sl and S2 are closed with the non-
overlapping signals <PI and <P2 respectively. Doing this, the top values Vbg+pVos
and Vbg-pVos of the square wave are sampled. Buffers A 31 , A32 and the resistors
R4l and R42 take care of the averaging of the two signals, resulting in the desired
Vbg signal at the output.
The advantage of the SC-filter over the continuous-time filter is obviously the
much smaller chip area. The resistors R4l and R42 can be quite small and also the
size of the capacitors Cll and C l2 is not determined by filter characteristics.

d
\{;hop
Vbg O.5T T 1.5T

C'I,.,
2T
:l~:-I'" q> O.5T T 1.5T 2T
~:rO ,0 q> O.5T T 1.5T 2T

[ . tIs)
~r----,--O
ss O.5T T
.0
1.5T 2T
• tIs)
Fig. 3-9 Filtering of modulated offset at output by SC-filter and

corresponding signals
However, charge injection caused by the switches Sl and S2 gives rise to spurious
signals at the output. To reduce these signals below the noise floor, it is still
necessary to use capacitors in the order of a few hundreds of pF.
A third method to implement the filter is shown in figure 3-10. It is again a

continuous-time filter, but the filtering is now being done inside the loop.
Compared to the two previous methods, a clear advantage of this approach is that
no buffer is needed at the output. In addition to the lower power consumption and
chip area, this has the advantage of not introducing additional offset at the output.

3.4 Realization
Fig. 3-10 Filtering of modulated offset inside the loop
H(dB)
Ho - - - - - .!t!.1..
. .. ....
.. .
.... " ....
.. ~
p+-----------------~
O+----------::-i-~-"""T":"-.. (()(S·l)
Fig. 3-11 Bode plot of second-order in-loop filter
Another great advantage is that the bandwidth of the filter is now determined by
the Miller capacitance Cm and the transconductance gm2 of amplifier A 2.
Compared to the conventional continuous-time filter, this reduces the chip area.
When implementing a second-order low-pass filter within the loop, attention

should be paid to stability. Figure 3-11 shows a Bode-plot ofthe second-order in-
loop filter. The dominant pole (01 is formed by gm2 and Cm. The second pole (02
can be formed by adding a second capacitor or by the load capacitance CL . We
decided to let it be determined by Cv which gives the circuit better stability
performance for heavy load capacitances. The dashed line indicates the amplifier
loop without feedback. The total amplification at 0 Hz is given by Ro. Further
information about stability analysis can be found in [3.21].
It is also possible to implement an SC-filter inside the loop. We showed that

in [3.22]. This has approximately the same advantages and disadvantages as the
regular SC-filter. We decided not to use this implementation here, because it
requires too much capacitance to reduce the spurious frequencies below the noise
floor.

L--4--~-+--------~V~
r-+--=~-r----~~
Fig.3-12 Bandgap reference with nested chopper technique
3.4.2 Nested chopper technique

Until now, we have always chosen a value of 10kHz as an example for the
chopping frequency. It would be much appreciated if this value could be higher,
because that would relax our filter requirements. This is, however, not possible
with a regular chopping technique, because higher chopping frequencies cause
higher residual offset. Measurements on implementations of chopper amplifiers
show a linear increase of 5-101l V per kHz. Keeping the residual offset well below
50ll V, the chopping frequency can therefore not be higher than 10kHz.
A method to increase the chopping frequency, while still maintaining a low

residual offset is found in applying the nested chopper technique as described in
chapter 2. The residual offset is then determined by the lower chopping
frequency, while the filter requirements can be lowered by the higher chopping
frequency. In our implementation, we chose a high chopping frequency of 50kHz
and a low chopping frequency of 6.25kHz. The implementation including the
nested chopper technique is shown in figure 3-12.
The high-frequency chopper pair CHI and CH2 is located across the first
amplifier stage formed by MIl' M 12, R21 and R 22 . The amplification of this stage
is approximately ten. The amplification is kept relatively low to assure a high
bandwidth, which is necessary to reduce errors due to the high-frequency

3.4 Realization
chopping (see chapter 2). The low-frequency pair CLI, CLzI and CLzz is located
across the first stage and a transconductance stage formed by MZI and Mzz . This
transconductance stage is biased at a relatively low bias current of only 50nA to
obtain with the Miller capacitor Cm a very low-frequency dominant pole. The
bandwidth between the low-frequency chopper pair, however, is relatively high,
because the chopping is done in the current domain, before the cascodes. The
second chopper is split into two choppers CLzI and CLzz, to be able to also
remove the offset of the mirror formed by M Z3 and M Z4 . Resistor R3 is added to
remove the zero in the right-hand plane. The amplification of the fed back
amplifier is approximately equal to 1+(RIZ+2RIO)/RI4 which is twelve. Because
the amplification of the first stage is also of the same order, the bandwidth of the
amplifier is approximately gml2nCm. Having a gm of the second stage of 500nAi
V and a Cm of 80pF, this yields a bandwidth of approximately 1 kHz. Having a
high chopping frequency of 50kHz, this gives for a first-order filter a suppression
of 34dB and for a second-order 68dB. According to equation (3-18) on page 48,
this should be at least 50dB to reduce the modulated offset below the noise floor.
This condition can be met easily by introducing an extra pole at the output by
adding a load capacitor.
The substrate bipolar transistors QI and Qz have an emitter area ratio of eight.
They are biased at slightly different currents determined by R II and the sum of
R12 and R 14 . Resistor RIO is formed out of a part of the parallel resistors Rl1 and
R IZ and is only introduced to reduce some chip area. The values of the resistors
Rl1 through RI4 are mainly determined by power consumption. The chip area is
of less importance, because for values below 200kQ the size of the resistors is not
determined by their value but by their matching constraints. The reason for this
unusually high "break-even point" is the availability of high-ohmic polysilicon
resistors with values of 2krusquare.
The reference temperature Tr at which the temperature coefficient of the bandgap

reference circuit is exactly zero, is chosen at 45 DC. This is exactly in the middle of
our target temperature range of _40DC to + l30D C. This value can be set by
changing the unity-emitter size of the bipolar transistors QI and Qz, or by the
absolute values of the emitter current controlling resistors R 11 through R 14.
Resistor R 13 is a very interesting one, because it has no influence on the DC

behaviour of the circuit. It is introduced to match the impedances for the input
choppers. This is necessary because spikes due to charge injection of the input
choppers are cancelled out if these input impedances are exactly matched.
Without R13 the impedance at the upper connection of CL I would be
approximately l/gm of transistor QI. At the lower connection this is
approximately RI4 plus l/gm of transistor Qz. Since transistors QI and Qz are

Fig. 3-13 Piece-wise-linear voltage generator for T<Tr
biased at approximately the same currents, they have equal gms. The impedance at
the input of eLl can therefore be made approximately equal by adding a resistor
with the same value as R 14•
3.4.3 Piece-wise-linear circuit implementation

In figure 3-12, the voltage source Vpw/ is not implemented yet. This voltage
source is meant to compensate the non-linearity of the VBE curve, by means of a
piece-wise-linear method as described in paragraph 3.3.2. To obtain enough
accuracy, we decided to make a PWL source with six segments. The
implementation of this circuit for temperatures smaller than the reference
temperature T,., which is 45°C, is shown in figure 3-13. For simplicity cascodes
are omitted. All current sources in this circuit are PTAT and derived from the
main bandgap circuit. The left part of the circuit generates a current that is equal
to
(3-23)
Vbe and pVptat are chosen in such a way that their values are equal at the reference
temperature Tr This equation is only valid for T<T,., because M12 can not drain a
negative current. The current through M 12 is copied three times and compared
with different current sources II through 13 . The differences are added and
transformed to a voltage by R2. The value of R2 is kept at a low value of lill to
reduce output resistance, which is necessary to reduce the influence of the base
currents of QI and Q2 in figure 3-12.

3.4 Realization
Fig. 3-14 Chip micrograph of the fabricated circuit
For T>Tr a circuit with an extra NMOS current mirror is added. The cutrent
generated by this circuit is added to the circuit described above at M 5 \.

The bandgap reference circuit is fabricated in a standard O.7f.lm CMOS process
having high-ohmic polysilicon resistors and high-density linear capacitors. A chip
micrograph is shown in figure 3-14. The total chip measures 1500f.lm x 11 OOf.l m.
Active area is lOOOf.lm x 600f.lm, of which 25% is occupied by capacitors and
10% by high-accuracy resistors. All circuitry is on the chip except for the
oscillator.
The measurement results of nine samples of the circuit without curvature

correction are shown in figure 3-15. The same measurements, but now with
curvature correction are shown in figure 3-16. The standard deviation at 45°C is
1.1 m V. This is in very good accordance with table 3-1 on page 44 if we take into
account that the spread in Vbe within one batch is much smaller than the given
value of 2 mV.
Over the full temperature range from -40°C to + 130°C, the 3cr-spread of the
bandgap references without curvature correction is 5.6 m V. The same
measurement for the circuits with curvature correction gives a 3cr-spread of
4.7mV.

1220.--------------------------------------------.
1218 .. .. . .. ~>-----'-'
. ".:..-
' "."""".
!G.I
1216
CI
1!!
"0 1214
>
1212 · . . ..
---_ . ... _- .. ...... __ ............ " .............. .
··· ..
.. .
· ..
1210+----.---.r_--+_---r--~r_--+_---r----.---;---~
-50 -30 -10 10 30 50 70 90 110130150

Temperature (OC)
Fig.3-15 Measurement results of nine samples without curvature

correction
1220.--------------------------------------------.
1218
l1216 .. :- ....... :. --_. _ .. :. _ .. --.. --

','
QI
en
1!!
"0 1214
>
1212
1210+----r----.---,,--~----T_--_r--~r_--~--~--__4
-50 -30 -10 10 30 50 70 90 110 130 150

Temperature (0C)
Fig. 3-16 Measurement results of 14 samples with curvature

correction

3.4 Realization
1220~--------------------------~--~----~--~----'
1218 .. :........'.
~ 1216 ~~~---':""~
"" ~
""' ~
""" §::
' ~ ...... .
CIl
. .
g)
~ . , .
........:........ :.........:...... ; ........:-
_-;
"0 1214 ..
. ' . ...
> .
..
.
.
.
.
. , ...
.., .. .
1212 . ..
.......................
1210+----r--~r_--;_--~----+---~---,----~--~--~
·50 ·30 ·10 10 30 50 70 90 110 130 150

Temperature (OC)
Fig.3-17 Measurement results of 14 samples with curvature

correction, normalized at 45°C to determine temperature
coefficients
Looking at temperature coefficients, the difference between the measurements

with and without curvature correction can become larger. Defining the
temperature coefficient as the maximum slope of the line that starts at the
reference temperature Tr at 45°C and follows the curve, we find for the nine
circuits without curvature correction a maximum of 45p.VfC or 37pprot>C, and
for the fourteen measurements with curvature correction a maximum of 28p. Vfc
or 23pprot>C. This difference is larger if we compensate for the small gain error
in the curvature correction which shifts the reference temperature to lower values.
This is clearly shown if we do a normalization of the circuit at 45°C, which is
shown in figure 3-17. If we, for example, redefine the reference temperature for
both measurements to 23°C and consider a temperature range from -40°C to
+85°C, the temperature coefficients for the measurements without correction
reduce to 24pprot>C, but for the circuits with correction to 12ppm/°C. These
values correspond to very low typical temperature coefficients of 16ppm/°C and
8pprot>C respectively.
Another conclusion that can be drawn from figure 3-17 is that the curvature is
slightly undercompensated, which indicates that further improvements can be
made by applying a stronger curvature correction. If this is done in a redesign,
temperature coefficients of typically less than 6ppm/°C can be obtained.

1 21 7~--------------------------------------------~
:> 1216
.s
QI
C>
~
g 1215
..
Q.
.. 121 4
C>
'0
r:
Ie
12 1 3 +-----~----~--~~--~----~----_+----_r----~
o 50 100 150 200 250 300 350 400

Chophigh (kHz)
Fig.3-18 Measurement results of the accuracy versus chophigh

frequency for nine samples, normalized at 10kHz
Measurements on the accuracy versus chopping frequency have also been done.
A plot of the bandgap voltage at room temperature for different values of
chophigh and choplow are shown in figure 3-18. The curves are normalized at
1216mV for chophigh is 10kHz. The ratio between chophigh and choplow is
fixed at eight. The output voltage dependency on chophigh has an average value
of -2/L V1kHz and a spread of 2.4/L V1kHz. For the nominal chophigh frequency of
50kHz this gives a worst-case 3cr-spread of approximately -500/LV or 0.04% at
room temperature. This is around 10% of the maximum spread of 0.3 %.
A list of specifications is shown in table 3-2.
3.5 Conclusions
It has been shown that the initial accuracy of CMOS bandgap references is mainly
dictated by the offset of the opamp. This offset can be removed by applying a
dynamic offset-cancellation technique. Using the nested chopper technique,
spurious signals at the output can be reduced below the noise floor, using a total
capacitor value of only 80pF.

3.5 Conclusions
Table 3-2 Specifications of PWL-corrected bandgap reference
Min Typ Max Unit
Supply voltage 2.4 3.0 5.5 V
Supply current 30 60 /lA
High chopping frequency 10 50 400 kHz
Low chopping frequency 1.25 6.25 50 kHz
Nominal voltage @27°C 1216 mV
Initial inaccuracy@27°C 0.1 0.3 %
Temperature coefficient
(-40 to +85°C) 8 16 ppm/DC
(-40 to + 130°C) 15 30
Noise (white) 1 /lVN(Hz)
Power supply regulation

(2.4-3.5V) 100 ppmN
(3.5-5.5V) 2000
Accuracy over temperature can be improved by applying a sixth-order piece-

wise-linear curvature correction technique. This technique has the advantage over
other techniques that it is easier to implement.
The measurement results show a high initial accuracy of typically 0.1 % . This is
the highest value ever reported for an uncalibrated bandgap reference. Also the
temperature drift of typically 8ppmJ°C is the best ever reported without
calibration.
After applying all the above-mentioned techniques, the dominant error in the
CMOS bandgap reference becomes the bipolar substrate transistor. The spread in
base-emitter voltage of this transistor can, however, be much smaller than in
comparable devices in bipolar technology. This work shows, therefore, that
although bandgap references are based on bipolar transistors, the better choice for
the implementation technology is CMOS.

References
[3.1] R.I. Widlar, "New developments in IC voltage regulators", IEEE Journal
of Solid-State Circuits, vol.6, pp. 2-7, Feb. 1971
[3.2] K.E. Kuijk, "A precision reference voltage source", IEEE Journal of
Solid-State Circuits, vol.8, pp. 222-26, June 1973
[3.3] YP. Tsividis and RW. Ulmer, "A CMOS voltage reference", IEEE
Journal of Solid-State Circuits, voLl3, pp. 774-778, Dec. 1978
[3.4] E.A Vittoz, "Mos transistors operated in the lateral bipolar mode and their
application in CMOS technology" IEEE Journal of Solid-State Circuits,
voLl8, pp. 273-279, June 1983
[3.5] M.G.R Degrauwe, O.N. Leuthold, E.A Vitoz, H.1. Oguey and A.
Descombes, "CMOS voltage references using lateral bipolar transistors",
IEEE Journal of Solid-State Circuits, vol.20, pp. 1151-1157, Dec. 1985
[3.6] A.-J. Annema, "Low-power bandgap references featuring DTMOST's",
IEEE Journal of Solid-State Circuits, vol.34, pp. 949-955, July 1999
[3.7] K.-M. Tham and K. Nagaraj, "A low supply voltage high PSRR voltage
reference in CMOS Process", IEEE Journal of Solid-State Circuits, vo1.30,
pp. 586-590, May 1995
[3.8] E.A Vittoz, and o. Neyroud, "A low-voltage CMOS bandgap reference",
IEEE Journal of Solid-State Circuits, voLl4, pp. 573-577, June 1979
[3.9] G. Nicollini and D. Senderowicz, "A CMOS bandgap reference for
differential signal processing", IEEE Journal of Solid-State Circuits,
vol.26, pp. 41-50, Jan. 1991
[3.10] 1. Michejda and S.K. Kim, "A precision CMOS bandgap reference", IEEE
Journal of Solid-State Circuits, voLl9, pp. 1014-1021, Dec. 1984
[3.11] M. Ferro, F. Salerno and R Castello, "A floating CMOS bandgap voltage
reference for differential applications", IEEE Journal of Solid-State
Circuits, vo1.24, pp. 690-697, June 1989
[3.12] E. Sanchez-Sinencio and AG. Andreou, "Low-voltage, low-power
integrated circuits and systems: low-voltage mixed-signal circuits",
Piscataway, ISBN 0-7803-3446-9, p.61, 1998
[3.13] G. Wang and G.C.M. Meijer, "The Temperature Characteristics of Bipolar
Transistors for CMOS Temperature Sensors", Proc. of Eurosensors XIII,
pp. 553-556, September 1999
[3.14] G.C.M. Meijer, "Thermal sensors based on transistors" Sensor and
Actuators, voLlO, pp.103-125, 1986
[3.15] C.R Palmer and R.C. Dobkin, "A curvature-corrected micropower voltage
reference", ISSCC Dig. Tech. Papers, pp.58-59, Feb. 1981

3.5 Conclusions
[3.16] G.C.M. Meijer, P.C. Schmale and K. van Zalinge, "A new curvature-
corrected bandgap reference", IEEE Journal of Solid-State Circuits,
voU7, pp. 1139-1143, Dec. 1982
[3.17] B.S. Song and P.R. Gray, "A precision curvature compensated CMOS
bandgap reference", IEEE Journal of Solid-State Circuits, vo1.18, pp.634-
643, Dec. 1983
[3.18] G.C.M. Meijer, "Integrated circuits and components for bandgap
references and temperature transducers" Ph.D.-thesis, Delft University of
Technology, Delft, The Netherlands, March 1982
[3.19] M. Gunawan, G.C.M. Meijer, J. Fonderie and J.H. Huijsing, "A curvature-
corrected low-voltage bandgap reference", IEEE Journal of Solid-State
Circuits, vol.28, pp. 667-670, June 1993
[3.20] G.A. Rincon-Mora and P.E. Allen, "A 1.1 V current-mode and piecewise-
linear curvature-corrected bandgap reference", IEEE Journal of Solid-
State Circuits, vol.33, pp. 1551-1554, Oct. 1998
[3.21] K.-J. de Langen, "Advanced Low-Voltage and High-Speed Techniques for
BiCMOS, CMOS and Bipolar Operational Amplifiers", Ph.D. Thesis,
ISBN 90-407-1846-6, Delft University Press, March 1999
[3.22] A. Bakker and J.H. Huijsing, "A CMOS chopper opamp with integrated
low-pass filter", Proc. ESSCIRC'97, Southampton, UK, September 1997,
pp. 200-203.

Design of CMOS
Smart Temperature
Sensors
This chapter discusses the various design aspects of CMOS smart temperature
sensors. It describes different kinds of analog-to-digital conversion, methods for
Kelvin-to-Celsius conversion, curvature correction and bus interfaces. Also an
electronic interface for the temperature read-out of a single remote bipolar
transistor is proposed. The design aspects that are considered most important are
high uncalibrated accuracy and low power consumption.
4.1 Introduction
The research on smart or integrated circuit temperature sensors started in the mid-
seventies and was mainly driven by the need for better interfaces. Until that time,
the market was dominated by resistance thermometers, such as the Pt-l00 and the
thermistor. The development of IC-technology gave researchers the possibility to
integrate bipolar transistor temperature sensors together with interface
electronics. Meijer describes in his Ph.D. thesis [4.1] the development of
monolithic temperature transducers with current, voltage and logic output.
The increasing level of complexity of integrated circuits in the eighties and

nineties paved the way for the addition of analog-to-digital conversion and bus
interfaces on the temperature sensor chip. The company Smartec was the first one
in 1992 to produce a temperature sensor with duty-cycle output (SMTl60) [4.2].
National Semiconductor's LM75 [4.3] was, in 1995, the first "fully" integrated
smart temperature sensor. This circuit has become the standard for smart
temperature sensors.

Design of CMOS Smart Temperature Sensors
The real breakthrough of the smart temperature sensor came in the second part of
the nineties, when Intel. decided to add thermal management to their
microprocessors and motherboards. Costs became a much more important issue.
All large chip manufacturers now have several kinds of smart temperature sensors
in their catalogue, making for a heavy competition and price erosion. The price
for an LM75 compatible circuit is already significantly below $1 in 2000.
The work described in this thesis focuses mainly on the application of electronic
thermometers in the above-mentioned microprocessor systems. The main
objective is to enhance the accuracy, to be able to reduce the costs by omitting the
need for calibration. Another important design aspect is power consumption,
because the applications for battery-supplied systems are expected to grow fast in
the near future.
4.1.1 Accuracy
The largest market for smart temperature sensors is currently found in thermal
management systems. Especially the thermal management in personal computers
yields a market of over 5 million pieces a year. The accuracy specification for this
application is 2°C in a limited temperature range from -20°C to + 100°C, and 3°C
for an extended temperature range from -40°C to +125°C. All existing
temperature sensors need at least one calibration to meet this accuracy. This
calibration can usually be done at room temperature at the wafer level test. The
long-term stability of the silicon temperature sensors is usually sufficient to keep
its specification during its lifetime.
Analysis of CMOS bandgap references that has been done in chapter 3 showed
that when applying dynamic offset-cancellation techniques and curvature
correction, it is possible to make a voltage reference with a typical uncalibrated
accuracy of 0.1 %. Taking into account that a bandgap reference has all the
necessary signals to make a smart temperature sensor (e.g. PfAT voltage and
reference voltage), it should be possible to make a temperature sensor with an
uncalibrated accuracy of better than 0.1%. Since the PfAT voltage gives a
temperature signal in Kelvin scale, 0.1 % corresponds to approximately 0.3°C
accuracy at room temperature (T=300K). For a production environment where is
calculated with 30' spreads, this indicates that a maximum inaccuracy of
approximately 1°C can be met at room temperature. Assuming that errors
introduced by the A-to-D converter can be neglected, it is theoretically possible to
make a CMOS smart temperature sensor with 1°C accuracy without calibration.
This would be a major cost breakthrough in the market for thermal management
because omitting the calibration means reduced manufacturing costs, firstly

4.1 Introduction
because no chip area is needed for EPROM or OTP (one time programmable),
secondly no additional processing steps like double poly are necessary, and
thirdly no temperature control and programming has to be done for calibration
itself.
In this chapter we will show that it is possible to approach this theoretical limit.
We will look at various aspects like A-to-D conversion, curvature correction,
Kelvin-to-Celsius conversion and we will do research on the best implementation
to meet the goal of uncalibrated 1°C accuracy.
4.1.2 Power consumption

Power consumption in smart temperature sensors has been an important issue
since the first introduction in the mid-seventies. At that time, the main reason for
reducing power consumption was self-heating. Having a thermal resistance of
lOOoCIW and drawing a few mili Amps from a 12 V supply already gives rise to a
temperature error of several degrees [4.1]. More modern sensors like the LM75
draw only a few hundreds of micro Amps from a 5 V supply, thus reducing the
power consumption below 1mWand the self-heating in the order of 0.1 °C, which
is negligible compared to the overall accuracy of 2°C.
For battery-powered systems, a power consumption of 1mW is usually not

negligible. These applications require a power consumption that approaches the
theoretical limit. An interesting question therefore is: what is the theoretical
minimal power consumption of a smart temperature sensor? This question can
only be answered if the bandwidth of the input signal and the required noise
performance are known.
The required bandwidth of a temperature sensor for application in thermal

monitoring systems is dictated by the thermal capacitance or mass of the
monitoring object, the (parasitic) heating source and the thermal resistance. For
example, in a microprocessor system the bandwidth is determined by the thermal
mass of the package, the maximum power dissipation of the microprocessor and
the worst-case thermal resistance when the fan is malfunctioning. This worst-case
approach gives maximum temperature slopes of, for example, lOoC per second.
The customer can then specify, for example, a maximum error of 2°C, giving a
required bandwidth of 5 samples/so In most applications the required bandwidth is
limited to a few samples/so
The maximum allowed noise is normally specified to be below 0.5 LSB (Least
Significant Bit). For the industry-standard LM75 the resolution is 9 bits or O.5°C,
thus giving a maximum allowed noise of O.25°C. Other sensors, like those from

Dallas Semiconductor [4.4] have resolutions up to 12 bits or 0.0625°C, which

enables the measurement of very small temperature changes.
Tuthill showed that the power consumption of a smart temperature sensor with a
bandwidth of 10 samples/s can be reduced to IJ.LW [4.5]. He made a circuit with a
successive-approximation A-to-D converter, which powers-up, does a conversion
and goes back to sleep again. Although the circuit dissipates approximately
1.25 mA from a 3 V supply, the short on-time of only 25 J.L s reduces the average
current consumption at 10 samples/s to below 0.3 J.LA.
The noise of a smart temperature sensor is almost completely determined by the

noise of the PTAT voltage generator, because this circuit has the smallest signal.
According to equation 3-1 in chapter 3, the signal from a PTAT generator with an
emitter-current density ratio of 10, is approximately 200 J.L vfc. To obtain
temperature noise below 0.25°C, the voltage noise of the read-out circuit should
therefore be less than 50J.L V. With a current consumption of the first amplifier
stage of IJ.LA, thermal noise can be kept below l00nVN(Hz). With a bandwidth
of a few Hz, it is quite easy to keep the thermal noise below 50J.L V. Even the
increased specification for the Dallas Thermometer of 0.03°C, which requires a
noise performance of less than 5 J.L V is easy to meet with a power consumption of
1J.L A. Flicker noise can be a greater problem, but this is solved using appropriate
dynamic offset-cancellation techniques, as shown in chapter 2.
The answer to the question on the theoretical minimal noise is that it is neither
determined by bandwidth nor by noise. These requirements only need less than
1 J.L W of power consumption. In practice the total power consumption wiII be
dominated by the digital interface and especially the buffers. This shifts the
challenges on power reduction to the system level, where choices are made on the
kind of data transfer. However, our goal will remain to reduce power consumption
to the J.L W level, to assure a negligible addition to the total power consumption.
4.2 Analog-to-Digital conversion

The requirements for the analog-to-digital converter in a smart temperature
sensor are quite relaxed regarding bandwidth. A bandwidth of 10 samples/s is
usually sufficient. The accuracy is somewhere between 9 and 12 bits, depending
on the application. These specifications give possibilities to choose an A-to-D
converter principle that is optimized for, for example, simplicity or robustness.
Literature shows implementations of smart temperature sensors with converters

Fout
Fig. 4-1 Principle of temperature to frequency conversion
based on successive-approximation [4.5], frequency conversion [4.6, 4.7], duty-

cycle modulation [4.2, 4.8], and sigma-delta modulation [4.3, 4.9, 4.10].
Successive approximation A-to-D converters are clearly the fastest converters

among the mentioned ones. They can do an n-bit conversion in n clock cycles,
which makes them easily achieve 10-100 ksamples/s. Their accuracy is however
limited to the matching properties of passive components on chip. Assuming a
best matching of capacitors or resistors of 0.1 %, accuracy is limited to 10 hits.
This accuracy is good enough for medium accuracy sensors like the 9-bit LM75,
but lacks possibilities to extend it to more sophisticated smart temperature
sensors. The author already mentioned in his paper [4.5] that the choice for the
successive approximation principle was not determined by the temperature
sensor, but by the necessity to use the same A-to-D converter for other higher
frequency input signals.
The other mentioned principles are all interesting for our smart temperature
sensor and will be discussed in the next paragraphs.
4.2.1 Frequency conversion

The principle of the temperature to frequency converter is shown in figure 4-1.
The circuit is a relaxation oscillator of which the frequency is determined by the
temperature-dependent input current [ptat" The circuit has two phases. In the first
phase, the capacitor C 1 is charged by lptat. When the voltage on C 1 reaches a level
equal to Vr~f plus a certain hysteresis voltage Vhyst ' the output FOUl switches to
zero. The switch S 1 is set to the sinking version of I ptat and C 1 starts to discharge.
When the voltage on C 1 is lower than Vrejminus Vhyst, Four switches again to one,
and the whole cycle starts over.

The output frequency is equal to
2Iptat
fout = Ct V;hyst (4-1)
The great advantage of this circuit is its simplicity. A simple PfAT generator, a
capacitor and a Schmitt-trigger are sufficient. The circuit also has only three
terminals (Vdd , Vss and F out )' which implies a very cheap package. The output
signal is in the frequency domain, which makes it easy to interpret by a simple
microcontroller. The signal is also quite robust to interfering signals, so it can be
easily transported over long wires. This frequency signal is a so-called "semi-
digital" signal, which means that it is digitized in amplitude, but not in time.
The great disadvantage of the circuit is its poor accuracy. The output frequency
fout is not only determined by Iptat but also by C t and V hyst. Especially C t can
have a poor absolute accuracy. Also the temperature dependencies of C t , V hyst
and the resistor R ptat which is needed to generate Iptat out of V ptat' will have a bad
influence on the accuracy of the total circuit. Also the reference oscillator, which
is used by the microcontroller needs to be taken into account.
From a designer's point of view, one can say that this circuit has a problem with
its reference. The reference of the temperature-dependent PfAT voltage V ptat is
formed by a resistor R ptat' a capacitor C 1, another voltage (Vhyst ) and an oscillator
(of the microcontroller). Most of these devices are badly matched and therefore
introduce errors.
4.2.2 Duty-cycle modulation

A method to overcome the problem with the reference is found in the duty-cycle
modulation. The principle is shown in figure 4-2. The difference compared to the
frequency converter is that the capacitor is now charged with a current I bg - Iptat
and discharged with Iptat . Another difference is that the temperature information
is now not found in the frequency but in the duty-cycle. The duty-cycle at the
output can be calculated as follows. The charge on capacitor C t at the end of each
period is always the same. That means that during exactly one period the charging
current times the charging time is equal to the discharging current times the
discharging time. This yields
Tt . I bg = T· Iptat (4-2)

:h
V(V)
[. t(5)
T1 2T
Fig. 4-2 Principle of duty-cycle modulation
where Ibg is derived from a bandgap voltage Vbg . Equation 4-2 can also be written
as
(4-3)
This type of converter is also called "charge balancing". It can be clearly seen
from equation (4-3) that the duty-cycle output is now not determined by a
capacitor or external oscillator, but only by I ptat and I bg . Also, the resistor's
absolute value, which is used to derive these currents from their corresponding
voltages, is now not important anymore, because both I ptat and I bg can be derived
by the same type of resistor.
4.2.3 Sigma-delta A-to-D conversion

In systems where only one microcontroller is used to perform different tasks, such
as in a thermal management system for pes. the microcontroller has usually not
enough time to process a duty-cycle signal during several tens or hundreds of
milli seconds. To reduce the tasks of the microcontroller, it is therefore necessary
to do a full digitalisation on the chip, instead of doing the time-discretization off-
chip in the microcontroller.
One of the problems when doing a time-discretization of a duty-cycle modulated

signal on-chip is the fact that the signal is not synchronized with the system clock.
This is disadvantageous because it can cause locking between the two oscillators
due to parasitic coupling. This will reduce the accuracy and resolution [4.9]. To
avoid this, the duty-cycle signal is synchronized with the system clock by adding
a flip-flop after the comparator. The result is shown in figure 4-3 and is called a
sigma-delta modulator. The difference compared to the duty-cycle converter is

data-out
Fig. 4-3 Principle of sigma-delta A-to-D converter
that the output signal of the Schmitt-trigger is now sampled by the clocked flip-
flop and is therefore synchronized with the system clock. For one period T, this
gives an obviously large error, because the free-running duty-cycle frequency is
not equal to the frequency of the system clock. However, this error is stored
(integrated) on the capacitor eland extracted in the next period. When a lot of
periods are taken into account, the error is averaged and becomes theoretically
zero when an infinite number of periods are taken. This strategy is called
"oversampling" and is the strength of the family of sigma-delta modulators. More
theory about sigma-delta modulators can be found in [4.11].
The pulses at the output of the flip-flop are counted for a fixed time defined by a
timer. The result is a digital word, which can be sent directly to the outside world.
One reason why this synchronization technique is usually not used in systems
where the time-discretization is done in the microcontroller is the fact that one
more communication line is necessary for a clock signal. Another reason is that
the parasitic coupling between the microcontroller oscillator and the duty-cycle
modulator is much smaller because they are not on the same substrate.
The sigma-delta modulator is the best trade-off between accuracy, simplicity and
power consumption. It has better accuracy than frequency converters or non-
integrating converters like successive-approximation and consumes less power
than duty-cycle modulators. In future, it may be worthwhile to switch to higher-
order sigma-delta converters, because this reduces sampling time. A shorter
sampling time reduces power consumption when a power-down mode is applied.
It also opens ways to increase the resolution, while still keeping the same
bandwidth.

4.3 Kelvin-to-Celsius conversion
I(norm)
Ibe+lptat
___-_...:::_-=-_-_L._=_::..._-_-_-_- _ - r - - - - - / 7 .
1.00 k-_-_-_-_-
0.95 ~ //
~ 2~tat - Ibe I / / Iptat
0.65 ---------~-----
"'",
--
I
0.35
"~": ~'" Ibe
0.05 .......- - - - ' 1 - - - - + - -__- - - -" .......... T( DC)

I ""'"
-273 -55 35 125 343
Fig. 4-4 Kelvin-to-Celsius converter principle with normalized

currents
4.3 Kelvin-to-Celsius conversion

As already discussed in chapter 3, the most accurate temperature-dependent
signal on-chip is the PTAT voltage. I~ is made by taking the difference of two
base-emitter voltages which have a different base-emitter current density. Having
a base-emitter current density ratio of p, the PfAT voltage can be written as
kT
y/Jtat = m-Inp (4-4)
q
where k is the Boltzmann's constant and q the electron charge. The factor m is
called the non-ideality factor, which is caused by base-width modulation [4.12].
This non-ideality factor is slightly process-dependent, but is quite stable between
batches of the same process. Its value is usually somewhere between 1.003 and
1.010.
As can be seen from equation (4-4), the PTAT signal is related to the temperature
in Kelvin. Because we are usually only interested in a temperature range from -
55°C to + BOoe or roughly 220K to 400K, a large part of the dynamic range is
not being used. This problem has already been encountered by Meijer [4.1, 4.8]
and was solved by subtracting a VBE signal from the basic PTAT signal.
Something similar is done in our smart temperature sensor. Figure 4-4 shows the
basic PTAT (lptat) and reference (lptat+ Ibe) signals of a smart temperature sensor.
The straightforward implementation using I ptat as input signal shows a dynamic
range usage of only 30% in a temperature range from -55°C to +125°C. By not

2lptat-lbe
Iptat + Ibe
Fig. 4-5 Kelvin-to-Celsius converter implementation in

combination with a sigma-delta modulator
using the standard Iptat signal, but a combination of 2Iptat minus I be , the dynamic
range usage can be increased to 90%.
An implementation of the Kelvin-to-Celsius converter for our sigma-delta based

thermometer is shown in figure 4-5. The output is calculated as follows. Just as in
the duty-cycle modulator in paragraph 4.2.2, the charge-balancing principle can
be applied. Defining the total number of clock cycles in one sample as M and the
number of ones as N, this yields
M·lptat+(M-N).Iptat = M·lbe+N·l be (4-5)
This can also be written as
(4-6)
The measured duty-cycle is the ratio of Nand M and equals
(4-7)
Compared to the conventional approach when only the Iptat signal is used as input
signal, the efficiency of the sigma-delta converter is increased with a factor of
three. This implies a three times smaller sampling time and a three times lower
power consumption at the cost of only one switch, an inverter and an extra ¥fAT
current source.

4.4 Curvature correction
4.4 Curvature correction

In contrast to the PfAT voltage, which is a highly linear function of temperature,
the signal related to the base-emitter voltage shows a slight non-linearity. This
non-linearity is already discussed in paragraph 3.2 and yields approximately SmV
in a temperature range from -SSoC to +12S°C. This corresponds to approximately
l.3°C.
Chapter 3 also discusses techniques to reduce the effects of this non-linearity in

bandgap references. These curvature correction techniques, that are based on
linearization of VBE or piece-wise-linear techniques, can also be applied to smart
temperature sensors, with approximately the same results.
Meijer et al describe in [4.8] a different but very elegant technique to reduce the
effects of non-linearity in their three-terminal temperature sensor. They show that
the non-linearity in a smart temperature sensor can be reduced by making the
reference signal (lptat+ lbe) slightly temperature-dependent. Introducing a factor u
which is the temperature dependence of the reference current and applying this to
our smart temperature sensor, equation (4-7) becomes
(4-8)
This equation shows that by applying a slight first-order temperature dependence

in the denominator, quadratic and higher-order components appear at the output.
The quadratic component can be used to compensate the curvature. The higher-
order components can be neglected for small values of u. In practice, values for u
around 0.04 are used, which suppress third-order components by approximately
2S. Equation 4-8 also shows a linear component (uTITr ) at the output. This
component is unwanted and needs to be compensated by a slight modification of
lptat or1be· Figure 4-6 shows typical curves for this kind of curvature correction.
Meijer et al [4.8] showed that by applying this method, a reduction of the

curvature can be achieved by a factor of approximately S.

2.0 .r---:--- - ; -----;------:------:--- -- - -- ---,
1.5 ·
1.0 . . ........... ; . . .
0-
...
~
g
w
0.5 '
(b)
0.0 · .
-0 .5 ..~--:---:---.;.----;--.......:.--.,__-__:_-____:_------.l
-75 -50 -25 o 25 50 75 100 125 150
Temperature (0C)
Fig. 4-6 Non-linearity error of smart temperature sensor before (a)

and after (b) correction by means of non-constant
reference current
4.5 Single transistor temperature sensors

Until now, the PfAT signal, which is used as the temperature signal, is derived
from the difference of the base-emitter voltages of two separate transistors. It is,
however, also possible to use only one transistor and multiplex the measurements
in time. This has the advantage that no problems can arise with possible mismatch
between the bipolar transistors, because for both measurements the same
transistor is used. This advantage is however quite small, because the error due to
this mismatch is relatively small (typically lOOIL V or O.5°C) compared to errors
due to amplifier offset and resistor mismatch. Table 3-1 in paragraph 3.3.1 shows
that the error in the bandgap reference is already much greater. The disadvantages
are obviously higher complexity which yields more chip area and higher power
consumption.
A much more important reason to study single transistor temperature sensors is

the situation when the transistor or p-n junction is on a different substrate. This is,
for a very important example, the case in many microprocessors. Because the
processes in which they are made are fully optimized for digital design and are

4.5 Single transistor temperature sensors
Temperature
J1 Processor measurement
chip ;t--+-,tI-----t'~ chip
Fig. 4-7 Principle of remote microprocessor temperature sensing
Fig. 4-8 PTAT-voltage generation by means ofSC-amplifier
updated very often, it is almost impossible to design a temperature sensor circuit

on the same substrate as the processor itself. To still be able to measure the real
temperature of the silicon itself and not of the package, the microprocessor
suppliers incorporate a single transistor on the microprocessor die. This single
transistor temperature sensor is then read out by an external temperature
measurement chip. The principle is shown in figure 4-7.
A straightforward way to generate the desired ¥fAT signal out of the

microprocessor transistor is by a regular switched-capacitor technique. The
principle is shown in figure 4-8. In the first phase, when <1>1 is high, the voltage on
C2 is reset and the voltage on C I is set to the base-emitter voltage of QI' which is
biased at the sum of the currents I I and lz. In the second phase, when <1>2 is high,
the base-emitter voltage of QI is lowered, because it is now biased only by II. The
corresponding charge difference on C I is dumped on C2 and sampled on C 3. The
output voltage Vptat is equal to the voltage on C3 and yields
(4-9)
This circuit has some potential drawbacks. First is the effect of the offset of
amplifier A I. This offset is sampled on C I during <1>1 and appears amplified at the
output. Because our input signal has a sensitivity of only 200p.Vf!C, this offset
can cause errors of several degrees Celsius. This offset can however be removed

Fig. 4-9 PTAT-voltage generator with offset cancellation and

improved interference suppression
by an autozeroing or double-correlated sampling technique as described in
chapter 2.
Another, more fundamental, drawback of this circuit is its sensItIvIty to

interference. Transistor QI is situated on a microprocessor chip with high clock
frequencies and steep edges. Spikes on base and emitter can appear of several
hundreds of mili Volts. To reduce their influence, the temperature measurement
chip should integrate the input signal. This is not done in the circuit of figure 4-8
where the whole bandwidth is sampled on C I.
An improvement of the circuit of figure 4-8 is shown in figure 4-9. In the first
phase CPI, the base-emitter voltage of QI for the bias current II is sampled on C I
together with the offset of transconductance amplifier gml. In the second phase
<P2' the base-emitter voltage of QI is raised by the PTAT voltage. This voltage
difference is amplified by gml in combination with R2 and sampled on C3 . The
output voltage yields
(4-10)
Advantages of this circuit over the regular SC-implementation is that the offset is
auto-zeroed and that the interference rejection is much better. The latter is
achieved by low-pass filtering in the autozeroing phase (<PI) by means of R4 and
C I and in the amplification phase (<P2) by R3 and C2.
The interference suppression is maximal when the filter time constants are chosen
as large as possible. In practical realizations, as will be shown in chapter 5, in

4.6 Bus interfaces
terms of chip area it is better to implement those large time-constants in the

digital domain, by using a combination of a comparator, counter and D-to-A-
converter instead of a capacitor which is basically an analog storage device.
4.6 Bus interfaces

One of the questions after digitization of the temperature signal is how to
transport it to a computer or microcontroller. For more general signals, this
question has been asked and answered already many times. It has led to the
development of several bus interfaces, each one having its own specific
application or optimization. The most widely used for distances between 10 and
1000 meters are the field buses, such as Fieldbus, RS-485 and CAN-bus. They are
characterized by an elaborate transmission protocol and high data transmission
rates.
For most smart sensor systems, where the demands for distance and transmission
rates are much more relaxed, these high-level buses are too expensive in terms of
chip area and power consumption. For these applications, very basic protocols
have been developed. Examples of these are the Microwire protocol from
National Semiconductor or the IS2 bus interface from Riedijk [4.14].
One of the major problems with these low-level bus interfaces has been the
standardization. No specific protocol could gain enough market share yet to
become a real standard. At this moment, the 12C protocol from Philips, that has
been designed over twenty years ago for communication in audio and video
equipment, seems to have become the leading standard. The reason for this is not
that it is the best available protocol in technical terms, but many peripheral chips
like microprocessors and RAMs can be bought with such an interface. Also the
smart temperature sensor standard, the LM75, has an 12C interface. Another very
important reason is that all modem laptops have a System Management bus (SM-
bus), which is upwards compatible with 12C [4.13].
Based on the above-mentioned considerations, the choice for the bus interface of
our smart temperature sensor will be the SM-bus. This has the advantages that it
will be completely compatible with the standard LM75, it can be easily interfaced
by several microcontrollers, and it can be directly applied in laptops. The latter is
becoming more and more important, and thermal management in laptops is at the
moment already the most important application for smart temperature sensors.

References
[4.1] G.C.M. Meijer, "Integrated Circuits and Components for Bandgap
References and Temperature Transducers", PH.D. Thesis, Delft University
of Technology, The Netherlands, March 1982
[4.2] Smartec, "SMTl60-30 Smart Temperature Sensor", http://
www.smartec.nl. November 1999
[4.3] National Semiconductor, "LM75 - Digital Temperature Sensor and
Thermal WATCHDOG with Two-Wire Interface", http://
www.national.com. November 1999
[4.4] Dallas Semiconductor, "DS75 - Digital Thermometer and Thermostat",
http://www.dalsemi.com. November 1999
[4.5] Mike Tuthill, "A Switched-Current, Switched-Capacitor Temperature
Sensor in 0.6-llm CMOS", IEEE Journal of Solid-State Circuits, vol.33,
pp. 1117-1122, July 1998
[4.6] P. Krummenacher and H. Oguey, "Smart Temperature Sensor in CMOS
Technology", Sensors and Actuators, A21-A23, pp.636-638, 1990
[4.7] D. van Maaren, J. Klijn and G.CM. Meijer, "An Integrated Micropower
Low-Voltage Temperature-Controlled Oscillator", IEEE Journal of Solid-
State Circuits, voLl7, pp. 1197-1201, 1982
[4.8] G.C.M. Meijer, R. van Gelder, V. Nooder, 1. van Drecht and H. Kerkvliet,
"A Three-Terminal Integrated Temperature Transducer with
Microcomputer Interfacing", Sensors and Actuators, A-18, pp.195-206,
1989
[4.9] FR. Riedijk and J.H. Huijsing, "An Integrated Absolute Temperature
Sensor with Sigma-Delta A-D Conversion" Sensors and Actuators, A-34,
pp.249-256, 1992
[4.10] A. Bakker and J.H. Huijsing, "Micropower CMOS Temperature Sensor
with Digital Output", IEEE Journal of Solid-State Circuits, vol.31, pp.
933-937, July 1996
[4.11] S.R. Norsworthy, R. Schreier and G.C Ternes, "Delta-Sigma Data
Converters", IEEE Press, ISBN 0-7803-1045-4,1997
[4.12] G.CM. Meijer and K. Vingerling, "Measurement of the Temperature
Dependence of the IC(VBE) Characteristics of Integrated Bipolar
Transistors", IEEE Journal of Solid-State Circuits, vol.l5, pp. 237-240,
April 1980
[4.13] Smart Battery System-Implementers Forum, "Smart Battery System
Specification", http://www.sbs-forum.org, rev.l.l, December 11,1998
[4.14] FR. Riedijk, "Integrated Smart Sensors with Digital Bus Interface", PH.D.
Thesis, Delft University of Technology, The Netherlands, November 1993

Realizations of
CMOS Smart
Temperature
Sensors
This chapter describes the realizations of three different CMOS smart temperature
sensors that have been designed in the past five years. The first realization finds
its application in a tyre monitoring system, where it watches the temperature of
the tyre and compensates thermal cross-sensitivities of a pressure sensor. The
second realization is a general-purpose ambient temperature sensor, where special
attention has been paid to high uncalibrated accuracy. The last version can
measure the temperature of a remote bipolar transistor and has its application in
microprocessor thermal management.
5.1 Tyre monitoring system
5.1.1 Motivation
A tyre monitoring system has been desired by transportation companies for
several years. The reasons for that are quite clear. Independent investigations
show that more than half of all road vehicles have under-inflated tyres. Under
pressures of only 0.2 bar result in a significant increase in fuel consumption and
decrease of tyre life-time. Furthermore, safety is increased when tyres are at the
correct pressure.

Realizations of CMOS Smart Temperature Sensors
--_.--------------------------------------,,
ASIC
Tyre ! 3V Battery
------------------------------------------~
-----------------------------------~
: !12V Battery! :
Fig. 5-1 Principle of the tyre monitoring system
At this time, many companies already offer a tyre monitoring system. Such
systems consist of pressure and temperature sensors within the different tyres and
a display in the cockpit of the vehicle. Data transmission between sensors and
display is done by radio signals. The frequency of these radio signals lies in the
reserved "low-power devices" bands on 434MHz, 869MHz or 2.456GHz, which
are the same frequencies used for cordless phones, baby phones and garage
openers [5.I].The principle of the tyre monitoring system is shown in figure 5-1.
Within all the tyres of the vehicle, which can be a car or a truck, a module is
connected that consists of a pressure sensor, an ASIC (Application-Specific
Integrated Circuit) containing a smart temperature sensor, a microcontroller, a
transmitter, an antenna and a power supplying device, usually a battery. The
ASIC has several functions. It can read out the pressure sensor and perform an
analog-to-digital conversion of the pressure signal. It can also generate a digital
code from its integrated smart temperature sensor. These two digital codes are
sent to a microcontroller by the digital interface. The microcontroller analyses the
results and sends it via a transmitter to the receiver unit in the cockpit of the
vehicle. The receiver unit transports the signal further to another microcontroller,

which drives the display in the cockpit and can sound an alarm bell in emergency
cases.
One of the major problems in these systems is the supply of power to the sensors
in the tyre. Batteries seem to be the most straightforward choice, but they should
be very small to avoid imbalances in the wheel. However, the batteries should
have enough energy to assure the specified life-time. This life-time should be at
least equal to the life-time of the tyre to avoid extra maintenance. In practical
situations, this can be up to a few years. This trade-off requires extremely low-
power circuitry for the sensor systems within the tyre.
Another possibility to supply power to the sensors is by electromagnetic

radiation. This principle is also used for non-contact read-out of ID cards or
transponders. Although this principle is feasible, it would be too costly for
application in a low-cost market such as the automotive industry.
The need for temperature information from the tyre may not be clear at first sight.
Still, almost all tyre monitoring systems measure temperature besides pressure.
The reason for this is that the temperature of the tyre can give a lot of extra
information. For example, on a cold winter day, when starting your engine the
tyre temperature can be -10°C. After driving a quarter of an hour your tyres easily
warm up to +40o C. During this warming-up, the pressure in your tyre will
increase by approximately 50/300 or 16%. A 16% under-inflation normally
sounds alarm bells, but at temperatures below zero, this can be quite normal.
Another reason for needing the temperature information is to be able to

compensate for the pressure sensor's temperature dependence. Especially low-
cost pressure sensors (automotive!) can have large thermal cross sensitivities. If
this sensitivity can be compensated for, the price for the pressure sensor can be
much lower.
A final reason for needing the temperature information is in cases where the
pressure sensor is broken or out of specification. When a tyre is under-inflated or
punctured, it will become hotter than usual. This information can warn the driver,
even when the pressure sensor transmits a normal condition.
The project to make a tyre monitoring system started in early 1994 and was
supported by the European Committee. Several companies were asked to
participate because of the multi-disciplinary character. Delft university was asked
to develop the integrated temperature sensor because of their experience in this
area. The pressure sensor interface has been developed by CSEM in Switzerland.
Results have been published by both TU Delft [5.3] and CSEM [5.4].

Table 5-1 Target specifications for the tyre temperature sensor
Minimal Typical Maximal Unit
Average supply current

3 /LA
(3V, 2 samples/s)
Temperature range -40 130 °c

Inaccuracy ±l °c
Bandwidth 2 samples/s
Resolution 8 bits
5.1.2 Specification
As already discussed in the previous paragraph, one of the major issues of the tyre
monitoring system is the power consumption. After discussions with battery
suppliers, it was found that for the maximum allowed size and weight, the
(lithium) battery has an energy content of approximately 2Ah at 3 Volt. This
indicates that for a minimal system life-time of six years (which is the maximum
life-time of a tyre), the maximum average current consumption of the whole tyre
monitoring system should be below 2Ahl6 years times 365 days times 24 hours,
which is approximately 40IlA. This 40llA has to be divided between the pressure
sensor plus interface electronics, the integrated smart temperature sensor, the
microcontroller and the transmitter. Because the microcontroller and the
transmitter needed most of the energy, only 31lA was left for the integrated smart
temperature sensor. The bandwidth for the smart temperature sensor was set to 2
samples/s, which is expected to be enough to follow the temperature changes
within the tyre with an accuracy of 1°C. The nominal supply voltage is set to 3 V,
but the circuit should stay functional at supply voltages down to 2.4 V, which is
the minimal voltage of the battery at the end of its life-time. The temperature
range of the circuit is set from - 40°C to + l30oC. The maximum temperature of
+l30oC is not expected to occur too often (tyres are usually guaranteed to
approximately lOO°C) , but investigations on tyre temperatures showed that
temperatures up to + l300C can occur when heavy and lasting braking are needed
during mountain descents. A summary of the main specifications is shown in
table 5-1.

5.1.3 Design of the tyre temperature sensor

A-to-D conversion
One of the design issues that has not been discussed yet in the specification is the
noisy environment in cars. This noisy environment is due to the many
interference signals, especially from the engine ignition. The tyre monitoring
system should be immune to these interfering signals, which indicates the
necessity of integration of the pressure and temperature sensor signals or
averaging of multiple samples.
From a power consumption point of view, it is better to use a slow, low-power

integrating A-to-D converter, than a fast, high-power, sampling one and take the
average of multiple samples. Although. faster A-to-D converters may consume
less power for single samples [5.2], obtaining the same noise immunity will
always take more power than an integrating converter.
From the available integrating A-to-D converters, it is shown in chapter 4 that the
best choice is the first-order continuous-time sigma-delta A-D converter. Higher-
order sigma-delta A-D converters consume more power in exchange for shorter
sampling times. These shorter sampling times are however unwanted, because of
the worse interference rejection. Sampling sigma-delta A-D converters also have
less interference suppression, because of the sampling action.
Technology
The choice for the implementation technology for the ASIC has been made after
discussions with the different partners in the project. For the integrated
temperature sensor, a bipolar or BiCMOS technology would be advantageous,
because of the availability of high-performance bipolar transistors. However, a
bipolar technology was not wanted by our partner who was responsible to read
out the pressure sensor. The pressure sensor is based on a capacitive principle and
can not be read out without the availability of high-performance switches. A
BiCMOS process was not wanted by the commercial partner because it would
increase the price for the ASIC too much. A choice was therefore made to
implement the ASIC in standard CMOS.
Block diagram
The block diagram of the integrated tyre temperature sensor is shown in figure
5-2. On the left is shown the temperature sensor and reference block, which
generates the temperature-dependent current Itemp and reference current I ref for

temp temp
'
sensor L~ data-out
' ref modulator
reference
ck
aunt-en
sd-reset
power-on
ck
dav
Control
ck
Fig. 5-2 Block diagram o/the integrated tyre temperature sensor
the sigma-delta modulator. This block also generates the bias current [bias' which
is necessary to bias the different parts of the sigma-delta modulator. The bitstream
output of the sigma-delta modulator is counted during a time that is specified by
the timer. All the blocks are controlled by the control block.
At the start of each sample, the sigma-delta modulator, the counter and the timer
are reset by the signal "sd-reset". The signal "count-en" becomes high, which
enables the counter to count the number of ones in the bitstream. When the timer
says "time-up", the "count-en" signal becomes low, which disables the counting
and the "dav" signal becomes high, showing that the data at "data-out" is valid.
The control block also has the ability to power down the whole circuit. When it is
in this mode, the signals "power-on" and "dav" are low while "sd-reset" is set
high. By doing this, the analog blocks are powered down and the digital blocks
consume the least amount of power, because there are no signal transitions,
except for the clock. This power-down facility is necessary, because at this stage
of the design it is expected that it is not possible to have all the blocks functioning
at a total current consumption of less than 3 Jl. A.
The only way to meet the power consumption requirement is by reducing the
sampling time and switching off the complete circuit between the samples.
However, making the sampling time too short will result in worse interference

rejection. Therefore, the sampling time should be taken as large as possible, but
small enough to have an average supply current of 3p.A. The exact sampling time
and ratio between power-off and power-on time will be decided at the end of the
design track.
The temperature dependent current ltemp and the reference current lrefwill both be
derived from a current that is PfAT (Proportional To Absolute Temperature) and a
current that is proportional to the base-emitter voltage of a substrate bipolar
transistor. Of those two, the PfAT current needs special attention because it is
derived from a very small PfAT voltage, which has a temperature coefficient of
typically 200p. VfC. To be able to reduce inaccuracies due to offsets or mismatch
by dynamic offset-cancellation techniques (see chapter 2), a clock signal is also
fed to the "temperature sensor and reference" block.
Calibration
It is expected that the integrated temperature sensor has to be calibrated to meet
the accuracy specification of ±1 °c over the whole temperature range from -40°C
to + 130°C. This calibration can be performed by laser trimming, programmable
fuses or E(E)PROM. Another possibility is to do the calibration in the
microcontroller's E(E)PROM. This has the advantage that the technology to
implement the ASIC does not need to have facilities for the above-mentioned on-
chip calibration techniques. A disadvantage is that the software engineer who
writes the program for the microcontroller has to deal with calibration figures
from the temperature sensor. This may complicate the high-volume production,
because each microcontroller E(E)PROM should be programmed with different
temperature calibration figures. However, because the pressure sensor interface
also had to be calibrated for mismatches between the different pressure
sensors [5.4], it was already impossible to calibrate the ASIC without a pressure
sensor. Therefore, the decision has been made to calibrate both the temperature
sensor and the pressure sensor interface in the microcontroller. This implies that
in the design of the temperature sensor no attention will be paid to calibration.
5.1.4 Detailed design of the tyre temperature sensor

Low-power, high-accuracy PTAT current generator
The schematic of the low-power high-accuracy PfAT current generator is shown
in figure 5-3. Cascodes are not shown because of simplicity, but are present at
each PMOS transistor that is connected to Vdd and each NMOS transistor that is
connected to VSS" Compared to a conventional PfAT current generator, the
accuracy is improved by the chopping of the first amplifier stage, which is formed

CH 1
power-on
Rptat
w=2u
1=200u
Fig. 5-3 Schematic of the low-power, high-accuracy PTAT

current generator. Cascodes are omitted for simplicity.
by Mil through M 14 . The offset of both the input stage and the mirror are
modulated to the chopping frequency, which is chosen equal to the clock
frequency. The filtering of the modulated offset is partly done by the Miller
capacitor Cm' but the main filtering is done in the LLl A-to-D converter. The LLl
A-to-D converter acts as a digital low-pass filter with notches at the clock
frequency and higher harmonics (see paragraph 4.2).
The current of the PTAT generator is determined by the emitter area ratio of Q2
and QI and the resistor Rptat . For the chosen emitter area ratio of 8 this yields:
[ _1_. kT ln8 (5-1)

ptat = R
ptat q
For a nominal value of R ptat of lOOkQ, [ptat equals approximately 500nA at

T=300K. This nominal PTAT current is a trade-off between power consumption
and accuracy. The accuracy reason can be explained as follows. A nominal
current of 500nA at 300K yields a sensitivity of approximately 1.7nAflC.
Especially at temperatures above 100aC and up to l30 aC, leakage currents can
easily rise close to the nA level. Calibration of these errors is possible, but
because leakage currents can change greatly after a certain time of operation,
major aging problems can occur.
The reason for using a two-stage amplifier is to have enough gain at the lowest
amount of power. This can be explained as follows. To have enough accuracy, it is

Rptat
100k
4
~-L __L -________________________L -____ ~ ______ ~ __ Vss
~
Fig.5-4 Simplified schematic of the circuit generating [temp' [ref

and [bias'
necessary to have a gain within the loop of at least a factor of 50. Higher is not
really necessary, because only offsets and mismatches need to be compensated.
To obtain a voltage gain of 50 with only one stage and an output resistor Rptat of
lOOkQ, would require a gm of 500IlAlV This would require a drain-current, even
in weak inversion, of at least 20IlA. which is far above our available budget. Our
two-stage amplifier with long input transistors Mil and M12 and cascodes on all
the mirrors has a voltage gain at room temperature of approximately 200. The
total current consumption is only 3/LA, which we believe is the lowest possible
power consumption for the required accuracy.
The power-down circuit requires special attention. If the signal power-on is high,
a narrow and long transistor M32 is switched on, resulting in a very small current
through the transistors M22 to M 26 . This is enough to start up the circuit. When
power-on is switched to low again, M3J is switched on, forcing the gates of M22 to
M 26 to V dd , resulting in a power-down of the circuit. Although not shown in
figure 5-3 for simplicity, the current supplied by M32 is switched off after a few
clock pulses to increase the accuracy. Also the start-up behaviour of the cascodes,
which is not shown nor explained here, needs special attention.
Generation of Itemp' Irefand Ibias

A simplified schematic of the circuit that generates the currents [temp' [ref and [bias
is shown in figure 5-4. On the left the PfAT current generator can be

"temp
Fig. 5-5 Schematic o/the.ELi modulator
distinguished. In the centre of the figure. the base-emitter voltage of Q2 is

transformed into a current by means of A 2 • M 20 and Rbe. The value of this current
is at room temperature approximately IJ-tA. which is a trade-off between power
consumption and chip area of the resistor Rbe- The lbe current is divided by four
and split into two parts by the current mirrors formed by M 21 • M22 and M 23 . The
left part of this current is added to a PfAT current generated by M 14 • which is half
the nominal PfAT current of 500nA. The sum of these two currents forms the
reference current 1ref. which is independent of temperature (if we do not take into
account the temperature dependencies of the resistors R ptat and Rbe)· Itemp is
formed by a PfAT current that is 0.75 times the nominallptat current minus the
right part of the lbe current from transistor M 23 . The bias current lbias is exactly
equal to the nominal PfAT current lptat. The reason for choosing a temperature
signal current ltemp as the difference between a certain amount of lptat and lbe is to
be able to fully use the dynamic range of the LLl modulator. This so-called
Kelvin-to-Celsius conversion technique is explained in paragraph 4.3.
The total power consumption of this circuit is kept as low as possible and yields
approximately 7J-t A.
Sigma-Delta modulator
The schematic of the LLl modulator is shown in figure 5-5. The bitstream output
of the modulator is given by
= 1.5lptat -lbe
bitstream (5-2)
lptat+lbe

The currents l temp and I rej are chosen in such a way that at the low end of the
temperature range, which is -40°C, this ratio is 0.1 and at the high end, which is
+ 130°C, the ratio is 0.9. The margins of around 10% at each corner are necessary
to be able to perform the calibration. The choice for the size of the integrating
capacitor C1 of 60pF is a trade-off between chip area and accuracy. The larger the
capacitance, the smaller the problems with charge injection from switch S I. A
large capacitance also offers lower possible clock frequencies. This is
advantageous because this implies that the frequency of the chopper amplifier in
the PTAT-current generator can also be lower. This results in better accuracy in
the chopper amplifier, because the residual error due to chopping is linearly
dependent on the chopping frequency. The clock frequency has been chosen
16kHz. This frequency can be easily derived from a low-cost 32kHz-watch
crystal. With a required resolution of 8 bits, this clock frequency implies a
maximum sampling speed of l6kHzl28, which is approximately equal to 60
samples/so
The reference voltage V rej is set to 1.2 V to be sure that both current sources I ref
and I temp have their cascodes working in the saturation domain, where they have
the highest possible output impedance. At the start of each sample the integrator
is reset by Sz to assure that the initial voltage at the beginning of each sample is
the same.
The power consumption of the complete LA modulator block is approximately

equal tolOJlA. Together with the temperature sensor and current reference block,
this yields 17 Il A. Adding a few micro Amps for the digital part, the total power
consumption of the circuit should be around 20llA at continuous operation at 60
samples/so For the required sampling rate of 2 samples/s this can theoretically be
reduced to less than lilA. This will, however, not be met in practice because of
the leakage currents that can be up to a few micro Amps.
Layout
The ASIC containing the circuitry for the tyre temperature sensor and the read-
out of the pressure sensor is implemented in a 2Jlm standard CMOS process. A
micrograph is shown in figure 5-6. Special attention has been paid to the
matching of transistors and resistors in the circuit that generates the temperature
and reference currents. The total chip measures l2mmz of which 25% is occupied
by digital cells. The analog part of the tyre temperature sensor is marked with a
white rectangle and measures 1.5mmz. Around 20% of this area is occupied by
the resistors Rbe and R ptat of 640k and lOOk resp. The integrating capacitor C 1 in
the LA modulator of 60pF occupies approximately 10% of the chip area.

Fig. 5-6 Micrograph of the integrated circuit for the tyre

monitoring system. The white rectangle shows the analog
part of the tyre temperature sensor.
To reduce costs, the circuit has afterwards also been implemented in a 0.7/Lm
CMOS process, with a reduced chip area of 5mm2 . The measurements did not
show significant differences and will therefore not be discussed here.

The chip has been encapsulated in a ceramic IC package and has been exposed to
temperatures in the range from -40°C to +120°C. The circuit showed full
functionality for supply voltages between 2.2V and 5.0V. The total current
consumption at continuous operation is 25/LA. At stand-by, the current
consumption drops to 2/LA. For the nominal sampling rate of 2 samples/s the
current consumption is 3/LA, which exactly meets our target specification. The
full specifications are listed in table 5-2.
Three samples have been measured more elaborately to analyse the temperature
inaccuracies over the temperature range. The results of the uncalibrated parts are
shown in figure 5-7. These samples show an error of ±5°C at room temperature
and ± 7°C over the full temperature range. To achieve the specified accuracy of
± 1°C over the full temperature range, the circuit has to be calibrated at lea9t two
temperatures. The results for a proposed calibration at -20°C and +lOOoC are
shown in figure 5-8.

Table 5-2 Specifications of the measured tyre temperature

sensor
Supply current
3
Nominal (3 V. 2 samples/s) p.A
25
During sample
Inaccuracy (2 calibrations) ±1 °c
Bandwidth 50 samples/s
Resolution 8 bits
Clock frequency 25 40 kHz
Power supply regulation 0.1 °CIV
Noise 0.1 °c

4.-----------------------------------------~
2 ........... "','. " .... .
o .. ..
................. .... .........:- ........ :......... "
· ..
·· .
u -2
~
• chip 1
.... • chip 2
e.... • chip 3
w -4 .... -..... - .............
. .
-6
. .
• • • • • • • • • • • '0"' ••••••••••••• _ ~
-8+----+----~---+----~---T----~---T--~
-40 -20 o 20 40 60 80 100 120
Temperature (OC)
Fig. 5-7 Temperature errors of three samples before calibration
.. . ... :- ........ ..... - .. ·........ -;... .

o.S
.
~
.
·
~
..
··· ..
·· ...
0
U • chip 1
'L.
e
w -O.S
• chip 2
• chip 3
-1 :
-1.S -f------i------r-------.------r------r------i-------i------l
-40 -20 o 20 40 60 80 100 120
Temperature (0C)
Fig. 5-8 Temperature errors after calibration at -2(/'C and + ]()(f'C

5.2 High-accuracy temperature sensor
Table 5-3 Manufacturing costs of smart temperature sensors

per piece
Description Cost
Design 1O¢
Processing 30¢
Test 15¢
Sawing/Bonding/Packaging 25¢
Calibration 20¢
Total $1.00
5.2.1 Motivation
One of the major issues in the tyre monitoring system project was the size of the
battery. This implied that the most important specification of the tyre monitoring
system was the extreme low power consumption. We succeeded in that by
reducing the amount of circuitry to the minimum, at the cost of a very simple
digital interface and medium uncalibrated temperature accuracy. The market for
tyre temperature sensors is however quite small. The largest markets at this
moment are found in thermal management applications, like personal computers
and domestic appliances. In these kinds of applications, power consumption is not
one of the most important issues. The magic word here is low-cost: How can I
make my device cheaper than that of my competitor?
Although the author does not pretend to have much experience in sales, a short
overview of the costs of smart temperature sensor manufacturing is considered
useful here. In this overview, which is shown in table 5-3, it is assumed that the
average sales are over I million per year. The calculation is also based on a lK+
selling price of $1, which is quite arbritrary, but reasonably matches the current
price of an LM75 equivalent. The costs have been divided into five parts. In the
next paragraphs the possibility of reducing costs related to each of these five parts
is discussed.

Design
The design costs are built up of costs related to the complete design process,
varying from salaries of design engineers to processing of first silicon and writing
the datasheets. These investment costs can be rather high and are estimated to be
somewhere between $500,000 and $1,000,000. However, divided by the total
expected sales of over 10 million pieces, the costs per piece can still be kept
below 10¢. The costs for design are quite hard to reduce. A simple design can,
however, reduce the risks and the additional costs of a redesign.
Processing
The processing costs for large volume production are mainly dictated by the size
of the chip and the complexity of the process, i.e. the number of processing steps.
The cheapest available process that can fulfil the specifications of a general smart
temperature sensor is obviously CMOS. The standard CMOS process, however,
may need to be extended with options for high-density capacitors, thin-film
resistors or calibration facilities like E(E)PROM or OTP (One Time PROM). The
choice for these extensions is usually a trade-off between costs and performance.
It is a challenge for the designer to reduce the processing costs by meeting the
specifications without the need for process extensions and without increasing the
chip size significantly.
Test
The costs for testing are almost fully dictated by the testing time. The testing time
can be reduced by adding special test features in the chip. However, these
additions should not increase the chip size too much.
Sawing/Bonding/Packaging
The cost for sawing, bonding and packaging are mainly dictated by the number of
pins of the chip. The number of pins is usually dictated by the customer or by
competitors and can therefore hardly be optimized.
Calibration
The costs for calibration depend mainly on the time the chip is in the tester. Time
is needed to assure temperature stability, to obtain the temperature information
and to do the programming. These costs can offcourse be removed if the sensor
has the desired accuracy without calibration. However, this seems hardly feasible
because datasheets from the different suppliers show that all currently available
smart temperature sensors need to be calibrated to meet the accuracy
specification.

Table 5-4 Specifications of the high-accuracy temperature

sensor
Su£ply current
I C inactive 250
12C active 1000 /LA
Shutdown mode I
Inaccuracy
TA=-25°C to +IOOoC ±2.0 °c
TA=-55°C to +125°C ±3.0
Conversion time 100 ms
Resolution 9 bits
0.5 °c
The conclusion from the above-mentioned discussion is that the costs can be
reduced by using a standard CMOS process, by minimizing the chip size and by
increasing the accuracy to be able to omit the calibration. If we succeed in
removing the need for calibration, around 20% of the costs can be directly
reduced from the calibration phase, according to table 5-3. Moreover, the
processing costs will be further reduced because of less chip area and less
processing steps. Adding this, it can be expected that the total manufacturing
costs can be reduced by approximately 25%.
The next paragraphs will describe a smart temperature sensor which is optimized
for high accuracy before calibration. The project has been done in cooperation
with Philips Semiconductors in Sunnyvale, California.
5.2.2 Specification
The specifications of our smart temperature sensor follow those of the industry-
standard LM75 from National Semiconductor [5.5]. These are listed in table 5-4.
The most challenging on this specification is, as already mentioned, to meet the
temperature accuracy without any calibration. National specifies a temperature

._---.----~~._---r--_.--------~----_.--~----~~d
Rptat
lOOk
4
~~~------------------------~----~--------~~.
Ifss
Fig. 5-9 Copy of the part of the tyre temperature sensor that
generates I temp and Irefto explore the sources of error.
inaccuracy of ±2°C in a limited range from -25°C to +lOOoC and ±3°C in the
total specified range from -55°C until +125°C. The major question for us is: Is it
possible to meet this accuracy specification without the need for trimming?
Expected accuracy before trimming

To estimate the uncalibrated accuracy of our smart temperature sensor, the most
important sources of error should be explored and modelled. If we consider the
circuit structure of the tyre temperature sensor, we can assume that all dominant
errors are made before the LA modulator. This is highly feasible, because the LA
modulator is known for its very high linearity which implies that resolutions up to
9 bits can be achieved without any problem. The major errors will therefore be
generated in the circuit generating I temp and I ref" This part of the circuit of the tyre
monitoring system is shown again in figure 5-9, together with the most important
sources of error. A list of these errors and their contributions are shown in table
5-5. The calculation of the contributions of the different error sources is not so
straightforward. For example, to calculate the error due to mismatch between M 12
and M I4 , one should know the transfer function between Iptat and the output
digital code. For the circuit of figure 5-9, the output is given by:
l temp = 1.5Iptat-Ibe
Tempdata (5-3)
I ref I ptat + Ibe

5.2 High-accuracy temperature sensor.
Table 5-5 Typical errors in tyre temperature sensor according to

figure 5-9
Kind of error
Typical Error contribution
value for typical value
Description Symbol
Offset Q1 and Q2 cr(Vos.Q) O.lmV 0.25°C
Mismatch M 12 , Ml1 cr(MI\2,l1) 1.0% 1.3°C
Mismatch M\2, M14 cr(M1 12,14) 1.0% 0.3°C
Mismatch M \2, M 15 cr(Ml I2 ,15) 1.0% 1.8OC
Mismatch M 32 , M31 cr(M132,31) 1.0% 1.8OC
Mismatch M 21 , M22 cr(M121 ,22) 1.0% 0.3°C
Mismatch M 21 , M 23 cr(Ml21 ,23) 1.0% I.ZOC
OffsetA 2 cr(Vos.A2) 1.0mV 0.25°C
Spread absolute value Rplat cr(MsJt) 4.0% O.25OC
Mismatch Rptat' Rbe cr(Mpt..,.be) 0.1% O.15OC
Spread absolute value V SE cr(~V.E) 2.0mV O.5OC
Total: 3.ZOC
Errors uncorrelated. VBE = 600 mY, T = 300K
It can be clearly seen from equation (5-3) that errors in the signal [ptat change
both the numerator and the denominator. If we assume that at room temperature
[ptat and [be are approximately equal, an error of ~ in [ptat results in:
Tempdata = 1.5(1 +~) -1 (5-4)

(1 + M + 1
Due to the Kelvin-to-Celsius conversion (see paragraph 4.3), the temperature

range is limited to approximately 6OOKI2.5 which equals 240K or 24O"C. A ~ of
1% therefore yields a temperature error of 0.62* 1%*24(t>C or 1.5OC.
HIGH-ACCURACY CMOS SMAItT 'TEMPERATURE SENSORS 97

From table 5-5 it can be seen that the largest contributors to the total error of
3.2°C are the mismatches in the various current mirrors. When we cancel these
with dynamic offset-cancellation techniques, the residual error will be greatly
reduced to approximately O.7°C. For a 3-0 production bandwidth, this feasible
accuracy is around 2.1°C which comes very close to the LM75 specification,
which specifies ±2°C in a limited temperature range and ±3°C over the full
range. The major difference, however, will be that we can achieve this accuracy
without one single calibration.
The next paragraphs will describe the detailed design of the high-accuracy smart
temperature sensor.
5.2.3 Design
As was seen in the previous paragraph, the largest contributors to the error in the
tyre temperature sensor were the various current mirrors. To improve the
accuracy, we can do a chopping action on all the current mirrors. It is, however,
better to first consider the necessity of these current mirrors and find out if we can
omit some of them. If we look in detail, we can see from table 5-5 that the largest
contributors to the error are the mismatches between M12 and MIS and between
M32 and M31 . The reason for this is that these current mirrors transport the Iptat
signal, which is the most important temperature signal. The need for these current
mirrors is explained by the fact that firstly the LL\ modulator needs both a
sourcing and a sinking current to achieve a charge balance and, secondly, that the
Iptat signal is needed both as a sourcing and a sinking current because it appears as
a positive signal, both in the numerator and the denominator of the tempdata
output. I
The conclusion of the above-mentioned reasoning is that the accuracy of the

smart temperature sensor can be much improved if it is possible to 1) make a LL\
modulator which only needs a sourcing Ibe and a sinking I ptat and, 2) make a high-
accuracy sinking PfAT-current generator without mirrors in the signal path .
.L1 modulator with sourcing Ibe and sinking Iptat

A trick to move the I ptat current source from the sourcing side to the sinking side
of the LL\ modulator is to use a switch with an inverted bitstream signal. This
principle is shown in figure 5-10. When the switch Sl in figure 5-10 (a) is closed,
1 The signal lbe is only needed as a sourcing current because it appears as a negative
signal in the numerator

(a)
(b)
Fig. 5-10 Method to move the Iptat current source from the
sourcing side to the sinking side in the 1:'A modulator.
Circuits (a) and (b) both have the same output.
the sourcing lptat cancels the sinking lptat. so the net result is zero. When switch
SI is open. lptat is sinked out of C 1. The same action can however also be
achieved by using the inverse bitstream signal to control switch S I and omitting
the sourcing lptat" This is shown in figure 5-10 (b).
The implementation of the L~ modulator with only sourcing lbe current sources
and sinking lptat current sources is shown in figure 5-11 The output yields
2lptat -lbe
bitstream = - (5-5)

Fig. 5-11 1:'.1 modulator implementation which only needs sourcing

Ibe current sources and sinking Iptat current sources.
More information about the derivation of this result can be found in paragraph
4.3. Compared to the tyre temperature system, the weight of Iptat in the numerator
has been slightly increased from 1.5 to 2. This results in an improved usage of
dynamic range of the ~~ A-to-D converter. Compared to the tyre temperature
sensor, the temperature range of this new high-accuracy smart temperature sensor
is slightly reduced from 240°C to 200°C. However, this reduced temperature
range still gives enough headroom to meet the minimal range specification of the
LM75 of 180°C (-55°C to 125°C).
High-accuracy PTAT-current generator

The principle of the sinking PTAT-current generator without current mirrors is
shown in figure 5-12. The bipolar transistors QI and Q2 are biased with two bias
currents II and 12 that have a ratio of n. The emitters of QI and Q2 are kept at the
same voltage by the loop involving amplifier A I. The bases of QI and Q2
therefore have a voltage difference that is equal to kT/q*ln(n). The PTAT current
that is flowing through R2 is split into two equal parts by MI and M 2, thus
generating the two I ptat currents that are needed by the ~~ modulator.
A problem with this circuit is that the base current of Q2 also flows through the
resistor R 2, which can significantly reduce the accuracy. To compensate for this
problem, a resistor RI is added to the base of Ql> which is n times smaller than R2.
The voltage drop across this resistor due to the base current of QI exactly
compensates for this error.
The major sources of inaccuracy in this circuit are the offset of the opamp AI, the
mismatch between M 1 and M2 , and the mismatch between the bias currents 11 and

. -____________, ,____________________-o~d
L -____- L______L -__________________--o 'Iss

Fig. 5-12 PTAT-current generator principle with sinking output
without current mirrors in the signal path.
h These inaccuracies will be cancelled by a chopping technique. The choice for
the chopping frequency should at first sight be as low as possible, because the
magnitude of residual errors increase linearly with the chopping frequency (see
paragraph 2.3). The lowest possible chopping frequency equals the sampling
frequency. However, we should take care that, at that frequency, large errors in the
denominator are not completely cancelled. This can be explained as follows.
Suppose we have an error in [ptat of!!.. If we choose the chopping frequency equal
to the sampling frequency, the output of the~!!. A-to-D converter will be equal to
the average of one sample with [ptat(l +!!.) and one with [ptat(l-!!.),
(5-6)
This equation is quite hard to solve for general values of [ptat and [be' However,
for T=Trep [ptat is equal to [be' Equation 5-6 is then reduced to
. 1{ -
Bltstream=- 1 +-
2!!.+1-- 2!!.}
- =-1 ----- {4 -
4!!.2} =-(1-0.75!!.2)
1 (5-7)
2 2 + !!. 2 -!!. 2 4 _!!.2 2
Equation 5-7 shows that with the lowest possible chopping frequency the errors
are approximately squared. This implies that. for example, an error of !!. of 1% is
reduced to 0.0075%, which equals approximately 0.0075%*200K is O.ol5°C. For
our specification with a maximum inaccuracy of ±2°C this can be assumed
negligible. However, errors of !!. of lO% are reduced to 0.75%, which equals
HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS lOl

approximately 0.75%*200K is 1.5°C. This latter error is definitely not negligible.

If we define that temperature errors of typically O.I°C are acceptable, only errors
in I ptat that are smaller than approximately 2.5% can be cancelled with a chopping
frequency that is equal to the sampling frequency. The question is therefore: Are
there errors in the PTAT-current generator of figure 5-12 that are larger than
2.5%? The mismatch in the bias currents II and I z will be approximately 1%. Also
the mismatch in MI and M z will not be larger than 1%. However, the offset of the
operational amplifier A I can be up to 1mV, which will, depending on the choice
of the bias current ratio n, give an error between 2 and 3 %.
The offset of the amplifier after low-frequency chopping will therefore be on the
edge of acceptable errors. Increasing the chopping frequency to the clock
frequency will completely cancel the errors, because the chopping moments will
fall between the decision moments of the comparator, so they are not "seen" by
the L~ modulator. Another advantage of increasing the chopping frequency of the
amplifier is that no special attention has to be given to minimize the offset.
Finally, the lifnoise of A I will also be reduced.
A drawback of increasing the chopping frequency is the larger residual error. This
can be up to a few hundreds of micro Volts for frequencies up to 10kHz, based on
experiences with regular chopper amplifiers. However, a residual error of 1001l V
gives a temperature error of 1 to 2°C, depending on the choice of the bias current
ratio n. A solution is therefore found in applying the nested chopper technique as
explained in paragraph 2.4. This results in the high-accuracy PTAT -current
generator with nested chopper amplifier as shown in figure 5-13. The amplifier is
split into three parts. The first part A I is chopped at the clock frequency which is
called in this figure chophigh. The second one A z is chopped together with the
first one A I at the sampling frequency, which is called choplow. The third part of
the amplifier, A 3 , has no amplification but serves only to make the output single-
ended. The output transistors M I and M z are chopped by CH6 . The bipolar
transistors QI and Qz are also chopped by Sz and S3·
The ratio n of the bias currents is chosen three. This eases the Dynamic Element
Matching because this can now be done in four phases, needing two control
signals. These signals are already available as choplow and chophigh. If we
would have chosen a bias current ratio n of for example seven, we would have
needed at least eight phases and three control signals to dynamically match these
currents.

Fig. 5-13 High-accuracy PTAT-current generator with nested

chopper amplifier.
High-accuracy [be generator

The errors of the [be generator are all smaller than 1%. This implies that all
mismatches can be chopped at the low sampling frequency and no nested chopper
technique is necessary. The implementation is shown in figure 5-14. The VBE
voltage at the input of the generator is made by a bias current [bias and a bipolar
transistor. This bias current is derived from a bias circuit and has an accuracy that
is approximately equal to the spread in sheet resistance, which is assumed to be
approximately 4%. According to table 5-5, this equals an inaccuracy of O.25°C.
The current mirror formed by M31 and M32 is chopped by CH3. The current
splitter formed by M21 and M22 is chopped by CH4. All the choppers are
controlled by the low frequency sampling signal choplow.
[2C bus interface

The I2C bus interface is completely designed by Philips. Specifications for this
interface can be found in [5.6].

r-------------------,----------.~--_.~--~~d
+
\biasp
,Ibias
500n
~-L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ L_ _ _ _
'Iss
~
Fig.5-l4 High-accuracy [be generator
Control
The control block is comparable to the tyre temperature sensor as compared to
handling of the power down. It has some additional features like over-temperature
and under-temperature watchdogs that are listed in the LM75 specification.
Layout
A micrograph of the layout is shown in figure 5-15. The circuit is made in a
standard 0.71lm CMOS process. Next to the high-accuracy temperature sensor, an
interface for an external bipolar temperature sensor has also been integrated. This
interface will be described in paragraph 5.3. The total chip size is 4.5mm2 of
which approximately 50% is occupied by digital circuitry. The analog building
blocks for the high-accuracy temperature sensor are marked by a white rectangle
and occupy approximately 0.7mm2. A stand-alone version with LM75
specifications is expected to have a chip size of 2mm 2.

Fig. 5-15 Micrograph o/the high-accuracy temperature sensor chip

The chip has been encapsulated in a standard plastic IC package and has been
exposed to temperatures in the range from -60°C to + 130°C. The circuit shows
full functionality for supply voltages between 2.9V and 5.5V
We tested 24 samples of the circuit from one batch over a temperature range from
-40°C to + 120°C. The results are shown in figure 5-16. All circuits are within
±1°C in a temperature range from -40°C to +80°C. The typical spread at room
temperature is ±O.4°C. Based on the error analysis from the tyre temperature
sensor on page 96, we expected ±O.7°C between batches. The largest error,
however, is the spread in VBE which is definitely much lower within one batch.
Until now, several hundreds of chips have been tested from different batches.
Errors were all within ±1°C at room temperature. This proves that it is possible to
make a smart CMOS temperature sensor with a 3-0 uncalibrated accuracy at
room temperature of better than ±2°C.
From the results shown in figure 5-16, it can also be seen that the LM75
specification of an accuracy of ±2°C in a limited temperature range from -25°C to
+ 100°C is met for these 24 samples. However, if we take into account the full 3-0
production bandwidth, this is not completely sure. We solved this problem by
doing a curvature correction in a subsequent version that is currently being
processed. This curvature correction will lower the high-temperature curves with

3.0 ~--:---------:-----:----:-----------,
2.0 ... . ........ . .......... . ...........:. ...... - .

. .· .
~ ~ ~
..
···
·
...
1.0 .......... ;. .... . . .. . .......... ;.......... .:.......... -:.. . ... - .
~
..e
6'
'a...
~ii~liii~;;.~. ~.~.~. !. ~.i.~.~. ii.iiiiii.~~~

0.0
aU
-10
. .. .................. ..
· .
-2.0 +---....------.-----.---"""T""---.---T---....-----l
-40 -20 o 20 40 60 80 100 120
Temperature (0C)
Fig.5-16 Temperature errors 0/24 samples without calibration.
approximately 1°C. With this new version the LM75 specification will be
completely met, without any calibration.
A summary of the measured specifications is listed in table 5-6.
The results of this work are published in [5.7].
5.3 Remote microprocessor temperature sensor
5.3.1 Motivation
One of the most important issues in laptop design is the thermal management.
Laptops are optimized for small size and low-weight. This implies that only a
minimum of heat sink mass will be used to cool high-power dissipating parts like
the microprocessor. To still maintain a high reliability, modern laptops have
variable microprocessor clock speeds. In situations where the microprocessor is
in danger because of a too high temperature, its power dissipation is reduced by
lowering the clock frequency.

Table 5-6 Measured specifications of the high-accuracy

temperature sensor
Su:£Ply current
I C inactive 50
I 2C active 500 /LA
Shutdown mode 1
Inaccuracy
TA=-25°C to + 100°C ±2.0 °c
TA=-55°C to + 125°C ±3.0
to bits
Resolution 0.25 °c
Noise 0.05 °c
A block diagram of the above-mentioned thermal control system is shown in

figure 5-17. Laptops, but also desktops, have a system management that takes
care of the system functions like the different power supply voltages.
Communication between the different parts of the system is done over a two-wire
SM-bus interface that is based on 12C [5.8]. The junction temperature of the
microprocessor is continuously measured by a temperature measurement chip,
which also measures the ambient temperature. This information is sent to the
system management. When the temperature becomes too high, the system
management decides whether or not to increase the fan speed or decrease the
microprocessor clock speed.
Our role in the project, that has been done in cooperation with Philips
Semiconductors in Sunnyvale, was the design of the temperature measurement
chip. For the measurement of the ambient temperature, the design of the high-
accuracy temperature sensor, as described in paragraph 5.2, has been used. The

System
Management
ambient
Temperature
measurement
~====:U
I-
fJProcessor
chip temperature
pProcessor
oscillator
SM-bus 112'~IL _ _ _-.....-.J
p Processor
chip
Fig. 5-17 Thermal control system in laptops and other PCs.

design of the remote microprocessor temperature sensor will be described in this
paragraph.
5.3.2 Specification
The most challenging part of the project is to reduce the influence of interference
of the microprocessor signals on the temperature measurement. Due to the high
clock speeds of up to 450MHz and the consequent steep edges, there is a lot of
noise that is coupled to the bipolar temperature sensor through the microprocessor
substrate. Measurements show spikes on the base-emitter voltage of the bipolar
transistor of more than 300mV. If we compare this with the sensor signal of
approximately 200Jl. vfc, it is obvious that this interference can cause great
problems.
The high-frequency interference problem implies that the sensor signal should be
integrated. However, due to the non-linearity of the bipolar transistor, some errors
will remain even when the integration action is ideal. This can be explained as
follows. Figure 5-18 shows the typical situation of the bipolar transistor on the
microprocessor chip. For simplicity it is assumed that the base of the transistor is
grounded and that the interference source is a triangular signal which is coupled
to the emitter via a capacitance C j . In practice, the effect of the parasitic coupling

+
\'noise
Fig.5-18 Influence of high-frequency interference on the DC-

behaviour of the bipolar transistor temperature sensor.
can somewhat be reduced by a floating measurement of the base-emitter voltage.
However, due to mismatches in impedances between the base and the emitter, the
effect will always be existent. The interference source Vnoise will add a small
current !!.Ieto the bias current Ie.
If the shape of Vnoise is triangular, the current
Me is a square wave. If we state that the collector current of Q r is equal to the
emitter current, the average output voltage VBE yields:
V 1{kT
= - -In (Ie(l+M) + -In kT (Ie(l-!!.»)} (5-8)
BE 2 q Is q Is
which equals:
V BE = 2q Is + In{(l +!!.)(1-!!.)} }
1kT{ 21n (Ie) (5-9)
or:
VBE = -In
kT (IeJlI - !!.2) (5-10)
q s
From equation (5-10) it can be seen that the DC voltage of a bipolar transistor is
changed due to high-frequency interference. To have a negligible influence on
VBE, the interference current should be small compared to Ie.
If the interference
can not be changed by the designer, which is usually the case, a possible way to
reduce the influence is to increase Ie.
However, this can not be done too much
because of self-heating and power consumption limitations. In practice, the

interference source and the coupling is not very well known. However, the
conclusions derived from equation (5-10) will still be applicable.
After deliberation with the microprocessor supplier, it was decided that the
current through the bipolar transistor is limited to 1DOll A. Simulations and
measurements, however, showed that the temperature read-out error, even with a
bias current of lOOIlA was several degrees Celsius. To reduce this error, it was
decided that an external capacitor between base and emitter of maximum 2.2nF
would be added.
The accuracy specification was set to ±2°C for temperatures between +70°C and
+100oC and ±3°C for the total temperature range from -20°C to +125°C. The
resolution was somewhat lowered to 8 bits, which equals 1°C. The other
specifications did not differ very much from the specifications of the high-
accuracy temperature sensor described in paragraph 5.2.
5.3.3 Design of the single-transistor temperature sensor

interface
The most accurate way to generate temperature information from a bipolar
transistor is to perform a differential measurement of two base-emitter voltages
biased at two currents with a fixed ratio. To generate such a PfAT signal from a
single transistor, it is always necessary to have a storage device to store the value
of the first measured base-emitter voltage. The most straightforward way is to use
a capacitor in a sample-and-hold circuit. This is also shown in figure 4-9 in
chapter 4. A major disadvantage of capacitors as storage devices is leakage.
Especially in our design, where large signal integration times are needed to reject
interference, this can be a major problem. The PfAT voltage will have a
sensitivity of approximately 2001l Vfc. To achieve leakages smaller than lOOIl V
during an integration period of several milliseconds would require large storage
capacitors, especially at temperatures above 100°C where leakage becomes very
high.
A different approach, that does not have the leakage problem, is to store the base-
emitter voltage digitally. This can be done in two ways. The first method is to
perform just two samples of the base-emitter voltage and subtract them digitally.
However, this requires a great improvement of performance of the A-to-D
converter. Normally, the A-to-D converter has to convert a signal with a maximal
value of approximately 80mV (kT/q*ln1O at T=400K) with an accuracy of
200ll V, which requires a dynamic range of 52 dB or 9 bits. In the proposed
method, the maximum input signal is increased to approximately 700m V which is

the nominal base-emitter voltage, while the maximal inaccuracy is decreased to

1OOIL V, because a factor two of resolution is lost with digital extraction. This
implies that an A-to-D converter is needed with a dynamic range of at least 77dB
or 13 bits.
The second method is to make a local digital sample-and-hold including an A-to-

D converter, a register and a D-to-A converter. Although this A-to-D converter
and D-to-A converter also need a resolution of 13 bits, the accuracy is of no
importance because it is used in a feed-back loop. However, to make an extra A-
to-D and D-to-A converter with a resolution of 13 bits still requires a lot of chip
area.
We propose a third method that does a digital storage of the base-emitter voltage
but does not have the disadvantages of the two above-mentioned methods. The
principle is shown in figure 5-19. We introduce an extra sample-and-hold phase
where a rough sampling is done of the base-emitter voltage at the high bias
current of WallA, which is called VbeIO' This sampling has a resolution of only 6
bits, which corresponds to approximately 10mV. In the next phases, a small offset
voltage VI of 20m V is subtracted from this sampled voltage, to assure that the
voltage Vs always lays between V beIO and VbeJ. which is the base-emitter voltage
at a bias current of 101LA. In the second phase, the voltage difference ofVbelO and
Vs is converted into a digital number. In the third phase, the voltage difference of
Vs and Vbel is converted. Both the conversions result in a positive number,
because Vs lies between VbelO and V bel . The two samples are added digitally,
which results in the value VbelO minus V beI , which is the desired PfAT signal.
The advantage of this method over the two others is that the maximum signal at
the input of the A-to-D converter is only 80mV and the required accuracy lOOILV,
which corresponds to a dynamic range of 58dB or 10 bits. This is much lower
than the required dynamic range of 13 bits, which is needed when doing a
digitization of the full base-emitter voltage. This is achieved by using a digital
sample-and-hold that has a resolution of only 6 bits.
5.3.4 Detailed design of the remote temperature sensor

.L:1 modulator
The first-order Ld modulator from the high-accuracy temperature sensor is also
used to convert the remote microprocessor temperature sensor signal to the digital
domain. The conversion of the ambient and microprocessor temperature is done
subsequently. In the phase when the microprocessor temperature is converted, the
HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS III

Vtemp(V)
~::~l::::: 1-
(a)
m - m l I
I • t(s}
To T+To 2T+To
<P1(V)
vd:i I I • t(s}
(b)
To T+To 2T+To
<P2(V)
vd:i I I • t(s}
(c)
To T+To 2T+To
Fig.5-19 Principle of low-resolution sample-and-hold circuit in

single-transistor temperature sensor interface
Iptat and Ibe signals from the ambient temperature measurement are added to
obtain a reference signal.
Single-transistor temperature sensor interface

Because the first-order ~~ modulator needs a current input, the instrumentation
amplifier from figure 5-19 is changed to have a current output. The bias currents
11 and lz are dynamically matched to obtain higher matching properties. The
digital sample-and-hold consists of a comparator, a counter and a resistor-string-
type 6-bit D-A converter. The counter has a size of 8 bits to perform some extra

4 .0r-----------------------------------------------~
3.0 ......... ~ ...:. ~ ........... : ...... "..... .:. -........... ~ .
2.0 .. .......... ..... ... . .
IT
'L. 1.0
·1 .0 .................. . ..... . .
_______. .,. ............... •••.••• ___ .0_.- ....
-2.0 .L---------;----------------+--------t--------_----~
o 20 40 60 eo 100 120
Temperature (oC)
Fig. 5-20 Temperature errors of 30 samples without calibration.
digital filtering. The 20mV offset is implemented in the D-A converter and can be
switched on with an additional control line.
Layout
The layout is already shown in figure 5-15. The single-transistor temperature
sensor interface occupies approximately O.3mm 2 . The ~~ modulator is shared
with the high-accuracy ambient temperature sensor and therefore needs no
additional chip area. The control block is a little bit enlarged.

The chip has been encapsulated in a standard plastic IC package and has been
exposed to temperatures in the range from -60°C to +130oC. The circuit shows
full functionality for supply voltages between 2.9V and 5.5V.
The accuracy of 30 samples of the circuit from one batch have been tested at OoC,
+25°C, +80oC and + 120°C. The results are shown in figure 5-20. The resolution
of measurement is 1°C. The reason why only a small number of the 30 tested
samples can be seen is because many samples have exactly the same inaccuracy
because of the limited resolution.

Table 5-7 Measured specifications of the remote

microprocessor temperature sensor
SUf,ply current
I C inactive 100
12C active 500 J1.A
Shutdown mode I
Temperature range -20 125 °C
Inaccuracy
TA=70°C to + 100°C ±3.0 °C
TA=-25°C to +12SoC ±5.0
8 bits
Resolution
I °c
Noise 0.1 °c
All circuits are within ±2°C in a temperature range from OOC to +80oC. The
typical spread at room temperature is ±1°C. The accuracy specification of ±2°C
for temperatures between + 70°C and + 100°C and ±3°C for the total temperature
range between -20°C and +125°C are not completely met. However. this can be
realized by doing a hard-wired shift of _1°C for the whole range and a curvature
correction.
A summary of the measured specifications is listed in table 5-7.
5.4 Conclusions
In this chapter three different CMOS smart temperature sensors have been
described. each one with its own optimization and application. It is shown that it
is possible to make a smart temperature sensor with a power consumption of less

5.4 Conclusions
than lOll W at a sampling rate of 2 samples/so A circuit is also shown that can
measure the temperature of a remote transistor, independent of the process in
which it is made.
However, the best result from the author's point of view, is the realization of the
first smart temperature sensor that meets the standard accuracy specifications
without any form of calibration. This implies a major cost breakthrough and will
further enlarge the number of smart temperature sensor applications.

References
[5.1] IQ Mobil, "Why use 2.45GHz for the RDKS system", http://
www.iqmobil.de. December 1999
[5.2] M. Tuthill, "A Switched-Current, Switched-Capacitor Temperature Sensor
in 0.6-JLm CMOS",IEEE Journal oJSolid-State Circuits, vol.33, pp. 1117-
1122, July 1998
[5.3] A. Bakker and J.H. Huijsing, "Micropower CMOS Temperature Sensor
with Digital Output", IEEE Journal oj Solid-State Circuits, vol.31, pp.
933-937, July 1996
[5.4] B. de Geeter, O. Nys and J.-P. Bardyn, "A Wide Temperature Range
Micropower Sensor Interface Circuit", Proc. ESSCIRC'96, Neuchatel,
Switzerland, pp. 136-139, September 1996
[5.5] National Semiconductor, "LM75 - Digital Temperature Sensor and
Thermal WATCHDOG with Two-Wire Interface", http://
www.national.com. November 1999
[5.6] Philips Semiconductors, "The I2C-bus and how to use it (including
specifications)", http://www.philips.com. April 1995
[5.7] A. Bakker and J.H. Huijsing, "A Low-Cost, High-Accuracy CMOS Smart
Temperature Sensor", Proc. ESSCIRC'99, Duisburg, Germany, pp. 302-
305, September 1999
[5.8] Smart Battery System-Implementers Forum, "Smart Battery System
Specification", http://www.sbs-Jorum.org, rev.l.1, December 11, 1998

Appendix
Derivation of V Bt:<1) by importing the constant VBE(Tr ). This derivation is

referenced in chapter 3 on page 40.
kT Ie
VsE = V: o + - I n - (2-1)
g q CTTI
(2-2)
(2-3)
(2-4)
kT I kT Tr
V,BE = v:gO +-In---..f....+-T]ln-
q 11 q T
(2-5)
CTr
(2-6)
(2-7)
(2-8)

Index
Numerics coherent detection 22

II/noise 11 correlated double-sampling 13, 17
II/noise comer frequency 11 curvature correction techniques 37,45,73
A D
accuracy 64 double-correlated sampling technique 76
accuracy versus chopping frequency 58 duty-cycle 19
aliasing 10 duty-cycle modulation 67, 68
Analog-to-Digital conversion 66 dynamic element matching 13
anti-aliasing filter 16 dynamic offset-cancellation technique 9,
automotive industry 81 10,44
auto zero technique 14 dynamic range usage 71
autozeroing 76
E
B electron charge 4, 38
bandgap voltage references 37 extrapolated bandgap voltage 40
base-width modulation 71
battery-powered systems 65 F
bipolar devices in CMOS technology 37 Fahrenheit 1
bipolar substrate transistor 4 filtering of modulated offset 48
Boltzmann's constant 4, 38 flicker noise 11
bus interfaces 77 folding of high-frequency components 16
frequency conversion 67
C
calibration 9 G
Celsius 1 gain accuracy 25
charge balancing 69
charge injection 18,32 H
charge-coupled devices (CCDs) 17 Hall plate 31
chopper opamp 26, 28 high-accuracy PTA T -current generator 100
chopper technique 20 high-accuracy temperature sensor 93
chopper-stabilization 10, 13, 18 higher-order sigma-delta converters 70

Index
high-frequency offset components 20 non-ideality factor 71

high-ohmic polysilicon resistors 55 nulling opamp 18, 19
I o
I2C interface 77 offset 10
I2C protocol 77 offset correction at start-up 16
instrumentation amplifier 22, 30 offset drift 16
integrating A-to-D converter 19 oversampling 70
interference of microprocessor signals 108
IS2 bus interface 77 p
piece-wise-linear 54
K piece-wise-linear curvature correction
Kelvin 1 technique 46
Kelvin-to-Celsius conversion 71 ping-pong opamps 13
power consumption 65
L power-bandwidth product 23
laptop 106 pressure sensor 80
lateral bipolar transistor 39 protection diodes 31
leakage 16, 110 Pt-l00 2, 63
linearized thermal behaviour 45 PI'AT voltage 4
long-term stability 10
low-pass filter 20, 22 R
low-sensitivity inputs 14 relaxation oscillator 67
low-sensitivity inverting inputs 18 remote microprocessor temperature sensor
106
M reproducibility 37
microcontroller 20 residual noise 15
microprocessor temperature sensor 108 residual offset 14,23,24,27,28
microprocessors 64 residual thermal noise 16
Microwire 77 resistance thermometer 2, 63
Miller capacitor 27, 31 resolution 65
Miller split 28
mixing 10 S
motherboards 64 sample-and-hold circuit 14-17, 110
sampled-data systems 17
N sampling frequency 15
naming conventions 13 saturation current 4
nested chopper technique 28-29, 52 scale 1
noise 10 self-calibrating opamp 13-16
noise bandwidth 11 self-heating 65
noise power spectrum 23 shot noise 10, 12
noise sources 11, 12 sigma-delta modulation 67
noise spectrum 15 sigma-delta modulator 69
non-idealities 44 signal-to-noise ratio 23

Index
single transistor temperature sensors 74

spike energy 24
spikes 23
spinning-current Hall plate 31
stability 37
substrate bipolar transistor. 39
sub-threshold slope factor 12
successive-approximation 67
switched-capacitor (SC) circuits 17
synchronous detection 13, 22
System Management bus (SM-bus) 77
T
temperature characteristics 40
temperature coefficient of PTA T signal 38
temperature coefficient of the base-emitter
voltage 37
theoretical minimal power consumption 65
thermal cross sensitivities 81
thermal management 64, 93
thermal modelling 37
thermal noise 10
thermal noise floor 10
thermal voltage 38
thermistor 2, 63
thermocouple effects 31
thermostats 2
trimming 9, 45
two or three-signal approach 13, 19
typical error of bandgap reference 44
tyre monitoring system 79
U
uncalibrated accuracy 96
unity-gain bandwidth 16,27
v
V-fconverter 19
voltage references 37
w
weak inversion 12, 39
Wheatstone bridge 31
white noise 10

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HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS

Springer Science+Business Media, LLC

ISBN 978-1-4419-4862-5 ISBN 978-1-4757-3190-3 (eBook)

Printed on acid-free paper

All Rights Reserved

2.1 Introduction ............................................................... 9

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS v

2.3.3 Residual offset .......................................................................... 23

3 CMOS bandgap references 37

4 Design of CMOS Smart

4.1 Introduction ............................................................. 63

VI HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS

4.3 Kelvin-to-Celsius conversion .................................. 71

5 Realizations of CMOS Smart

5.1 Tyre monitoring system ........................................... 79

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS VII

The accuracy of conventional CMOS smart temperature sensors is degraded by

Chapter two gives an elaborate description of the different kinds of dynamic

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS IX

Sunnyvale, August 2000

x HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS

1.1 Temperature sensing

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS 1

Fig. 1-1 Communication between a temperature sensor and a

The early function of thermometers was to literally read the temperature.

To communicate with a computer, the resistance changes have to be converted

2 HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS

Fig. 1-2 Ie VBE characteristic of a bipolar transistor, which can be

1.2 CMOS smart temperature sensors

When a transistor is biased at a collector current of I}> it will have a base-emitter

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS 3

where k is Boltzmann's constant (1.3807-lO- 23 J/K), T the absolute temperature

1.3 Motivation and objectives

4 HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS

knowledge needs to be compensated by an increase of intelligence in the smart

1.4 Organization of the work

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS 5

Chapter 4 describes general design aspects of CMOS bandgap references. It

Chapter 5 describes the realizations of three different kinds of CMOS smart

6 HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS 7

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS 9

Comparing conventional trimming with dynamic offset-cancellation techniques,

• Reduction of both offset and 1If noise

In this chapter a systematic overview of all existing dynamic offset-cancellation

2.1.1 Offset and noise in CMOS amplifiers

10 HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS

lit noise . / ' / " ,-lit noise comer frequency

~:' thermal noise

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS 11

~s, norm (2-3)

12 HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS

Table 2-1 Classification of dynamic offset-cancellation techniques

correlated double-sampling synchronous detection

2.1.2 Naming conventions and classification

HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS 13

Fig. 2-3 Autozero principle

2.2 Autozero techniques

The residual offset of the autozero principle is determined by: