TLV 9061

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TLV9061, TLV9062, TLV9064

SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
TLV906xS 10-MHz, RRIO, CMOS Operational Amplifiers for Cost-Sensitive Systems

1 Features 3 Description
•
1 Rail-to-rail input and output The TLV9061 (single), TLV9062 (dual), and TLV9064
(quad) are single-, dual-, and quad- low-voltage (1.8
• Low input offset voltage: ±0.3 mV V to 5.5 V) operational amplifiers (op amps) with rail-
• Unity-gain bandwidth: 10 MHz to-rail input- and output-swing capabilities. These
• Low broadband noise: 10 nV/√Hz devices are highly cost-effective solutions for
• Low input bias current: 0.5 pA applications where low-voltage operation, a small
footprint, and high capacitive load drive are required.
• Low quiescent current: 538 µA Although the capacitive load drive of the TLV906x is
• Unity-gain stable 100 pF, the resistive open-loop output impedance
• Internal RFI and EMI filter makes stabilizing with higher capacitive loads
simpler. These op amps are designed specifically for
• Operational at supply voltages as low as 1.8 V low-voltage operation (1.8 V to 5.5 V) with
• Easier to stabilize with higher capacitive load due performance specifications similar to the OPAx316
to resistive open-loop output impedance and TLVx316 devices.
• Shutdown version: TLV906xS
Device Information(1)
• Extended temperature range: –40°C to 125°C
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications SOT-23 (5) 1.60 mm × 2.90 mm

SC70 (5) 1.25 mm × 2.00 mm
• E-bikes TLV9061 (2)
SOT553 (5) 1.65 mm × 1.20 mm
• Smoke detectors
X2SON (5) 0.80 mm × 0.80 mm
• HVAC: heating, ventilating, and air conditioning TLV9061S SOT-23 (6) 1.60 mm × 2.90 mm
• Motor control: AC induction SOIC (8) 3.91 mm × 4.90 mm
• Refrigerators TSSOP (8) 3.00 mm × 4.40 mm
• Wearable devices TLV9062 VSSOP (8) 3.00 mm × 3.00 mm
• Laptop computers SOT-23 (8) 1.60 mm × 2.90 mm
• Washing machines WSON (8) 2.00 mm × 2.00 mm
• Sensor signal conditioning VSSOP (10) 3.00 mm × 3.00 mm
TLV9062S
• Power modules X2QFN (10) 1.50 mm × 2.00 mm
• Barcode scanners SOIC (14) 8.65 mm × 3.91 mm

TSSOP (14) 4.40 mm × 5.00 mm
• Active filters TLV9064
WQFN (16) 3.00 mm × 3.00 mm
• Low-side current sensing
X2QFN (14) 2.00 mm × 2.00 mm
TLV9064S WQFN (16) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Package is for preview only.
Single-Pole, Low-Pass Filter

RG RF
Small-Signal Overshoot vs Load Capacitance
60
50
R1 VOUT
40
Overshoot (%)
VIN
C1 30
1
f-3 dB =
2pR1C1
20
VOUT
VIN (
= 1+
RF
RG (( 1
1 + sR1C1 ( 10 Overshoot+
Overshoot-
0
0 50 100 150 200 250 300
Capacitive Load (pF) C025
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TLV9061, TLV9062, TLV9064
SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 9.2 Functional Block Diagram ....................................... 23
2 Applications ........................................................... 1 9.3 Feature Description................................................. 24
3 Description ............................................................. 1 9.4 Device Functional Modes........................................ 25
4 Revision History..................................................... 2 10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
5 Description (continued)......................................... 5
10.2 Typical Applications .............................................. 26
6 Device Comparison Table..................................... 5
11 Power Supply Recommendations ..................... 28
7 Pin Configuration and Functions ......................... 6
11.1 Input and ESD Protection ..................................... 28
8 Specifications....................................................... 12
12 Layout................................................................... 29
8.1 Absolute Maximum Ratings .................................... 12
12.1 Layout Guidelines ................................................. 29
8.2 ESD Ratings............................................................ 12
12.2 Layout Example .................................................... 30
8.3 Recommended Operating Conditions..................... 12
8.4 Thermal Information: TLV9061 ............................... 13 13 Device and Documentation Support ................. 31
13.1 Documentation Support ........................................ 31
8.5 Thermal Information: TLV9061S ............................. 13
13.2 Related Links ........................................................ 31
8.6 Thermal Information: TLV9062 ............................... 13
13.3 Receiving Notification of Documentation Updates 31
13.4 Community Resources.......................................... 31
8.8 Thermal Information: TLV9064 ............................... 14
13.5 Trademarks ........................................................... 31
13.6 Electrostatic Discharge Caution ............................ 31
8.10 Electrical Characteristics....................................... 15
13.7 Glossary ................................................................ 31
8.11 Typical Characteristics .......................................... 17
9 Detailed Description ............................................ 23 14 Mechanical, Packaging, and Orderable
Information ........................................................... 32
9.1 Overview ................................................................. 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (May 2019) to Revision J Page
• Deleted TLV9062IDDFR (SOT-23 (8)) package preview notations throughout data sheet ................................................... 1
• Added industry standard package names to Device Comparison Table .............................................................................. 5
• Added note to packages with thermal pads, specifying that the thermal pads need to be connected to V–......................... 7
• Added link to Shutdown Function section in SHDN pin function rows ................................................................................. 11
• Added EMI Rejection section to the Feature Description section ........................................................................................ 24
• Changed Shutdown Function section to add more clarification .......................................................................................... 25
Changes from Revision H (April 2019) to Revision I Page
• Added DDF (SOT-23) thermal information to replace TBDs ................................................................................................ 13
Changes from Revision G (December 2018) to Revision H Page
• Added SOT-23 (8) information to Device Information ........................................................................................................... 1

• Added DDF package column to Device Comparison Table ................................................................................................... 5
• Added DDF (SOT-23) package to Pin Functions ................................................................................................................... 7
• Added DDF (SOT-23) package to Thermal Information....................................................................................................... 13
• Added TLV9062 RUG (X2QFN) thermal information to replace TBDs ................................................................................ 14
2 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated
Product Folder Links: TLV9061 TLV9062 TLV9064

TLV9061, TLV9062, TLV9064
www.ti.com SBOS839J – MARCH 2017 – REVISED SEPTEMBER 2019
Changes from Revision F (September 2018) to Revision G Page
• Changed TLV9064 RUC package name From WQFN (14) : To X2QFN (14) in Device Information table ........................... 1
• Added TLV9064 RUC (X2QFN) pinout drawing to Pin Configuration and Functions section................................................ 9
• Added RUC (X2QFN) package pinout information to Pin Functions: TLV9064 table ............................................................ 9
• Added RUC (X2QFN) to Thermal Information: TLV9064 table ............................................................................................ 14
Changes from Revision E (July 2018) to Revision F Page
• Deleted Shutdown part numbers from datasheet header ..................................................................................................... 1

• Deleted X2QFN (10) package from TLV9062 Device Information table ................................................................................ 1
• Added references to shutdown part numbers in Description section .................................................................................... 5
• Changed TLV906xS series to TLV906xS family throughout datasheet ................................................................................. 5
• Added Shutdown devices to Device Comparison Table ....................................................................................................... 5
• Changed pin namings for all pinout drawings to reflect updated nomenclature ................................................................... 6
• Added TLV9061S Thermal Information Table ...................................................................................................................... 13
• Added TLV9064S Thermal Information Table ...................................................................................................................... 14
• Deleted Partial Shutdown Amplifer Enable Time ................................................................................................................. 16
• Added clarification on selecting resistors for a current sensing application in the Typical Applications Section ................ 27
• Changed wording of third bullet in Layout Guidelines .......................................................................................................... 29
Changes from Revision D (June 2018) to Revision E Page
• Added TLV9061S device to Device Information table............................................................................................................ 1

• Added RUC and RUG packages to the Device Comparison table ........................................................................................ 5
• Added TLV9061S DBV (SOT-23) pinout drawing to Pin Configuration and Functions section ............................................. 7
• Added TLV9061S DBV (SOT-23) package pinout information to Pin Functions: TLV9061S table ....................................... 7
• Added TLV9062S RUG (VSSOP) package pinout drawing to Pin Configuration and Functions section .............................. 8
• Added TLV9062S RUG (VSSOP) package pinout information to Pin Functions: TLV9062S table ....................................... 8
• Added TLV9064 RTE (WQFN) pinout drawing to Pin Configuration and Functions section ................................................ 9
• Added TLV9064 RTE pinout information to Pin Functions: TLV9064 table ........................................................................... 9
• Added TLV9064S RTE (WQFN) pinout drawing to Pin Configuration and Functions section ............................................ 11
Changes from Revision C (March 2018) to Revision D Page
• Added shutdown suffix to "TLV906x" to document title.......................................................................................................... 1

• Added "Shutdown Version" bullet to Features list ................................................................................................................. 1
• Added shutdown text to Description (continued) section ....................................................................................................... 5
• Added "(VS = [V+] – [V–]) supply voltage parameter in Absolute Maximum Ratings table .................................................. 12
• Added "input voltage range" and "output voltage range" parameters and values to Recommended Operating
Conditions table .................................................................................................................................................................... 12
• Added shutdown pin recommended operating conditions in Recommended Operating Conditions table .......................... 12
• Added "TA" symbol to "specified temperature" parameter to Recommended Operating Conditions table ......................... 12
• Added Thermal Information: TLV9062S thermal table data ................................................................................................. 14
• Added Thermal Information: TLV9062S thermal table data ................................................................................................. 14
• Added shutdown section to Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V table...... 16
Copyright © 2017–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

TLV9061, TLV9062, TLV9064
• Added Shutdown Function section ...................................................................................................................................... 25
Changes from Revision B (October 2017) to Revision C Page
• Changed device status from Production Data/Mixed Status to Production Data .................................................................. 1
• Deleted package preview note from TLV9061 DPW (X2SON) package in Device Information table .................................. 1
• Deleted package preview note from TLV9061 DPW (X2SON) package pinout drawing ...................................................... 6
• Changed formatting of ESD Ratings table to show different results for all packages ......................................................... 12
• Deleted package preview note from DPW (X2SON) package in Thermal Information: TLV9061 table ............................. 13
• Deleted package preview note from DPW (X2SON) package in Thermal Information: TLV9061 table ............................. 13
Changes from Revision A (June 2017) to Revision B Page
• Added 8-pin PW package to Pin Configuration and Functions section ................................................................................. 7

• Added DSG (WSON) package to Thermal Information table ............................................................................................... 13
• Added PW (TSSOP) to TLV9062 Thermal Information table .............................................................................................. 13
• Changed maximum input offset voltage value from ±1.6 mV to 2 mV ................................................................................. 15
• Changed maximum input offset voltage value from ±1.5 to ±1.6 mV................................................................................... 15
• Changed minimum common-mode rejection ratio input voltage range from 86 dB to 80 dB ............................................. 15
• Changed typical input current noise density value from 10 to 23 fA/√Hz............................................................................. 15
• Changed THD + N test conditions from VS = 5 V to VS = 5.5 V........................................................................................... 15
• Added VCM = 2.5 V test condition to THD + N parameter in Electrical Characteristics table .............................................. 15
• Added maximum output voltage swing value from 25 mV to 60 mV.................................................................................... 15
• Changed maximum output voltage swing value from 15 mV to 20 mV .............................................................................. 15
Changes from Original (March 2017) to Revision A Page
• Changed device status from Advance Information to Production Data ................................................................................. 1

TLV9061, TLV9062, TLV9064
5 Description (continued)
The TLV906xS devices include a shutdown mode that allow the amplifiers to switch into standby mode with
typical current consumption less than 1 µA.
The TLV906xS family helps simplify system design, because the family is unity-gain stable, integrates the RFI
and EMI rejection filter, and provides no phase reversal in overdrive condition.
Micro size packages, such as X2SON and X2QFN, are offered for all the channel variants (single, dual and
quad), along with industry-standard packages, such as SOIC, MSOP, SOT-23, and TSSOP.
6 Device Comparison Table

PACKAGE LEADS
NO. OF
DEVICE SOIC SOT-23 SC-70 VSSOP VSSOP X2SON SOT-553 WSON TSSOP SOT-23 WQFN X2QFN X2QFN
CHANNELS
D DBV DCK DGK DGS DPW DRL DSG PW DDF RTE RUC RUG
TLV9061 8 5 5 — — 5 5 — — — — — —
1
TLV9061S — 6 — — — — — — — — — — —
TLV9062 8 — — 8 10 — — 8 8 8 — — —
2
TLV9062S — — — — 10 — — — — — — — 10
TLV9064 14 — — — — — — — 14 — 16 14 —
4
TLV9064S — — — — — — — — — — 16 — —

TLV9061, TLV9062, TLV9064
7 Pin Configuration and Functions
TLV9061 DBV, DRL Packages

5-Pin SOT-23, SOT-553 TLV9061 DCK Package
Top View 5-Pin SC70
Top View
OUT 1 5 V+
IN+ 1 5 V+
V± 2
V± 2
IN+ 3 4 IN±
IN± 3 4 OUT
Not to scale
Not to scale
TLV9061 DPW Package

5-Pin X2SON
Top View
OUT 1 5 V+
V±
IN± 2 4 IN+
Not to scale
Pin Functions: TLV9061

PIN
SOT-23, I/O DESCRIPTION
NAME SC70 X2SON
SOT-553
IN– 4 3 2 I Inverting input
IN+ 3 1 4 I Noninverting input
OUT 1 4 1 O Output
V– 2 2 3 I or — Negative (low) supply or ground (for single-supply operation)
V+ 5 5 5 I Positive (high) supply

TLV9061, TLV9062, TLV9064
TLV9061S DBV Package

6-Pin SOT-23
Top View
OUT 1 6 V+
V± 2 5 SHDN
+IN 3 4 ±IN
Not to scale
Pin Functions: TLV9061S

PIN
I/O DESCRIPTION
NAME NO.
IN– 4 I Inverting input
IN+ 3 I Noninverting input
OUT 1 O Output
Shutdown: low = amp disabled, high = amp enabled. See Shutdown Function section for
SHDN 5 I
more information.
V– 2 I or — Negative (low) supply or ground (for single-supply operation)
V+ 6 I Positive (high) supply
TLV9062 D, DGK, PW, DDF Packages

8-Pin SOIC, VSSOP, TSSOP, SOT-23 TLV9062 DSG Package
Top View 8-Pin WSON With Exposed Thermal Pad
Top View
OUT1 1 8 V+
OUT1 1 8 V+
IN1± 2 7 OUT2
IN1± 2 7 OUT2
IN1+ 3 6 IN2± Thermal
Pad
IN1+ 3 6 IN2±
V± 4 5 IN2+
V± 4 5 IN2+
Not to scale
Not to scale
(1) Connect thermal pad to V–

PIN
I/O DESCRIPTION
NAME NO.
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
OUT1 1 O Output, channel 1
V– 4 — Negative (lowest) supply or ground (for single-supply operation)
V+ 8 — Positive (highest) supply

TLV9061, TLV9062, TLV9064
TLV9062S DGS Package

10-Pin VSSOP TLV9062S RUG Package
Top View 10-Pin X2QFN
Top View
OUT1 1 10 V+
IN1+
IN1± 2 9 OUT2
IN1+ 3 8 IN2± V± 1 9 IN1±
10
V± 4 7 IN2+
SHDN1 5 6 SHDN2 SHDN1 2 8 OUT1
Not to scale
SHDN2 3 7 V+
5
IN2+ 4 6 OUT2
Not to scale
IN2±
PIN
I/O DESCRIPTION
NAME VSSOP X2QFN
IN1– 2 9 I Inverting input, channel 1
IN1+ 3 10 I Noninverting input, channel 1
IN2– 8 5 I Inverting input, channel 2
IN2+ 7 4 I Noninverting input, channel 2
OUT1 1 8 O Output, channel 1
OUT2 9 6 O Output, channel 2
Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Shutdown
SHDN1 5 2 I
Function section for more information.
Shutdown: low = amp disabled, high = amp enabled. Channel 2. See Shutdown
SHDN2 6 3 I
Function section for more information.
V– 4 1 I or — Negative (low) supply or ground (for single-supply operation)
V+ 10 7 I Positive (high) supply

TLV9061, TLV9062, TLV9064
TLV9064 D, PW Packages
14-Pin SOIC, TSSOP TLV9064 RUC Package
Top View 14-Pin X2QFN
Top View
OUT1 1 14 OUT4
OUT1
OUT4
IN1± 2 13 IN4±
IN1+ 3 12 IN4+ IN1± 1 12 IN4±
V+ 4 11 V±
14
13
IN2+ 5 10 IN3+ IN1+ 2 11 IN4+
IN2± 6 9 IN3±
V+ 3 10 V±
OUT2 7 8 OUT3
IN2+ 4 9 IN3+
7
Not to scale
IN2± 5 8 IN3±
TLV9064 RTE Package
16-Pin WQFN With Exposed Thermal Pad
OUT2
OUT3
Top View Not to scale
OUT1
OUT4
IN1±
IN4±
16
15
14
13
IN1+ 1 12 IN4+
V+ 2 11 V±
Thermal
IN2+ 3 Pad 10 IN3+
IN2± 4 9 IN3±
5
8
OUT2
NC
NC
OUT3
Not to scale

PIN
SOIC, I/O DESCRIPTION
NAME WQFN X2QFN
TSSOP
IN1– 2 16 1 I Inverting input, channel 1
IN1+ 3 1 2 I Noninverting input, channel 1

TLV9061, TLV9062, TLV9064
Pin Functions: TLV9064 (continued)

PIN
SOIC, I/O DESCRIPTION
NAME WQFN X2QFN
TSSOP
NC — 6, 7 — — No internal connection
OUT1 1 15 14 O Output, channel 1
V– 11 11 10 I or — Negative (low) supply or ground (for single-supply operation)
V+ 4 2 3 I Positive (high) supply

TLV9061, TLV9062, TLV9064
TLV9064S RTE Package

16-Pin WQFN With Exposed Thermal Pad
Top View
OUT1
OUT4
IN1±
IN4±
16
15
14
13
IN1+ 1 12 IN4+
V+ 2 11 V±
Thermal
IN2+ 3 Pad 10 IN3+
IN2± 4 9 IN3±
8
OUT2
SHDN12
SHDN34
OUT3
Not to scale

PIN
I/O DESCRIPTION
NAME NO.
Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Shutdown Function
SHDN12 6 I
section for more information.
Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Shutdown Function
SHDN34 7 I
section for more information.
V– 11 I or — Negative (low) supply or ground (for single-supply operation)
V+ 2 I Positive (high) supply

TLV9061, TLV9062, TLV9064
8 Specifications
8.1 Absolute Maximum Ratings
over operating ambient temperature (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage [(V+) – (V–)] 0 6 V
Common-mode (V–) – 0.5 (V+) + 0.5 V
Voltage (2)
Signal input pins Differential (V+) – (V–) + 0.2 V
Current (2) –10 10 mA
Output short-circuit (3) Continuous mA
Specified, TA –40 125
Temperature Junction, TJ 150 °C
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
8.2 ESD Ratings

VALUE UNIT
TLV9061 PACKAGES
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500
ALL OTHER PACKAGES
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage (VS = [V+] – [V–]) 1.8 5.5 V
VI Input voltage range (V–) – 0.1 (V+) + 0.1 V
VO Output voltage range V– V+ V
VSHDN_IH High level input voltage at shutdown pin (amplifier enabled) 1.1 V+ V
VSHDN_IL Low level input voltage at shutdown pin (amplifier disabled) V– 0.2 V
TA Specified temperature –40 125 °C

TLV9061, TLV9062, TLV9064
8.4 Thermal Information: TLV9061

TLV9061
THERMAL METRIC (1) DBV (SOT-23) DCK (SC70) DPW (X2SON) UNIT
5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 221.7 263.3 467 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 144.7 75.5 211.6 °C/W
RθJB Junction-to-board thermal resistance 49.7 51 332.2 °C/W
ψJT Junction-to-top characterization parameter 26.1 1 29.3 °C/W
ψJB Junction-to-board characterization parameter 49 50.3 330.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 125 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
8.5 Thermal Information: TLV9061S

TLV9061S
THERMAL METRIC (1) DBV (SOT-23) UNIT
6 PINS
RθJA Junction-to-ambient thermal resistance 216.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 155.1 °C/W
RθJB Junction-to-board thermal resistance 96.2 °C/W
ψJT Junction-to-top characterization parameter 80.3 °C/W
ψJB Junction-to-board characterization parameter 95.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics.

TLV9062
(1)
THERMAL METRIC D (SOIC) DGK (VSSOP) DSG (WSON) PW (TSSOP) DDF (SOT-23) UNIT
8 PINS 8 PINS 8 PINS 8 PINS 8 PINS
Junction-to-ambient thermal
RθJA 157.6 201.2 94.4 205.8 184.4 °C/W
resistance
Junction-to-case (top) thermal
RθJC(top) 104.6 85.7 116.5 106.7 112.8 °C/W
resistance
Junction-to-board thermal
RθJB 99.7 122.9 61.3 133.9 99.9 °C/W
resistance
Junction-to-top
ψJT 55.6 21.2 13 34.4 18.7 °C/W
characterization parameter
Junction-to-board
ψJB 99.2 121.4 61.7 132.6 99.3 °C/W
characterization parameter
Junction-to-case (bottom)
RθJC(bot) N/A N/A 34.4 N/A N/A °C/W
thermal resistance

TLV9061, TLV9062, TLV9064

TLV9062S
THERMAL METRIC (1) DGS (VSSOP) RUG (X2QFN) UNIT
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 170.4 197.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 84.9 93.3 °C/W
RθJB Junction-to-board thermal resistance 113.5 123.8 °C/W
ψJT Junction-to-top characterization parameter 16.4 3.7 °C/W
ψJB Junction-to-board characterization parameter 112.3 120.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

TLV9064
THERMAL METRIC (1) PW (TSSOP) D (SOIC) RTE (WQFN) RUC (X2QFN) UNIT
14 PINS 14 PINS 16 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 135.8 106.9 65.1 205.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 64 64 67.9 72.5 °C/W
RθJB Junction-to-board thermal resistance 79 63 40.4 150.2 °C/W
ψJT Junction-to-top characterization parameter 15.7 25.9 5.5 3.0 °C/W
ψJB Junction-to-board characterization parameter 78.4 62.7 40.2 149.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 23.8 N/A °C/W

TLV9064S
THERMAL METRIC (1) RTE (WQFN) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 65.1 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 67.9 °C/W
RθJB Junction-to-board thermal resistance 40.4 °C/W
ψJT Junction-to-top characterization parameter 5.5 °C/W
ψJB Junction-to-board characterization parameter 40.2 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 23.8 °C/W

TLV9061, TLV9062, TLV9064
8.10 Electrical Characteristics

For VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VS = 5 V ±0.3 ±1.6
VOS Input offset voltage mV
VS = 5 V, TA = –40°C to 125°C ±2
dVOS/dT Drift VS = 5 V, TA = –40°C to 125°C ±0.53 µV/°C
PSRR Power-supply rejection ratio VS = 1.8 V – 5.5 V, VCM = (V–) ±7 ±80 µV/V
Channel separation, DC At DC 100 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range VS = 1.8 V to 5.5 V (V–) – 0.1 (V+) + 0.1 V
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
80 103
TA = –40°C to 125°C
VS = 5.5 V, VCM = –0.1 V to 5.6 V,
57 87
TA = –40°C to 125°C
CMRR Common-mode rejection ratio dB
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
88
TA = –40°C to 125°C
VS = 1.8 V, VCM = –0.1 V to 1.9 V,
81
TA = –40°C to 125°C
INPUT BIAS CURRENT
IB Input bias current ±0.5 pA
IOS Input offset current ±0.05 pA
NOISE
Input voltage noise (peak-to-
En VS = 5 V, f = 0.1 Hz to 10 Hz 4.77 µVPP
peak)
VS = 5 V, f = 10 kHz 10
en Input voltage noise density nV/√Hz
VS = 5 V, f = 1 kHz 16
in Input current noise density f = 1 kHz 23 fA/√Hz
INPUT CAPACITANCE
CID Differential 2 pF
CIC Common-mode 4 pF
OPEN-LOOP GAIN
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
100
RL = 10 kΩ
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
104 130
RL = 10 kΩ
AOL Open-loop voltage gain dB
VS = 1.8 V, (V–) + 0.06 V < VO < (V+) – 0.06 V,
100
RL = 2 kΩ
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
130
RL = 2 kΩ
FREQUENCY RESPONSE
GBP Gain bandwidth product VS = 5 V, G = +1 10 MHz
φm Phase margin VS = 5 V, G = +1 55 °
SR Slew rate VS = 5 V, G = +1 6.5 V/µs
To 0.1%, VS = 5 V, 2-V step , G = +1, CL = 100 pF 0.5
tS Settling time To 0.01%, VS = 5 V, 2-V step, µs
1
G = +1, CL = 100 pF
tOR Overload recovery time VS = 5 V, VIN × gain > VS 0.2 µs
Total harmonic distortion + VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1,
THD + N 0.0008%
noise (1) f = 1 kHz
OUTPUT
Voltage output swing from supply VS = 5.5 V, RL = 10 kΩ 20

VO mV
rails VS = 5.5 V, RL = 2 kΩ 60
ISC Short-circuit current VS = 5 V ±50 mA
ZO Open-loop output impedance VS = 5 V, f = 10 MHz 100 Ω
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.

TLV9061, TLV9062, TLV9064
Electrical Characteristics (continued)

For VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VS = 5.5 V, IO = 0 mA 538 750
IQ Quiescent current per amplifier µA
VS = 5.5 V, IO = 0 mA, TA = –40°C to 125°C 800
SHUTDOWN
VS = 1.8 V to 5.5 V, all amplifiers disabled,
IQSD Quiescent current per amplifier 0.5 1.5 µA
SHDN = Low
Output impedance during
ZSHDN VS = 1.8 V to 5.5 V, amplifier disabled 10 || 8 GΩ || pF
shutdown
VSHDN_THR High level voltage shutdown
VS = 1.8 V to 5.5 V (V–) + 0.9 V (V–) + 1.1 V V
_HI threshold (amplifier enabled)
VSDHN_THR Low level voltage shutdown
VS = 1.8 V to 5.5 V (V–) + 0.2 V (V–) + 0.7 V V
_LO threshold (amplifier disabled)
Amplifier enable time VS = 1.8 V to 5.5 V, full shutdown; G = 1,
tON 10 µs
(shutdown) (2) VOUT = 0.9 × VS / 2, RL connected to V–
VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2,
tOFF Amplifier disable time (2) 0.6 µs
RL connected to V–
SHDN pin input bias current (per VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V 130
pA
pin) VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V– + 0.8 V 40
(2) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

TLV9061, TLV9062, TLV9064
8.11 Typical Characteristics

at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
35 50
30
40
25
Population (%)
Population (%)
20 30
15
20
10
10
5
0 0
0.4
0.8
1.2
1.6
2.4
2.8
0
2
-1500
-1250
-1000
250
500
750
-750
-500
-250
1000
1250
1500
Offset Voltage Drift (µV/C)
Offset Voltage (µV) C001 C002
TA = –40°C to 125°C
Figure 1. Offset Voltage Production Distribution Figure 2. Offset Voltage Drift Distribution
500 2500
400 2000
300 1500
Offset Voltage (µV)
200 1000
100 500
0 0
±100 ±500
±200 ±1000
±300 ±1500
±400 ±2000
±500 ±2500
±50 ±25 0 25 50 75 100 125 150 -4 -3 -2 -1 0 1 2 3 4
Temperature (ƒC) C003 Input Common Mode Voltage (V) C005
V+ = 2.75 V V– = –2.75 V
Figure 3. Offset Voltage vs Temperature Figure 4. Offset Voltage vs Common-Mode Voltage

1000 120 180
Gain
100
Open Loop Voltage Gain (dB)
Phase
500 135 Phase Margin (deg)
80
60
0 90
40
20
±500 45
0
±1000 ±20 0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 100 1k 10k 100k 1M 10M
Supply Voltage (V) C004 Frequency (Hz) C006
VS = 1.8 V to 5.5 V CL = 10 pF
Figure 5. Offset Voltage vs Power Supply Figure 6. Open-Loop Gain and Phase vs Frequency

TLV9061, TLV9062, TLV9064
Typical Characteristics (continued)

20 40
VS = 5.5 V
30
Open Loop Voltage Gain (µV/V)
Closed Lopp Voltage Gain (dB)

VS = 1.8 V
16
20
12 10
0
8 ±10
±20 G=+1
4
G=-1
±30
G=+10
0 ±40
±50 ±25 0 25 50 75 100 125 1000 10k 100k 1M 10M
Temperature (ƒC) C022 Frequency (Hz) C007
RL = 2 kΩ
Figure 7. Open-Loop Gain vs Temperature Figure 8. Closed-Loop Gain vs Frequency

250 3
Input Bias Current and offset current (pA)
IBN
200 IBP 2
IOS -40ƒC
Output Voltage (V)
150 1 125ƒC 85ƒC

25ƒC
100 0
85ƒC 25ƒC
50 ±1 -40ƒC
125ƒC
0 ±2
±50 ±3
±50 ±25 0 25 50 75 100 125 10 20 30 40 50 60
Temperature (ƒC) C008 Output Current (mA) C009
V+ = 2.75 V V– = –2.75 V
Figure 9. Input Bias Current vs Temperature Figure 10. Output Voltage Swing vs Output Current
120 55
CMRR
100 PSRR-
50
PSRR and CMRR (dB)
PSRR+
80
CMRR (µV/V)
45
60
40 40
20
35
0
1000 10k 100k 1M 10M 30
Frequency (Hz) C011
±50 ±25 0 25 50 75 100 125
Temperature (ƒC) C012
VS = 5.5 V VCM = –0.1 V to 5.6 V TA= –40°C to 125°C

RL= 10 kΩ
Figure 11. CMRR and PSRR vs Frequency
(Referred to Input) Figure 12. CMRR vs Temperature

TLV9061, TLV9062, TLV9064

10 10
8 9
7
CMRR (µV/V)
PSRR (µV/V)
8
6
5
7
4
3 6
2
1 5
±50 ±25 0 25 50 75 100 125 150 ±50 ±25 0 25 50 75 100 125
Temperature (ƒC) C016 Temperature (ƒC) C013
VCM = (V–) – 0.1 V to (V+) – 1.4 V VS = 1.8 V to 5.5 V

TA= –40°C to 125°C RL= 10 kΩ VS = 5.5 V
Figure 13. CMRR vs Temperature Figure 14. PSRR vs Temperature

120
,QSXW 9ROWDJH 1RLVH 6SHFWUDO 'HQVLW\ Q9 ¥+] 100

Voltage (1µV/div)
80
60
40
20
0
Time (1s/div) 10 100 1k 10k 100k
C014 Frequency (Hz) C015
VS = 1.8 V to 5.5 V
Figure 15. 0.1-Hz to 10-Hz Input Voltage Noise Figure 16. Input Voltage Noise Spectral Density vs
Frequency
±90 ±40
±95
±60
±100
THD + N (dB)
THD + N (dB)
±105 ±80
±110
±100
±115
±120 ±120
100 1k 10k 0.001 0.01 0.1 1
Frequency (Hz) C017 Output Voltage Amplitude (VRMS) C018
VS = 5.5 V VCM = 2.5 V RL = 2 kΩ VS = 5.5 V RL = 2 kΩ G = +1

VOUT = 0.5 VRMS BW = 80 kHz G = +1 VCM = 2.5 V BW = 80 kHz f = 1 kHz
Figure 17. THD + N vs Frequency Figure 18. THD + N vs Amplitude

TLV9061, TLV9062, TLV9064

±40 600
580
Quiescent current (µA)

±60
THD + N (dB)
560
±80
540
±100
520
±120 500
0.001 0.01 0.1 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Output Voltage Amplitude (VRMS) C019 Supply Voltage (V) C020
VS = 5.5 V VCM = 2.5 V RL = 2 kΩ

G = –1 BW = 80 kHz f = 1 kHz
Figure 19. THD + N vs Amplitude Figure 20. Quiescent Current vs Supply Voltage
800 200
Open Loop Output Impedance (Ÿ)

700
160
Quiescent Current (µA)
600
500
120
400
300 80
200
40
100
0 0
±50 ±25 0 25 50 75 100 125 10k 100k 1M 10M
Figure 21. Quiescent Current vs Temperature Figure 22. Open-Loop Output Impedance vs Frequency
60 60
50 50
40 40
Overshoot (%)
Overshoot (%)
30 30
20 20
10 Overshoot+ 10 Overshoot(+)
Overshoot- Overshoot(-)
0 0
0 50 100 150 200 250 300 0 50 100 150 200 250 300
Capacitive Load (pF) C025 Capacitive Load (pF) C026
V+ = 2.75 V V– = –2.75 V G = +1 V/V V+ = 2.75 V V– = –2.75 V G = –1 V/V

VOUT step = 100 mVp-p RL = 10 kΩ VOUT step = 100 mVp-p RL = 10 kΩ
Figure 23. Small-Signal Overshoot vs Load Capacitance Figure 24. Small-Signal Overshoot vs Load Capacitance

TLV9061, TLV9062, TLV9064

Voltage (2 V/V)
Voltage (1V/div)
Input INPUT
Output OUTPUT
Time (200 µs/div) Time (1 µs/div)
C036 C028
V+ = 2.75 V V– = –2.75 V V+ = 2.75 V V– = –2.75 V G = –10 V/V
Figure 25. No Phase Reversal Figure 26. Overload Recovery
Input
Output
Voltage (20 mV/div)
Voltage (1 V/div)
Input
Output
Time (0.1µs/div) Time (1 µs/div)
C030 C031
V+ = 2.75 V V– = –2.75 V G = 1 V/V V+ = 2.75 V V– = –2.75 V CL = 100 pF

G = 1 V/V
Figure 27. Small-Signal Step Response Figure 28. Large-Signal Step Response
80 6
60
Short Circuit Current Limit (mA)
Maximum Output Voltage (V)
5
40
4
20
Sinking
0 3
Sourcing
±20
2
±40
1 VS = 5.5 V
±60
VS = 1.8 V
±80 0
±50 ±25 0 25 50 75 100 125 1 10 100 1k 10k 100k 1M 10M
RL = 10 kΩ CL = 10 pF
Figure 29. Short-Circuit Current vs Temperature Figure 30. Maximum Output Voltage vs Frequency and
Supply Voltage

TLV9061, TLV9062, TLV9064

140 0
120 ±20
Channel Separation (dB)

100 ±40
EMIRR (dB)
80 ±60
60 ±80
40 ±100
20 ±120
0 ±140
10M 100M 1G 100 1k 10k 100k 1M 10M
Frequency (Hz) C041 Frequency (Hz) C038
PRF = –10 dBm V+ = 2.75 V V– = –2.75 V
Figure 31. Electromagnetic Interference Rejection Ratio Figure 32. Channel Separation vs Frequency
Referred to Noninverting Input (EMIRR+) vs Frequency
90 200
Open Loop Voltage Gain (dB)
75
160
Phase Margin (degrees)
60
120
45
80
30
40
15
0 0
0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
Capacitive Load (pF) C037 Output Voltage (V) C023
VS = 5.5 V VS = 5.5 V
Figure 33. Phase Margin vs Capacitive Load Figure 34. Open Loop Voltage Gain vs Output Voltage
100 100
75 75
50
50
Output Voltage (mV)
Output voltage (mV)
25
25 0
0 -25
±25 -50
-75
±50
-100
±75 -125
±100 -150
0 0.3 0.6 0.9 0 0.3 0.6 0.9 1.2 1.5
Settling time (µs) C032 Settling time (µs) C033
Figure 35. Large Signal Settling Time (Positive) Figure 36. Large Signal Settling Time (Negative)

TLV9061, TLV9062, TLV9064
9 Detailed Description
9.1 Overview
The TLV906x devices are a family of low-power, rail-to-rail input and output op amps. These devices operate
from 1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications.
The input common-mode voltage range includes both rails and allows the TLV906x series to be used in virtually
any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially
in low-supply applications. The high bandwidth enables this family to drive the sample-hold circuitry of analog-to-
digital converters (ADCs).
9.2 Functional Block Diagram
V+
Reference
Current
V V
IN+ INÛ
V Class AB
BIAS1
Control V
O
Circuitry
V
BIAS2
VÛ
(Ground)

TLV9061, TLV9062, TLV9064
9.3 Feature Description

9.3.1 Rail-to-Rail Input
The input common-mode voltage range of the TLV906x family extends 100 mV beyond the supply rails for the
full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage: an
N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 200 mV
above the positive supply, whereas the P-channel pair is active for inputs from 200 mV below the negative
supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in
which both pairs are on. This 200-mV transition region can vary up to 200 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
9.3.2 Rail-to-Rail Output

Designed as a low-power, low-voltage operational amplifier, the TLV906x series delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 15 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
9.3.3 EMI Rejection

The TLV906x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV906x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 37 shows the results of this testing on the TLV906x. Table 1 shows the EMIRR IN+ values for the
TLV906x at particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of
Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it
relates to op amps and is available for download from www.ti.com.
140
120
100
EMIRR (dB)
80
60
40
20
0
10M 100M 1G
Frequency (Hz) C041
Figure 37. EMIRR Testing
Table 1. TLV906x EMIRR IN+ For Frequencies of Interest

FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
400 MHz 59.5 dB
applications
Global system for mobile communications (GSM) applications, radio communication, navigation,
900 MHz 68.9 dB
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 77.8 dB

TLV9061, TLV9062, TLV9064
Feature Description (continued)

Table 1. TLV906x EMIRR IN+ For Frequencies of Interest (continued)
FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
2.4 GHz 78.0 dB
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.8 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
5 GHz 87.6 dB
operation, C-band (4 GHz to 8 GHz)
9.3.4 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TLV906x family is approximately 200 ns.
9.3.5 Shutdown Function
The TLV906xS devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode. In
this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active-low, meaning that
shutdown mode is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown
feature lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has
been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown
pin must either be connected to a valid high or a low voltage or driven, and not left as an open circuit. There is
no internal pull-up to enable the amplifier.
The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled, and
quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may
be used to greatly reduce the average current and extend battery life. The enable time is 10 µs for full shutdown
of all channels; disable time is 6 µs. When disabled, the output assumes a high-impedance state. This
architecture allows the TLV906xS to be operated as a gated amplifier (or to have the device output multiplexed
onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to
midsupply (VS / 2) is required. If using the TLV906xS without a load, the resulting turnoff time is significantly
increased.
9.4 Device Functional Modes

The TLV906x family are operational when the power-supply voltage is between 1.8 V (±0.9 V) and 5.5 V
(±2.75 V). The TLV906xS devices feature a shutdown mode and are shut down when a valid logic low is applied
to the shutdown pin.

TLV9061, TLV9062, TLV9064
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information

The TLV906x family features 10-MHz bandwidth and 6.5-V/µs slew rate with only 538 µA of supply current per
channel, providing good AC-performance at very low power consumption. DC applications are well served with a
very low input noise voltage of 10 nV/√Hz at 10 kHz, low input bias current, and a typical input offset voltage of
0.3 mV.
10.2 Typical Applications

10.2.1 Typical Low-Side Current Sense Application
Figure 38 shows the TLV906x configured in a low-side current-sensing application.
VBUS
ILOAD ZLOAD
5V
+
TLV906x VOUT
Rshunt
VSHUNT 0.1 RF
165 k
RG
3.4 k
Figure 38. TLV906x in a Low-Side, Current-Sensing Application
10.2.1.1 Design Requirements

The design requirements for this design are:
• Load current: 0 A to 1 A
• Output voltage: 4.95 V
• Maximum shunt voltage: 100 mV

TLV9061, TLV9062, TLV9064
Typical Applications (continued)

10.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 38 is given in Equation 1.
VOUT ILOAD u RSHUNT u Gain (1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2.
VSHUNT _ MAX 100mV
RSHUNT 100m:
ILOAD _ MAX 1A (2)
Using Equation 2, RSHUNT equals 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is amplified by the
TLV906x to produce an output voltage of approximately 0 V to 4.95 V. Equation 3 calculates the gain required for
the TLV906x to produce the required output voltage.
VOUT _ MAX VOUT _ MIN
Gain
VIN _ MAX VIN _ MIN
(3)
Using Equation 3, the required gain equals 49.5 V/V, which is set with the RF and RG resistors. Equation 4 sizes
the RF and RG, resistors to set the gain of the TLV906x to 49.5 V/V.
RF
Gain 1
RG (4)
Selecting RF to equal 165 kΩ and RG to equal 3.4 kΩ provides a combination that equals approximately 49.5
V/V. Figure 39 shows the measured transfer function of the circuit shown in Figure 38. Notice that the gain is
only a function of the feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and
the actual resistor values are determined by the impedance levels that the designer wants to establish. The
impedance level determines the current drain, the effect that stray capacitance has, and a few other behaviors.
There is no optimal impedance selection that works for every system, you must choose an impedance that is
ideal for your system parameters.
10.2.1.3 Application Curve
4
Output (V)
0
0 0.2 0.4 0.6 0.8 1
ILOAD (A) C219
Figure 39. Low-Side, Current-Sense, Transfer Function

TLV9061, TLV9062, TLV9064
11 Power Supply Recommendations

The TLV906x series is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to 125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V can permanently damage the device; see the Absolute
Maximum Ratings table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
11.1 Input and ESD Protection

The TLV906x series incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA, as shown in the Absolute Maximum Ratings table. Figure 40 shows how a series input resistor can be
added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier
input and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
Device VOUT
VIN
5 kW
Figure 40. Input Current Protection

TLV9061, TLV9062, TLV9064
12 Layout
12.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply
applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more
detailed information, see Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much
better as opposed to running the traces in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 42, keeping RF and
RG close to the inverting input minimizes parasitic capacitance on the inverting input.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

TLV9061, TLV9062, TLV9064
12.2 Layout Example
VIN 1 + VIN 2 +
RG VOUT 1 RG VOUT 2
RF RF
Figure 41. Schematic Representation for Figure 42
Place components OUT 1

close to device and to Use low-ESR,
VS+ ceramic bypass
each other to reduce
parasitic errors . capacitor . Place as
close to the device
as possible .
OUT1 V+ GND
RF
OUT 2
GND IN1 ± OUT2
RG RF
VIN 1 IN1 + IN2 ± GND
RG
V± IN2 + VIN 2
Keep input traces short

Use low-ESR,
and run the input traces
ceramic bypass GND as far away from
capacitor . Place as VS± Ground (GND) plane on another layer the supply lines
close to the device as possible .
as possible .
Figure 42. Layout Example

TLV9061, TLV9062, TLV9064
13 Device and Documentation Support
13.1 Documentation Support

13.1.1 Related Documentation
Texas Instruments, TLVx313 Low-Power, Rail-to-Rail In/Out, 500-μV Typical Offset, 1-MHz Operational Amplifier
for Cost-Sensitive Systems
Texas Instruments, TLVx314 3-MHz, Low-Power, Internal EMI Filter, RRIO, Operational Amplifier
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
Texas Instruments, QFN/SON PCB Attachment
Texas Instruments, Quad Flatpack No-Lead Logic Packages
Texas Instruments, Circuit Board Layout Techniques
Texas Instruments, Single-Ended Input to Differential Output Conversion Circuit Reference Design
13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
TLV9061 Click here Click here Click here Click here Click here
13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

TLV9061, TLV9062, TLV9064
14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

PACKAGE OPTION ADDENDUM
www.ti.com 21-Apr-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TLV9061IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 1OAF Samples
TLV9061IDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 1CA Samples
TLV9061IDPWR ACTIVE X2SON DPW 5 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 CG Samples
TLV9061SIDBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1OEF Samples
TLV9062IDDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T062 Samples
TLV9062IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 T062 Samples
| NIPDAUAG
TLV9062IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 T062 Samples
| NIPDAUAG
TLV9062IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 TL9062 Samples
TLV9062IDSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T062 Samples
TLV9062IDSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T062 Samples
TLV9062IPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 TL9062 Samples
TLV9062SIDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 1TDX Samples
TLV9062SIRUGR ACTIVE X2QFN RUG 10 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 EOF Samples
TLV9064IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TLV9064D Samples
TLV9064IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TLV9064 Samples
TLV9064IPWT ACTIVE TSSOP PW 14 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 TLV9064 Samples
TLV9064IRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T9064 Samples
TLV9064IRUCR ACTIVE QFN RUC 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1DD Samples
TLV9064SIRTER ACTIVE WQFN RTE 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 T9064S Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 21-Apr-2023
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV9061, TLV9062, TLV9064 :
• Automotive : TLV9061-Q1, TLV9062-Q1, TLV9064-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Oct-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9061IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV9061IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV9061IDCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
TLV9061IDPWR X2SON DPW 5 3000 178.0 8.4 0.91 0.91 0.5 2.0 8.0 Q2
TLV9061SIDBVR SOT-23 DBV 6 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TLV9062IDDFR SOT-23- DDF 8 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
THIN
TLV9062IDGKR VSSOP DGK 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV9062IDGKT VSSOP DGK 8 250 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV9062IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV9062IDSGR WSON DSG 8 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV9062IDSGT WSON DSG 8 250 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2
TLV9062IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLV9062SIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV9062SIRUGR X2QFN RUG 10 3000 178.0 8.4 1.75 2.25 0.56 4.0 8.0 Q1
TLV9064IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
Pack Materials-Page 1
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9064IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV9064IPWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV9064IRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TLV9064IRUCR QFN RUC 14 3000 180.0 9.5 2.16 2.16 0.5 4.0 8.0 Q2
TLV9064SIRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV9061IDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV9061IDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV9061IDCKR SC70 DCK 5 3000 190.0 190.0 30.0
TLV9061IDPWR X2SON DPW 5 3000 205.0 200.0 33.0
TLV9061SIDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0
TLV9062IDDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0
TLV9062IDGKR VSSOP DGK 8 2500 356.0 356.0 35.0
TLV9062IDGKT VSSOP DGK 8 250 356.0 356.0 35.0
TLV9062IDR SOIC D 8 2500 356.0 356.0 35.0
TLV9062IDSGR WSON DSG 8 3000 210.0 185.0 35.0
TLV9062IDSGT WSON DSG 8 250 210.0 185.0 35.0
TLV9062IPWR TSSOP PW 8 2000 356.0 356.0 35.0
TLV9062SIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0
TLV9062SIRUGR X2QFN RUG 10 3000 205.0 200.0 33.0
TLV9064IDR SOIC D 14 2500 356.0 356.0 35.0
TLV9064IPWR TSSOP PW 14 2000 366.0 364.0 50.0
TLV9064IPWT TSSOP PW 14 250 366.0 364.0 50.0
TLV9064IRTER WQFN RTE 16 3000 367.0 367.0 35.0
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV9064IRUCR QFN RUC 14 3000 205.0 200.0 30.0
TLV9064SIRTER WQFN RTE 16 3000 367.0 367.0 35.0
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA
1 5
2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)
4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00
1.45
0.90
0 -10
0.25
GAGE PLANE 0.22
TYP
0.08 0 -10
8
TYP 0.6
0 TYP SEATING PLANE
0.3
0 -10
0 -10
ALTERNATIVE PACKAGE SINGULATION VIEW
4214839/H 09/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
(R0.05) TYP (2.6)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/H 09/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/H 09/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)

www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
www.ti.com
GENERIC PACKAGE VIEW
DSG 8 WSON - 0.8 mm max height
2 x 2, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A SCALE 5.500
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2.1 B
A
1.9
0.32
PIN 1 INDEX AREA 0.18
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE

TYPICAL
0.8 C
0.7
SEATING PLANE
0.05 SIDE WALL
0.08 C
0.00 METAL THICKNESS
DIM A
OPTION 1 OPTION 2
0.1 0.2
EXPOSED
THERMAL PAD 0.9 0.1 (DIM A) TYP
4 5
6X 0.5
2X
9
1.5 1.6 0.1
8
1
PIN 1 ID 0.32
8X
(45 X 0.25) 0.4 0.18
8X
0.2 0.1 C A B
0.05 C
4218900/E 08/2022
NOTES:
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
DSG0008A WSON - 0.8 mm max height
(0.9) ( 0.2) VIA

8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM 9
(1.6)
6X (0.5)
5
4
(R0.05) TYP SYMM
(1.9)

SCALE:20X
0.07 MAX 0.07 MIN

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
DSG0008A WSON - 0.8 mm max height
8X (0.5) SYMM METAL

1
8
8X (0.25)
(0.45)
SYMM
9
6X (0.5) (0.7)
5
4
(R0.05) TYP (0.9)
(1.9)

EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
C
6.6 SEATING PLANE
TYP
6.2
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
3.1 2X
2.9
NOTE 3 1.95
4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.75 0.15
0 -8 0.05
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
per ASME Y14.5M.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
PW0008A TSSOP - 1.2 mm max height
8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8
SYMM
6X (0.65)
5
4
(5.8)

SCALE:10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK
0.05 MAX 0.05 MIN


DEFINED DEFINED
SOLDER MASK DETAILS

NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)

www.ti.com
PW0008A TSSOP - 1.2 mm max height
8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8
SYMM
6X (0.65)
5
4
(5.8)

SCALE:10X
4221848/A 02/2015
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
RUC0014A X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
2.1 A
B 1.9

1.9
0.4 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 0.4 (0.15) TYP

6 7
8X 0.4
5
8
SYMM
1.6
12
1
14 13 14X 0.25
0.15
PIN 1 ID SYMM
(45oX0.1) 14X 0.5 0.1 C A B
0.3
0.05 C
4220584/A 05/2019
NOTES:
per ASME Y14.5M.
www.ti.com
SYMM
14X (0.6)
14X (0.2)
8X (0.4) SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)

EXPOSED METAL SHOWN
SCALE: 23X
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND SOLDER MASK
METAL
OPENING
EXPOSED METAL SOLDER MASK EXPOSED METAL METAL UNDER

OPENING SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220584/A 05/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
SYMM
14X (0.6)
14X (0.2)
8X (0.4) SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)

BASED ON 0.100mm THICK STENCIL
SCALE: 23X
4220584/A 05/2019
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
DBV0006A SCALE 4.000
3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA
1
6
2X 0.95
3.05
2.75
1.9 5
2
4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
1.45 MAX
0 -10
0.25
GAGE PLANE 0.22
TYP 0 -10
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
0 -10
-10 -10
ALTERNATIVE PACKAGE SINGULATION VIEW
4214840/D 09/2023
NOTES:
per ASME Y14.5M.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
www.ti.com
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X (0.95)
3 4
(R0.05) TYP (2.6)

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING SOLDER MASK
0.07 MAX 0.07 MIN

ARROUND ARROUND

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/D 09/2023
NOTES: (continued)

www.ti.com
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X(0.95)
3 4
(R0.05) TYP
(2.6)

SCALE:15X
4214840/D 09/2023
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
C
5.05
TYP SEATING PLANE
4.75
A PIN 1 ID 0.1 C
AREA
8X 0.5
10
1
3.1
2.9 2X
NOTE 3 2
5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4
0.23
TYP
SEE DETAIL A 0.13
0.25
GAGE PLANE
0.7 0.15
0 -8 0.05
0.4
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
per ASME Y14.5M.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
DGS0010A VSSOP - 1.1 mm max height
10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10
SYMM
8X (0.5) 5 6
(4.4)

SCALE:10X

METAL OPENING
OPENING SOLDER MASK
0.05 MAX 0.05 MIN


DEFINED DEFINED
SOLDER MASK DETAILS

NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)

www.ti.com
DGS0010A VSSOP - 1.1 mm max height
10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10
SYMM
8X (0.5)
5 6
(4.4)

SCALE:10X
4221984/A 05/2015
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
DPW0005A SCALE 12.000
X2SON - 0.4 mm max height
0.85 A
B
0.75

0.75
0.4 MAX C
SEATING PLANE
NOTE 3
(0.1)
4X (0.05) (0.324) 0.05

0.00
2 0.25 0.1
4
NOTE 3
2X 3
2X (0.26)
0.48
5
1
0.27
0.239 4X
0.17
0.139
0.1 C A B
0.288
3X 0.05 C
0.188
4223102/D 03/2022
NOTES:
per ASME Y14.5M.
3. The size and shape of this feature may vary.
www.ti.com
DPW0005A X2SON - 0.4 mm max height
(0.78)
SYMM ( 0.1)
4X (0.42) VIA 0.05 MIN
ALL AROUND
1 TYP
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2 4
(R0.05) TYP
SOLDER MASK
4X (0.06) OPENING, TYP
( 0.25)
(0.21) TYP METAL UNDER
EXPOSED METAL SOLDER MASK
CLEARANCE TYP

SOLDER MASK DEFINED
SCALE:60X
4223102/D 03/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
DPW0005A X2SON - 0.4 mm max height
4X (0.42) 4X (0.06)
5
4X (0.22) 1
( 0.24)
4X (0.26)
SYMM
(0.21) (0.48)
TYP
SOLDER MASK
EDGE 3
2
4
(R0.05) TYP
SYMM
(0.78)

EXPOSED PAD 3
SCALE:100X
4223102/D 03/2022
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA
1 5
2X 0.65 NOTE 4
2.15
1.3 (0.15) 1.3
2 1.85
(0.1)
4
0.33 3
5X
0.23
0.1
0.1 C A B (0.9) TYP
0.0
0.15
GAGE PLANE 0.22
TYP
0.08
8 0.46
TYP TYP
0 0.26
SEATING PLANE
4214834/C 03/2023
NOTES:
per ASME Y14.5M.
4. Support pin may differ or may not be present.
www.ti.com
DCK0005A SOT - 1.1 max height
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
2X (0.65)
3 4
(R0.05) TYP (2.2)

EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING SOLDER MASK
0.07 MAX 0.07 MIN

ARROUND ARROUND

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)

www.ti.com
DCK0005A SOT - 1.1 max height
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
2X(0.65)
3 4
(R0.05) TYP
(2.2)

BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
DDF0008A SCALE 4.000
PLASTIC SMALL OUTLINE
C
2.95 SEATING PLANE
TYP
2.65
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
2.95
2.85 2X
NOTE 3 1.95
4
5
0.38
8X
0.22
1.65 0.1 C A B
B 1.1 MAX
1.55
0.20
TYP
0.08
SEE DETAIL A
0.25
GAGE PLANE
0.1
0 -8 0.6 0.0
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
per ASME Y14.5M.
www.ti.com
DDF0008A SOT-23 - 1.1 mm max height
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP (2.6)

SCALE:15X

METAL OPENING
OPENING SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)

www.ti.com
DDF0008A SOT-23 - 1.1 mm max height
8X (1.05) SYMM
(R0.05) TYP
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)

SCALE:15X
4222047/C 10/2022
NOTES: (continued)
www.ti.com
GENERIC PACKAGE VIEW
RTE 16 WQFN - 0.8 mm max height
3 x 3, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C SCALE 3.600
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.1 B
A
2.9
PIN 1 INDEX AREA

3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1 OPTION 2
0.1 0.2
C
0.8 MAX
SEATING PLANE
0.05
0.00 0.08
1.68 0.07 (DIM A) TYP

5 8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X 17 SYMM
1.5
1
12
0.30
16X
0.18
PIN 1 ID 16 13 0.1 C A B
(OPTIONAL) SYMM
0.05
0.5
16X
0.3
4219117/B 04/2022
NOTES:
per ASME Y14.5M.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
RTE0016C WQFN - 0.8 mm max height
( 1.68)
SYMM
16 13
16X (0.6)
1
12
16X (0.24)
17 SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
( 0.2) TYP
VIA
5 8
(R0.05) (0.58) TYP
ALL PAD CORNERS
(2.8)

EXPOSED METAL SHOWN
SCALE:20X
0.07 MAX 0.07 MIN

SOLDER MASK
METAL OPENING
EXPOSED EXPOSED
SOLDER MASK METAL METAL UNDER
METAL
OPENING SOLDER MASK
NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
RTE0016C WQFN - 0.8 mm max height
( 1.55)
16 13
16X (0.6)
1
12
16X (0.24)
17 SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5 8
SYMM
(R0.05) TYP
(2.8)

EXPOSED PAD 17:

SCALE:25X
4219117/B 04/2022
NOTES: (continued)
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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TLV9061, TLV9062, TLV9064

TLV906xS 10-MHz, RRIO, CMOS Operational Amplifiers for Cost-Sensitive Systems

2 Applications SOT-23 (5) 1.60 mm × 2.90 mm

• Barcode scanners SOIC (14) 8.65 mm × 3.91 mm

Single-Pole, Low-Pass Filter

Changes from Revision I (May 2019) to Revision J Page

Changes from Revision H (April 2019) to Revision I Page

• Added DDF (SOT-23) thermal information to replace TBDs ................................................................................................ 13

Changes from Revision G (December 2018) to Revision H Page

• Added SOT-23 (8) information to Device Information ........................................................................................................... 1

2 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated

Product Folder Links: TLV9061 TLV9062 TLV9064

Changes from Revision F (September 2018) to Revision G Page

Changes from Revision E (July 2018) to Revision F Page

• Deleted Shutdown part numbers from datasheet header ..................................................................................................... 1

Changes from Revision D (June 2018) to Revision E Page

• Added TLV9061S device to Device Information table............................................................................................................ 1

Changes from Revision C (March 2018) to Revision D Page

• Added shutdown suffix to "TLV906x" to document title.......................................................................................................... 1

Copyright © 2017–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

• Added Shutdown Function section ...................................................................................................................................... 25

Changes from Revision B (October 2017) to Revision C Page

Changes from Revision A (June 2017) to Revision B Page

• Added 8-pin PW package to Pin Configuration and Functions section ................................................................................. 7

Changes from Original (March 2017) to Revision A Page

• Changed device status from Advance Information to Production Data ................................................................................. 1

4 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated

Product Folder Links: TLV9061 TLV9062 TLV9064

6 Device Comparison Table

Copyright © 2017–2019, Texas Instruments Incorporated Submit Documentation Feedback 5

7 Pin Configuration and Functions

TLV9061 DBV, DRL Packages

TLV9061 DPW Package

Pin Functions: TLV9061

6 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated

Product Folder Links: TLV9061 TLV9062 TLV9064

TLV9061S DBV Package

Pin Functions: TLV9061S

TLV9062 D, DGK, PW, DDF Packages

(1) Connect thermal pad to V–

Pin Functions: TLV9062

Copyright © 2017–2019, Texas Instruments Incorporated Submit Documentation Feedback 7

TLV9062S DGS Package

IN1+ 3 8 IN2± V± 1 9 IN1±

SHDN1 5 6 SHDN2 SHDN1 2 8 OUT1

8 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated

Product Folder Links: TLV9061 TLV9062 TLV9064

IN1+ 3 12 IN4+ IN1± 1 12 IN4±

(1) Connect thermal pad to V–

Pin Functions: TLV9064

Copyright © 2017–2019, Texas Instruments Incorporated Submit Documentation Feedback 9

Pin Functions: TLV9064 (continued)

10 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated

Product Folder Links: TLV9061 TLV9062 TLV9064

TLV9064S RTE Package

(1) Connect thermal pad to V–

Pin Functions: TLV9064S