A Four-Channel GNSS Front-End IC for a Compact

Interference- and Jamming-Robust Multi-Antenna

Galileo/GPS Receiver

Eric Schäfer1, Safwat Irteza2, André Jäger1, Björn Bieske1, André Richter1, Muhammad Abdullah Khan1,*,
Muralikrishna Sathyamurthy1, Sebastian Kerkmann1, Alexander Rolapp1, Eckhard Hennig1, and Ralf Sommer1
1
IMMS Institut für Mikroelektronik- und Mechatronik-Systeme gemeinnützige GmbH, Ilmenau, Germany,
*
now with RWTH Aachen University, Aachen, Germany,
2
RF and Microwave Research Laboratory, Ilmenau University of Technology, Ilmenau, Germany

Abstract—We present a four-channel GNSS front-end IC for compact 2×2-antenna Galileo E1-B/C and GPS L1 receiver for
a compact interference- and jammer-robust multi-antenna sub- future handheld devices. Our system incorporates novel
sampling receiver for Galileo E1-B/C and GPS L1 signals. The concepts to reduce the size of the antenna array and the front-
front end includes four coherent RF-to-IF signal paths with an end circuitry significantly as well as to improve the
intermediate frequency of 75.42 MHz, a common PLL frequency interference robustness of the receiver [2]. As per the authors’
synthesizer, which generates the 1500-MHz local-oscillator best knowledge, a monolithically integrated multi-channel
signal, and an I2C interface for parameter adjustment. The front GNSS front end for beamforming purposes has not been
end exhibits a gain of 83 dB, a noise figure of 2.8 dB, and an presented in the literature yet.
input-referred 1-dB compression point of −73.5 dBm preventing
the front end from saturation while jammed. A path-to-path In Section II, we summarize the concept behind the new
isolation of at least 30 dB leads to a high spatial resolution. The receiver system. A detailed description of the front-end IC is
power consumption is 231.7 mW and 255.7 mW with and without given in Section III. In Section IV, we present the main results
interferers, respectively. of the evaluation-board and outdoor measurements. Finally,
conclusions are drawn in Section V.
Keywords—antenna arrays; mutual coupling; radio-frequency
integrated circuits; satellite navigation systems
II. SYSTEM CONCEPT
I. INTRODUCTION The compactness of the new receiver system is achieved by
reducing the size of the single antenna elements and the front
The integration of global navigation satellite system ends as well as the distances between them. This implies
(GNSS) receivers in handheld devices, e.g. mobile phones or additional challenges, mainly mutual coupling between the
tablet computers, enables its application software to access the antenna elements, which are solved by a combination of
user’s position and velocity data. With current state-of-the-art hardware and software techniques [2].
navigation receivers, unwanted interferences from nearby radio
services, or intended jamming, e.g. through personal privacy
devices (PPDs), can lead to incorrect position, velocity, or time
information, which might cause inconvenient or even
dangerous situations in safety-critical applications, as shown in
Fig. 1.
Conventional single-antenna receivers, which are small
enough to fit into handheld devices, only allow for certain
enhancements in terms of multi-path, interference, and jammer
suppression by using digital signal processing techniques.
Multi-antenna receivers, however, benefit from digital
beamforming algorithms for suppressing unwanted signals and
increasing the gain in the direction of the desired satellites.
Multi-antenna solutions have been known for many years and
have already been successfully implemented in GNSS
receivers [1].
The main problem of today’s multi-antenna systems is the Fig. 1. Interferences from other radio services, nearby jammers, and multi-
large area required for the antenna array. In this paper, we path components disturb the acquisition and tracking of navigation satellites
present a four-channel GNSS front-end IC as part of a new and lead to incorrect position, velocity, or time information.

978-1-4799-6529-8/14/$31.00 ©2014 IEEE

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 DC ADC an integer-N PLL with a divider ratio of 150 can be employed.
Antenna Array

Visualization and
The resulting image and half-IF bands that might mix into our

Back-end PC
ADC
DMN
Front End IF band are mainly allocated to radio-astronomy services, i.e.,

FPGA
ADC they are free of high-power signals.
ADC Based on published figures for conventional GNSS
receivers, we aim for a front-end noise figure below 4 dB.
Upconverter DAC
Since the signal-to-noise ratio strongly depends on the antenna
characteristics, the direction-of-arrival of the signal and
Fig. 2. Block diagram of the complete system. interference components, and the beamforming configuration,
a classical minimum-required front-end noise figure cannot be
Fig. 2 illustrates the new hardware architecture. The highly calculated a priori for diversity receivers with mutually
coupled antenna reception patterns are decomposed by a coupled antennas. However, the DMN simplifies this situation
passive decoupling and matching network (DMN) into an and allows for a noise budget allocation [8]. Based on
orthogonal subspace of beams [3]. The front end converts the measurements of antenna array, DMN, and DC, we assume a
received RF signals, including high-power interferences, into total equivalent noise temperature for the antenna array, the
the IF domain where they can be digitized and processed with DMN, and the directional couplers of 290 K. If we neglect the
an FPGA. The FPGA also generates an additional spreading array gain of the antenna, a front-end noise figure of 4 dB
code that is up-converted to RF and injected into the receiver corresponds to a minimum carrier-power-to-noise-power-
paths via directional couplers (DC) in order to calibrate the spectral-density ratio (C/N0) of about 43 dBHz, which is 5 dB
phase differences between the receiver paths [4]. The external better than the target limit of 38 dBHz, sometimes assumed as
upconverter is supplied with the front-end’s LO signal. the acquisition limit for GPS L1 signals.
In the digital domain, beamforming is used before and after
correlation with the satellite spreading codes in order to III. FRONT-END IC
mitigate high-power interferers and multi-path components,
The main part of the front end is implemented in a
respectively [5]. Since each output of the network represents a
commercial 180-nm 1P6M silicon CMOS process. Fig. 4
different orthogonal beam, the digital beamforming algorithms
shows the block diagram. We use an external SAW filter for
must operate in the beam space rather than in the usual element
pre-selection of the RF band (RFF). In order to reduce the out-
space [6].
of-band noise before sampling, we employ an external high-Q
Compared to conventional single-antenna receivers, we IF filter (IFF), since an integrated IF filter with the required
increase the dynamic range of the new receiver to avoid transition steepness would be too noisy.
saturation of the system due to high-power signals. Our
objective is to remain operable with a maximum in-band A. Signal Path
interference power of about −80 dBm at the antenna outputs, The input of the front-end IC consists of an LNA followed
which defines the minimum input-referred 1-dB compression by the external RF filter (RFF). Compared to architectures with
point of the front end. Since the received satellite power is leading RFF, two additional 50-Ω ports are necessary, and the
about −127 dBm [7], a discrete 14-bit analog-to-digital first LNA must be robust against high-power out-of-band
converter (ADC) is employed. The six least significant bits are interferers. However, the advantage in the over-all noise figure
covered with the receiver noise, including the satellite signals, justifies the effort. A second LNA meets the 50-Ω matching
while the eight remaining bits are reserved for high-power requirement of the RFF, and, moreover, converts the received
interferences. The full-scale input range of the ADC is 0 dBm. single-ended signal into a differential signal, which is robust
Hence, the total gain of the front end needs to be 80 dB plus against IC-internal supply noise. Both LNAs employ inductive
some variation in order to compensate gain of the DMN and source degeneration in cascode configuration [9], as shown on
the DC. A path-to-path isolation of at least 25 dB is required the left-hand side in Fig. 5.
for all signal-processing blocks following the DMN to
maintain the decoupling. The following mixer (MIX) is implemented as double-
balanced Gilbert cell with current bleeding and resistive load
The sampling frequency of the ADC is 104 MHz leading to [10]. The programmable-gain IF amplifier (IF PGA) comprises
an optimal IF for maximum bandwidth of either 26 MHz in two differential pairs, each with current-source load, common-
case of Nyquist sampling, or 78 MHz, 130 MHz, and 182 MHz drain output stage, and common-mode feedback (CMFB). The
in case of sub-sampling, as shown in Fig. 3. Higher frequencies gain can be adjusted through a 4-bit tunable resistor in order to
would be outside of the ADC bandwidth. An IF of 78 MHz is a
good compromise between the influence of the phase noise of
PSD Nyquist band Subsampling bands
the PLL and the implementation costs for the high operation
frequency of the IF stages. For the front-end IC, we selected a
slightly lower IF of 75.42 MHz, which shifts the required
signal frequency of the local oscillator (LO) to 1500 MHz. This f (MHZ)
26 52 78 104 130 156 182 204
simplifies the PLL significantly without causing new fs/2 fs 3/2 fs 2fs
shortcomings. In order to perform carrier-phase tracking, all
oscillator signals in the complete receiver system have to be Fig. 3. Selection scheme for the intermediate frequency. Gray boxes: ideal IF
derived from a common 10-MHz reference oscillator. Hence, bands with respect to the given ADC of the data-acquisition platform.

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 RFF RFF

MCU

LNA2 LNA2
RF3 LNA1 I2C INTERFACE LNA1 RF2

Signal RF
LO LO
RF Signal
IFF
path 3 IF IF
path 2 IFF
LOB LOB
IF IF
IF3 IFA IFA IF2
PGA PGA

LO _ in VCO DIV PFD REF

50R

CP

LO _ o u t BUF PLL
IFF IFF

IF IF
IF0 IFA IFA IF1
PGA PGA
LOB LOB

Signal IF
LO LO
IF Signal
path 0 RF RF
path 1
RF0 LNA1 LNA1 RF1
LNA2 LNA2

RFF RFF

Fig. 4. Block diagram of the front-end IC and external signal-path components. The colored frame represents the pad ring of the IC.

compensate process variations and mismatch between the differences of the inductor. The loop filter can be tuned with
signal paths. The last amplifier (IFA) in the signal path is off-chip components. The gain of the IF PGA, the center
implemented with a class-AB output stage. It converts the frequency of the VCO, and the selection of the LO source are
signal back to single-ended and drives the following 50-Ω IFF. initially set to a default configuration at power-on and can be
adjusted afterwards over the I2C interface.
In order to facilitate high output power and to reduce the
coupling through the power supply, each IFA is provided with
a dedicated 3.3-V supply voltage. All stages are AC coupled. C. Layout
The bias voltages VB1-VB8 are derived either by diode- A microphotograph of the manufactured front-end IC is
connected MOSFETs or with resistive voltage dividers from shown in Fig. 6. The four individual signal paths are placed
the supply voltages. symmetrically in the corners of the IC in order to reduce
coupling through the inductors or the substrate of the chip. The
B. Frequency Synthesizer and Auxiliary Blocks five on-chip inductors shown in Fig. 5 are clearly visible in the
layout. The frequency synthesizer (PLL), including the
The mixers’ LO signal is synthesized with a conventional inductor of the VCO, is located on the center right-hand side of
integer-N PLL or, alternatively, could be provided externally. the IC. The chip size is 5×5 mm2, however, about 50 percent of
The PLL is optimized for low phase noise to reduce the the area, which is unframed in Fig. 6, is used for testing
influence of blocking and self-mixing. The center frequency of purposes only. All RF and IF signal pads are surrounded by
the voltage-controlled LC oscillator (VCO) is 3-bit adjustable ground pads in order to reduce the coupling between the bond
to compensate process variations and possible modeling wires.

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 LNA1 LNA2 MIX IF PGA (w/o CMFB) IFA
1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 3.3V 3.3V 3.3V 3.3V 3.3V

SAWI VB8

IN SAWO
off-chip

off-chip

4-bit

VB3 OUT

LOP LON LOP

VB3

VB2

VB7

VB4 VB4 VB5 VB5 VB6 VB6

VB1 VB2
GND GND GND GND GND GND GND GND GND GND

Fig. 5. Simplified schematic of the signal path. Current bleeding of MIX and second IF PGA stage are not shown.

evaluation board is shown in Fig. 7.

IV. EVALUATION BOARD AND MEASUREMENTS
Fig. 8 shows the measured gain and noise curves of the
The front-end IC was characterized on wafer level and evaluation board. We adjusted the gain via the GUI to 83 dB,
within an evaluation board, which implements an extended which is slightly above the required 80 dB. The IF PGA allows
version of the block diagram shown in Fig. 4. The board itself for a tuning range of the gain from about 60 dB to 100 dB. The
consists of a 10-mil RF substrate laminated on a 52-mil FR4 noise figure is 2.8 dB and 3.1 dB without and with IFF,
carrier substrate. Off-chip matching of the LNA is realized respectively. The complete evaluation board has an input-
with transmission lines and capacitors instead of lumped referred 1-dB compression point of −80.5 dBm and −73.5 dBm
inductors (as shown in Fig. 5) in order to minimize the losses without and with RFF, respectively as shown in measured
of the matching circuit. A micro-controller unit (MCU) is used curves in Fig. 9. The path-to-path isolation of the evaluation
to store different configurations and to setup the front end after board is in the range of 30 dB to 40 dB. Fig. 10 shows the
power-on independently. Using the USB interface of the MCU, worst-case, i.e. lowest, isolation between two adjacent signal
the front end can be configured directly via a dedicated paths.
graphical user interface (GUI) from a connected PC. The
The measured phase noise of the PLL is −107 dBc/Hz at
1 MHz offset from the LO frequency, which is sufficiently low
I2C that the influence of the VCO on the front-end noise figure is
negligible. The output power of the VCO buffer (BUF) is about
−20 dBm, which is enough to drive the external upconverter.
Signal path 3 Signal path 2 The power consumption of each signal path is 52.3 mW

USB

IF2
MCU
PLL
RFF RFF

IFF IFF
IF3
REF
IF0 IC
IFF IFF

Signal path 0 Signal path 1 RFF RFF

5V IF1

Fig. 6. Chip photograph of the front-end IC. The framed area contains the Fig. 7. Evaluation board with front-end IC under glob top in the center of the
active front-end components. Other structures are for characterization board. The RF inputs are mounted on the back side. Board size: 14×9 (cm)2.
purposes only. Die size: 5×5 (mm)2.

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Noise Figure /dB Gain /dB
12.00 86.00
TABLE I. PERFORMANCES OF THE EVALUATION BOARD
11.00 84.00
Parameter Spec Measured Unit
10.00 82.00
Gain 80 83 dB
9.00 80.00 Noise figure <4 2.8 dB
Input-referred 1-dB compression point > −80 −73.5 dBm
8.00 78.00 Path-to-path isolation > 25 30…40 dB
7.00 76.00
Intermediate frequency 75.42 75.42 MHz
LO power > 20 20 dBm
6.00 74.00 PLL phase noise at 1 MHz carrier offset 107 dBc/Hz
Power consumption 231.7 mW
5.00 72.00

4.00 70.00

3.00 68.00 environment, constellation of the satellites and the interferers,

2.00 66.00
and the used algorithms as well as the setup of the receiver, a
1545 MHz 6 MHz / DIV 1605 MHz simple quantitative figure of merit cannot be given and a
profound performance analysis is quite comprehensive.
Fig. 8. Gain and noise figure vs. frequency. Filled triangles: without IFF, Nevertheless, certainly some valid statements can be
blank triangles: with IFF.
mentioned here. The complete receiver was able to maintain a
without interference and 58.3 mW with a −80-dBm continuous C/N0 above 38 dBHz for one CW interferer with a jammer-to-
wave (CW) interference signal which is directly injected into signal-power ratio (JSR) of up to 45 dB. In case of three
the signal path’s RF input port. The PLL draws a power of spatially separated CW interferers, a C/N0 of 38 dBHz was
22.5 mW. A compilation of the specified and measured generally obtained with a maximum JSR of up to 30 dB, which
performances is given in Table I. is limited mainly due to the low efficiency of the compact
antenna array when nulling the maximum number of
The evaluation board has been successfully integrated into interferers. Further detailed measurement results for the
the complete receiver system, shown in Fig. 11. The front end complete receiver system can be found in [11].
is mounted into the antenna housing, which has a size of about
15×15 (cm)2. V. CONCLUSIONS
An outdoor measurement campaign with real Galileo/GPS We successfully implemented a robust front-end IC for
E1/L1-band satellite and terrestrial CW-jammer signals has compact multi-antenna GNSS receivers. It contains four
been carried out. Our demonstrator was able to acquire and coherent signal paths with reference-signal supply from a
track the satellites while a conventional low-cost single- common PLL frequency synthesizer. The front-end IC
antenna reference receiver completely lost them in the presence integrates the main components which are needed for RF and
of interferers. Since the quality of the received signals not only IF signal processing within a high-end multi-antenna GNSS
depends on the front-end performance but also on the receiver. While having a significantly reduced size compared

Fig. 9. Gain vs input power. Upper: with RFF, lower: without RFF. Fig. 10. Gain (marker 1) and isolation between two adjacent paths (delta
marker 2) vs. frequency. RFF and IFF included.

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to commercially available front-end solutions that employ
discrete components; the low noise figure, the high path-to- Antenna array and DMN
path isolation, and the high compression point are the achieved Evaluation board
key features that enable the suppression of multipath with front-end IC
components and high-power interferences.
Extensive lab and real-signal outdoor measurements have IF and reference signals
proven the feasibility of using low-cost CMOS technology to
meet the performance, space, and cost requirements of multi-
antenna GNSS receivers for future handheld devices. Next Graphical user
steps comprise the extension of the receiver to the safety-of-life interface
Galileo E5a/GPS L5 band and further reduction and shrinking
of peripheral components.

ACKNOWLEDGMENT Digital back-end PC

We gratefully acknowledge our project partners, especially with FPGA-based data
A. Dreher, M. A. Hein, R. Stephan, L. Kurz, M. Cuntz, acquisition platform
N. Basta as well as our colleagues D. Krauße, V. Nakov,
R. Pevgonen, D. Murugan, and S. Engelhardt for their valuable
suggestions, discussions, and assistance during the design and Fig. 11. Complete receiver system during outdoor measurement campaign.
the measurements.
[5] N. Basta et al., “System concept of a compact multi-antenna GNSS
This work has been carried out in the research project receiver,” in 7th German Microwave Conference (GeMiC), Ilmenau,
KOMPASSION that has been supported by the German Germany, Mar. 2012.
Aerospace Center (DLR) on behalf of the German Federal [6] H. L. Van Trees, Optimum Array Processing - Part IV of Detection,
Estimation and Modulation Theory, New York: John Wiley & Sons,
Ministry of Economics and Technology under grant 50 NA 2002.
1007 and 50 NA 1009.
[7] (2010, Sep.). Galileo OS SIS ICD. [Online]. Available:
http://ec.europa.eu/enterprise/policies/satnav/galileo/files/galileo-os-sis-
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