Unit 4: Design Vision Tutorial

Carlos Jesús Jiménez Fernández

Instituto de Microelectrónica de Sevilla / Universidad de Sevilla

Version 2.0, October 2023

Outline:

In this tutorial, we will see some more advanced aspects of design_vision:

• Initialization and basic configuration.

• Clock signals.
• Advanced optimization.
• Reports.
• Save the results.
• Command Mode: scripts.
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I. INITIALIZATION AND BASIC CONFIGURATION.

A. Before starting.

Following the recommendations of good practices, within the folder MHCAD create a subfolder
called “tema4” which is where you will be working in this tutorial.

In this tutorial we will use the description of a block cipher as a design example. Block ciphers
are circuits that use an n-bit message (plaintext) and an m-bit key to generate an encrypted message of
n bits (ciphertext). Specifically, we use the Present cipher, which is a lightweight cipher that encrypts
a 64-bit message using an 80-bit key. You can copy the Verilog source files from this location:

/mnt/cnm/master/MHCAD/tema4/Present_Block_Cipher.zip

When you unzip the file, the doc folder contains information about the cipher and the design.
The src folder contains the Verilog codes of Present and the tb folder contains a test_bench. The Present
cipher is designed with hierarchy. The top-level design is called "present_encryptor_top". The
hierarchy structure is shown in the next figure. You can find more information in the “Unit_4_Task”
document.

For this tutorial, each student needs a personal key. The design to use is the
“present_encryptor_top” with the student's personal key. You need to request the key by sending an
email to [email protected].

B. Questa-Modelsim functional simulation

Before synthesising, you must carry out a functional simulation and write down the values of the
encrypted output data (output_oo) and the time at which they change, in hexadecimal. This data will
be used later in this tutorial.

Follow the steps:

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 Create a modelsim folder.

 In this folder create a work library folder (vlib work) and map the folder with the work
logical library (vmap work work).
 Compile all the Verilog codes of the src folder (vlog command).
 Comple the testbench of the tb folder (vlog command).
 Carry out a simulation and write down the outputs values (vsim command).
In the file “present_encryptor_top.v” change the value of local_key with your personal key.
Repeat the simulation and write down the new values of the output.

I. RUN DESIGN_VISION

Create a folder named “design_vision” which will run the program with the same name.

Copy into the folder “design_vision” the Synopsys initialization file which is located in:

mnt/cnm/master/MHCAD/tema4/.synopsys_dc.setup

A. Reading the design and selection of “wire_loads”.

During optimisation, Design Vision needs to know both the delay of the cells and the
interconnections between the cells. Cell delays are relatively fixed. They depend on an intrinsic delay
and the number of connections that have their inputs and outputs (fan-in and fan-out). However,
interconnect delays cannot be accurately determined before Place & Route. The tool makes a
pessimistic estimate of these delays to ensure that the estimated delay is never greater than the delay
after place & route. Otherwise the circuit would malfunction.

The values of the interconnection delays are pre-calculated by the foundry and included in the
technology library. For larger designs, longer lengths of interconnection and therefore, longer delays.
Delay models are associated with area ranges in what is called “wire_load”.

We will make a test of how delays vary depending on the “wire_load” selected.

1) Start the Design Vision tool.

Move to the subdirectory created for this purpose and follow the steps and
recommendations from the previous tutorial.

2) Read all the Verilog files located in the src folder but the top level
(present_encryptor_top.v). After that, read the top level design. Make sure it is this design
that appears in the “logical hierarchy” window (left side of the screen).

3) Impose a restriction in the clock input of a maximum frequency of 10 ns.

Remember the steps in the previous tutorial. The clock signal name is “clk_i”.

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4) Optimize the design.

Design -> Compile Design...
(leave the default options).

5) Select the “present_encryptor_top” design (top level) and generates a report of the
maximum delay path. This can be done using the command:
Design Vision> report_timing
And gives the result in the message window. It can also be done graphically:
a) Opening a histogram of the “Path Slack”:
Timing -> Path Slack... (leave the defaults and press OK)
b) Selecting the worst Slack bar (the leftmost) and selecting in the right the path with more
slack. The windows opened is similar to this one:

c) Run the command:

Timing -> Report Timing Path... (leave the defaults and press OK)

6) Analyse the results:

Note that before beginning to specify the maximum delay path, in the report window
appears information appears of the “Wire Load Model”:

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As is not specified any delay model, Design Vision selects the most appropriate depending
on the number of cells.
Write down the maximum delay (“data arrival time”).

7) Change “wire_load” of both components. Do this by selecting each of them, giving it a

wire_load of “G5000K”

Attributes -> Operating Environtment -> Wire Load

8) Generates a new timing report. Check that you have changed the information on the “Wire
Load Model” and compare the value of the maximum delay with that obtained in the
previous case. You can find out this delay by running the command:
Design Vision> report_timing

9) Close the design_vision tool. que componentes? los dos bloques que estan en la
jerarquia?
me sale en en report present_encryptor_top y sbox16
solo veo que cambia el load del primero

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I. OPTIMIZATION OPTIONS.

A. Timing restrictions.

Let's try out some restriction options within Design_Vision. It is convenient to start with no
design loaded.

1) Starting the Design Vision tool.

2) Read the Verilog files for the Present Block Cipher. NO SE HACER ESTO
Follow another way to read the design. Use:
File -> Analyze (add all the designs in the src folder).
File -> Elaborate (write “WORK” in the Library area, and select as Design the top level
design).

3) Perform the optimization process (Design -> Compile Design) without introducing any
restriction.

4) See the result: the hierarchy levels are the same.

5) Generate a timing report. To do this, select the “top-level” design and run the command:
Design Vision> report_timing
Write the value of the data arrival time. Note that is a message “Path is unconstrained”.

6) Set the “clk_i” input as a clock signal with a period of 20 ns. (follow the steps in the
previous tutorial).

7) Without any optimization, generates a new timing report and compare the results with those
obtained previously.

Conclusion: In sequential circuits, in order to correctly estimate the maximum delay and
frequency of operation, the clock signal must be defined beforehand.

The slack is more than 18 ns, i.e. this is the time left to the circuit. The clock period can therefore
be reduced to 2 ns. We analyse both the maximum frequency that can be achieved and the area
consumed.

1) Generate a report area for the design optimized with a period of 20 ns.
Design -> Report Area...

2) Change the clock timing restriction to 2 ns.

3) Perform a new optimization.

el area no cambia al pasar de 20 a 2

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 para 20 ns data arrival: 1.21 slack 18.68
Unit 4: Design Vision Tutorial
para 2ns data arrival: 1.21 slack 0.68

4) Generates a new timing report and check whether they have achieved the desired results.

5) Generate a new report of area. para 1ns data arrival: 0.89 slack 0

6) Do the same with a clock timing restriction of 1 ns. Change the restriction and perform an
optimization. haciendo el slack patch para 1ns
Write down the area and the worst slack of this design. el peor es 5.5e-5

7) Save the results in Synopsys database format (DDC) with the name
“present_encryptor_top.1ns.ddc”. Be sure that the “Save all designs in hierarchy” is
selected.
el area paso de 7000 con algo a 9000 para
File -> Save As... el caso de 1 ns

Conclusion: If the time constraints imposed are higher frequency, the area of the circuit increases.

B. Check Design.

We will perform a design check to see if there have been errors during synthesis.

1) First we will see the description of the potential problems. We selected the highest
hierarchy design and execute:
Design -> Check Design...
We ensure that the option “Current level and all sub-designs” is selected”.

You can display the results in detail (the selected) or in reduced form (summary).

The messages displayed (in reduced form) are like:

Warning: In design 'key_update', input port 'data_i[76]' is connected directly to output port 'data_o[57]'.
(LINT-29)

Warning: In design 'permutation', input port 'data_i[58]' is connected directly to output port 'data_o[46]'.
(LINT-29)

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2) We analyse the messages. These are of two types:

- Messages unconnected nets.
- Messages of input ports connected directly to the output.

3) The unconnected nets messages are due to the fact that the original design has been modified
to include the key within the design itself. Therefore, we should not be concerned in this case.
So we will look at the second type of messages: The input ports connected directly to the output.
Open the schematic of the module sub_per_permutation. You will see something like:

That means that some bits of input A is connected directly to the output.

4) These connections may cause problems in some synthesis and place & route tools, so let's
remove them. The way is through a Design Vision configuration variable. For that we
execute the command:

Design Vision> set_fix_multiple_port_nets -feedthroughs

5) To be effective we have to carry out a new optimization.

6) Analyse the results. To do this, we run “Check Design” and see that such warnings have
disappeared. We also see that buffers have been added to the direct connections in the schematic.

7) Get a new Area report and the worst slack. Compare with previous results.

Conclusion: In order to solve this potential problem, additional buffers have been introduced,
which consume area and introduce some additional delay.
el diseño ahora ocupa 8442 y tiene una respuesta temporal
diferente caso 2ns
C. Area optimization: Working with hierarchies. mayor arrival menor slack
arrival:1.28 slack:0.61
We look now at area optimization. Design Compiler generated the smaller design that keep the
time constraints imposed. Therefore, one way to try to reduce the area is to dissolve the design
hierarchy. This way can eliminate unnecessary logic.

This step must be done very carefully as creating designs that are too large can increase the time
required for optimisation. Typically, some of the operators introduced by Design Vision are dissolved
at this stage, which should be done in the final optimisation step.

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There are several ways to dissolve the hierarchy:

a) It can dissolve the entire hierarchy by selecting the compilation option “Ungroup
All”:
Design -> Compile Design...
b) Selectively, choosing the blocks you want to dissolve in the area of “Logical
Hierarchy” and with the right button by selecting “Ungroup”. In the window that
appears we have different options:
- All cells
- Selected cells
- Those blocks with a number of cells lower than a given number.

In our case, we dissolve the hierarchy of all components and check the effect on the area. There
should be no change in frequency, as the clock restriction has not been changed.

1) Before starting we check the area of the design:

Design -> Report Area...
Leave the default options.

2) Write down the result (number of nets, cells and area).

3) Make a new optimization where we select the option “Ungroup All”.

We check that after optimization the hierarchy has disappeared.

4) Generate a new area report and a timing report. Check that the area has been reduced slightly
and that the circuit meets the timing constraints.

las restricciones temporales se mantienen y el area disminuyo a 7900

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IV. REPORTS.

The available reports are located under the Design menu and the Timing menu:

The Design menu contains design reports (area, cells, etc.) and the Timing menu contains timing
reports. All reports can also be generated by typing the appropriate commands. Some other commands
and options not available from the menus are available in command mode.

You can open a help for an explanation of commands by:

Help -> Man Pages

Open man page and see the commands report_design and report_timing. Try using different
options seeing the results it produces.

V. SAVE THE RESULTS.

The results obtained after synthesis can be saved in different formats, independent of the source
format. The most common are three: DDC, VHDL and Verilog.

The "DDC" format is the Design Compiler database. It is very useful if you have not yet
completed the synthesis optimisation process and want to continue at another time. Its generation and
subsequent loading is very fast. It also serves as a backup.

The VHDL format is used to perform post-synthesis simulations. It is often useful if the input
format is also VHDL, since the same simulation environment is used, so that the test_bench used for

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the RTL design can be reused and the results obtained from post-synthesis simulations can be
compared with those obtained from RTL simulations. The use of the "SDF" file is required to obtain
correct delay values.

The Verilog format is also used to perform post-synthesis simulations, but is also the input format
for some place & route tools. As in the case of VHDL, its use in post-synthesis simulation is very
useful for designs described in Verilog at RT level. In these cases it is possible to reuse the test benches
and compare the results.

Before saving the design in VHDL or Verilog format, you should ensure that the cell and
component names comply with the requirements of these languages. Internal signals generated by
Design Vision may have names that are not accepted in these languages. To do this, select the top level
design and run Design Vision in the command window:

Design Vision> change_names -rules verilog -hierarchy -verbose

(when saving in verilog format)

Design Vision> change_names -rules vhdl -hierarchy -verbose

(when saving in VHDL format)

Generate the following files:

• Design database format:

File -> Save As...
Choose “ddc” format and the name present_encryptor_top.1ns_flat.ddc
• Verilog format:
File -> Save As...
Choose Verilog format and the name present_encryptor_top.1ns_flat.v
• Delay file “SDF”. To do this run the command:
Design Vision> write_sdf present_encryptor_top.1ns_flat.sdf

• Restrictions file (used in place & route tool). In the command window run:
Design Vision> write_sdc present_encryptor_top.1ns_flat.sdc

VI. COMMAND MODE: SCRIPTS

All commands that can be executed in graphical form, and many more, can be executed from the
"dc_shell" window. This can be done without starting the graphical environment (using the command
dc_shell unix) or by opening the command window from the graphical environment). The Design
Vision script usually has a .tcl extension.

There are two tabs at the bottom left of the window: "Log, which is usually selected, and History.
If you select the History tab, all the commands executed during the session will appear in the window.

no hice esto del script hay que ver con el profe por si acaso

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This is useful for creating a script that runs automatically, without the need to enter the entire synthesis
and optimisation process in the graphical environment.

To complete this tutorial, you will need to generate a script that does the following:

• - Read the design present_encryptor_top.v and all its components.

• - Introduce a clock constraint of 5 ns on the clock signal (clk_i).

• - Perform optimisation using the default options.

• - Generate a timing report and an area report. Save both reports to files.

• - Change net names to follow Verilog rules.

• - Save the results in DDC and Verilog formats and generate the SDF and SDC files.

The names of the files must be present_encryptor_top.5ns and the appropriate extension. The
extension of the script file should be “.tcl”. Once you have created the script, you can test it by running
it with the command.

File -> Execute Script

NOTE: The files generated for this script will be used in the next unit.

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