Ex.

No: 1 Synthesize and implement Combinational and

Sequential Circuits in VERILOG HDL

Aim:

To Synthesize and implement Combinational and Sequential Circuits in VERILOG / VHDL

SOFTWARE REQUIRED:

 Xilinx ISE Design Suite 6.1

Theory:

SYNTHESIS

Synthesis is the process of converting a high-level description of design (Verilog/VHDL)

into an optimized gate-level representation. Logic synthesis uses a standard cell library which
have simple cells, such as basic logic gates like AND, OR, and NOR, or macro cells, such as adder,
muxes, memory, and flip-flops. Standard cells put together are called technology library. Normally
the technology library is known by the transistor size (eg. 65nm). Usually, a circuit description is
written in Hardware Description Language (HDL), such as Verilog. There are different topologies
that can be applied for the same design. There are different approaches for designing a large
system. One of the approaches is bottom up, i.e. start with the smallest module of the system and
individually test them using test benches to make sure proper operation before integrating them
into higher level modules.
COMBINATIONAL CIRCUIT:
 The output of a Combinational Circuit depends entirely on the present input.
 It exhibits a faster speed.
 It is comparatively easier to design.
 No feedback is present between the input and output.
 The combinational circuit depends on time.
 Logic gates form the building blocks of such circuits.
 One can make use of it for both boolean and arithmetic operations.
 They don’t hold the capacity of storing any state.
 These circuits do not have a clock- thus, they don’t require triggering.
 They do not possess any memory element.
 Users can feasibly use as well as handle them
 Example – Demultiplexer, Multiplexer, Decoder, Encoder, etc.
SEQUENTIAL CIRCUIT :
 The output of a Sequential Circuit depends on both- past as well as present inputs.
 It works at a comparatively slower speed.
 The design of these circuits is comparatively much tougher than the Combinational
 Circuit.
 A feedback path exists between the output and the input.
 The circuit is time-dependent.
 Flip-flops constitute the building blocks of such a circuit.
 People mainly use them for storing data and information.
 They possess the capability of storing any data state or retaining an earlier state at anygiven
point. Because a Sequential circuit depends on a clock, it usually requires triggering
 They always possess a memory element.
 A user may not be able to handle and use these circuits easily.
 For Example – Counters, Flip-flops, etc

VERILOG is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a

digital system like a network switch or a microprocessor or a memory or a flip−flop. It means, by
using a HDL we can describe any digital hardware at any level. Designs, which are described in
HDL are independent of technology, very easy for designing and debugging, and are normally
more useful than schematics, particularly for large circuits. Verilog supports a design at many
levels of abstraction. The major three are
 Behavioral level
 Register-transfer level
 Gate level
Behavioral level
This level describes a system by concurrent algorithms (Behavioural). Every algorithm is
sequential, which means it consists of a set of instructions that are executed one by one. Functions,
tasks and blocks are the main elements. There is no regard to the structural realization of the
design.
Register−Transfer Level
Designs using the Register−Transfer Level specify the characteristics of a circuit using operations
and the transfer of data between the registers. Modern definition of an RTL code is "Any code that
is synthesizable is called RTL code".
Gate Level
Within the logical level, the characteristics of a system are described by logical links and their
timing properties. All signals are discrete signals. They can only have definite logical values (`0',
`1', `X', `Z`). The usable operations are predefined logic primitives (basic gates). Gate level
modelling may not be a right idea for logic design. Gate level code is generated using tools like
synthesis tools and his netlist is used for gate level simulation and for backend

Procedure:
1.Start theXilinxISE by using Start>Program files> XilinxISE> project navigator
2. Click File>New Project
3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbolof FPGAdevice and then right click>click on new source.
6. Select the Verilog Module and give the filename>click next and define ports >click next and
finish.
7. Type the Verilog Code in Verilog Editor.
8. Run theCheck syntax>Process window >synthesize>double click check syntax.If any errors
found then remove the errors with proper syntax &coding.
9. Click on the symbol of FPGA device and then right click>click on new source.
10. Select the Test Bench Waveform and give the filename>select entity click next and finish.
11. Select the desired parameters for simulating your design.In this case combinational circuit and
simulation time click finish.
12. Assign all input signal using just click on graph and save file.
13. From the source process window. Click Behavioral simulation from drop-down menu 14. Select
the test bench file (.tbw) and click process button>double click the Simulation Behavioral Model
15. Verify your design in wave window by seeing behavior of output signal with respect to input
signal
CODE:
To synthesis and implement the following combinational circuit using data flow or gate level
modelling along with their test bench.

a. Basic Gates

b. Half-Adder and Full-Adder

c. Half-Subtractor and Full-Subtractor

d. 2:4 Decoder
e. 8:3 Encoder

f. Parity Checker

g. 8:1 Multiplexer

h. 1:4 De-multiplexer

i. Binary to gray converter

j. Gray to binary convertor

k. 2 bit magnitude comparator

 Ex No 1.(a) BASIC GATES
Aim:
Realize the Basic gates using Verilog HDL.
Apparatus Required:
Synthesis tool: Xilinx ISE.
Simulation tool: ModelSim Simulator
Theory:
AND Gate is a circuit which performs, one of the basic logical or switching operation, namely AND
operation. It has N inputs (N ≥ 2) and one output. Digital signals are applied at the input terminals A, B,
C…N. The output is obtained at the output terminal marked Y and it is also a digital signal. The AND
operation is defined as: the output of an AND gate is 1 if and only if all the inputs are 1. Mathematically, it is
written as
Y = A AND B AND C… AND N
where A, B, C … N are the input variables and Y is the output variable.
OR Gate is a circuit which performs, one of the basic logical or switching operation, namely the OR
operation. It has N inputs (N ≥ 2) and one output. Digital signals are applied at the input terminals A, B,
C…N. The output is obtained at the output terminal marked Y and it is also a digital signal. The OR operation
is defined as: the output of an OR gate is 0 if and only if all the inputs are 0. Mathematically, it is written as
Y = A OR B OR C… OR N
where A, B, C … N are the input variables and Y is the output variable.
NAND Gate is a circuit which performs, the logic or Boolean operation derived from the basic logic
operations NOT and AND, namely the NAND operation. It has N inputs (N ≥ 2) and one output.
Digital signals are applied at the input terminals A, B, C…N. The output is obtained at the output
terminal marked Y and it is also a digital signal. The NAND operation is defined as: the output of an
NAND gate is 0 if and only if all the inputs are 1. It is the inverse of the AND operation. The NAND
gate is known to be one of the Universal gates. Mathematically, it is written as
________
Y=AB…N
where A, B, C … N are the input variables and Y is the output variable
NOR Gate is a circuit which performs, the logic or Boolean operation derived from the basic logic
operations NOT and OR, namely the NOR operation. It has N inputs (N ≥ 2) and one output. Digital
signals are applied at the input terminals A, B, C…N. The output is obtained at the output terminal
marked Y and it is also a digital signal. The NOR operation is defined as: the output of an NOR gate
is 1 if and only if all the inputs are 0. It is the inverse of the OR operation. The NOR gate is known
to be one of the Universal gates. Mathematically, it is written as
___________
Y = A +B+ … +N
where A, B, C … N are the input variables and Y is the output variable
NOT Gate is a circuit which performs, the one of the basic logic or Boolean operation, namely the
NOT operation. It has one input and one output. Digital signal is applied at the input terminal A.
The output is obtained at the output terminal marked Y and it is also a digital signal. The NOT
operation is referred to as Inversion or Complementation. Mathematically, it is written as Y = NOT
A.
where A is the input variable and Y is the output variable
Truth Table for AND Gate :

INPUT OUTPUT
A B QN+1
0 0 0
0 1 0
1 0 0
1 1 1
Logic Diagram for AND Gate:

Waveform for AND Gate :

Truth Table for OR Gate :

INPUT OUTPUT
A B QN+1
0 0 0
0 1 1
1 0 1
1 1 1

Logic Diagram for OR Gate :

Waveform for OR gate :

XNOR Gate or EX-NOR Gate or Exclusive-NOR Gate is a circuit which performs, the logic or
Boolean operation derived from the basic logic operations AND, OR and NOT or the Universal gates
NAND or NOR, namely the XNOR operation. It has N inputs (N ≥ 2) and one output. Digital signals
are applied at the input terminals A, B, C…N. The output is obtained at the output terminal marked
Y and it is also a digital signal. The XNOR operation is defined as: the output of an XNOR gate is 1 if
all the inputs are same, whereas the output is 0, if the inputs are not the same. It is the inverse of
the NOR gate. Mathematically, it is written as
Y = A EX-NOR B …
where A, B, C … N are the input variables and Y is the output variable.
Program :
AND Gate in Gate Level Design in Verilog
module my_andgatevlog (y,a,b);
output y;
input a,b;
and (y,a,b);
endmodule
OR Gate in Gate Level Design in Verilog
module my_orgatevlog (y,a,b);
output y;
input a,b;
or (y,a,b);
endmodule
NAND Gate in Gate Level Design in Verilog
module my_nandgatevlog (y,a,b);
output y;
input a,b;
nand (y,a,b);
endmodule
NOR Gate in Gate Level Design in Verilog
module my_norgatevlog (y,a,b);
output y;
input a,b;
nor (y,a,b);
endmodule

Truth Table for NAND Gate:

INPUT OUTPUT
A B QN+1
0 0 1
0 1 1
1 0 1
1 1 0
Logic Diagram for NAND gate :
Waveform for NAND gate:

Truth Table for NOR Gate :

INPUT OUTPUT
A B QN+1
0 0 1
0 1 0
1 0 0
1 1 0

Logic diagram for NOR Gate:

Waveform for NOR Gate:

Truth Table for NOT Gate :

INPUT OUTPUT
A B
0 1
1 0

NOT Gate in Gate Level Design in Verilog

module my_notgate (y,a);
output y;
input a;
not(y,a);
endmodule
XNOR Gate in Gate Level Design in Verilog
module my_xnorgatevlog (y,a,b);
output y;
input a,b;
xnor (y,a,b);
endmodule
Logic Diagram for NOT Gate:

Waveform for NOT Gate:

Truth Table for XNOR gate:

INPUT OUTPUT
A B QN+1
0 0 1
0 1 0
1 0 0
1 1 1

Logic Diagram for XNOR gate:

Waveform:

Result : Thus the Basic Gates are designed in Verilog HDL and the output is verified.
 Ex No 1 (b) ADDER and SUBTRACTOR REALISATION
Aim:

Realize the adder and subtractor using VHDL and Verilog.

Apparatus Required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator

Theory:

Half Adder A combinational circuit that performs the addition of two bits is called a half-adder.
This circuit needs two binary inputs and produces two binary outputs. One of the input
variables designates the augend and other designates the addend. The output variables produce
the sum and the carry.

The simplified Boolean functions of the two outputs can be obtained as below:
Sum S = x’y + xy’
Carry C = xy
Where x and y are the two input variables.

Full Adder A combinational circuit that performs the addition of three bits is called a half-
adder. This circuit needs three binary inputs and produces two binary outputs. One of the input
variables designates the augend and other designates the addend. Mostly, the third input
represents the carry from the previous lower significant position. The output variables produce
the sum and the carry.

The simplified Boolean functions of the two outputs can be obtained as below:
Sum S = x xor y xor z
Carry C = xy + xz + yz
Where x, y & z are the two input variables.
A half subtractor is a combinational circuit that subtracts two binary inputs and produces
their difference. It also has an output to specify if a 1 has been borrowed. The circuit has two
inputs, one representing the Minuend bit and the other Subtrahend bit. The circuit produces
two outputs, the difference and borrow. The Boolean functions for the tow outputs can be
written as

D = x’y + xy’

B = x’y
Truth Table for HALF ADDER:

INPUT OUTPUT
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Logic Diagram for Half Adder:

Waveform for Half Adder:

Truth Table for Full Adder:

INPUT OUTPUT
A B CIN SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Logic Diagram:
Full subtractor is a combinational circuit that subtraction between two binary inputs, taking into account
that a 1 may have been borrowed by a lower significant sage. The circuit has three inputs, representing the
minuend bit, the Subtrahend bit and the previous borrow bit respectively. The two outputs, d and b
represent the difference and output borrows. The Boolean functions for the tow outputs can be written as

D = x’yz + xy’z+xy’z’+xyz

B = x’y+x’z+yz

Program

Half Adder Design in Verilog

module my_halfadrvlog (s,c,x,y);

output s,c;

input x,y;

xor (s,x,y);

and (c,x,y);

endmodule

Full Adder Design in Verilog

module my_fuladrvlog (s,c,x,y,z);

output s,c;

input x,y,z;

xor (s,x,y,z);

assign c = ((x & y) | (y & z) | (z & x));

endmodule

Half Subtractor Design in Verilog

module my_halfsubvlog (d,b,x,y);

output d,b;

input x,y;

xor (d,x,y);

and (b,~(x),y);

endmodule
Waveform:

Truth Table for HALF SUBTRACTOR :

INPUT OUTPUT
A B SUM CARRY
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Logic Diagram for HALF SUBTRACTOR:

Waveform:
Full Subtractor Design in Verilog

module my_fulsubvlog (d,b,x,y,z);

output d,b;

input x,y,z;

xor (d,x,y,z);

assign b = ( ( (~(x))&y) | (y & z) | ((~(x)) & z));

endmodule

Truth Table for FULL SUBTRACTOR:

INPUT OUTPUT
A B CIN SUM CARRY
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Logic Diagram:

Waveform:

Result : Thus the Adder Circuits are designed in Verilog HDL and the output are verified.
 1. C) MULTIPLEXER REALISATION IN VERILOG

Aim:
Design a 4 to 1 multiplexer and 1 to 4 De multiplexer circuit in Verilog.

Apparatus Required:

Simulation Tools: Verilog – Xilinx Model Sim;

Theory:
A digital multiplexer is a combinational circuit that selects binary information from one of
many input lines and directs it to a single output line. Multiplexing means transmitting a large
number of information units over a smaller number of channels or lines. The selection of a
particular input line is controlled by a set of selection lines. Normally, there are 2 n input lines and
n selection lines whose bit combinations determine which input is selected. A multiplexer is also
called a data selector, since it selects one of many inputs and steers the binary information to the
output lines. Multiplexer ICs may have an enable input to control the operation of the unit. When
the enable input is in a given binary state (the disable state), the outputs are disabled, and when it
is in the other state (the enable state), the circuit functions as normal multiplexer. The enable
input (sometimes called strobe) can be used to expand two or more multiplexer ICs to digital
multiplexers with a larger number of inputs.
The size of the multiplexer is specified by the number 2n of its input lines and the single output
line. In general, a 2n – to – 1 line multiplexer is constructed from an n – to 2n decoder by adding to
it 2n input lines, one to each AND gate. The outputs of the AND gates are applied to a single OR gate
to provide the 1 – line output.

The de-multiplexer performs the reverse operation of a multiplexer. It is a combinational

circuit which accepts a single input and distributes it over several outputs. The number of output
lines is ‘n’ and the number of select lines is 2n lines. De-multiplexer ICs may have an enable input
to control the operation of the unit. When the enable input is in a given binary state (the disable
state), the outputs are disabled, and when it is in the other state (the enable state), the circuit
functions as normal de-multiplexer. The size of the de-multiplexer is specified by the single input
line and the number 2n of its output lines.

4 – to – 1 Multiplexer Design in Verilog

module my_4to1muxbehavirvlog (y,i,en,sel);
output y;
input [0 : 3] i;
input [0 : 1] sel;
input en;
reg y;
always @ (i or en or sel)
begin
if (en === 0)
begin
case (sel)
2'b00 : y = i[0];
2'b01 : y = i[1];
2'b10 : y = i[2];
2'b11 : y = i[3];
default : y = 1'bX;
endcase
end
else
y = 1'bZ;
end
endmodule

1 – to – 4 De-multiplexer Design in Verilog

module my_1to4demuxgatevlog(y,i,en,s);
output [0 :3] y;
input i,en;
input [0 : 1] s;
and (y[0],~en,~s[1],~s[0],i);
and (y[1],~en,~s[1],s[0],i);
and (y[2],~en,s[1],~s[0],i);
and (y[3],~en,s[1],s[0],i);
endmodule

Logic Diagram:

Waveform:
Logic Diagram for Demultiplexer :

Waveform:

Conclusion:

Thus the logic circuit for the 4 to 1 multiplexer and 1 to 4 Demultiplexer are designed in
Verilog HDL and the output are verified.
 Ex No 1.(d) Encoder and Decoder
Aim:

Realize Encoder and Decoder in Verilog .

Apparatus Required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator;

Theory:

An encoder has 2n (or fewer) input lines and ‘n’ output lines. The output lines generate the
binary code corresponding to the input value. In encoders, it is assumed that only one input has
a value of 1 at any given time. The encoders are specified as m-to-n encoders where m ≤ 2n.

A decoder is a combinational circuit that converts binary information from ‘n’ input lines to
a maximum of 2n unique output lines. It performs the reverse operation of the encoder. If the n-
bit decoded information has unused or don’t-care combinations, the decoder output will have
fewer than 2n outputs. The decoders are represented as n-to-m line decoders, where m ≤ 2n.
Their purpose is to generate the 2n (or fewer) minterms of n input variables. The name decoder
is also used in conjunction with some code converters such as BCD-to-seven-segment decoders.
Most, if not all, IC decoders include one or more enable inputs to control the circuit operation. A
decoder with an enable input can function as a de-multiplexer.

Program

4 – to – 2 Encoder Design in Verilog

module my_encodr2 (y,x);

output [0:3] y;

input [0:3] x;

reg [0:1] y;

always @ (x)

case (x)

4'b0001: y = 11;

4'b0010: y = 10;

4'b0100: y = 01;

4'b1000: y = 00;
 default : $display ("Invalid Input");

endcase

endmodule

2 – to – 4 Decoder Design in Verilog:

module my_decodr(d,x);

output [0:3] d;

input [0:1] x;

wire [0:1] temp;

not n1(temp[0],x[0]);

not n2(temp[1],x[1]);

and a0(d[0],temp[0],temp[1);

and a1(d[1],temp[0],,x[1]);

and a2(d[2],x[0], temp[1]);

and a3(d[3], x[0],x[1]);

endmodule

Logic Diagram for Encoder:

Truth Table:

i/p 0 i/p1 i/p 2 i/p3 o/p0 o/p1

1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1
Waveform:

Logic diagram for Decoder :

Truth Table:

INPUTS OUTPUTS
DIN X Y D0 D1 D2 D3

1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

Result :

Thus the logic circuit for the Encoder and decoder are designed in Verilog HDL and the output are verified.
 Ex No 1.(e) Code Converter
Aim:
Realize the code converter in Verilog

Apparatus Required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator.

Theory:

The availability of a large variety of codes for the same discrete elements of information
results in the use of different codes by different digital system. It is sometimes necessary to use the
output of one system as the input to another. A conversion circuit must be inserted between the
two systems if each uses different codes for the same information. Thus, a code converter is a
circuit that makes the two systems compatible even though each uses a different binary code. To
convert from binary code A to binary code B, the input lines must supply the bit combination of
elements as specified by code A and the output lines must generate the corresponding bit
combination of code B. A combinational circuit which performs this transformation by means of
logic gates, is known to be Code Converter.

Code Converters Design in Verilog:

module my_codeconvertrvlog (op,ip);

output [4 : 0] op;
input [1 : 0] ip;
reg [4 : 0] op;
integer choice;
initial
choice = 1'd0;
always @ (choice or ip)
begin
case (choice)
0:
begin
$display ("Enter UR Choice ");
$display (" 1'd1 For Binary to Gray");
$display (" 1'd2 For Gray to Binary");
end
1:
begin
op[0] = (ip[1] ^ ip[0]);
op[1] = (ip[2] ^ ip[1]);
op[2] = (ip[3] ^ ip[2]);
op[3] = ip[3];
 op[4] = 1'b 0;
end
2:
begin
op[0] = ((ip[3]^ip[2])^(ip[1]^ip[0]));
op[1] = ip[3]^ip[2]^ip[1];
op[2] = ip[3]^ip[2];
op[3] = ip[3];
op[4] = 1'b 0;
end
default :
begin
$display ("Entered a Wrong Option");
$display ("To Know the choices Enter 1'd0");
end

endcase
end
endmodule
Binary to Gray Code Converter

Binary to Gray Converter

BINARY CODE GRAY CODE

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
 1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Binary to Gray Converter

Gray to Binary Converter

Gray to Binary Converter

GRAY CODE BINARY CODE

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
Waveform:

Result :

Thus the code Converter is designed using Verilog HDL and the outputs also verified.
 Ex No 1.(f) Flipflop Realization
Aim:

Realize the S-R Flip-Flop in Verilog HDL.

Apparatus required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator

Theory:

A flip-flop circuit can maintain a binary state indefinitely (as long as power is delivered to
the circuit) until directed by an input signal to switch states. The basic flip-flop has two outputs
Q and Q’. The outputs Q and Q’ are always complementary. The flip-flop has two stable states
which are known as the 1 state and 0 state. In the 1 state, the output Q = 1 and hence called Set
state. In the 0 state, the output Q’ = 0 and also called as Reset or Clear state. The basic flip-flop
can be obtained by using NAND or NOR gates. The basic flip-flop circuit is also called latch, since
the information is latched or locked in this circuit. The basic flip-flop is also called the basic
binary memory cell, since it maintains a binary state as long as power is available. It is often
required to set or reset the basic memory cell in synchronism with a train of pulses known as
clock. Such a circuit is referred to as clocked set-reset (S-R) Flip-Flop. In the S-R flip-flop, when
the power is switched on, the state of the circuit is uncertain. It is desired to initially set or reset
the flip-flop, i.e. the initial state of the flip-flop is to be assigned. This is accomplished by using
the direct or asynchronous inputs, referred to as preset and clear inputs. These inputs may be
applied at any time between clock pulses and are not in synchronism with the clock.

SR Flip Flop Gate Level Design in Verilog

module my_srffgatevlog (q,qbar,s,r,clk,clr);
output q,qbar;
input s,r,clk,clr;
wire a,b,c,d,high;
assign high = 1'b1;
nand na0(a,s,clk);
nand na1(b,r,clk);
nand na2(c,qbar,a);
nand na3(d,q,b);
and a0 (q,c,clr);
and a1 (qbar,d,high);
endmodule
Truth Table:

INPUTS OUTPUTS
CLK S R QN QN+1 STATE
↑ 0 0 0 0 NO CHANGE
↑ 0 0 1 1 NO CHANGE
↑ 0 1 0 0 RESET
↑ 0 1 1 0 RESET
↑ 1 0 0 1 SET
↑ 1 0 1 1 SET
↑ 1 1 0 X INDETERMINATE
↑ 1 1 1 X INDETERMINATE.
0 X X 0 0 NO CHANGE
0 X X 1 1 NO CHANGE
Logic Diagram:

Waveforms:

Conclusion:

Thus the S-R flip-flop is realized in Verilog HDL and the output is verified.
 Ex No 1.(g) Asynchronous ripple counter
Aim:

To realize an asynchronous ripple counter in Verilog

Apparatus required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator

Theory:

In a ripple counter, the flip-flop output transition serves as a source for triggering other
flip-flops. In other words, the Clock Pulse inputs of all flip-flops (except the first) are triggered
not by the incoming pulses, but rather by the transition that occurs in other flip-flops. A binary
ripple counter consists of a series connection of complementing flip-flops (JK or T type), with
the output of each flip-flop connected to the Clock Pulse input of the next higher-order flip-flop.
The flip-flop holding the LSB receives the incoming count pulses. All J and K inputs are equal to
1. The small circle in the Clock Pulse /Count Pulse indicates that the flip-flop complements
during a negative-going transition or when the output to which it is connected goes from 1 to 0.
The flip-flops change one at a time in rapid succession, and the signal propagates through the
counter in a ripple fashion. A binary counter with reverse count is called a binary down-
counter. In binary down-counter, the binary count is decremented by 1 with every input count
pulse.

4-Bit Asynchronous Ripple Counter Design in Verilog

module my_asyncbincnt (q,qbar,clk,reset);

output [0 : 3] q;
output [0 : 3] qbar;
input clk,reset;
wire [0 : 1] temp;
reg high;
initial
high = 1'b1;
my_jkffbehaviorvlog ff1 (q[0],qbar[0],high,high,clk,reset);
my_jkffbehaviorvlog ff2 (q[1],qbar[1],high,high,q[0],reset);
my_jkffbehaviorvlog ff3 (q[2],qbar[2],high,high,q[1],reset);
my_jkffbehaviorvlog ff4 (q[3],qbar[3],high,high,q[2],reset);
endmodule
 module my_jkffbehaviorvlog (q,qbar,j,k,clk,reset);
output q,qbar;
input j,k,clk,reset;
reg q,qbar;
always @ (negedge clk or reset)
if (~reset)
begin
q = 1'b0;
qbar = 1'b1;
end
else if (reset)
begin
if (j==0 && k ==0)
begin
q = q;
qbar = qbar;
end
else if ( j== 0 && k ==1)
begin
q = 1'b0;
qbar = 1'b1;
end
else if (j==1 && k == 0)
begin
q = 1'b1;
qbar = 1'b0;
end
else if (j ==1 && k ==1)
begin
q = ~q;
qbar = ~qbar;
end
else
begin
q = 1'bz;
qbar = 1'bz;
end
end
endmodule;
Logic Diagram:
State Table:

Truth Table for JK flip-flop:

J K Qn+1

0 0 Qn

0 1 0

1 0 1

1 1 Qn

Waveforms In Binary

Conclusion:

Thus the asynchronous ripple counter is designed in Verilog HDL and the output is verified.
 Ex No 1.(h) RANDOM NUMBER GENERATOR REALIZATION IN
VERILOG.

Aim:

Realize the Random Number generator in Verilog.

Apparatus Required:

Synthesis tool: Xilinx ISE.

Simulation tool: ModelSim Simulator;

Theory:

Random numbers for polynomial equations are generated by using the shift register
circuit. The random number generator is nothing but the Linear Feedback Shift Register(LFSR).
The shift registers are very helpful and versatile modules that facilitate the design of many
sequential circuits whose design may otherwise appear very complex. In its simplest form, a
shift register consists of a series of flip-flops having identical interconnection between two
adjacent flip-flops. Two such registers are shift right registers and the shift left registers. In the
shift right register, the bits stored in the flip-flops shift to the right when shift pulse is active.
Like that, for a shift left register, the bits stored in the flip-flops shift left when shift pulse is
active. In the shift registers, specific patterns are shifted through the register. There are
applications where instead of specific patterns, random patterns are more important. Shioft
registers can also built to generate such patterns , which are pseudorandom in nature. Called
Linear Feedback Shift Registers (LFSR’s), these are very useful for encoding and decoding the
error control codes. LFSRs used as a generators of pseudorandom sequences have proved
externally useful in the area of testing of VLSI chips.

Main Module:
module main(q,qbar,clk,reset);
inout [0:3]q;
inout [0:3]qbar;
input clk,reset;

wire a,b;
xor (a,q[3],qbar[2]);
not (b,a);
jk ff0(q[0],qbar[0],a,b,clk,reset);
jk ff1(q[1],qbar[1],q[0],qbar[0],clk,reset);
jk ff2(q[2],qbar[2],q[1],qbar[1],clk,reset);
jk ff3(q[3],qbar[3],q[2],qbar[2],clk,reset);
endmodule

JK Flip-flop:

module jk(q,qbar,j,k,clk,reset);
output q,qbar;
input j,k,clk,reset;
 reg q,qbar;
always @(posedge clk or posedge reset)
if (reset)
begin
q=1'b0;
qbar=1'b1;
end
else
begin
if (j==0 && k==0)
begin
q=q;
qbar=qbar;
end
else if (j==0 && k==1)
begin
q=1'b0;
qbar=1'b1;
end
else if (j==1 && k==0)
begin
q=1'b1;
qbar=1'b0;
end
else if (j==1 && k==1)
begin
q=~q;
qbar=~qbar;
end
else
begin
q=1'bz;
qbar=1'bz;
end
end
endmodule

Logic Diagram:
Waveforms:

Conclusion:

Thus the Random number Generator is designed and simulated in Verilog HDL
 EX NO. 2 DESIGN OF MAC UNIT USING VERILOG

Aim:
To design an MAC unit using Verilog HDL.
Apparatus required:
Synthesis tool: Xilinx ISE.
Simulation tool: ModelSim Simulator
THEORY
The Multiplier-accumulator (MAC) unit supports large number of digital signal processing (DSP)
applications. It also furnishes signal processing ability to the microcontroller for various applications such
as servo/audio control etc. MAC, being an execution unit in the processor implements a 3-stage pipelined
arithmetic architecture which optimizes 16×16 multipliers. This design supports both 16-bit and 32-bit
operands. It also supports signed/unsigned integers plus signed, fixed-point fractional input operands .
The MAC unit supports mainly three functions:
 Signed and unsigned integer multiplies
 Multiply-accumulate operations
 supporting signed, unsigned, and signed fractional operands
 Miscellaneous register operations
An accumulator adder and multiplier together form a MAC unit.
DIAGRAM

Procedure:

1. The 3 bit MAC UNIT is designed.

2. The VERILOG HDL program source code for the circuit is written.

3. It is implemented in Model Sim and Simulated.

4. Signals are provided and Output Waveforms are viewed.

VERILOG CODE
module MAC_UNIT(clk,rst, a,b, z);
input clk,rst;
input [2:0] a,b;
output [5:0] z;
wire [5:0] w;
multiplier U1(.a(a),.b(b),.p(w));
pipo U2(.RIN(w), .clk(clk),.rst(rst),.ROUT(z));
endmodule
module multiplier(a,b, p);
input [2:0] a,b;
output [5:0] p;
wire [7:0]u;
wire [1:0]su;
wire [8:0]i;
and (p[0],a[0],b[0]);
and (u[0],a[1],b[0]);
and (u[1],a[2],b[0]);
and (u[2],a[0],b[1]);
and (u[3],a[1],b[1]);
and (u[4],a[2],b[1]);
and (u[5],a[0],b[2]);
and (u[6],a[1],b[2]);
and (u[7],a[2],b[2]);
hadd h1(.l(u[0]),.m(u[2]),.sum(p[1]),.cry(i[0]));
hadd h2(.l(i[0]),.m(u[1]),.sum(su[0]),.cry(i[1]));
hadd h3(.l(u[3]),.m(u[5]),.sum(su[1]),.cry(i[2]));
hadd h4(.l(su[0]),.m(su[1]),.sum(p[2]),.cry(i[4]));
hadd h5(.l(i[1]),.m(i[2]),.sum(i[5]),.cry(i[6]));
or (i[7],i[5],i[4]);
fadd f3(.d(i[7]),.e(u[4]),.cin(u[6]),.s(p[3]),.cout(i[8]));
fadd f4(.d(i[8]),.e(i[6]),.cin(u[7]),.s(p[4]),.cout(p[5]));
endmodule
module pipo(RIN, clk,rst, ROUT);
input [5:0] RIN;
input clk,rst;
output [5:0] ROUT;
reg [5:0] ROUT;
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
ROUT <= 6'b000000;
end
else
begin
ROUT <= RIN;
end
end
endmodule

module fadd(s,cout,d,e,cin);
input d,e,cin;
output s,cout;
assign s = (d ^ e ^ cin);
assign cout = ((d&e) | (e&cin) | (d&cin));
endmodule

module hadd(sum,cry,l,m);
input l,m;
output sum,cry;
wire sum,cry;
assign sum = (l^m);
assign cry = (l&m);
endmodule
SIMULATION OUTPUT

RESULT:

The MAC UNIT was designed using verilog HDL

 EX NO. 4 DESIGN Of UART/USART

AIM:

To synthesis and stimulate of UART/USART implementation

APPARATUS REQUIRED:

Software: Xilinx Project navigator,Modelsim

THEORY:
In any asynchronous interface, the first thing you need to know is when in time you should
sample (look at) the data. If you do not sample the data at the right time, you might see the wrong
data. In order to receive your data correctly, the transmitter and receiver must agree on the baud
rate. The baud rate is the rate at which the data is transmitted. For example, 9600 baud means
9600 bits per second. The code below uses a generic in VHDL or a parameter in Verilog to
determine how many clock cycles there are in each bit. This is how the baud rate gets determined.

The FPGA is continuously sampling the line. Once it sees the line transition from high to
low, it knows that a UART data word is coming. This first transition indicates the start bit. Once the
beginning of the start bit is found, the FPGA waits for one half of a bit period. This ensures that the
middle of the data bit gets sampled. From then on, the FPGA just needs to wait one bit period (as
specified by the baud rate) and sample the rest of the data. The figure below shows how the UART
receiver works inside of the FPGA. First a falling edge is detected on the serial data line. This
represents the start bit. The FPGA then waits until the middle of the first data bit and samples the
data. It does this for all eight data bits.

UART Serial Data Stream

The above data stream shows how the code below is structured. The code below uses one Start Bit,
one Stop Bit, eight Data Bits, and no parity. Note that the transmitter modules below both have a
signal o_tx_active. This is used to infer a tri-state buffer for half-duplex communication. It is up
your specific project requirements if you want to create a half-duplex UART or a full-duplex UART.
The code below will work for both!
Verilog Code:
module uart ( reset,
txclk ,
ld_tx_data ,
tx_data ,
tx_enable ,
tx_out , tx_empty , rxclk ,
uld_rx_data , rx_data ,
rx_enable , rx_in ,
rx_empty
);
// Port declarations input reset ;
input txclk ;
input ld_tx_data ;input[7:0]tx_data ; input tx_enable
; output tx_out ; output tx_empty
; input rxclk ;
input uld_rx_data ; output [7:0] rx_data ; input rx_enable;
input rx_in ; output rx_empty ;

// Internal Variables
reg[7:0] tx_reg ; reg tx_empty ;
reg tx_over_run ; reg[3:0] tx_cnt ;
reg tx_out ; reg[7:0] rx_reg ;
reg[7:0] rx_data ; reg[3:0] rx_sample_cnt ; reg[3:0] rx_cnt ;
reg rx_frame_err ;
reg rx_over_run ;
reg rx_empty ;
reg rx_d1 ;
reg rx_d2 ;
reg rx_busy ;

// UART RX Logic
always @ (posedge rxclk or posedge reset) if (reset) begin
rx_reg <=0;
rx_data <=0;
rx_sample_cnt <= 0;
rx_cnt <=0;
rx_frame_err <=0;
rx_over_run <=0;
rx_empty <=1;
rx_d1 <=1;
rx_d2 <=1;
rx_busy <= 0; end elsebegin
// Synchronize the asynch signal rx_d1 <= rx_in;
rx_d2 <= rx_d1;
// Uload the rx data
if (uld_rx_data) begin rx_data <= rx_reg; rx_empty <= 1;
end
// Receive data only when rx is enabled if (rx_enable) begin
// Check if just received start offrame if ( ! rx_busy && ! rx_d2) begin rx_busy <=1;
rx_sample_cnt <= 1;
rx_cnt <= 0; end
// Start of frame detected, Proceed with rest of data if (rx_busy) begin
rx_sample_cnt <= rx_sample_cnt + 1;
// Logic to sample at middle of data if (rx_sample_cnt == 7) begin
if ((rx_d2 == 1) && (rx_cnt == 0)) begin rx_busy <= 0;
end else begin
rx_cnt <= rx_cnt + 1;
// Start storing the rx data
if (rx_cnt > 0 && rx_cnt < 9) begin rx_reg[rx_cnt - 1] <= rx_d2;
end
if (rx_cnt == 9) begin rx_busy <= 0;
// Check if End of frame received correctly if (rx_d2 == 0) begin
rx_frame_err <=1; end else begin rx_empty <=0;
rx_frame_err <= 0;
// Check if last rx data was not unloaded, rx_over_run <= (rx_empty) ? 0 : 1;
end end end
end
end end
if ( ! rx_enable) begin rx_busy <= 0;
end end

// UART TX Logic
always @ (posedge txclk or posedge reset) if (reset) begin
tx_reg <=0;
tx_empty <=1;
tx_over_run <=0;
tx_out <=1;
tx_cnt <= 0; end elsebegin
if (ld_tx_data) begin
if ( ! tx_empty) begin tx_over_run <= 0; end else begin
tx_reg <= tx_data; tx_empty <=0;
end end
if (tx_enable && ! tx_empty) begin tx_cnt <= tx_cnt + 1;
if (tx_cnt == 0) begin tx_out <= 0;
end
if (tx_cnt > 0 && tx_cnt < 9) begin tx_out <= tx_reg[tx_cnt -1];
end
if (tx_cnt == 9) begin tx_out <= 1;
tx_cnt <= 0;
tx_empty <= 1; end
end
if ( ! tx_enable) begin tx_cnt <= 0;
end end

endmodule
Output

Result:

Synthesis and simulation of UART/USART implementation has been completed successfully.

 EX NO. 5 DESIGN of 16 bit RISC processor
AIM:

To design a RISC processor using Verilog HDL.

APPARATUS REQUIRED:

Software: Xilinx Project navigator,Modelsim

Theory :
RISC is an abbreviation of Reduced Instruction Set Computer. RISC processor has
‘instruction sets’ that are simple and have simple ‘addressing modes’. A RISC style
instruction engages “one word” in memory. Execution of the RISC instructions
are faster and take one clock cycle per instruction.
RISC Processor Architecture (Block diagram)
RISC processor is implemented using the hardwired control unit. The hardwired
control unit produces control signals which regulate the working of processors
hardware. RISC architecture emphasizes on using the registers rather than memory.
This is because the registers are the ‘fastest’ available memory source. The registers
are physically small and are placed on the same chip where the ALU and the control unit
are placed on the processor. The RISC instructions operate on the operands present
in processor’s registers.
Below we have the block diagram for the RISC architecture.
Verilog code for Instruction Memory

include "Parameter.v"
module Instruction_Memory(
input[15:0] pc,
output[15:0] instruction );

reg [`col - 1:0] memory [`row_i - 1:0];

wire [3 : 0] rom_addr = pc[4 : 1];
initial
begin
$readmemb("./test/test.prog", memory,0,14);
end
assign instruction = memory[rom_addr];
endmodule

Verilog code for register file:

`timescale 1ns / 1ps
module GPRs(
input clk,
input reg_write_en,
input [2:0] reg_write_dest,
input [15:0] reg_write_data,
input [2:0] reg_read_addr_1,
output [15:0] reg_read_data_1,
input [2:0] reg_read_addr_2,
output [15:0] reg_read_data_2
);
reg [15:0] reg_array [7:0];
integer i;
initial begin
for(i=0;i<8;i=i+1)
reg_array[i] <= 16'd0;
end
always @ (posedge clk ) begin
if(reg_write_en) begin
reg_array[reg_write_dest] <= reg_write_data;
end
end
assign reg_read_data_1 = reg_array[reg_read_addr_1];
assign reg_read_data_2 = reg_array[reg_read_addr_2];
endmodule

Verilog code for Data Memory:

`include "Parameter.v"
module Data_Memory(
input clk,
input [15:0] mem_access_addr,
input [15:0] mem_write_data,
input mem_write_en,
input mem_read,
output [15:0] mem_read_data
);
reg [`col - 1:0] memory [`row_d - 1:0];
integer f;
wire [2:0] ram_addr=mem_access_addr[2:0];
initial
begin
$readmemb("./test/test.data", memory);
f = $fopen(`filename);
$fmonitor(f, "time = %d\n", $time,
"\tmemory[0] = %b\n", memory[0],
"\tmemory[1] = %b\n", memory[1],
"\tmemory[2] = %b\n", memory[2],
"\tmemory[3] = %b\n", memory[3],
"\tmemory[4] = %b\n", memory[4],
"\tmemory[5] = %b\n", memory[5],
"\tmemory[6] = %b\n", memory[6],
"\tmemory[7] = %b\n", memory[7]);
`simulation_time;
$fclose(f);
end
always @(posedge clk) begin
if (mem_write_en)
memory[ram_addr] <= mem_write_data;
end
assign mem_read_data = (mem_read==1'b1) ? memory[ram_addr]: 16'd0;
endmodule
Verilog code for ALU unit:
module ALU(
input [15:0] a, //src1
input [15:0] b, //src2
input [2:0] alu_control, //function sel
output reg [15:0] result, //result
output zero
);

always @(*)
begin
case(alu_control)
3'b000: result = a + b; // add
3'b001: result = a - b; // sub
3'b010: result = ~a;
3'b011: result = a<<b;
3'b100: result = a>>b;
3'b101: result = a & b; // and
3'b110: result = a | b; // or
3'b111: begin if (a<b) result = 16'd1;
else result = 16'd0;
end
default:result = a + b; // add
endcase
end
assign zero = (result==16'd0) ? 1'b1: 1'b0;
endmodule
Verilog code for Datapath of RISC Processor
`timescale 1ns / 1ps
module Datapath_Unit(
input clk,
input jump,beq,mem_read,mem_write,alu_src,reg_dst,mem_to_reg,reg_write,bne,
input[1:0] alu_op,
output[3:0] opcode
);
reg [15:0] pc_current;
wire [15:0] pc_next,pc2;
wire [15:0] instr;
wire [2:0] reg_write_dest;
wire [15:0] reg_write_data;
wire [2:0] reg_read_addr_1;
wire [15:0] reg_read_data_1;
wire [2:0] reg_read_addr_2;
wire [15:0] reg_read_data_2;
wire [15:0] ext_im,read_data2;
wire [2:0] ALU_Control;
wire [15:0] ALU_out;
wire zero_flag;
wire [15:0] PC_j, PC_beq, PC_2beq,PC_2bne,PC_bne;
wire beq_control;
wire [12:0] jump_shift;
wire [15:0] mem_read_data;
// PC
initial begin
pc_current <= 16'd0;
end
always @(posedge clk)
begin
pc_current <= pc_next;
end
assign pc2 = pc_current + 16'd2;
Instruction_Memory im(.pc(pc_current),.instruction(instr));
assign jump_shift = {instr[11:0],1'b0};
assign reg_write_dest = (reg_dst==1'b1) ? instr[5:3] :instr[8:6];
assign reg_read_addr_1 = instr[11:9];
assign reg_read_addr_2 = instr[8:6];

GPRs reg_file
(
.clk(clk),
.reg_write_en(reg_write),
.reg_write_dest(reg_write_dest),
.reg_write_data(reg_write_data),
.reg_read_addr_1(reg_read_addr_1),
.reg_read_data_1(reg_read_data_1),
.reg_read_addr_2(reg_read_addr_2),
.reg_read_data_2(reg_read_data_2)
);
assign ext_im = {{10{instr[5]}},instr[5:0]};
alu_control ALU_Control_unit(.ALUOp(alu_op),.Opcode(instr[15:12]),.ALU_Cnt(ALU_Control));
assign read_data2 = (alu_src==1'b1) ? ext_im : reg_read_data_2;
ALU
alu_unit(.a(reg_read_data_1),.b(read_data2),.alu_control(ALU_Control),.result(ALU_out),.zero(zero_
flag));
assign PC_beq = pc2 + {ext_im[14:0],1'b0};
assign PC_bne = pc2 + {ext_im[14:0],1'b0};

assign beq_control = beq & zero_flag;

assign bne_control = bne & (~zero_flag);
assign PC_2beq = (beq_control==1'b1) ? PC_beq : pc2;

assign PC_2bne = (bne_control==1'b1) ? PC_bne : PC_2beq;

assign PC_j = {pc2[15:13],jump_shift};

assign pc_next = (jump == 1'b1) ? PC_j : PC_2bne;

Data_Memory dm
(
.clk(clk),
.mem_access_addr(ALU_out),
.mem_write_data(reg_read_data_2),
.mem_write_en(mem_write),
.mem_read(mem_read),
.mem_read_data(mem_read_data)
);
assign reg_write_data = (mem_to_reg == 1'b1)? mem_read_data: ALU_out;
assign opcode = instr[15:12];
endmodule

Verilog code for the 16-bit RISC processor:

`timescale 1ns / 1ps
module Risc_16_bit(
input clk
);
wire jump,bne,beq,mem_read,mem_write,alu_src,reg_dst,mem_to_reg,reg_write;
wire[1:0] alu_op;
wire [3:0] opcode;
// Datapath
Datapath_Unit DU
(
.clk(clk),
.jump(jump),
.beq(beq),
.mem_read(mem_read),
.mem_write(mem_write),
.alu_src(alu_src),
.reg_dst(reg_dst),
.mem_to_reg(mem_to_reg),
.reg_write(reg_write),
.bne(bne),
.alu_op(alu_op),
.opcode(opcode)
);

endmodule
EX NO. 6 SIMULATION AND ANALYSIS OF CMOS
COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUITS
USING CAD TOOLS
AIM:
To Simulate and Analyze the CMOS combinational and sequential logic circuits using CAD tools

SOFTWARE REQUIRED:
 LT Spice XVII- CAD Tool
THEORY:

LT SPICE:

LTspice® is high performance SPICE simulator software, including a graphical

schematic capture interface. Schematics can be probed to produce simulation results—
easily explored through LTspice’s built-in waveform viewer. LTspice’s enhancements
and models improve the simulation of analog circuits when compared to other SPICE
solution
List of some hotkeys for creating schematic:
R: Place resistor
C: Place capacitor
L: Place inductor
D: Place diode
G: Place ground
F2: Component menu
F3: Draw wire
F4: Label net

F5: Delete (press F5 then click the component)

F6: Copy
F7: Move without wires
F8: Drag/move with wires
F9: Undo (shift + F9 to redo)
 CTRL+R: Rotate (when component
CTRL+E:is selected)
Mirror (when component is selected)
COMBINATIONAL CIRCUIT

 The output of a Combinational Circuit depends entirely on the present input.

 It exhibits a faster speed.
 It is comparatively easier to design.
 No feedback is present between the input and output.
 The combinational circuit depends on time.
 Logic gates form the building blocks of such circuits.
 One can make use of it for both boolean and arithmetic operations.
 They don’t hold the capacity of storing any state.
 These circuits do not have a clock- thus, they don’t require triggering.
 They do not possess any memory element.
 Users can feasibly use as well as handle them.
 Example – Demultiplexer, Multiplexer, Decoder, Encoder, etc.

SEQUENTIAL CIRCUIT

 The output of a Sequential Circuit depends on both- past as well as present inputs.
 It works at a comparatively slower speed.
 The design of these circuits is comparatively much tougher than the Combinational Circuit.
 A feedback path exists between the output and the input.
 The circuit is time-dependent.
 Flip-flops constitute the building blocks of such a circuit.
 People mainly use them for storing data and information.
 They possess the capability of storing any data state or retaining an earlier state at any given point.
 Because a Sequential circuit depends on a clock, it usually requires triggering.
 They always possess a memory element.
 A user may not be able to handle and use these circuits easily.
 For Example – Counters, Flip-flops, etc.
PROCEDURE:

1) Select File -> New Schematic then press the icon and navigate to the component you need
2) Click on the Label icon and add IN to the input and OUT to the output.
3) To set the simulation conditions, click on Simulate -> Edit Simulation cmd and enter 10ms in the stop
Time box
 4) Click on the Running Man symbol in the toolbar as shown
5) The screen will divide showing the schematic in one half and the simulation window in the other.
6) Click the mouse anywhere in the schematic window. Moving the mouse over certain parts of the circuit
will highlight either a voltage probe or current probe.

Voltage Probe

Current Probe

7) Hover the mouse over the output of the circuit and click when the probe appears to show the voltage at
the output .
8) Repeating this process at the input of the circuit shows the input voltage.

o All circuits must have a ground.

o Drawing a wire straight through several components is an easy way of connecting the
components in series.

o If you need to plot a differential voltage, move the mouse to the positive node of the voltage to
be measured and once the probe symbol has appeared, left click the mouse then drag the probe
to the negative node. The probe colour will change from red to black. Release the mouse and the
differential voltage will be displayed.

o If you want to plot multiple waveforms with respect to a node other than ground, navigate to
that node, right click the mouse and the following list of options will appear:
o Select 'Mark Reference'. Thereafter all plots will be referenced with respect to that node.

o Sometimes it is convenient to have 2 plot panes, especially when comparing 2 voltages of very
different amplitudes. To create multiple plot panes, move the mouse to the plot pane, right click
and select Add Plot Pane. Left clicking on a specific pane loads the probe results into that pane.
Left clicking on the waveform icon (eg V(out)) and dragging the icon to the other pane, moves
the waveform to the other pane.

o To remove a waveform from the plot pane, hit the <F5> key and delete the appropriate
waveform logo at the top of the plot pane. As with the schematic editor, the <F9> key undoes
the last action performed in the plot pane.

o Holding down the ALT key and left clicking over a wire plots the current in the wire.
o Holding down the ALT key and left clicking over a components displays the instantaneous
power in that component.

o The latest version of LTspice (LTspice XVII) allows the use of multiple monitors, so the
schematic can be displayed on one monitor, while the plot results are displayed on a second
monitor. Right click in the Schematic Window and select 'Float Window'. The Schematic
Window can now be moved between screens. The same can be done with the Plot Window.

o The toolbar can, however, only address non floating windows, so the Running Man symbol is
greyed out when windows are floating. To run the simulation, select the Schematic Window,
right click then select 'Run'.
COMBINATIONAL CIRCUITS 1.CMOS INVERTER

SIMULATION ANALYSIS:
CIRCUIT SCHEMATIC:
2. HALF ADDER – GATE LEVEL

SIMULATION ANALYSIS:
CIRCUIT SCHEMATIC:
3. HALF ADDER- CMOS IMPLEMENTATION

SIMULATION ANALYSIS:
SEQUENTIAL CIRCUIT
CIRCUIT SCHEMATIC:
JK FLIPFLOP – CMOS IMPLEMENTATION

SIMULATION ANALYSIS:
Year/Sem/Branch : I / II / M.E(A.E) AP4211/ VLSI Design Laboratory

TRUTH TABLE:
JK-FF

J K QN+1

0 0 QN

0 1 0

1 0 1

1 1 TOGGLE

RESULT:
Thus the Combinational and Sequential Circuits are designed using CAD Tool and the design is
simulated & verified by transient analysis.