This document contains configuration settings for a Si5351A clock generator chip. It defines two PLL configurations operating at 25 MHz and 900 MHz and 875 MHz respectively. It then configures 3 output channels to generate clocks of 0.35 MHz, 0.25 MHz and 0.3 MHz from the two PLLs. The remainder of the document contains register maps for programming the chip.
This document contains configuration settings for a Si5351A clock generator chip. It defines two PLL configurations operating at 25 MHz and 900 MHz and 875 MHz respectively. It then configures 3 output channels to generate clocks of 0.35 MHz, 0.25 MHz and 0.3 MHz from the two PLLs. The remainder of the document contains register maps for programming the chip.
This document contains configuration settings for a Si5351A clock generator chip. It defines two PLL configurations operating at 25 MHz and 900 MHz and 875 MHz respectively. It then configures 3 output channels to generate clocks of 0.35 MHz, 0.25 MHz and 0.3 MHz from the two PLLs. The remainder of the document contains register maps for programming the chip.
This document contains configuration settings for a Si5351A clock generator chip. It defines two PLL configurations operating at 25 MHz and 900 MHz and 875 MHz respectively. It then configures 3 output channels to generate clocks of 0.35 MHz, 0.25 MHz and 0.3 MHz from the two PLLs. The remainder of the document contains register maps for programming the chip.