Ijett V68i1p204
Ijett V68i1p204
Ijett V68i1p204
Fig 5: Encryption
c) Decryption Unit
Fig 3: Encryption with Private Key This unit again is same as encryption unit as shown
in Figure 6. The block does same mathematical
II. METHODOLOGY operation as encryption unit i.e. modular
exponentiation. It generates the plaintext back at the
A. RSA Algorithm receiver end.
a) Key Generation Unit 5 Calculate d*e=1 mod ∅(n) we get (private key)d
6 Compute ciphertext C=M e mod n for plaintext M
This module is used for the generation of the private
key and public key that are to be used in Public Key 7 Compute plaintext M=C d mod n using ciphertext C
C cryptographic algorithms. The prime numbers, The above Table 1 depicts the overall steps included
denoted by p and q are multiplied by the multiplier in RSA algorithm.
and mod of the product is calculated. Then
subtractor and the second multiplier block calculate III. IMPLEMENTATION
Euler’s totient function. GCD calculator checks The RSA algorithm is implemented in Matlab
whether е and ∅(n) are prime or not relatively. coding and in VHDL coding by using Matlab tool
Another calculator, called multiplicative inverse is and Xilinx ISE 13.2.The parameters such as
used to calculate d, which is nothing but private key encryption decryption time i.e, Overall execution
[8]. time, operating frequency and memory (CPU time)
are taken for the analysis in both the cases.
REFERENCES
[1] Sushanta Kumar Sahu and Manoranjan Pradhan, “FPGA
Implementation of RSA Encryption system”, International
Journal of Computer Applications, vol. 19, Issue 9, 2011.
[2] Ari Shawkat Tahir, “Design and Implementation of RSA
Algorithm using FPGA”, Research Gate, 2015.
[3] Sandeep Singh, Parminder Singh Jassal, “Synthesis and
Analysis of 32-Bit RSA Algorithm Using VHDL”,
International Journal of Engineering Sciences, vol. 1, Jan.
2016.
[4] Ankit A. and Pushkar P, “Implementation of RSA
Algorithm on FPGA”, International Journal of Engineering
Research & Technology (IJERT), ISSN: 2278-0181, vol.
1, Issue 5, 2012.
[5] Amit Thobbi, Shriniwas Dhage, Pritesh Jadhav and
Akshay Chandrachood,“Implementation of RSA
Encryption Algorithm on FPGA”, American Journal of
Engineering Research (AJER), vol. 4, Issue 6, pp-144-
151,2015.
[6] Khaled Shehata, Hanady Hussien, Sara Yehia, “FPGA
Implementation of RSA Encryption Algorithm for E-
Passport Application”, World Academy of Science,
Engineering and Technology International Journal of
Computer and Information Engineering, vol. 8, 2014.
[7] Gurpreet K. and Vishal A, “An Efficient Implementation
of RSA Algorithm using FPGA and Big Prime Digit”,
International Journal of Computer & Communication
Engineering Research (IJCCER), Volume 1 - Issue 4,
2013.
[8] M. A. Smadi, Qasem A. and Abdullah A, “Efficient FPGA
Implementation of RSA Coprocessor Using Scalable
Modules”, International Symposium on Emerging Inter-