SiR474DP

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Vishay Siliconix
N-Channel 30 V (D-S) MOSFET
FEATURES
PowerPAK® SO-8 Single
D • TrenchFET® power MOSFET
D 8
D 7 • Low thermal resistance PowerPAK® package
D 6 with low 1.07 mm profile
5
• Optimized for high side synchronous rectifier
operation
• 100 % Rg and UIS tested
6. 1
15 2 • Material categorization: for definitions of compliance
m S
m m 3 S please see www.vishay.com/doc?99912
m
1 5.15 4 S
G APPLICATIONS
Top View Bottom View D
• Notebook CPU core
PRODUCT SUMMARY
- High side switch
VDS (V) 30
RDS(on) max. () at VGS = 10 V 0.0095 G
RDS(on) max. () at VGS = 4.5 V 0.0120
Qg typ. (nC) 8
ID (A) 20 a, g N-Channel MOSFET
S
Configuration Single

ORDERING INFORMATION
Package PowerPAK SO-8
Lead (Pb)-free and halogen-free SiR474DP-T1-GE3

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 30
V
Gate-source voltage VGS ±20
TC = 25 °C 20 g
TC = 70 °C 20 g
Continuous drain current (TJ = 150 °C) ID
TA = 25 °C 15 b, c
TA = 70 °C 12 b, c
A
Pulsed drain current IDM 50
TC = 25 °C 20 g
Continuous source-drain diode current IS
TA = 25 °C 3.2 b, c
Single pulse avalanche current IAS 20
L = 0.1 mH
Avalanche energy EAS 20 mJ
TC = 25 °C 29.8
TC = 70 °C 19
Maximum power dissipation PD W
TA = 25 °C 3.9 b, c
TA = 70 °C 2.5 b, c
Operating junction and storage temperature range TJ, Tstg -55 to +150
°C
Soldering recommendations (peak temperature) d, e 260

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYPICAL MAXIMUM UNIT
Maximum junction-to-ambient b, f t  10 s RthJA 27 32
°C/W
Maximum junction-to-case (drain) Steady state RthJC 3.5 4.2
Notes
a. TC = 25 °C
b. Surface mounted on 1" x 1" FR4 board
c. t = 10 s
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components
f. Maximum under steady state conditions is 70 °C/W
g. Packaged limited

S-82749-Rev. A, 10-Nov-2008 1 Document Number: 68996

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SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 250 μA 30 - - V
VDS temperature coefficient VDS/TJ - 34 -
ID = 250 μA mV/°C
VGS(th) temperature coefficient VGS(th)/TJ - -4.7 -
Gate-source threshold voltage VGS(th) VDS = VGS, ID = 250 μA 1 - 2.2 V
Gate-source leakage IGSS VDS = 0 V, VGS = ± 20 V - - ± 100 nA
VDS = 30 V, VGS = 0 V - - 1
Zero gate voltage drain current IDSS μA
VDS = 30 V, VGS = 0 V, TJ = 55 °C - - 10
On-state drain current a ID(on) VDS  5 V, VGS = 10 V 30 - - A
VGS = 10 V, ID = 10 A - 0.0075 0.0095
Drain-source on-state resistance a RDS(on) 
VGS = 4.5 V, ID = 7 A - 0.0100 0.0120
Forward transconductance a gfs VDS = 15 V, ID = 10 A - 30 - S
Dynamic b
Input capacitance Ciss - 985 -
Output capacitance Coss VDS = 15 V, VGS = 0 V, f = 1 MHz - 205 - pF
Reverse transfer capacitance Crss - 76 -
VDS = 15 V, VGS = 10 V, ID = 10 A - 18 27
Total gate charge Qg
- 8 12
nC
Gate-source charge Qgs VDS = 15 V, VGS = 4.5 V, ID = 10 A - 2.4 -
Gate-drain charge Qgd - 2.3 -
Gate resistance Rg f = 1 MHz 0.3 1.3 2.6 
Turn-on delay time td(on) - 14 25
Rise time tr VDD = 15 V, RL = 1.5 , - 12 24
Turn-off delay time td(off) ID  10 A, VGEN = 4.5 V, Rg = 1  - 19 35
Fall time tf - 9 18
ns
Turn-on delay time td(on) - 8 16
Rise time tr VDD = 15 V, RL = 1.5 , - 10 20
Turn-off delay time td(off) ID  10 A, VGEN = 10 V, Rg = 1  - 16 30
Fall time tf - 9 18
Drain-Source Body Diode Characteristics
Continuous source-drain diode current IS TC = 25 °C - - 20
A
Pulse diode forward current a ISM - - 50
Body diode voltage VSD IS = 3 A - 0.76 1.1 V
Body diode reverse recovery time trr - 14 28 ns
Body diode reverse recovery charge Qrr IF = 10 A, di/dt = 100 A/μs, - 5 10 nC
Reverse recovery fall time ta TJ = 25 °C - 8 -
ns
Reverse recovery rise time tb - 6 -
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %
b. Guaranteed by design, not subject to production testing

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

S-82749-Rev. A, 10-Nov-2008 2 Document Number: 68996

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

50 8.0

VGS = 10 thru 4 V
40 6.4

I D - Drain Current (A)

I D - Drain Current (A)

30 4.8
VGS = 3 V

20 3.2 TC = 25 °C

TC = 125 °C
10 1.6

TC = - 55 °C
0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5

VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)

Output Characteristics Transfer Characteristics

0.015 1300

Ciss
0.013 1040
R DS(on) - On-Resistance (Ω)

C - Capacitance (pF)

0.011 VGS = 4.5 V 780

0.009 520 Coss

VGS = 10 V

0.007 260
Crss

0.005 0
0 10 20 30 40 50 0.0 2.4 4.8 7.2 9.6 12.0

ID - Drain Current (A) VDS - Drain-to-Source Voltage (V)

On-Resistance vs. Drain Current and Gate Voltage Capacitance

10 1.8

ID = 10 A ID = 10 A
R DS(on) - On-Resistance (Normalized)

1.6
VGS - Gate-to-Source Voltage (V)

8
VGS = 10 V
1.4
VDS = 20 V
6
VDS = 10 V
1.2
VGS = 4.5 V
4 VDS = 15 V
1.0

2
0.8

0 0.6
0.0 3.7 7.4 11.1 14.8 18.5 - 50 - 25 0 25 50 75 100 125 150

Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C)

Gate Charge On-Resistance vs. Junction Temperature

S-82749-Rev. A, 10-Nov-2008 3 Document Number: 68996

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

100 0.05

10 TJ = 150 °C 0.04

R DS(on) - On-Resistance (Ω)

I S - Source Current (A)

TJ = 25 °C
1 0.03

0.1 0.02
TJ = 125 °C

0.01 0.01

TJ = 25 °C
0.001 0.00
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 1 2 3 4 5 6 7 8 9 10

VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)

Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage

0.4 80

0.2
64
VGS(th) Variance (V)

0.0
Power (W)

48

- 0.2 ID = 5 mA

32
- 0.4

ID = 250 µA
16
- 0.6

- 0.8 0
- 50 - 25 0 25 50 75 100 125 150 0.001 0.01 0.1 1 10
TJ - Temperature (°C) Time (s)

Threshold Voltage Single Pulse Power, Junction-to-Ambient

100
Limited by RDS(on)*

10
ID - Drain Current (A)

1 ms

1 10 ms
100 ms

1s
10 s
0.1
TA = 25 °C DC
single pulse
BVDSS limited
0.01
0.1 1 10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified

Safe Operating Area, Junction-to-Ambient

S-82749-Rev. A, 10-Nov-2008 4 Document Number: 68996

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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

46.0

36.8

I D - Drain Current (A)

27.6
Package Limited

18.4

9.2

0.0
0 25 50 75 100 125 150

TC - Case Temperature (°C)

Current Derating a

36.0 2.20

28.8 1.76

21.6 1.32
Power (W)
Power (W)

14.4 0.88

7.2 0.44

0.0 0.00
0 25 50 75 100 125 150 0 25 50 75 100 125 150

TC - Case Temperature (°C) TA - Ambient Temperature (°C)

Power Derating, Junction-to-Case Power Derating, Junction-to-Ambient

Note
a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit

S-82749-Rev. A, 10-Nov-2008 5 Document Number: 68996

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 SiR474DP
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

1
Duty Cycle = 0.5
Normalized Effective Transient
Thermal Impedance

0.2

0.1 Notes:
0.1
PDM
0.05

t1
0.02 t2
t1
1. Duty Cycle, D =
t2
2. Per Unit Base = RthJA = 70 °C/W
3. TJM -- TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10 -4 10 -3 10 -2 10 -1 1 10 100 1000
Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

1
Duty Cycle = 0.5
Normalized Effective Transient

0.2
Thermal Impedance

0.1

0.05
0.1
0.02
Single Pulse

0.01
10 -4 10 -3 10 -2 10 -1 1 10
Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Case

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?68996.

S-82749-Rev. A, 10-Nov-2008 6 Document Number: 68996

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 Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® SO-8, (Single/Dual)
H L
E2 K
W E4

D4
θ
1 1

M
Z
2 2

D5
D

D1

D2
D
2
e
3 3

4 4

b
θ
L1
E3
A1 Backside View of Single Pad
θ θ
H L
E2 K
E4
A
c

D3 (2x) D4
E1 Detail Z 1
E
D1
2

D5
K1
D2
3
D2

b
Notes
1. Inch will govern.
2 Dimensions exclusive of mold gate burrs. E3
Backside View of Dual Pad
3. Dimensions exclusive of mold flash and cutting burrs.

MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.97 1.04 1.12 0.038 0.041 0.044
A1 - 0.05 0 - 0.002
b 0.33 0.41 0.51 0.013 0.016 0.020
c 0.23 0.28 0.33 0.009 0.011 0.013
D 5.05 5.15 5.26 0.199 0.203 0.207
D1 4.80 4.90 5.00 0.189 0.193 0.197
D2 3.56 3.76 3.91 0.140 0.148 0.154
D3 1.32 1.50 1.68 0.052 0.059 0.066
D4 0.57 typ. 0.0225 typ.
D5 3.98 typ. 0.157 typ.
E 6.05 6.15 6.25 0.238 0.242 0.246
E1 5.79 5.89 5.99 0.228 0.232 0.236
E2 3.48 3.66 3.84 0.137 0.144 0.151
E3 3.68 3.78 3.91 0.145 0.149 0.154
E4 0.75 typ. 0.030 typ.
e 1.27 BSC 0.050 BSC
K 1.27 typ. 0.050 typ.
K1 0.56 - - 0.022 - -
H 0.51 0.61 0.71 0.020 0.024 0.028
L 0.51 0.61 0.71 0.020 0.024 0.028
L1 0.06 0.13 0.20 0.002 0.005 0.008
 0° - 12° 0° - 12°
W 0.15 0.25 0.36 0.006 0.010 0.014
M 0.125 typ. 0.005 typ.
ECN: S17-0173-Rev. L, 13-Feb-17
DWG: 5881

Revison: 13-Feb-17 1 Document Number: 71655

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 VISHAY SILICONIX
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Power MOSFETs Application Note AN821

PowerPAK® SO-8 Mounting and Thermal Considerations

by Wharton McDaniel PowerPAK SO-8 SINGLE MOUNTING
MOSFETs for switching applications are now available with The PowerPAK single is simple to use. The pin arrangement
die on resistances around 1 m and with the capability to (drain, source, gate pins) and the pin dimensions are the
handle 85 A. While these die capabilities represent a major same as standard SO-8 devices (see figure 2). Therefore, the
advance over what was available just a few years ago, it is PowerPAK connection pads match directly to those of the
important for power MOSFET packaging technology to keep SO-8. The only difference is the extended drain connection
pace. It should be obvious that degradation of a high area. To take immediate advantage of the PowerPAK SO-8
performance die by the package is undesirable. PowerPAK single devices, they can be mounted to existing SO-8 land
is a new package technology that addresses these issues. patterns.
In this application note, PowerPAK’s construction is
described. Following this mounting information is presented
including land patterns and soldering profiles for maximum
reliability. Finally, thermal and electrical performance is
discussed.
THE PowerPAK PACKAGE
The PowerPAK package was developed around the SO-8
package (figure 1). The PowerPAK SO-8 utilizes the same
footprint and the same pin-outs as the standard SO-8. This Standard SO-8 PowerPAK SO-8
allows PowerPAK to be substituted directly for a standard
SO-8 package. Being a leadless package, PowerPAK SO-8
Fig. 2
utilizes the entire SO-8 footprint, freeing space normally
occupied by the leads, and thus allowing it to hold a larger
die than a standard SO-8. In fact, this larger die is slightly The minimum land pattern recommended to take full
larger than a full sized DPAK die. The bottom of the die advantage of the PowerPAK thermal performance see
attach pad is exposed for the purpose of providing a direct, Application Note 826, Recommended Minimum Pad
low resistance thermal path to the substrate the device is Patterns With Outline Drawing Access for Vishay Siliconix
mounted on. Finally, the package height is lower than the MOSFETs. Click on the PowerPAK SO-8 single in the index
standard SO-8, making it an excellent choice for of this document.
applications with space constraints. In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and top
of the drawn pattern. This extension will serve to increase
the heat dissipation by decreasing the thermal resistance
APPLICATION NOTE

from the foot of the PowerPAK to the PC board and

therefore to the ambient. Note that increasing the drain land
area beyond a certain point will yield little decrease
in foot-to-board and foot-to-ambient thermal resistance.
Under specific conditions of board configuration, copper
weight and layer stack, experiments have found that
more than about 0.25 in2 to 0.5 in2 of additional copper
(in addition to the drain land) will yield little improvement in
thermal performance.

Fig. 1 PowerPAK 1212 Devices

Revision: 16-Mai-13 1 Document Number: 71622

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 Application Note AN821
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Vishay Siliconix

PowerPAK® SO-8 Mounting and Thermal Considerations

PowerPAK SO-8 DUAL For the lead (Pb)-free solder profile, see
The pin arrangement (drain, source, gate pins) and the pin www.vishay.com/doc?73257.
dimensions of the PowerPAK SO-8 dual are the same as
standard SO-8 dual devices. Therefore, the PowerPAK
device connection pads match directly to those of the SO-8.
As in the single-channel package, the only exception is the
extended drain connection area. Manufacturers can likewise
take immediate advantage of the PowerPAK SO-8 dual
devices by mounting them to existing SO-8 dual land
patterns.
To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended land
pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click on the
PowerPAK 1212-8 dual in the index of this document.
The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the Fig. 3 Solder Reflow Temperature Profile
PowerPAK SO-8 dual package.
REFLOW SOLDERING Ramp-Up Rate + 3 °C /s max.
Temperature at 150 - 200 °C 120 s max.
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder Temperature Above 217 °C 60 - 150 s
reflow as a test preconditioning and are then Maximum Temperature 255 + 5/- 0 °C
reliability-tested using temperature cycle, bias humidity, Time at Maximum
30 s
HAST, or pressure pot. The solder reflow temperature profile Temperature
used, and the temperatures and time duration, are shown in Ramp-Down Rate + 6 °C/s max.
figures 3 and 4.

30 s
260 °C

3 °C(max) 6 °C/s (max.)

217 °C
150 - 200 °C

150 s (max.)

60 s (min.) Reflow Zone

APPLICATION NOTE

Pre-Heating Zone

Maximum peak temperature at 240 °C is allowed.

Fig. 4 Solder Reflow Temperatures and Time Durations

Revision: 16-Mai-13 2 Document Number: 71622

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 Application Note AN821
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PowerPAK® SO-8 Mounting and Thermal Considerations

THERMAL PERFORMANCE
Introduction Because of the presence of the trough, this result suggests
A basic measure of a device’s thermal performance a minimum performance improvement of 10 °C/W by using
is the junction-to-case thermal resistance, RthJC, or the a PowerPAK SO-8 in a standard SO-8 PC board mount.
junction-to-foot thermal resistance, RthJF This parameter is The only concern when mounting a PowerPAK on a
measured for the device mounted to an infinite heat sink and standard SO-8 pad pattern is that there should be no traces
is therefore a characterization of the device only, in other running between the body of the MOSFET. Where the
words, independent of the properties of the object to which standard SO-8 body is spaced away from the pc board,
the device is mounted. Table 1 shows a comparison of allowing traces to run underneath, the PowerPAK sits
the DPAK, PowerPAK SO-8, and standard SO-8. The directly on the pc board.
PowerPAK has thermal performance equivalent to the
Thermal Performance - Spreading Copper
DPAK, while having an order of magnitude better thermal
performance over the SO-8. Designers may add additional copper, spreading copper, to
the drain pad to aid in conducting heat from a device. It is
TABLE 1 - DPAK AND POWERPAK SO-8 helpful to have some information about the thermal
EQUIVALENT STEADY STATE performance for a given area of spreading copper.
PERFORMANCE Figure 6 shows the thermal resistance of a PowerPAK SO-8
device mounted on a 2-in. 2-in., four-layer FR-4 PC board.
PowerPAK Standard
DPAK The two internal layers and the backside layer are solid
SO-8 SO-8
Thermal
copper. The internal layers were chosen as solid copper to
1.2 °C/W 1 °C/W 16 °C/W model the large power and ground planes common in many
Resistance RthJC
applications. The top layer was cut back to a smaller area
and at each step junction-to-ambient thermal resistance
Thermal Performance on Standard SO-8 Pad Pattern measurements were taken. The results indicate that an area
Because of the common footprint, a PowerPAK SO-8 above 0.3 to 0.4 square inches of spreading copper gives no
can be mounted on an existing standard SO-8 pad pattern. additional thermal performance improvement. A
The question then arises as to the thermal performance subsequent experiment was run where the copper on the
of the PowerPAK device under these conditions. A back-side was reduced, first to 50 % in stripes to mimic
characterization was made comparing a standard SO-8 and circuit traces, and then totally removed. No significant effect
a PowerPAK device on a board with a trough cut out was observed.
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The results Rth vs. Spreading Copper
are shown in figure 5. (0 %, 50 %, 100 % Back Copper)
56
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board
SO-8 Pattern, Trough Under Drain
60
51
Impedance (C/watts)

50
Impedance (C/watts)

40 46
Si4874DY
APPLICATION NOTE

30
41 100 %
Si7446DP
0%
20
50 %
10 36
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Spreading Copper (sq in)
0
0.0001 0.01 1 100 10000 Fig. 6 Spreading Copper Junction-to-Ambient Performance
Pulse Duration (sec)
Fig. 5 PowerPAK SO-8 and Standard SO-0 Land Pad Thermal
Path

Revision: 16-Mai-13 3 Document Number: 71622

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 Application Note AN821
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PowerPAK® SO-8 Mounting and Thermal Considerations

SYSTEM AND ELECTRICAL IMPACT OF Suppose each device is dissipating 2.7 W. Using the
PowerPAK SO-8 junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die
In any design, one must take into account the change in
temperature is determined to be 107 °C for the PowerPAK
MOSFET RDS(on) with temperature (figure 7).
(and for DPAK) and 148 °C for the standard SO-8. This is a
2 °C rise above the board temperature for the PowerPAK
On-Resistance vs. Junction Temperature and a 43 °C rise for the standard SO-8. Referring to figure 7,
1.8 a 2 °C difference has minimal effect on RDS(on) whereas a
R DS(on) - On-Resistance ( ) (Normalized)

VGS = 10 V
43 °C difference has a significant effect on RDS(on).
1.6 ID = 23 A Minimizing the thermal rise above the board temperature by
using PowerPAK has not only eased the thermal design but
1.4 it has allowed the device to run cooler, keep rDS(on) low, and
permits the device to handle more current than the same
1.2 MOSFET die in the standard SO-8 package.

1.0 CONCLUSIONS
PowerPAK SO-8 has been shown to have the same thermal
0.8 performance as the DPAK package while having the same
footprint as the standard SO-8 package. The PowerPAK
0.6 SO-8 can hold larger die approximately equal in size to the
- 50 - 25 0 25 50 75 100 125 150 maximum that the DPAK can accommodate implying no
sacrifice in performance because of package limitations.
TJ - Junction Temperature (°C)
Recommended PowerPAK SO-8 land patterns are provided
Fig. 7 MOSFET RDS(on) vs. Temperature to aid in PC board layout for designs using this new
A MOSFET generates internal heat due to the current package.
passing through the channel. This self-heating raises the Thermal considerations have indicated that significant
junction temperature of the device above that of the PC advantages can be gained by using PowerPAK SO-8
board to which it is mounted, causing increased power devices in designs where the PC board was laid out for
dissipation in the device. A major source of this problem lies the standard SO-8. Applications experimental data gave
in the large values of the junction-to-foot thermal resistance thermal performance data showing minimum and
of the SO-8 package. typical thermal performance in a SO-8 environment, plus
PowerPAK SO-8 minimizes the junction-to-board thermal information on the optimum thermal performance
resistance to where the MOSFET die temperature is very obtainable including spreading copper. This further
close to the temperature of the PC board. Consider two emphasized the DPAK equivalency.
devices mounted on a PC board heated to 105 °C by other PowerPAK SO-8 therefore has the desired small size
components on the board (figure 8). characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.

PowerPAK SO-8 Standard SO-8

107 °C 148 °C
APPLICATION NOTE

0.8 °C/W 16 C/W

PC Board at 105 °C

Fig. 8 Temperature of Devices on a PC Board

Revision: 16-Mai-13 4 Document Number: 71622

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single

0.260
(6.61)
0.150
(3.81)

0.024
(0.61)

(3.91)

(4.42)
0.154

0.174
0.026
(0.66)
(1.27)
0.050

0.050 0.032 0.040

(1.27) (0.82) (1.02)

Recommended Minimum Pads

Dimensions in Inches/(mm)

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APPLICATION NOTE

Document Number: 72599 www.vishay.com

Revision: 21-Jan-08 15
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