L9333

QUAD LOW SIDE DRIVER

PRODUCT PREVIEW

■ WIDE OPERATING SUPPLY VOLTAGE

MULTIPOWER BCD TECHNOLOGY
RANGE FROM 4.5V UP TO 32V FOR
TRANSIENT 45V
■ VERY LOW STANDBY QUIESCENT
CURRENT TYPICALLY < 2µA
■ INPUT TO OUTPUT SIGNAL TRANSFER
FUNCTION PROGRAMMABLE
SO20 & SO20 (12+4+4)
■ HIGH SIGNAL RANGE FROM -14V UP TO 45V
FOR ALL INPUTS ORDERING NUMBER:
■ 3.3V CMOS COMPATIBLE INPUTS L9333MD (SO20 12+4+4)
L9333 (SO20)
■ DEFINED OUTPUT OFF STATE FOR OPEN
INPUTS
■ FOUR OPEN DRAIN DMOS OUTPUTS, WITH
■ STATUS MONITORING FOR
- OVERTEMPERATURE
RDSon = 1.5Ω FOR VS > 6V AT 25°C
- DISCONNECTED GROUND OR SUPPLY
■ OUTPUT CURRENT LIMITATION VOLTAGE
■ CONTROLLED OUTPUT SLOPE FOR LOW EMI
■ OVERTEMPERATURE PROTECTION FOR
DESCRIPTION
EACH CHANNEL
The L9333 is a monolithic integrated quad low side
■ INTEGRATED OUTPUT CLAMPING FOR FAST
driver. It is intended to drive lines, lamps or relais in
INDUCTIVE RECIRCULATION VFB > 45V automotive or industrial applications.

BLOCK DIAGRAM

IN 4 C HA NN E L 4 OU T 4

VS

R IN OU T 1
IN 1
=
&

PR G

TH ER M A L
S H UT-
D OW N C H A NN E L1

4
R IN
DIA G
PR G D IA G-
N O S TIC
LO G IC

R EN
EN

V int
VS
R E FER E NC E V log ic
G ND

January 2000 1/13

This is preliminary information on a new product now in development. Details are subject to change without notice.
L9333

PIN CONNECTION (Top view)

NC 1 20 NC IN1 1 20 PRG
VS 2 19 DIAG IN2 2 19 OUT1
NC 3 18 NC DIAG 3 18 OUT2
SO 20 STD

Med. Power
IN3 4 17 IN2

So 12+4+4
GND 4 17 GND
IN4 5 16 IN1 GND 5 16 GND
EN 6 15 PRG GND 6 15 GND
OUT4 7 14 OUT1 GND 7 14 GND
OUT3 8 13 OUT2 VS 8 13 OUT3
GND 9 12 NC IN3 9 12 OUT4
NC 10 11 NC IN4 10 11 EN

PIN FUNCTION
Package
Pin Name Description
SO20 SO20 (SO 12+4+4)

VS Supply Voltage 2 8

GND Ground 9 4, 5, 6, 7, 14, 15, 16, 17

EN Enable 6 11

PRG Programming 15 20

DIAG Diagnostic 19 3

IN 1 Input 1 16 1

IN 2 Input 2 17 2

IN 3 Input 3 4 9

IN 4 Input 4 5 10

OUT 1 OUTPUT 1 14 19

OUT 2 OUTPUT 2 13 18

OUT 3 OUTPUT 3 8 13

OUT4 OUTPUT4 7 12

NC Not Connected 1,3,10,11,12,18,20 -

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 L9333

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VS Supply voltage DC -0.3 to 32 V

Supply voltage Pulse (T = 400ms) -0.3 to 45 V

dV S/dt Supply voltage transient -10 to +10 V/µs

VIN, VEN, Input, Enable, Programming -14 to 45 V

VPRG Pin voltage

VOUT Output voltage -0.3 to 45 1) V

VDIAG Diagnostic output voltage -0.3 to 45 V

Notes: 1. In flyback phase the output voltage can reach 60V.

ESD - PROTECTION
Value
Parameter Unit
against GND

Supply pins and signal pins ±2 KV

Output pins ±4 KV

Note: Human-Body-Model according to MIL 8832. The device widthstand ST1 class level.

THERMAL DATA
Symbol Parameter Min Typ Max Unit

TJSD Temperature shutdown threshold 175 220 °C

TJSDhys Temperature shutdown hysteresis 20 K

SO 12+4+4

Rth (j-p) Thermal resistance junction to pins 15 °C/W

Rth (j-a) Thermal resistance junction to ambient 2) 50 °C/W

SO 20

Rth (j-a) Thermal resistance junction to ambient 3) 97 °C/W

2. With 6cm2 on board heat sink area.

3. Mounted on SMPCB2 board

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L9333

LIFE TIME
Symbol Parameter Condition Value Unit

tB useful life time V S ≤ 14V 20 years

EN = low

tb operating life time 4.5V ≤ VS ≤ 32V 5000 hours

EN = high

OPERATING RANGE:
Within the operating range the IC operates as described in the circuit description, including the diagnostic table.
Symbol Parameter Condition Min Max Unit

VS Supply voltage 4.5 32 V

VIN, VEN, Input voltage -14 45 V

V PRG

VOUT Output voltage Voltage will be limited by internal Z- -0.3 60 V

Diode clamping

VDIAG Diagnostic output voltage -0.3 45 V

TJ Junction temperature -40 150 °C

ELECTRICAL CHARACTERISTCS
The electrical characteristics are valid within the defined Operating Conditions, unless otherwise specified.
The function is guaranteed by design until TJSDon switch-on-threshold.
Symbol Parameter Test Conditio n Min. Typ. Max. Unit

SUPPLY

IQ Quiescent current V S ≤ 14V; VEN ≤ 0.3V

Tamb 85 °C <2 10 µA

V S ≤ 14V; VEN ≤ 0.3V

Ta 150°C 50 µA

V S ≤ 14V; EN = high, Output = off 1 2 mA

EN = high, Output = on 3.5 mA

Inputs, IN1 - IN4; Programming, PRG

VINlow Input voltage LOW -14 1 V

VINhigh Input voltage HIGH 2 45 V

IIN Input current 0V ≤ VIN ≤ 45V 4) -25 50 µA

RIN Input impedance V IN < 0V; V IN > VS 10 60 kΩ

4. Current direction depends on the programming setting (PRG=high leads into a positive current see also Blockdiagram page 1)

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 L9333

ELECTRICAL CHARACTERISTCS (continued)

Symbol Parameter Test Conditio n Min. Typ. Max. Unit

Enable EN

VENlow Input voltage LOW -14 1 V

VENhigh Input voltage HIGH 2 45 V

REN Input impedance -14V < VEN < 1.5V 5 kΩ

IEN Input current 1.5V < VEN < 45V 5 80 µA

Outputs OUT1- OUT4

RDSon Output ON-resistor V S > 6V, I O = 0.3A 1.7 3.8 Ω

IOLeak Leakage current VO = VS = 14V; Ta < 125°C 1 5 µA

VO = VS = 14V; Ta < 150°C 25 µA

VOClamp Output voltage during clamping E FB ≤ 2mJ; 10 mA < IO < 0.3A 45 52 60 V

IOSC Short-circuit current V S > 6V 400 700 1000 mA

CO internal output capacities VO > 4.5V 100 pF

Diagnostic Output DIAG

VDlow Output voltage LOW IDL = 0.6mA 0.8 V

IDmax Max. output current internal current limitation; VD = 1 5 15 mA

14V

IDLeak Leakage current V D = VS = 14 V; Ta < 125 °C 0.1 1 µA

V D = VS = 14 V; Ta < 150 °C 5 µA

Timing Characteristics 5)

td,on On delay time V S = 14V 2 3.5 µs

td,off Off delay time C ext = 0F; Lext = 0H 3 4.5 µs

tset Enable settling time only testing condition 20 µs

td,DIAG ON or OFF Diagnostic delay time 10mA ≤ I0 ≤ 200mA 10 µs

Sout Output voltage slopes 2.5 9 16 V/µs

Note : All parameters are measured at 125°C.
5. See also Fig.3 Timi ng Characteristics

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L9333

Figure 1. Timing Characteristics

VE N

Active

t
V PR G

N o n - In v e r tin g M o d e In v e r ti n g M o d e

t
V
IN

t
VO U T

VS

0.8 V S
6)

0.2 V S

t set t d,off t d,on t set

6. Output voltage slope not controlled for enable low!

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 L9333

FUNCTIONAL DESCRIPTION
The L9333 is a quad low side driver for lines, lamps or inductive loads in automotive and industrial applications.
The logic input levels are 3.3V CMOS compatible. This allows the device to be driven directly by a microcon-
troller. For the noise immunity, all input thresholds have a hysteresis of typ. 100mV. Each input (IN, EN and
PRG) is protected to withstand voltages from -14V to 45V. The device is activated with a ’high’ signal on ENable.
ENable ’low’ switches the device into the sleep mode. In this mode the quiescent current is typically less than
2µA. A high signal on PRoGramming input changes the signal transfer polarity from noninverting to the inverting
mode. This pin can be connected either to VS or GND. If these pins are not connected, the forced status of the
PRG and EN pin is low. For packaged applications it is still recommended to connect all input pins to ground
respective VS to avoid EMC influence. The forced condition leads to a mode change if the PRG pin was high
before the interruption. Independent of the PRoGramming input, the OUTput switches off, if the signal INput pin
is not connected. This function is verified using a leakage current of 5µA (sink for PRG=high; source for
PRG=low) during circuit test.
Each output driver has a current limitation of min 0.4A and an independent thermal shut-down. The thermal
shut-down deactivates that output, which exceeds temperature switch off level. When the junction temperature
decreases 20K below this temperature threshold the output will be activated again. This 20K is the hysteresis
of the thermal shutdown function. The Gates, of the output DMOS transistors are charged and discharged with
a current source. Therefore the output slope is limited. This reduces the electromagnetic radiation. For induc-
tive loads an output voltage clamp of typically 52V is implemented.
The DIAGnostic is an open drain output. The logic status depends on the PRoGramming pin. If the PRG pin is
’low’ the DIAG output becomes low, if the device works correctly. At thermal shut-down of one channel or if the
ground is disconnected the DIAGnostic output becomes high. If the PRG pin is ’high’ this output is switched off
at normal function and switched on at overtemperature. For the fault condition of interrupted ground, the poten-
tial of VS and Diagnostic should be equal.

DIAGNOSTIC TABLE
Pins EN PRG IN OUT DIAG

Normal function H L L L (on) L (on)

H L H H (off) L (on)

H H L H (off) H (off)

H H H L (on) H (off)

L X X H (off) H (off)

Overtemperature, H L X H (off) * H (off)

disconnected ground or
supply voltage

Overtemperature H H X H(off) * L(on)

X = not relevant
* selective for each channel at overtemperature

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L9333

Figure 2. Application for Inverting Transfer Polarity

BOARD VOLTAGE 14 V

VCC = 5V or 3.3V

33µF

VCC VS
INT PRG
MICROCONTROLLER

DIAG M VCC = 5V
A 0:8 Adressdecoder EN
8
L9333 2W 12 mH 250 mA
D0 IN 1 OUT 1
D1 IN 2 OUT 2 240Ω
VCC
D2 IN 3 OUT 3
D3 IN 4 OUT 4 IN
50 kHz 10µH
GND GND GND
50pF

Figure 3. Application for non Inverting Transfer Polarity

BOARD VOLTAGE 14 V

33µF

VS
PRG

DIAG M VCC = 5V
EN
L9333 2W 12 mH 250 mA
IN 1 OUT 1
IN 2 OUT 2
240Ω VCC
IN 3 OUT 3
IN 4 OUT 4 IN
10µH
GND 50pF
GND

Note We recommend to use the device for driving inductive loads with flyback energy EFB ≤ 2mJ.

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 L9333

EMC SPECIFICATION
EMS (electromagnetic susceptibility)
Measurement setup:
DUT mounted on a specific application board is driven in a typical application circuit (see below). Two devices
are stimulated by a generator to read and write bus signals. They will be monitored externally to ensure proper
function.

Figure 4. PCB layout

TOPSIDE BACKSIDE

Measurement method:
a) The two bus lines are transferred 2m under a terminated stripline. That’s where they were exposed to the
RF-field. Stripline setup and measurement method is described in DIN 40839-4 or ISO 11452-5.
b) DUT mounted on the same application board is exposed to RF through the tophole of a TEM-cell. Mea-
surement method according SAE J1752.
c) The two bus lines are transferred into a BCI current injection probe. Setup and measurement method is
described in ISO 11452-4.

Failure criteria:
Failure monitoring is done by envelope measurement of the logic signals with a LeCroy oscilloscope with ac-
ceptance levels of 20% in amplitude and 2% time.

Limits:
The device is measured within the described setup and limits without fail function.
The Electromagnetic Susceptivity is not tested in production.

a) Field strength under stripline of > 250V/m in the frequency range 1 - 400MHz modulation:AM 1kHz 80%.
b) Field strength in TEM-cell of > 500V/m in the frequency range 1 - 400MHz modulation: AM 1kHz 80%.
c) RF-currents with BCI of > 100mA in the frequency range 1 - 400MHz modulation: AM 1kHz 80%.

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10/13
L9333

Figure 5.
Measured Circuit

2m ANECHOIC CHAMBER
Flat cable
125Hz 16

7
8
9
1
Stripline

13
14
11
SMBYW01-200 Jumper
f 1 11
2
17 33µF
250Hz
10kΩ 10kΩ 20kΩ 4 ∗ 100Ω
f
optional
2 SM6T39A
10nF 4.7nF 4.7nF
4 U(t)
500Hz
f
2 Jumper
VS EN PRG
5 19
The EMS of the device was verified in the below described setup.

1kHz DIAG
4 ∗ 10kΩ
+ 16 14
14V IN1 OUT1
-
17 13
IN2 L9333 OUT2
4 IN3 8
OUT3
5 7
IN4 OUT4
9 GND

4 ∗ 4.7n 4.7nF 4 ∗ 1 nF
optional
 L9333

mm inch OUTLINE AND

DIM.
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2.65 0.093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

E 7.4 7.6 0.291 0.299

e 1.27 0.050

H 10 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.4 1.27 0.016 0.050

SO20
K 0° (min.)8° (max.)

L
h x 45°

B e K A1 C
H

20 11
E

1 1
0

SO20MEC

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L9333

PAD

L9333

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 L9333

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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