2200 Chapter - 6 - Addendum (Ebook) Actualizacion y Mejoras Fisica Orban 2200
2200 Chapter - 6 - Addendum (Ebook) Actualizacion y Mejoras Fisica Orban 2200
2200 Chapter - 6 - Addendum (Ebook) Actualizacion y Mejoras Fisica Orban 2200
®
OPTIMOD-FM
2200
Digital Audio Processor
P/N 96120.000.01
About This Addendum
Over the years, there have been a number of manufacturing variants of the 2200 circuit
boards. This publication contains parts lists, schematics, and parts locator diagrams for
each variant. It therefore serves as a complete reference to all manufacturing variants of
the 2200.
For the most part, the variations have not affected the 2200’s specifications except to im-
prove minor aspects of its performance. We implemented the variations mainly to im-
prove manufacturing efficiencies or to replace components that their manufacturers have
obsoleted. In some cases, this required creation of small daughterboards to plug in the
circuit board footprints originally occupied by the obsoleted parts.
Specifications
It is impossible to characterize the listening quality of even the simplest limiter or com-
pressor based on the usual specifications because such specifications cannot adequately
describe the crucial dynamic processes that occur under program conditions. Therefore,
the only way to evaluate the sound of an audio processor meaningfully is by subjective
listening tests.
Certain specifications are presented here to assure the engineer that they are reasonable,
to help plan the installation, and to help make certain comparisons with other processing
equipment. Some specifications are for features that are only available on the 2200-D.
Performance
Specifications apply for measurements from analog left/right input to stereo composite out-
put and to FM analog left/right output.
Frequency Response (Bypass Mode): Follows standard 50µs or 75µs pre-emphasis curve
±0.15 dB, 2.0 Hz–15 kHz. Analog left/right output and Digital output can be user config-
ured for flat or pre-emphasized output.
Dynamic Range: Output noise floor will depend upon how much gain the processor is set
for (Limit Drive, AGC Drive, Two-Band Drive, and/or Multi-Band Drive), gating level,
equalization, noise reduction, etc. It is primarily governed by the dynamic range of the
A/D Converter, which has a specified overload-to–noise ratio of 110 dB. The dynamic
range of the digital signal processing is 144 dB.
Total System Distortion (de-emphasized, 100% modulation): <0.01% THD, 20 Hz–1 kHz,
rising to <0.05% at 15 kHz. <0.02% SMPTE IM Distortion.
Total System Separation: >60 dB, 20 Hz–15 kHz.
Polarity (Bypass Mode): Absolute polarity maintained. Positive-going signal on input will re-
sult in positive-going signal on output.
Installation
Power
Voltage: 90-120VAC, 100-132VAC or 200-264VAC, 50-60 Hz; 40VA.
Connector: IEC; detachable 3-wire power cord supplied. AC is EMI-suppressed.
Ground: Circuit ground is independent of chassis ground; can be isolated or connected
with a rear panel switch.
Safety Standards: UL, CE, CSA
Environmental
Operating Temperature Range: 32°F to 122°F, 0°C to 50°C at nominal operating volt-
ages.
Humidity: 0-95% RH, non-condensing.
Dimensions (W x D x H ): 19” x 14.25” x 1.75”/48.3cm x 36.2cm x 4.5cm. 1 rack unit high.
Weight: 12 lbs/5.4kg.
Shipping Weight: 15 lbs/6.8kg.
Warranty
One Year, Parts and Labor: Subject to the limitations set forth in Orban’s Standard War-
ranty Agreement.
Specifications are subject to change without notice.
OPTIMOD-FM DIGITAL TECHNICAL DATA 6-5
Circuit Description
This section provides a detailed description of circuits used in the 2200/2200-D. It starts
with an overview of the 2200/2200-D system, identifying circuit sections and describing
their purpose. Then each section is treated in detail by first giving an overview of the cir-
cuits followed by a component-by-component description. Keywords are highlighted
throughout the circuit descriptions to help you quickly locate the information you need.
Overview
The block diagram on page 6-44 illustrates the following overview of 2200/2200-D cir-
cuit sections.
• The 16.384 MHz Oscillator and System Clocking section provides the various
clocks needed by the control, I/O and DSP circuits to carry out their functions.
• The User Control Interface and LED Display Circuits section includes the con-
nector, RF-filtering, and circuitry for the remote control inputs. It also includes
circuitry for the front panel pushbutton switches, LED control status indicators,
and LED Meters. The LED Meters measure various 2200/2200-D signal levels
and display the results on six front panel 10-segment LED meters.
• The L/R Input Circuits include the connectors and RF-filtering for the left and
right audio inputs and the digital audio input, and the circuitry to interface these
inputs to the digital processing.
• The L/R Output Circuits include the connectors and RF-filtering for the left and
right audio outputs and the digital audio output, and the circuitry to interface the
digital processing to these outputs.
• The Composite Output Circuits include the connectors and RF-filtering for the
two composite outputs, and the circuitry to interface the digitally processed, ste-
reo encoded signal to these outputs.
• The DSP Circuits implement the bypass, test tone, audio processing, and stereo
encoding functions using digital signal processing.
clock signals. The only clocks that run asynchronous to this clock are the AES/EBU
digital audio input related clocks and the 11.2896 MHz free running crystal clock os-
cillator providing the 44.1 kHz AES/EBU output sample rate (this does not fall within
a sensitive region of the A/D). Synchronous counters divide the 16.384 MHz clock to
produce the various clock signals for the system. A PLL circuit synthesizes an 18.432
MHz clock for operating the host microprocessor and a 6.144 MHz clock for provid-
ing the 48 kHz AES/EBU output sample rate clock in addition to providing the
AES/EBU input receiver with the ability to measure the input sample rate.
Component-Level Description:
The 16.384 MHz digital output from crystal oscillator Y602 feeds the master
clock (MCLK) inputs of both the input and the output SRC chips IC603 and
IC615. The 16.384 MHz clock also feeds flip-flop IC604, which divides by two to
produce an 8.192 MHz clock. The 8.192 MHz clock feeds digital multiplexer chip
IC610, which routes the 8.192 MHz to AES/EBU digital audio transmitter chip
IC616 when an internally generated 32 kHz output sample rate is selected. The
8.192 MHz clock is also sent to an 8-bit synchronous counter, implemented in
programmable logic array (PLA) IC613.
This counter divides down to obtain the lower frequency system clocks. All out-
puts of the PLA have their transitions coincident with the rising edge of the 8.192
MHz clock. The 8.192 MHz clock is inverted by buffers IC605-A, -B to provide
clocks 8.192M HZA* and 8.192M HZB* that have falling edges coincident with
the transitions of the lower frequency clocks. 8.192M HZA* feeds the bit clock of
the inter-DSP communication links following buffers IC710-B, -D. 8.192M
HZB* feeds the A/D input clock (256 x sample rate), the L/R output D/A master
clock, and the input bit clock on both the L/R output D/A and the composite D/A.
The 2.048 MHz clock output from IC613 feeds the PLL circuit made up of PLA
IC618, 74HC4046 phase detector/VCO IC619 and associated components. The
PLA first buffers the 2.048 MHz signal, providing a clean 2.048 MHz output at
pin 12 used as the reference input to the PLL phase detector (IC619 pin 14). Of
the three detectors included in the 74HC4046, the phase frequency detector (PFD)
is used by the 2200/2200-D. The output of the phase detector (pin 13) feeds the
loop filter made up of resistors R607, R608 and capacitor C605 that provide a
single pole low-pass filter forming a second order loop. Pin 9 of IC619 is the in-
put control voltage to the VCO. Resistor R614 eliminates subharmonic frequency
modulation of the VCO caused by parasitic capacitance. Resistors R605 and R606
set the PLL’s lock-in frequency range. A divide-by-nine counter is placed be-
tween the VCO output and the phase detector comparator input. This places the
VCO output at 18.432 MHz. The PLA IC618 between pins 2 and 15 implements
the divide-by-nine. A 6.144 MHz clock is derived at the counter’s divide-by-three
point and is provided at pin 17 of the PLA. The PLA provides a buffered 18.432
MHz output at pin 14, which feeds Z-180 microprocessor IC100.
IC614-A, -D provide buffered clocks 2.048M HZA and 2.048M HZB for driving
the EXTAL inputs (pin 27) of the DSP chips. Each buffer drives four DSP chips.
The 256 kHz clock output of IC613 (pin 15) is required for the DSP-to-composite
D/A interface. The 128 kHz clock (pin 14) is used for the inter-DSP word clock.
OPTIMOD-FM DIGITAL TECHNICAL DATA 6-7
The 128 kHz, 64 kHz, and 32 kHz clocks are all used in the LCD backlight drive
circuit. The 32 kHz clock is also used for the input word clock of both the output
sample-rate converter (SRC) and the L/R output D/A. The 32 kHz clock is used to
generate DSP interrupt request signals (IRQBA, IRQBB) required for process
timing and interchip synchronization. The circuit consisting of flip-flop IC612
and IC614-B, -C is required to ensure that the first falling edges of all IRQB sig-
nals are coincident. This synchronization occurs every time the unit is powered up
and when there is a processing algorithm change. It is controlled by the Z-180 via
pin 2 of latch IC611. The 32 kHz clock is also used, along with IC313, in the A/D
clock synchronizing circuit. This circuit makes the IRQB and the L/R clocks, both
operating at 32 kHz, phase synchronous. This ensures that the process-to-output
buffer transfer internal to the DSP does not overlap the output buffer-to-peripheral
transfer. The 8.192M HZB* clock that feeds the A/D input clock (IC312 pin 19)
is internally divided down to produce a 32 kHz word clock at IC312 pin 13 and a
2.048 MHz bit clock at pin 14. These clocks are used to control the A/D-to-DSP
serial interface and the input SRC-to-DSP serial interface.
AC terminations are used on various clocks throughout the board to improve sig-
nal integrity for sensitive devices.
Control Circuits
The control circuits process and execute user-initiated requests to the system. The source
of these requests is the front panel buttons and the remote contact closures. These
changes affect hardware function and/or DSP processing. The control circuits also send
information to the LCD display, LED status, and LED meter circuits. A RAM chip stores
code segments. For quick access, an EEPROM chip stores dynamic system state informa-
tion. A ROM chip contains the executable form of 2200/2200-D DSP and Control soft-
ware.
The Z-180 communicates to the DSP through the synchronous serial data host port.
When the DSP requires executable code, the Z-180 reads it from the ROM and sends
it to the DSP. The Z-180 sends parameter control data to the DSP and receives status
data from the DSP. If status from DSP is irregular, the Z-180 will place the
2200/2200-D hardware and DSP in a reset state and execute initialization procedures.
6-8 TECHNICAL DATA ORBAN Model 2200
Component-Level Description:
The Z-180 is IC100. Watchdog timer/voltage monitor IC122 provides the system
reset function. IC122 pin 7 monitors pulses generated every 1 second by the Z-
180. If the Z-180 is not operating correctly to provide the pulses, IC122 will reset
the Z-180. IC122 also monitors the voltage on the +5V source that supplies power
to the 2200/2200-D digital electronics. When the +5V line is above the minimum
operating voltage of +4.75V, R103 will pull RESET* high which allows the Z-
180 to exit the reset condition. When the +5V line is below the minimum operat-
ing voltage, the open-collector output of IC122 pulls Z-180’s RESET* low which
puts the Z-180 into the reset condition, thereby preventing the Z-180 and the
2200/2200-D electronics from executing incorrectly due to low +5V line voltage.
Z-180 IC100 pins 55, 56, and 57 comprise the host serial data communication
port. The Z-180 uses this port to communicate with the DSP IC700-IC707 via
host port interface pins 26, 35, and 41; and with EEPROM IC107 via pins 2, 5,
and 6. Communication is SPI type with Z-180 as master and DSP as slave.
A RAM chip provides temporary storage for Z-180 data and program code segments.
A ROM chip provides permanent storage of the executable control software and the
executable DSP software. System state information that must be maintained while the
2200/2200-D is powered down is stored in an EEPROM. The EEPROM does not lose
data when the 2200/2200-D is powered down.
Component-Level Description:
IC104 decodes Z-180 memory addresses to access instructions to execute from
ROM IC105 and to read or write data from 32KB RAM IC106. EEPROM IC107
is selected by latch IC611 pin 6.
Digital logic decodes Z-180 I/O addresses, allowing the Z-180 to access RAM, ROM
and EEPROM. The logic provides Z-180 data bus allocation by using latches and tri-
state data buffers to allow other 2200/2200-D hardware to communicate to the Z-180.
To control other hardware, the Z-180’s data bus state is latched at the appropriate
time, and the latched control signals are provided to other hardware. For the Z-180 to
read information from other hardware, the Z-180’s data bus is connected at appropri-
ate times to other hardware’s source signals through tri-state data buffers (e.g. IC120).
Component-Level Description:
Decoder IC104 allows the Z-180 to access ROM IC105 and RAM IC106. Decod-
ers IC101, IC102, and IC103 allow the Z-180 to access all other 2200/2200-D
hardware. The decoded outputs from IC101, IC102, and IC103 are used to latch
the state of the Z-180 data bus at appropriate times with data latches IC202,
IC205, IC207, IC303, IC305, IC609, IC611, IC708, and IC709, and to allocate
OPTIMOD-FM DIGITAL TECHNICAL DATA 6-9
the Z-180 data bus at appropriate times to various peripherals via tri-state data
buffers IC120, IC204, and IC601. IC120 buffers or tri-states status information
from the remote contact closure circuitry onto the Z-180 data bus. IC204 buffers
or tri-states information from the user control interface onto the Z-180 data bus.
IC601 buffers or tri-states status information from AES/EBU Receiver IC600
onto the Z-180 data bus.
1. Remote Interface
A remote interface connector and circuitry enables remote control of certain operating
modes; the 2200 has eight remote contact closure inputs.
A valid remote signal is a momentary pulse of current flowing through the particular
remote signal pins. Current must flow consistently for 50 msec for the signal to be in-
terpreted as valid. Generally, the 2200/2200-D will respond to the most recent control
operation whether it came from the front panel, or remote interface.
Component-Level Description:
J101 is a 25-pin D-connector that connects the remote control input signals. The
connector incorporates a ferrite block to filter out RFI from the signals. The asso-
ciated opto-isolators (e.g. IC110) isolate the inputs from the detector circuitry on
the 2200/2200-D. The associated diodes (e.g. CR102) prevent the opto-isolators
from breaking down under a reverse bias. The outputs of the opto-isolators are in-
verted and buffered (e.g. by IC118-A) and latched by tri-state data buffer IC120.
When REMOTE* signal provided to IC120 pin 19 is brought low, IC120 places
remote signals on the Z-180 data bus.
Ten front panel pushbutton switches are arranged in a matrix, configured as two col-
umns and six rows (the FUNCTION and CONTRAST keys have dedicated rows).
These switches are the primary element of the physical user interface to the
2200/2200-D control software. The host microprocessor controls the system setup and
function of the DSP according to the switch/rotary encoder entered commands, the
AES Status bits from the Digital Input signal, and the remote control interface status;
it then updates the LED control status indicators accordingly.
6-10 TECHNICAL DATA ORBAN Model 2200
Component-Level Description:
S200-S208 and S210 are the front panel pushbutton switches. CR200-CR204 and
CR206 are the front panel LED control status indicators. Via decoder IC102, the
host microprocessor Z-180 periodically selects data latch IC202 (on the display
board) to drive one of the two columns in the switch matrix low, then commands
tri-state data buffer IC204 (also on the display board) to read its inputs to deter-
mine if any new information is being received from one or more of the switches
in that column. If no switches are closed, pull-up resistors R202, R210-R213 pull
the buffer inputs to +5V. The buffer, in turn, de-bounces the signals and places
the appropriate word on the data bus for the Z-180 to read. The Z-180 transmits
the updated information to data latch IC202 which directly drives the LED Con-
trol Status Indicators.
The meter LEDs are arranged in an 8x8 matrix, in rows and columns. Each row of
LEDs in the matrix has a 1/8 duty cycle ON time. The rows are multiplexed at a fast
rate so that the meters appear continuously illuminated. Via the serial port, the DSP
sends meter data values to the Z-180, which alternately sends pairs of mapped 8-bit
words to the data bus. One of the words, latched by a <169>row selector<170> latch,
has a single rotating active bit to select one of the eight rows. The other word, latched
by a <169>column selector<170> latch, has active bits corresponding to those of the
eight LEDs in the selected row that are to be lit. The latched words control high-
current Darlington transistor arrays, which drive the LED matrix.
Component-Level Description:
The meter LED matrix consists of six 10-segment LED bargraph assemblies
(CR208-CR213) and three discrete LEDs (CR214-CR216). IC208 contains eight
Darlington transistors, each of which is connected to the cathodes of a row of the
LEDs. Row selector latch IC207, controlled by the Z-180, alternately turns one of
the eight transistors on, such that it will sink current through the LEDs selected by
column selector latch IC205, also controlled by the Z-180. IC205 turns on the ap-
propriate transistors inside current driver IC206 to drive the selected row of
LEDs. IC206 gets its current from a storage capacitor fed directly by the power
transformer’s lower voltage secondary winding. Resistors RP200 function as cur-
rent limiting resistors.
The RF-filtered left and right analog input signals are each applied to a resistor load
and a resistor pad. The pad and load are enabled or disabled by jumpers that are posi-
tioned by hand. The loaded and padded signal is applied to a floating-balanced ampli-
fier that has an adjustable (digitally controlled) gain. FET transistors and analog
switches set the gain. The state of the FETs and switches is set by the outputs of a
latch. The control circuits control the gain according to what the user specifies from
the front panel controls by writing data to the latch. The gain amplifier output feeds a
circuit that scales, balances, and removes DC from the signal. This circuit feeds an RC
low-pass filter, which applies the balanced signal to the analog-to-digital (A/D) con-
verter.
Component-Level Description:
The left channel balanced audio input signal is applied to the filter/load/pad net-
work made up of L300, L301, L302, L303, R300-R305, C323 and C324. J301 is
a jumper that removes or inserts the optional 600Ω termination load (R300) on
the input signal. J302 and J303 are the jumpers that remove or insert the resistive
divider (R301-R303) that pads the input signal before it is applied to IC300, a dif-
ferential amplifier. R306, R307, R310-R313, FETs Q300-Q301, and quad analog
switch IC307 make up the circuit that sets the gain of IC300. The FETs, along
with IC307, are used as switches to change the resistive paths in the circuit. The
state of the FET switches is set by the outputs of digital latches IC304 and IC305.
The latch outputs feed IC306, a quad comparator, which outputs 0V to turn on a
FET and –15V to turn off a FET. The control circuit writes directly to IC307 to
control the state of the switches on IC307. IC300 feeds IC302 and associated
components. This stage balances the signal and attenuates by 3.5 dB to scale the
signal to the proper level for the analog-to-digital (A/D) converter. IC301-B and
associated components comprise a servo amp to prevent DC from passing to the
DSP. R334, R337, C302, and C303 make a simple RC filter necessary to filter
high frequency energy that would otherwise cause aliasing distortion in the A/D
converter. The corresponding right channel circuitry is functionally identical to
that just described.
The A/D is a stereo, 20-bit sigma-delta converter. The A/D oversamples the audio at
2.048 MHz. It applies noise shaping; then it filters and decimates to a 32 kHz sample
rate. The samples are output in two’s complement, 32-bit word, two-word frame serial
format, with SPI compatible timing, MSbit first, and transmitted to the DSP. The 32
kHz frame clock and 2.048 MHz bit clock from the A/D function as master clocks for
the 2200/2200-D input to the DSP. For more information on 2200/2200-D input
clocking, please refer to 16.384 MHz Oscillator and System Clocking on page 6-5.
6-12 TECHNICAL DATA ORBAN Model 2200
Component-Level Description:
The balanced left and right analog inputs are applied to the A/D (IC312). The
maximum differential signal that the A/D can accept is ±7.36Vpeak. The A/D
samples the left and right inputs simultaneously at 64 times the 2200/2200-D sam-
ple rate of 32 kHz. ICLKD, the master clock input of the A/D (pin 19), is fed an
8.192 MHz clock providing the 2.048 MHz input sample rate required. The A/D
sends the digitized stereo audio to the first DSP chip (IC700) via its synchronous
serial port formed by the data SDATA (pin 15), the bit clock SCLK (pin 14) and
the word clock L/R* (pin 13). The SPI communication standard is used for this
audio interface, with A/D as master and DSP IC700 as slave. The SPI format is:
32-bits/word, multiplexed stereo, word clock low represents left data present,
MSB first, data transitions occur on rising edge of the bit clock, first 18 bits are
valid, trailing bits are set low, MSB delayed one bit period from word clock edge.
IC314 provides buffering to reduce the drive requirement of the on-board drivers
on the A/D and to ensure that there are no overshoots or undershoots as a result of
transmission line reflections that may degrade the performance of the A/D.
IC109-D is required to invert the word clock to support the SPI interface.
The digital input receiver accepts digital audio signals using the AES/EBU interface
format (AES3-1992). The receiver and input sample rate converter (SRC) together
will accept and sample-rate convert any of the “standard” 32 kHz, 44.1 kHz, 48 kHz
rates in addition to any digital audio sample rate within the range of 25 kHz and 55
kHz. The audio signal received is decoded by the AES receiver and sent to the SRC.
The SRC converts the input sample rate to the 32 kHz 2200-D system sample rate.
Via a synchronous serial interface, the SRC sends the 32 kHz sample rate audio to the
DSP for processing.
Component-Level Description:
The differential digital input signal is received through a shielded 1:1 pulse trans-
former (T600). T600 has very low inter-winding capacitance, providing a high
level of isolation for high frequency common mode interference. IC600 is a dedi-
cated AES/EBU digital audio receiver integrated circuit. It contains a phase
locked loop that recovers the clock and the synchronization information present in
the AES/EBU signal. A Schmitt trigger at the input provides 50mV of hysteresis
for added noise immunity. R600 provides an 110Ω input impedance per the
AES/EBU specification.
The Z-180 provides the active high reset signal (AES_RST) to IC600 mode con-
trol pins 17, 18, and 23, via latch IC609 pin 6. This is used when the 2200-D is
asked to respond to analog audio input. When in the reset state, the receiver holds
all outputs inactive (except MCK pin 19).
IC600 pins 2 through 6 and pin 27 are an output latch that provides AES/EBU
status information, selected by the STATSEL line. The information on this latch
is provided to the Z-180 data bus via tri-state data buffer IC601. STATSEL signal
from IC611 pin 12 is applied to IC600 pin 16. When STATSEL is high, pins 2
OPTIMOD-FM DIGITAL TECHNICAL DATA 6-13
through 6 and pin 27 contain information about the channel status bits. When
STATSEL is low, pins 2 through 6 and pin 27 contain input sample rate and error
information. The Z-180 reads these to determine if a valid AES/EBU signal and
sample rate is present. CHSEL is used to select whether channel A or channel B
status bits are present on IC600’s output latch. When STATSEL is low, left chan-
nel status is made available, and when STATSEL is high, right channel status is
made available.
Received AES audio is transmitted from the AES receiver to the input sample rate
converter (SRC IC603), in the synchronous serial SPI format. The AES receiver
is master and the SRC is slave. The AES receiver outputs data on pin 26, the bit
clock on pin 12, and the frame clock on pin 11. The frame clock is inverted by
IC605-F for compatibility with the SRC’s input port. These signals are sent to the
SRC serial input interface pins 3, 4, and 6 respectively.
The MCK clock output at pin 19 of the AES receiver chip has a frequency 256
times the input sample rate of the received signal. This is used to drive the output
AES/EBU transmitter when an output sample rate that is synchronous to the input
sample rate (external sync) is required.
The crystal oscillator (Y602) provides the SRC a master clock of 16.384 MHz on
pin 2. This MCLK frequency allows the input SRC to operate with input sample
rates in the range of 8.192 kHz (MCLK/2000) to 57 kHz (MCLK/286). SRC_RST
is an active low reset signal tied to pin 13 of the SRC. This signal is controlled by
the Z-180 via pin 2 of latch IC609.
The MSDLY_I, BKPOL_I, and TRGLR_I pins of the SRC chip configure the
chip for SPI format. Pin 1 of the SRC (GPDLYS) is tied high to minimize the
chip’s group delay to approximately 700µs as opposed to approximately 3ms, giv-
ing up some tolerance to variations in sample rates. Pin 28 (SETLSLW) is tied
high to cause the SRC to settle slowly to changes in sample rates, resulting in the
best rejection of sample rate jitter.
The sample rate converted output of the input SRC feeds the first DSP chip
(IC700). The SRC output port and the DSP input port are both slaves, with clocks
supplied by the L/R input A/D converter (IC312). The SRC generates DIG_IN
(data) on pin 23, and receives the bit clock and the word clock on pins 26 and 24
respectively. An inverted version of this word clock is used by the DSP chip to
conform with the SPI format it requires.
output sample rate converter (SRC) and transmits them in AES/EBU-format digital audio
signals on the digital output connector.
For information on 2200/2200-D system clocking, please refer to 16.384 MHz Oscil-
lator and System Clocking on page 6-5.
Component-Level Description:
IC400 is the digital-to-analog (D/A) converter for the left and right output signals.
The synchronous serial input interface consists of the bit clock, data and latch en-
able pins that are configured for the SPI format via DIF0 and DIF1 pins (for de-
tails on SPI, see page 6-12. The processed digital output (ANLG_OUT) is pro-
vided by DSP IC706 on its SAI output port SDO0 (pin 47), and is received by the
D/A on pin 18.
An 8.192 MHz bit clock is provided from the system clock circuitry to both the
DSP and the D/A chips. The DSP output data format is SPI (32 bits per word, two
words per frame). DSP chip IC706 receives a 128 kHz frame clock at its WST in-
put (pin 50) that sets the word transfer rate to eight words per 32 kHz period. The
D/A receives a 32 kHz clock at its LRCK input (pin 20). LRCK delineates the left
and right samples used by the D/A; therefore the D/A uses the first sample re-
ceived for the left output and the fifth sample for the right output. The DSP output
samples are formatted to ensure that the D/A uses a left and right output pair that
represent the simultaneously sampled analog input.
The left and right analog signals emerging from the digital-to-analog (D/A) converter
are each RC low-pass filtered and applied to an inverting amplifier having an adjust-
able (digitally controlled) gain. The gain is set by an MDAC. The state of the MDAC
is set by the outputs of a latch. The control circuits control the gain according to what
the user specifies from the front panel controls by writing data to the latch. The gain
amplifier feeds a programmable de-emphasis filter stage with its response digitally
controlled by JFET switches. The de-emphasis stage feeds a floating-balanced line
driver, having a 30Ω ±5% output impedance. The line driver outputs are applied to the
RF-filtered left and right analog output connectors.
Component-Level Description:
The left channel signal emerging from the digital-to-analog (D/A) converter is RC
low-pass filtered by R402 and C407 to remove high frequency images. It is then
applied to an adjustable gain amplifier formed by VR400, R404-R406, C409,
IC401, and IC402-A. These components form an inverting amplifier circuit.
IC401 is an 8-bit MDAC, which is a resistor ladder with a programmable resis-
tance. The control circuit writes an 8-bit word directly to IC401, which has a latch
OPTIMOD-FM DIGITAL TECHNICAL DATA 6-15
on board to store the word. The word sets the resistance value between pin 15 and
pin 1 of IC401. IC402-A forces pin 1 of IC401 to virtual ground. The resistance
between pin 1 and pin 16 of IC401, and resistors R404-R406 and VR400 are in
the feedback loop of IC402-A. C409 stabilizes this stage. VR400 is a factory gain
trim to correct for tolerances in IC401, IC400, and the rest of the analog output
circuits.
IC402-A feeds the stage consisting of IC402-B and associated components, which
are a programmable de-emphasis filter. JFETs Q400 and Q401 are used to switch
C410 and C411, respectively, in or out of the circuit. The state of the JFET
switches is set by the outputs of IC305, a digital latch. The latch outputs feed
IC407, a quad comparator, which outputs 0V to turn on a FET and –15V to turn
off a FET. If neither of the JFETs are on, the circuit is a unity-gain inverting am-
plifier. The circuit becomes a first-order low-pass filter if one of the JFETs is
turned on. If Q400 is on, capacitor C410 is in circuit to create a 75µs time con-
stant. If Q411 is on, capacitor C401 is in circuit to create a 50µs time constant.
IC402-B feeds the stage consisting of IC403-A, IC403-B, IC408-A, and associ-
ated components, which is a floating-balanced line driver. The floating character-
istic is achieved by complex cross-coupled positive and negative feedback be-
tween two 5532 opamps, and its operation is not readily explainable except by a
detailed mathematical analysis. Opamps may be replaced; resistors are specially
matched and should not be replaced. IC408-A, R444, R445, R447, and C419
comprise a servo amplifier that centers around ground the average DC level at
output connector J400.
The balanced audio output signal is applied to the RF filter network made up of
L400, L401, L402, and L403, and then to XLR connector J400.
The corresponding right channel circuitry is functionally identical to that just de-
scribed.
An output sample rate converter (SRC) chip is used to convert the 32 kHz 2200-D
system sample rate to any of the standard 32 kHz, 44.1 kHz or 48 kHz rates. A digital
audio interface transmitter chip is used to encode digital audio signals using the
AES/EBU interface format (AES3-1992). A synchronous serial interface is used for
all interchip communication.
Component-Level Description:
The processed digital output (DIG_OUT) provided at the SAI output port SDO0
(pin 47) of DSP IC706 is received by asynchronous sample rate converter (SRC)
IC615 pin 3. An 8.192 MHz bit clock is provided from the system clock circuitry
to both the DSP and the SRC chips. The DSP output data format is SPI (32 bits
per word two words per frame). DSP chip IC706 receives a 128 kHz frame clock
at its WST input (pin 50) that sets the word transfer rate to eight words per 32
kHz period. The SRC receives a 32 kHz clock at its L/R*_I input (pin 6). L/R*_I
6-16 TECHNICAL DATA ORBAN Model 2200
delineates the left and right samples used by the SRC; therefore the SRC uses the
first sample received for the left input and the fifth sample for the right input. The
DSP output samples are formatted to ensure that the SRC uses a left and right out-
put pair that represent the simultaneously sampled analog input.
The crystal oscillator (Y602) provides the SRC a master clock of 16.384 MHz on
pin 2. This MCLK frequency allows the output SRC to operate with an output
sample rate in the range between 30 kHz and 57 kHz (operation between 8 kHz
and 30 kHz will result in a one sample delay between the left and right channels).
SRC_RST is an active low reset signal tied to pin 13 of the SRC. This signal is
controlled by the Z-180 via pin 2 of latch IC609.
The MSDLY_I, BKPOL_I, and TRGLR_I pins of the SRC chip configure the
chip for SPI format. Pin 1 of the SRC (GPDLYS) is tied high to minimize the
chip’s group delay to approximately 700µs as opposed to approximately 3ms,
giving up some tolerance to variations in sample rates. Pin 28 (SETLSLW) is tied
high to cause the SRC to settle slowly to changes in sample rates, resulting in the
best rejection of sample rate jitter.
The output side of the sample rate converter is tied directly to IC616, an
AES/EBU digital audio transmitter integrated circuit. This interface uses the SPI
format with the AES transmitter as master. The transmitter chip encodes the audio
data it receives to the AES/EBU interface standard, and transmits it.
The SRC output sample rate and the sample rate that the AES/EBU transmitter
transmits with is based on the MCK clock provided to pin 5 of IC616. This clock
is received via digital multiplexer chip IC610 which is used to select one of four
available clocks. Three free-running clocks provide the standard sample rates of
32 kHz, 44.1 kHz and 48 kHz when an internal sync is requested. These clocks
run at a frequency that is 128 times the sample rate they represent. They have a
frequency stability of ±100PPM. The fourth clock is the EXTMCK clock that is
recovered from the AES/EBU receiver chip. This clock has a frequency of 256
times the input sample rate of the received signal. This is used to drive the output
AES/EBU transmitter when an output sample rate is required that is synchronous
to the input sample rate (external sync).
The inter-chip serial data format, the input MCK multiplication factor, and the
output channel status data are controlled by the Z-180 via internal control regis-
ters and data memory accessed through the parallel port made up of the 5-bit ad-
dress bus (pins 9-13), the 8-bit data bus (pins 1-4, 21-24) and the CS* and
RD/WR* control pins (pins 14 and 16) of IC616.
The on-chip RS422 line driver provided by IC616 is a low skew, low impedance,
differential output capable of driving a 110Ω transmission line with a 4Vp-p sig-
nal. Shielded 1:1 pulse transformer T601 transmits the differential digital output
signal to XLR connector J601. T601 has very low inter-winding capacitance, pro-
viding a high level of isolation from high frequency common mode interference.
OPTIMOD-FM DIGITAL TECHNICAL DATA 6-17
Composite Output Circuits
This circuitry provides several functions. It interfaces the digital stereo multiplex output
from the stereo encoder DSP to a digital-to-analog (D/A) converter, which converts it to
an analog signal. The low-pass reconstruction filter removes high frequency images from
the D/A converter output and feeds the output buffers. Two output stages with separate
level controls buffer the stereo multiplex signal and feed the composite output connectors.
The composite D/A is a single chip, 18-bit resistor ladder type. It has a single channel
serial input that receives the digital stereo encoded output samples from the DSP. It is
a surface-mount part that is mounted on a small daughterboard, replacing the DIP
package previously used in the 2200.
Component-Level Description:
IC500 is the digital-to-analog converter for the stereo-encoded composite signal.
The synchronous serial input interface consists of the bit clock, data and latch en-
able pins. DSP IC707 provides serial data (COMP_O) to pin 7 of the composite
D/A.
An 8.192 MHz bit clock is provided from the system clock circuitry to both the
DSP and the D/A chips. The DSP output data format is 32-bits per word two
words per frame, MSB first (first 24-bits are significant). DSP IC707 receives a
128 kHz frame clock at its WST input (pin 50) that sets the word transfer rate to
256 kHz. The D/A receives a 256 kHz clock at its latch enable (LE) input (pin 6).
The D/A uses the last 18-bits received prior to the falling edge of LE (last 18-bits
are significant). Flip-flop IC604-A is used to invert and shift the 256 kHz system
clock to produce an LE signal that has a falling edge aligned with the 18th signifi-
cant data bit.
Pin 9 is the analog voltage output of IC500. The voltage changes to the current
sample value on the falling edge of the 256 kHz clock. A full scale output is ap-
proximately ±3.0Vpeak, which corresponds to 141% modulation. C517 prevents
slew-induced distortion.
The reconstruction filter removes the ultrasonic energy “images” present at the D/A
output. It is a passive seventh-order elliptic filter with a cutoff frequency of approxi-
mately 70 kHz and >90 dB stopband attenuation above 203 kHz.
Component-Level Description:
The reconstruction filter is a passive seventh-order LC ladder filter, realized by
resistors R501, R502 and R504, capacitors C508-C512, C516, and C518, and in-
6-18 TECHNICAL DATA ORBAN Model 2200
The filter is buffered by non-inverting amplifier IC502-A and applied to the out-
put stages. IC501-A is a DC servo to prevent DC from appearing at the composite
outputs.
The buffered filter output is applied to two power buffers each capable of driving two
75Ω loads in parallel.
Component-Level Description:
The stereo modulator output is fed into two separate output buffers. The first con-
sists of IC503-A and IC504. IC504 is a special high slew rate power buffer, which
is located within the overall amplifier feedback loop. It isolates IC503-A from the
destabilizing effects of capacitive loads and permits 75Ω loads to be driven with-
out degradation. This line driver will drive up to ±1.5Vpeak into 0.047uF in paral-
lel with 37.5Ω before significant nonlinear errors (increases in spurious compo-
nents as observed on a baseband spectrum analyzer) or linear errors (noticeable
deterioration of baseline flatness at 15 kHz in the separation test mode) are appar-
ent. Output level is adjusted by varying the feedback resistor VR500. The second
output buffer made by IC505-A and IC506 is functionally identical to the one just
described.
DSP Circuits
The DSP circuits consist of eight general-purpose DSP chips that execute DSP software
code to implement digital signal processing algorithms. The algorithms filter, compress,
limit, and stereo encode the audio signal. The eight DSP chips, operating at 25 million
instructions per second (MIPS) for a total of 200MIPS, provide the necessary signal
processing. Sampling rates from 32 kHz to 128 kHz are used. Two of the on-board serial
audio interface (SAI) peripherals on each DSP chip are used to transfer data chip-to-chip
at a 16.384Mbit/s rate maintaining a 24-bit word length. The DSP chips are cascaded,
processing the audio serially. The first chip receives the analog input via the A/D chip and
the digital input via the SRC chip. Input source selection is performed seamlessly, inter-
nal to the DSP chip.
During system initialization (which normally occurs when power is first applied to the
2200/2200-D), and when processing algorithms are changed, the Z-180 downloads the
DSP executable code stored in the ROM, via the serial host interface (SHI) port of each
DSP chip. Once a DSP chip begins executing its program, execution is continuous. The
Z-180 provides the DSP program with parameter data, and extracts the front panel meter-
ing data from the DSP chips via this same SHI port.
OPTIMOD-FM DIGITAL TECHNICAL DATA 6-19
The left and right analog and digital outputs are sent to the L/R output D/A and the output
SRC chip via the SAI port of DSP chip IC706. The last DSP chip (IC707) outputs the
composite audio signal on its SAI port where it is directed to the composite D/A.
Component-Level Description:
IC700 thru IC707 are the DSP chips. Do not attempt to remove these chips from
the PCB; only the Orban service department should remove these chips. A chip
can be ruined by static discharge or by damage to its delicate pins.
The EXTAL pin of each DSP chip receives a 2.048 MHz clock. All DSP chips
use their internal PLL to multiply this by 24 to operate the chip’s internal oscilla-
tor (Fosc) at 49.152 MHz. Each DSP chip is reset by the Z-180 via latch IC709.
DSP mode configuration is controlled by the state of the MODA, MODB and
MODC (pins 37, 38, 39) on each chip as the chip is brought out of reset. All DSP
chips are configured to bootstrap via the SHI port. The MODB pin, which also
serves as the IRQB input after leaving the reset state, is forced low prior to bring-
ing the DSP chips out of reset.
Pins 26, 35, 41 and 42 comprise the DSP host port. Host port communication con-
forms to the SPI format with the Z-180 set-up as the master and the DSPs as
slaves. The Z-180 generates the HOSTCK clock signal and provides it to SCK
(pin 26) of each DSP. The Z-180 provides the data on the HOSTTX line tied to
pin 41 of each DSP. The data output (pins 35) of each DSP have tri-state outputs
that are wire-ORed to provide the data on the HOSTRX line sent to the Z-180.
The Z-180 controls the slave select (SS*) (pin 42) of each DSP via latch IC708.
The SS* pin is used to enable each of the slaved DSP SPI ports for transfer.
DSP IC700 pins 56 and 57 receive serial stereo audio from the digital and analog
inputs. These are the two input ports of the synchronous serial audio interface
(SAI) receiver internal to the DSP. The communication protocol is SPI with DSP
as a slave, and L/R input A/D converter IC312 as master. Left and right data
words, each of 32-bit length, constitute a frame. Eighteen significant bits are re-
ceived from the analog input A/D and twenty significant bits are received from
the digital input SRC. The two serial stereo audio streams are received simultane-
ously. Both inputs share the same frame clock, L*/R (32 kHz) provided to DSP
IC700 pin 55 and the same bit clock, SCK (2.048 MHz) provided to DSP IC700
pin 51.
Communication between DSP chips IC700 (first) thru IC707 (last) is one-way, in
series from the first to the last. Two of the on-board SAI peripherals on each DSP
are used to transfer eight words each per frame chip-to-chip. The SPI communica-
tion protocol (two 32-bit words per cycle of the word clock) is used with the
DSPs as slaves, and the 2200/2200-D system clocking as master. Data is sent
from the two transmit data port pins 46 and 47 of one chip to the next chip’s re-
ceive data port pins 56 and 57. A 128 kHz word clock is provided to the transmit
pin 50 and the receive pin 55. An 8.192 MHz bit clock is provided to the transmit
pin 49 and the receive pin 51. The SAI links between DSPs are synchronized to
each other (to align the SAI time slots) by making the first occurrence of all
IRQBs coincident, (controlled by Z180 and external hardware) and having all
6-20 TECHNICAL DATA ORBAN Model 2200
The “analog” and digital outputs are transferred respectively to the L/R output
D/A and the output SRC from the second to the last DSP chip (IC706). These sig-
nals are identical except for any De-Emphasis, J.17 Pre-Emphasis, J.17 Emphasis
makeup gain, or output attenuation (DO 100% level) applied to the digital output.
The “analog” output is also passed on to the last DSP chip (IC707) for stereo en-
coding. (“Analog”refers to DSP signal that ultimately gets converted to analog.)
The composite FM stereo signal is output from the last DSP chip (IC707) via its
SAI transmitter, formed by DSP IC707 pins 47, 49, and 50. A communication
protocol compatible with the composite D/A (IC500) is used with the DSP and
D/A as slave and the 2200/2200-D system clocking as master. The serial compos-
ite audio bit stream output on pin 47 feeds D/A IC500 pin 7. DSP IC707 pin 50
receives a 128 kHz frame clock and pin 49 receives an 8.192 MHz bit clock. Two
consecutive composite audio data words, each of 32-bit length, constitute a frame.
Power Supply
The power supply converts an AC line voltage input to various power sources used by the
2200/2200-D. Five linear regulators provide ±15VDC and ±5VDC for the analog circuits
and +5VDC for the digital circuits. An unregulated voltage powers the LED meters and
the LED backlight on the LCD display.
Component-Level Description:
L1 is a power line filter that filters out RFI. F1 is a ½-amp “Slo-Blo” fuse. T1 is a
dual-primary dual-secondary power transformer used to step down the input volt-
age for the ±15VDC analog and +5VDC digital supply regulators. Each primary
winding has a metal-oxide varistor (V1, V2) connected in parallel to suppress
high-voltage spikes across the AC line. Rear panel switch S1 configures the pri-
mary windings either in parallel (for 115V ±15% line voltages) or series (for
230V ±15% line voltages).
T1 has two pairs of secondary windings for stepping down the AC line voltage.
The lower voltage pair is configured in parallel, and feeds storage capacitors C15
and C19 through full-wave bridged rectifier diodes CR13, CR14, CR15, CR17,
and CR18. C15 filters the rectified voltage for input to low-dropout linear voltage
regulator IC5, which provides the +5VDC source used to power all of the digital
circuits in the 2200/2200-D. C19 filters the rectified voltage to power the LED
backlight on the LCD display, and the LED meters. Components Q1, Q2, R3-R7,
and CR20 form a pulsed current source to illuminate the 25x2 LED array (the
backlight on the LCD display). The signal LEDPULSE, a 32 kHz pulse at c duty
cycle, feeds the base of high-current Darlington transistor Q1. The feedback cir-
cuit consisting of Q2, CR20 and R3-R7 controls the magnitude of the signal
LEDPULSE so as to limit Q1’s current pulses to about 1.5A (1/8 duty cycle).
These current pulses illuminate the 25 x 2 LED array via keyed header J201,
which attaches the LED array between the collector of Q1 and supply cap C19.
The signal LEDPULSE is gated on for approximately one hour after the 2200 has
last been powered up or a front panel button has last been pressed; otherwise, it is
OPTIMOD-FM DIGITAL TECHNICAL DATA 6-21
gated off. This drastically increases the lifetime of the LCD display and saves
about two Watts of power. The LED meter circuits are described in User Control
Interface and LED Display Circuits on page 6-9.
Test points and supply bypass capacitors are placed throughout the PC board. S2
is the ground lift switch used to connect or lift 2200/2200-D circuit ground from
chassis ground.
Abbreviations
Some of the abbreviations used in this manual may not be familiar to all readers:
Orban normally maintains an inventory of tested, exact replacement parts that can be
supplied quickly at nominal cost. Standardized spare parts kits are also available. When
ordering parts from the factory, please have available the following information about the
parts you want:
Full parts lists are only shown for the oldest version of the board. After that, parts lists
only show parts that have changed from one version to the next. [deleted] in a list indi-
cates that a part existing in the next oldest version has been removed.
Widely used common parts are described generally below (examine the part to determine
its exact value). See the following assembly drawings for locations of components.
• Signal diodes, if not listed by reference designator in the following parts list, are:
Orban part number 22101-000; JEDEC part number 1N4148; also available
from many other vendors. This is a silicon small-signal diode with ultra-fast
recovery and high conductance. It can be replaced with 1N914 (BAY-61 in
Europe).
(BV: 75V min. @ Ir = 5µA; Ir: 25nA max. @ Vr = 20V; Vf: 1.0V max. @ If =
100mA; trr: 4ns max.)
6-24 TECHNICAL DATA ORBAN Model 2200
Display Assembly
2200 PCA Display 31875.000.01 Rev 01, ECO 2216A
Schematic Rev 01 ECO 2216A Displ r01 ECO 2216A
[no difference]
Main Board
2200 PCA Main 31810.001 Rev 01, ECO 2216A, 2254, 2284
Schematic Rev ECO 2216A Main r01 ECO 2216A, 2254, 2284
01
Schematic Rev ECO 2216A Main r01 ECO 2216A, 2254, 2284
01
20041.301.01 RESISTOR, METAL 2 R350, R606
FILM,1/8W,1%,3.01 kohm
20041.316.01 RESISTOR, METAL 1 R607
FILM,1/8W,1%,3.16 kohm
20041.392.01 RESISTOR, METAL 2 R312, R328
FILM,1/8W,1%,3.92 kohm
20041.402.01 RESISTOR, METAL 2 R448, R453
FILM,1/8W,1%,4.02 kohm
20041.432.01 RESISTOR, METAL 2 R446, R451
FILM,1/8W,1%,4.32 kohm
20041.499.01 RESISTOR, METAL FILM 1/8W 1% 10 R301, R302, R317, R318,
4.99 Kohm R335, R336, R344, R345,
R405, R424
20041.634.01 RESISTOR, METAL 2 R313, R329
FILM,1/8W,1%,6.34 kohm
20041.665.01 RESISTOR, METAL 2 R331, R340
FILM,1/8W,1%,6.65 kohm
20042.100.01 RESISTOR, METAL 15 R101, R102, R104, R105,
FILM,1/8W,1%,10.0 kohm R107, R128, R214, R215,
R314, R315, R351, R404,
R423, R434, R443
20042.133.01 RESISTOR, METAL 1 R605
FILM,1/8W,1%,13.3 kohm
20042.150.01 RESISTOR, METAL 1 R352
FILM,1/8W,1%,15.0 kohm
20042.200.01 RESISTOR, METAL 5 R103, R330, R339, R507,
FILM,1/8W,1%,20.0 kohm R510
20042.475.01 RESISTOR, METAL 8 R308, R309, R324, R325,
FILM,1/8W,1%,47.5 kohm R409, R410, R427, R429
20042.499.01 RESISTOR, METAL 4 R407, R408, R426, R428
FILM,1/8W,1%,49.9 kohm
20042.698.01 RESISTOR, METAL 2 R332, R341
FILM,1/8W,1%,69.8 kohm
20042.750.01 RESISTOR, METAL 1 R614
FILM,1/8W,1%,75.0 kohm
20043.100.01 RESISTOR, METAL FILM,1/8W,1%,100 37 R126, R304, R305, R320,
kohm R321, R700-R731
20043.432.01 RESISTOR, METAL FILM,1/8W,1%,432 1 R504
kohm
20044.100.01 RESISTOR, METAL FILM,1/8W,1%,1 4 R333, R342, R444, R449
MEG
20044.365.01 RESISTOR, METAL 4 R445, R447, R450, R452
FILM,1/8W,1%,3.65 MEG
20045.100.01 RESISTOR, METAL FILM,1/8W,1%,10 1 R506
MEG
20056.154.01 RESISTOR, METAL 4 R413, R420, R432, R440
FILM,1/8W,0.1%,15.4 ohm
20058.301.01 RESISTOR, METAL 2 R418, R438
FILM,1/8W,0.1%,3.01 koh
20058.357.01 RESISTOR, METAL 1 R501
FILM,1/8W,0.1%,3.57 kohm
20058.453.01 RESISTOR, METAL 4 R416, R417, R436, R437
FILM,1/8W,0.1%,4.53 kohm
20058.464.01 RESISTOR, METAL 4 R415, R419, R435, R439
FILM,1/8W,0.1%,4.64 kohm
20058.475.01 RESISTOR, METAL 1 R502
FILM,1/8W,0.1%,4.75 kohm
OPTIMOD-FM DIGITAL TECHNICAL DATA 6-29
Schematic Rev ECO 2216A Main r01 ECO 2216A, 2254, 2284
01
20059.102.01 RESISTOR, METAL 4 R412, R422, R431, R442
FILM,1/8W,0.1%,10.2 koh
20059.133.01 RESISTOR, METAL 4 R411, R421, R430, R441
FILM,1/8W,0.1%,13.3 kohm
20080.301.01 RESISTOR, METAL FILM,1/2W,1%,301 1 R127
ohm
20221.101.01 RESISTOR,NETWORK, 2 R106, R124
SIP,2%,100K,10PIN
20511.310.01 TRIMPOTS,10K,20%,TOP ADJ 2 VR400, VR401
20512.325.01 TRIMPOTS, CERMET 15T 25K 2 VR500, VR501
20513.000.01 ADAPTER, TRIMPOT 2
21017.015.01 CAPACITOR,RAD LEADS,15PF,500V 1 C509
21017.022.01 MICA 1/2PF CD15 22PF 2 C521, C522
21017.033.01 CAPACITOR,RAD LEADS,33PF,500V 1 C518
21018.051.01 CAPACITOR,RADIAL 3 C513, C514, C516
LEADS,51PF,500V,1%
21018.122.01 CAPACITOR,RADIAL 1 C512
LEADS,220PF,500V,1%
21018.139.01 CAPACITOR,RADIAL 1 C508
LEADS,390PF,500V,1%
21022.162.01 CAPACITOR,RADIAL 1 C511
LEADS,620PF,500V,1%
21022.182.01 CAPACITOR,RADIAL 1 C510
LEADS,820PF,500V,1%
21022.210.01 CAPACITOR,RADIAL 2 C411, C417
LEADS,1000PF,500V
21022.215.01 CAPACITOR,RADIAL 2 C410, C416
LEADS,1500PF,500V
21127.010.01 CAPACITOR,AXIAL 2 C412, C418
LEADS,10PF,100V,5%
21127.033.01 CAPACITOR,AXIAL 9 C103, C409, C415, C515,
LEADS,33PF,100V,5% C519, C600, C608, C612,
C613
21127.068.01 CAPACITOR,AXIAL 1 C517
LEADS,68PF,100V,5%
21127.115.01 CAPACITOR,AXIAL 1 C604
LEADS,150PF,100V,5%
21127.168.01 CAPACITOR,AXIAL 2 C523, C525
LEADS,680PF,100V,5%
21127.210.01 CAPACITOR,AXIAL 4 C323, C324, C325, C326
LEADS,1NF,100V,5%
21131.410.01 CAPACITOR, SUFACE-MOUNT 105 C11-C53, C56-C62, C66-
1206,0.1UF,50V,20% C71, C73-C78, C85-C90,
C100, C101, C200, C306,
C307, C311, C313, C314,
C316-C319, C321, C322,
C401, C402, C404, C405,
C413, C500, C503, C504,
C506, C524, C601, C603,
C606, C609, C611, C801,
C803, C805, C807, C809,
C811, C812, C815
21209.522.01 CAPACITOR,RAD,LDS,2.2UF,63V,20% 1 C102
21263.610.01 CAPACITOR,RADIAL 5 C82-C84, C91, C92
LEADS,10uF,25V,10%
21263.710.01 CAPACITOR,RADIAL 1 C607
6-30 TECHNICAL DATA ORBAN Model 2200
Schematic Rev ECO 2216A Main r01 ECO 2216A, 2254, 2284
01
LEADS,100uF,25V,10%
21303.710.01 CAPACITOR,RADIAL 1 C308
LEADS,100UF,10V,10%
21305.610.01 CAPACITOR,RADIAL 1 C406
LEADS,10UF,20V,10%
21307.510.01 CAPACITOR,RADIAL 10 C312, C315, C320, C400,
LEADS,1.0UF,35V,10% C403, C414, C501, C502,
C505, C507
21445.247.01 CAPACITOR,M/POLY,.0047UF,50V,5% 4 C302-C305
21445.310.01 CAPACITOR,M/POLY,.01UF,50V,5% 10 C407, C408, C800, C802,
C804, C806, C808, C810,
C813, C814
21445.347.01 CAP M/PLYES 50V 5% .04UF 1 C602
21445.410.01 CAPACITOR,M/POLY,0.1UF,50V,5% 6 C201, C300, C301, C419,
C420, C520
21445.422.01 CAPACITOR,M/POLY,.22UF,50V,5% 2 C309, C310
21445.510.01 CAPACITOR,M/POLY,1.0UF,50V,5% 1 C605
22102.001.01 DIODE 1N5711TR 8 CR300-CR307
22201.400.01 DIODE REC IN4004 PRV400V 8 CR102-CR109
23402.101.01 TRANSISTOR,JFET/N 4 Q300-Q303
23406.101.01 TRANSISTOR 4 Q400-Q403
24008.202.01 IC,LINEAR,SNGL OP-AMP 3 IC502, IC503, IC505
24207.202.01 IC,LINEAR,DUAL OP AMP 4 IC302, IC311, IC403, IC406
24209.202.01 IC,LINEAR,DUAL OP AMP 6 IC301, IC310, IC402, IC405,
IC408, IC501
24643.000.01 IC,CS5389 DIP/28 600 WIDE 1 IC312
24644.000.01 IC,D/AUDIO TX CS8401A 1 IC616
24707.102.01 IC,LT1010 OBS USE 24026 2 IC504, IC506
24710.302.01 IC,SPECIAL FUNCTION,4 COMPARTR 2 IC306, IC407
24714.302.01 IC,MULTIPLYING DAC,8 BIT 2 IC401, IC404
24727.402.01 IC,SLF CONTND AUD,PREAMP 2 IC300, IC308
24728.302.01 IC,QUAD,SPST SWITCH,DIP/16 2 IC307, IC309
24733.000.01 IC,ST ASYNC S.R.C AD1890JP 2 IC603, IC615
24742.000.01 IC, AD1861N DIP/16 1 IC500
24817.000.01 IC,SRAM,32K X 8 1 IC106
24821.000.01 IC,CS4328KP 1 IC400
24822.000.01 IC,PLCC/68,SMD 1 IC100
24829.000.01 IC,TMS27C010A 10JL DIP/32 1 IC105
24847.000.01 IC,D/AUDIO INT REC CS8412CS 1 IC600
24850.000.01 IC,SO/14,SMT 5 IC201, IC314, IC606, IC614,
IC710
24851.000.01 IC,SOL20,SMT 2 IC120, IC601
24853.000.01 IC,74HC00 SIOC/14 SMD 1 IC602
24857.000.01 IC,74HC374 DLATCH SOL20 6 IC303, IC305, IC609, IC611,
IC708, IC709
24858.000.01 IC,SO/14,SMT 3 IC313, IC604, IC612
24872.000.01 IC,DIP/8 1 IC122
24896.000.01 IC,74HC153 SOIC/16 SMD 1 IC610
24897.000.01 IC,QFP/80,SMT 8 IC700-IC707
24898.000.01 IC,NM25C04M8 1 IC107
24899.000.01 IC,SO/16,SMT 4 IC101-IC104
24900.000.01 IC,HEX INVERTER,SMT 4 IC109, IC118, IC119, IC605
24901.000.01 IC,S016 HC/HCT4046A 1 IC619
24902.000.01 IC,74HC373 SMT SOL20 1 IC304
25003.000.01 IC,OPTOISOLATOR 8 IC110-IC117
26081.000.01 SWITCH,ROTARY,HORIZONTAL 1 S209
OPTIMOD-FM DIGITAL TECHNICAL DATA 6-31
Schematic Rev ECO 2216A Main r01 ECO 2216A, 2254, 2284
01
MNT,2 BIT
27017.025.01 CONNECTOR,RIGHT ANGLE,PC 1 J101
MOUNT,25 P
27053.003.01 CONNECTOR,MALE,INSERT,RIGHT 3 J400, J401, J601
ANGLE
27054.003.01 CONNECTOR,FEM,INSERT,RIGHT 3 J300, J304, J600
ANGLE
27106.000.01 CONNECTOR,BNC,RIGHT ANGLE,PC 2 J500, J501
MOUNT
27147.008.01 IC,SOCKET,DIP,8 PINS,DUAL 6 IC300, IC308, IC403, IC406,
IC503, IC505
27147.020.01 IC,SOCKET,DIP,20 PIN,DUAL 2 IC613, IC618
27147.024.01 IC SOCKET 24PIN DIP 1 IC616
27147.032.01 IC,SOCKET,DIP,32 PIN,DUAL 1 IC105
27161.016.01 IC SOCKET DIP/16 3 J203, J900, J901
27165.128.01 IC, SOCKET DIP/28 2 IC312, IC400
27401.000.01 CONNECTOR,JUMPER,RECPT,BLACK 9 JA, JB, J301, J302, J303,
J305, J306, J307, J308
27406.014.01 CONNECTOR,SOCKET,STRIP,14 PIN 1 J200
27421.004.01 CONNECTOR,HEADER,DBL RW,4P,2 6 JA, JB, J302, J303, J306,
X2 J307
27421.006.01 CONNECTOR,HEADER,DBL RW,6P,2 1 J100
X3
27426.003.01 CONNECTOR,HEADER,3 PIN,SINGLE 3 J301, J305, J308
RW
27630.001.01 JUMPER,PC MOUNT,TEST POINT 32 TP1-TP6, TP300-TP305,
TP400-TP403, TP500,
TP501, TP600-607, TP609-
611, TP700, TP701, TP901
28071.000.01 OSC-XTAL-11.2896MHz-50PPM 1 Y601
28073.001.01 OSC-XTAL-8.192MHz-50PPM 1 Y602
29015.000.01 TRANSFORMER PULSE 1:1 AES/EBU 2 T600-601
29501.004.01 INDUCTOR-.007mH-OHMITE Z-50 8 L100, L400, L401, L404,
L405, L802-L804
29503.000.01 INDUCTOR-1.2mH-MILLER 73F 4 L301, L303, L305, L307
29505.002.01 BEAD, FERRITE .56" ID 9
29508.210.01 FLTR-EMI SUPPRESSION-50V- 12 L300, L302, L304, L306,
L402, L403, L406, L407,
L600-603
29705.008.01 INDUCTOR-9.725MH-1%-SELECTED 1 L500
29705.009.01 INDUCTOR-10.41MH-1%-SELECTED 1 L502
29705.012.01 INDUCTOR-12.91MH-1%-SELEC 1 L501
31811.000.01 CIRCUIT BOARD MAIN 2200 1
44031.100.01 ASSEMBLY-PAL-PRGD-N_DIV.JED-2 1 IC618
44032.100.01 ASSEMBLY-PAL-PRGD-8B_CNTR.JED 1 IC613
61171.000.01 SCHEMATIC, MAIN 2200D 0
2200 PCA Main 31810.001 Rev 02, ECO 2416, 2416A, 2408
Schematic Rev 04 ECO 2416, 2416A, 2491 Main r02 ECO 2416, 2416A, 2408
2200 PCA Main 31810.001, Rev 03, ECO 2449, 2459, 2475
Schematic Rev 04 ECO 2416, 2416A, 2491 Main r03 ECO 2449, 2459, 2475
[no difference]
Power Supply
2200 Power Supply 31865.000 Rev 01
Schematic Rev 01 ECO 2216 Power r01 31865.000
The following drawings are included in this manual. Complete drawings are included for
the first version of the product. For later versions, drawings are included only if a given
drawing has changed compared to the previously shown version of that drawing.
NOTES:
OPTIMOD-FM DIGITAL TECHNICAL DATA 6-43
FR Fair-Rite NEU Neutrik USA Inc. 5555 N. Elation Avenue
Vendor Codes 195 Lehigh Ave Chicago, IL 60630
FSC Fairchild Camera & Instr. Corp. Lakewood, NJ 08701-4527
See National Semiconductor TAI Taiga America, Inc.
AB Rockwell Allen-Bradley NIC Nichicon 700 Frontier Way
625 Liberty Ave GI General Instruments 927 East State Parkway Bensenville, IL 60106
Pittsburgh, PA 15222-3123 Optoelectronics Division Schaumburg, IL 60713
See Quality Technologies TAT Taitron
AD Analog Devices, Inc. NOB Noble USA Inc.
2105 S Bascom Ave GS General Silicones Co. USA Inc. 5450 Meadowbrook Industri TI Texas Instruments, Inc.
Suite 325 650 W Duarte Rd, Ste 401 Rolling Meadows, IL PO Box 655012
Campbell, CA Arcadia, CA 91007 60008-3800 Dallas, TX 75265
95008
HP Hewlett-Packard Co. OHM Ohmite Manufacturing Company TOS Toshiba America, Inc.
BEK Beckman Industrial Corporation 321 E Evelyn Ave PO Box 49150 9740 Irvine Blvd.
4141 Palm Street Mountain View, CA 94039 Chicago, IL 60678 Irvine, CA 92718
Fullerton, CA 92635-1025
KEM KEMET Electronics Corporation ORB Orban, Inc. TRW TRW Electronics Components
BRN Bourns, Inc Post Office Box 5928 1525 Alvarado Street Connector Division
2533 N 1500 W Greenville, South Carolina 29606 San Leandro, CA 94577 1501 Morse Avenue
Ogden UT 84404 Elk Grove Village, IL 60007
LFE Littlefuse PHI Phillips Components – Signetics
BUS Bussmann Division A Subsidiary of Tracor, Inc. See Signetics XI Xicor
Cooper Industries 800 E. Northwest Hwy
PO Box 14460 Des Plaines, IL 60016 PAN Panasonic Industrial Company WIM Wima Division
St. Louis, MO 63178 Two Panasonic Way 2269 Saw Mill Rd
LT Linear Technology Corp 7E-2T Building 4C
CD Corning 1630 McCarthy Blvd. Secaucus, NJ 07094 PO Box 217
Milpitas, CA 95035 Elmsford, NY 10533
CEN Mepcopal/Centralab QT Quality Technologies, Inc.
See Mepcopal LUM Lumex Opto/Components Inc. 610 North Mary Ave. ZI ZILOG Inc.
292 E. Hellen Road Sunnyvale, CA 94086 210 Hacienda Ave.
CSC Crystal Semiconductor Corp. Palatine, IL 60067 Campbell, CA 95008
50 Airport Parkway ROH Rohm Electronics
San Jose, CA 95110 MAT Matsushita Electric Corp 3034 Owens Dr.
of America Antioch, TENN 37013
CW CW Industries One Panasonic Way
130 James Way Secaucus, NJ 07094 SIE Siemens Components Inc.
Southampton, PA 18966 MIL J.W. Miller Division Heimann Systems Div.
Bell Industries 186 Wood Avenue South
DAL Dale 306 E. Alondra Iselin, NJ 08830
1122 23rd St Gardena, CA 90247
Columbus, NE 68601-3647 SIG Signetics - Philips Components
MOT Motorola Semiconductor North American Phillips Corp.
DEL Delta Products Corp 5005 E McDowell Rd 811 E. Arques
3225 Laurel View Ct. Phoenix, AZ 85008 Sunnyvale, CA 94088
Fremont, CA 94538
MUR Murate Erie North America SPR Sprague Magnetics, Inc
DEN Densitron Corporation 2200 Lake Park Drive 15720 Stagg Street
P.O. BOX 11189 Smyrna, GA 30080 Van Nuys, CA 91406
Torrance, CA 90510-1189
NAT National Semiconductor Corp. SPE Spectrol
EXR Exar Corporation 2900 Semiconductor Drive
2222 Qume Dr. PO Box 61659 SW Switchcraft
PO Box 49007 Santa Clara, CA 95051 A Raytheon Company
San Jose, CA 95161-9007
6-44 TECHNICAL DATA Orban Model 2200
9 10
JUMPERS
+5
+5 3 4 2200
9200 6200
C2 JP-C
INPUT CLOCK 2.048M 6.144M
12
CAP_.01UF PLL OUT 1 6.144M 4.096M
C1
PLL OUT 2 18.432M 18.432M
2
CAP_.01UF D U2
11
1 2 1 2
2
VDD
U1 5
CLK
VDD
D 5 1 7
CLK ICLK OE N/C +5
JP-B
1 7 8
ICLK OE N/C X2 N/C 5 6
GND
8
S0
S1
X2 N/C
GND
ICS501
S0
S1
+5 P618
X3/X2
4
1 20
ICS501
7 8 2 19
X3 N/C
3
3 18
D 4 17
N/C +5 5 16
D 6 15
7 14 13 14 13 14
14 13 8 13
9 12
10 11
+5
20PIN-ADAPTER
C3 C4 D D
CAP_.01UF
CAP_.01UF
14
D U4A
D U4B
VCC
5
4 10
1 PRE 2PRE
U3 1 5 N/C 13 9
1 CLR 1Q 2CLR 2Q
1
4 3 6 11 8
1 CLK 1Q 2CLK 2Q
2
2 12
GND
1D 2D
AHCT86
3
AHCT74
AHCT74
7
D
D
2.048M X3 = 6.144M
6.144M X3 = 18.432M
+15V
Gnd Lift
Plus15V
3
1
S2 N/C 1 2
C20 CR21
R2
1 2 1 2
20%
IC1 R11 120 Ω 5%
20%
IC3 TP2
2
1
Chassis Ground Pigtail, 3" long
0.1 F, 50v
1
0.1 F, 50v
1
C3
C4
20%
20%
(Lug w/Green AWG 18)
C10
C9
0.1 F, 50v
2
100 F, 25v
2
0.1 F, 50v
5.6v Zener
10%
1N4734A
2
C11
10%
CR10
2
1N4004
H13
1N4004
1000 F, 35v
1
2
Chassis_Gnd Power Transformer
1
CR4
100 F, 25v
CR3
1N4004
20%
AGND
C1
1
CR7
L1 PlusRAW
1
2
2
YELLOW/WHITE
2
Toroid Assy AGND 1-6D
2
(off board)
2
Line Filter Assembly 1-6C
TP3
C5
MinusRAW
YELLOW
Plus15V
1N4004
1
1N4004
1N4004
1
2
BLUE ORANGE
CR8
1
1
1000 F, 35v
CR1
CR2
CR6
100 F, 25v
16013.000.01
1
CR11
20%
5.6v Zener
1
1N4734A
2
C2
2 1 2 1
C14
10%
2
2
Minus15V
CR12
BROWN RED/WHITE
C6
2
1N4004
2
1N4004
Cap
2
F1b
-15V
BLACK RED
-15v Reg -5v Reg
1/2 A, Slow Blow Blow
MinusRAW 2 3 1 2 2 3 Minus5VA
Fuse
F1
Minus15V
20%
IC2 120 Ω 5% IC4 Power +5VD
1
2
R13
20%
0.1 F, 50v
0.1 F, 50v
1 2
20%
20%
C8
C7
—5VA
0.1 F, 50v
2
1-2C
1
J4 J6 DGND
120 Ω 5%
C13
R15 1
C12
0.1 F, 50v
1 2 Power
2 1
2
DGND
TP11 3
4
2
3
4
2
5
3
6
1
2
2
120 Ω 5%
1
R14 4
1 2 5 3
2
AGND +5VA
6
115v/230v 4
7
AGND Plus5VA
1
V1 V2 CR22 8
1 2 9 J202
DPDT
4
AGND 10
S1 1N4736 6.8v Zener TP4 N/C (Key)
Minus5VA DGND
Minus15V J1
—5VA
Testing Access Display Supply
CR13 Chassis_Gnd
CR19 -15V
1
1 2
2
3 1N4004
CR15 TP7 +5v Reg +5VD
SBL1630CT
3 LT1086/CK-5
4-40x.3125 +9v
2 1 3 Power
1 +15V +5VA +5VD
6800 F, 16v 20%
20%
IC5 TP6
2
CR14 Analog Supply Digital Supply
20%
5.6v Zener
2
C15
1N4734A
1
1
C18
C17
2
CR16
0.1 F, 50v
C16
0.1 F, 50v
3
2
2
1
2
4-40x.3125 SBL1630CT TP9 P900 P901
DGND 1 2 Power 1 2
3 4 3 4
5 6 5 6
7 8 7 8
DGND 9 10 9 10
IC1 11 12 11 12
DGND 13 14 13 14
Mounting Heatsink 15 16 15 16
Kit 50281.000.01
LCD Backlight 16013.000.01 8.5" Flat Cable 4" Flat Cable
J201 DGND
15025.000.01
IC2 TP8 1 2
Mounting CR18
3 4
Kit 2 1 N/C N/C
1N4004 Heatsink AGND
2
+9vB —5VA -15V
Q1 H10
15025.000.01 CR17 1 LED_Pulse LED_Pulse
TIP120
4-40x.375 4-40x.375 2 1 2N4400
+9vB
1N4004 Q2
3
3
IC5 R7
2
1000 F, 35v
2
20%
10.0K 1%
C19
1N4148
2.0 W 5%
2.0 W 5%
CR20
5%
2.0 W 5%
1
1
1/2 w.
1/2 w.
1/2 w.
1/2 w.
TO3 Insulator
R3
R4
R5
R6
2
2.0 W
Gnd Lift
Plus15V
3
1
S2 N/C 1 2
C20 CR21
R2
1 2 1 2
20%
IC1 R11 120 Ω 5%
20%
IC3 TP2
2
1
Chassis Ground Pigtail, 3" long
0.1 F, 50v
1
0.1 F, 50v
1
C3
C4
20%
20%
(Lug w/Green AWG 18)
C10
C9
0.1 F, 50v
2
2
100 F, 25v
0.1 F, 50v
5.6v Zener
10%
1N4734A
2
10%
C11
CR10
2
1N4004
H13
1N4004
1000 F, 35v
1
2
Chassis_Gnd Power Transformer
1
CR4
100 F, 25v
CR3
1N4004
20%
AGND
C1
1
CR7
L1 PlusRAW
1
2
2
YELLOW/WHITE
2
Toroid Assy AGND 1-6D
2
(off board)
2
Line Filter Assembly 1-6C
TP3
C5
MinusRAW
YELLOW
Plus15V
1N4004
1
1N4004
1N4004
1
2
BLUE ORANGE
CR8
1
1
1000 F, 35v
CR1
CR2
CR6
C6
16013.000.01
1
CR11
20%
100 F, 25v
5.6v Zener
1
1N4734A
2
C2
2 1 2 1
C14
10%
2
2
Minus15V
CR12
BROWN RED/WHITE
2
1N4004 1N4004
2
Cap
2
F1b
-15V
-15v Reg -5v Reg
BLACK RED
1/2 A, Slow Blow Blow
MinusRAW 2 3 1 2 2 3 Minus5VA
Fuse
F1
Minus15V
20%
IC2 120 Ω 5% IC4 Power +5VD
0.1 F, 50v
1
1
2
R13
1
0.1 F, 50v
20%
20%
1 2
20%
C8
C7
—5VA
0.1 F, 50v
2
1-2C
1
J4 J6 DGND
120 Ω 5%
C13
R15 1
C12
0.1 F, 50v
1 2 Power
2 1
2
DGND
TP11 3
4
2
3
4
2
5
3
6
1
2
2
120 Ω 5%
1
R14 4
1 2 5 3
2
AGND +5VA
6
115v/230v 4
7
AGND Plus5VA
1
V1 V2 CR22 8
1 2 9 J202
DPDT
4
AGND 10
S1 1N4736 6.8v Zener TP4 N/C (Key)
Minus5VA DGND
Minus15V J1
—5VA
Testing Access Display Supply
CR13 Chassis_Gnd
CR19 -15V
1
1 2
2
3 Q3 1N4004
TP7 MJ2955
CR15 2 C +5VD
SBL1630CT
4-40x.3125 3 +9v IC6
2 Power
1 +5v Reg.
+5VD
1
+15V +5VA
LP2950-5.0
R16 TP6
CR14 6800 F, 16v 20% 1 2 3 1
Analog Supply Digital Supply
470 F, 25v
SBL1630CT
5.6v Zener
M is c . H a rd w a re A c c e s s o rie s
1N4734A
1
1
C18
1
10%
1
CR16
332 W
2
C15
0.1 F, 50v
1
2
0.1 F, 50v
1%
20%
3
2
2
20%
C16
C17
2
2
4-40x.3125 SBL1630CT TP9 P900 P901
DGND 1 2 Power 1 2
3 4 3 4
5 6 5 6
7 8 7 8
DGND 9 10 9 10
IC1 11 12 11 12
DGND 13 14 13 14
Mounting Heatsink 15 16 15 16
Kit 50281.000.01
LCD Backlight 16013.000.01 8.5" Flat Cable 4" Flat Cable
J201 DGND
15025.000.01
IC2 TP8 1 2
Mounting CR18
3 4
Kit 2 1 N/C N/C
1N4004 Heatsink AGND
2
+9vB —5VA -15V
Q1 H10
15025.000.01 CR17 1 LED_Pulse LED_Pulse
TIP120
4-40x.375 4-40x.375 2 1 2N4400
+9vB
1N4004 Q2
3
3
IC5 R7
2
1000 F, 35v
2
20%
10.0K 1%
C19
1N4148
2.0 W 5%
2.0 W 5%
CR20
5%
2.0 W 5%
1
1
1/2 w.
1/2 w.
1/2 w.
1/2 w.
TO3 Insulator
R3
R4
R5
R6
2
2.0 W