Juncitonless Nanowire Fet

JUNCTIONLESS Si- NANOWIRE FIELD EFFECT TRANSISTOR :
With the advancement in semiconductor industry followed by implications of moores law ,

mosfets are scaled down to ultra low sub nanometer regime which is obviously enhancing
the performance limits of transistors ,imposing some fabrication complication and
parameter degradation at the same time.
In order to cater all this shortcomings in mosfets many styles of fabrication techniques and
structural modification were proposed.
Lets discuss first the shortcoming/limitations faced in the conventional mosfets
- Fabrication challenges.
-Realization of ultrasteep doping profile becomes difficult at sub nano scale
-Constraints posed on thermal budget during annealing
-Short channel effect like DIBL etc.
One of the structural modification is JUNTIONLESS NANOWIRE TRANSISTOR which will be discussed
below in this report.
Junctionless si-nanowire transistor :
JUNCTIONLESS FET are also called gated resisitor since the gate control its resistance and thus
controls the current flowing under it.
DEVICE STRUCTURE:
It’s a heavily doped semiconductor film with a gate terminal that basically controls the channel
carrier concentration. The source and drain are built with ohmic contacts by heavily doping them too
and hence the doping concentration right from the source to channel and to drain is same and has
zero doping gradient thus eliminating the need of ultrasteep doping profile with no mettalurgical
junction. The JLFET forms a MOS capacitor at the centre which plays significant role in its operation.
WORKING PRINCIPLE:
FULL DEPLETION MODE:
 We will be considering the metal-semiconductor work function to be positive ,means the

the fermi level of metal is less than that of semiconductor. As a result the electrons from
semiconductor will flow towards the metal creating a positive charge at the interface and
negative chare at the metal surface thus producing an electric field from semiconductor to
gate metal which basically deplets all the charge carries present in the channel and is said to
be volume depletion mode.
 For full depletion its necessary t adjust the gate electrode work function at Vgs=0 volt.
(work fun>5.1ev).
PARTIAL DEPLETION MODE:
 Some positive potential is applied to gate electrode which leads to reduction in the
depletion width and a neutral region is formed at the centre of the channel through which
current can easily start to flow.
 The gate voltage at which this neutral region disappears called threshold voltage.
FLAT BAND MODE:
 If we go on increasing the gate voltage ,at a certain voltage the gate induced depletion regio
would disappear and the channel throughout will be neutral and actively provides majority
charge carriers to flow. JLFETs are generally operated in flat band condition to avoid surface
scattering.
ACCUMULATION MODE:
 If the gate voltage is further increased the electrons would be attracted towards the surface
of the channel and electrons will be accumulated at the interface.
DESIGN PARAMETER AND FABRICATION FLOW OF JLNWFET:
 In order to develop the ohmic contacts we have to dope silicon film heavily but the high
doping also reduces the electron mobility due to ionized impurity scattering.
 Threshold voltage in JLFET is basically dependent on silicon film thickness and silicon film
doping.
To fabricate the NWJLFET we can take a uniformly doped (10^19 cm^-3) SOI wafer and then
the channel can defined on it by E-BREAM LITHOGRAPHY followed dry etch. Similary the
source and drain contacts pads are defiend buth width and height are kept greater than
channel.
Gate oxide of some thickness is grown. A gate metal layer such as TiN or polysilicon is
deposited.
IMPORTANT PARAMETER THAT EFFECTS THE PERFORMANE OF JLFET:
 Mobility
The mobility dependency of JLFET is different compared to MOSFET because of bulk
conduction and not surface conduction . also the ongitudinal electric field in JLFET is nearly
zero and thus the surface roughness and electric field doesn’t impact the mobility of carriers.
 Impact of strain on mobility:

Application of strain leads to variation in energy band structure and thus alters the effective
carrier mobility.
The four probe bending technique was used to establish the fact that drain current in JLFET
increases with compressive and tensile stress based on type of JLFET.

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JUNCTIONLESS Si- NANOWIRE FIELD EFFECT TRANSISTOR :

With the advancement in semiconductor industry followed by implications of moores law ,

-Realization of ultrasteep doping profile becomes difficult at sub nano scale

-Constraints posed on thermal budget during annealing

-Short channel effect like DIBL etc.

Junctionless si-nanowire transistor :

FULL DEPLETION MODE:

 We will be considering the metal-semiconductor work function to be positive ,means the

PARTIAL DEPLETION MODE:

FLAT BAND MODE:

DESIGN PARAMETER AND FABRICATION FLOW OF JLNWFET:

 Impact of strain on mobility:

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