Vinafix S20-30 - BM5406.

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D D

Bitland Confidential
C
Beetle M/B Schematics Document C

Intel Baytrail-M Platform

B B

2013-xx-xx

A A

Bitland Information Technology Co.,Ltd.


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Date: Tuesday, March 04, 2014 Sheet 1 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

https://vinafix.com
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D D

C C

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Bitland Information Technology Co.,Ltd.


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Custom <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 2 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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https://vinafix.com
5 4 3 2 1

BATTERY Intel BYT-M SoC


CPU VCORE@12A CPU VCORE
11.1V 24WHr CHARGER CPU VCORE
+VCORE@21A
(single phase)
DCBATOUT CPU GXFCORE@14A CPU GXFCORE
CPU GXFCORE
+VGFX@17A
AC ADAPTER
Bq24735 (single phase)
D
[email protected] VDDQ
D

OZ8296
20V 45W DDR_VTT@ DDR_VTT Power States
Power Rail On S0 On S3 On S4/S5 On G3
VDDQ
+V_VDDQ_VR@7A +V3.3A@50mA +V3.3A
VCORE ON OFF OFF OFF
Notes:
1.remove 1.2A in diagram DDR_VTT
[email protected] +V3.3S@25mA +V3.3S VGFX ON OFF OFF OFF
2.current data from EDS and old project
+V1P8A@68mA V1P0S ON OFF OFF OFF
NB675 +V1P8A
V1P05S ON OFF OFF OFF
3V BATT LDO +V3.3A_RTC(100uA)
[email protected] V1P5S ON OFF OFF OFF
+5V LDO
+V1P8S@10mA +V1P8S V1P35S ON OFF OFF OFF
+3V LDO
[email protected]
Output power rail
+V1P5S@10mA V1P8S ON OFF OFF OFF
+V1P5S
Input power rail for power transition
+5V SW
+V3.3A@2A+1A V3P3S ON OFF OFF OFF
+V1P35S@45mA +V1P35S
Input power rail for end IC
[email protected]+3.75A V5S ON OFF OFF OFF
+3V SW
+V1P05S@1A +V1P05S VDDQ_VTT ON OFF OFF OFF
Bq24735 TPS51125 VDDQ_VR ON ON OFF OFF
C +V1P0A@325mA +V1P0A
Bq24735 C

Bq24735 V1P0A ON ON ON OFF


+V1P0S@850mA +V1P0S
Bq24735 1.0A V1P2A ON ON ON OFF
CHARGER
[email protected]+9.616A
CHARGER
Bq24735
CHARGER Bq24735 NB671 V1P8A ON ON ON OFF
CHARGER
CHARGER Bq24735
CHARGER ALC280 V3P3A ON ON ON OFF
CHARGER Bq24735
CHARGER [email protected]
1.8A LDO 5V(S0)@0.25A V5A ON ON ON OFF
+V3.3A@2A+1A [email protected]+9.616A
[email protected] 3.3V(S0)@0.25A
UP0111AMA5-00
[email protected] 1.5V(S0)@0.1A
1.05S LDO
+V_VDDQ_VR@1A [email protected]
uP0104SSW8
LCD-Panel
1.5S LDO [email protected]
+V3.3A@2A+1A [email protected] [email protected] for LCDVCC

UP0111AMA5-00 [email protected]
B
[email protected] for backlight B

+V5A@2A +V5S@2A
MOS SWITCH
[email protected] USB Camera
+V3.3A@2A +V3.3S@2A
MOS SWITCH
[email protected]

+V1P0A@2A +V1P0S@2A
MOS SWITCH
USB2.0+USB3.0
+V_VDDQ_VR@2A +V1P35S@2A
MOS SWITCH [email protected]
[email protected]+0.9A

+V1P8A@2A +V1P8S@2A
MOS SWITCH
[email protected] WIFI/BT
+V5A@2A +V5S@2A
MOS SWITCH
[email protected]

DDR3L Memory
[email protected]
[email protected]
A A
[email protected]
[email protected]

Vinafix.com [email protected]
EC
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Bay Trail

Rev
[email protected] for LCDVCC A2 <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 3 of 42
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documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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SMBus block diagram

D
CPU VR D

EDID0
HDMI

SM BUS0 Charger

SOC
EC Battery

SM BUS1
C C

SMBus

PS2 Port2

PS2
Touch pad
32.768KHZ

CK_SRC1_DN/P
B
100MHz WiFi B

PCH
25MHZ

CK_LPC_0_R
25MHz EC

Clock block diagram

A A

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Date: Tuesday, March 04, 2014 Sheet 4 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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D D

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Vinafix.com

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Date: Tuesday, March 04, 2014 Sheet 5 of 42
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Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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+V1P8S

+V1P8S +V3.3S

1
+V1P8S 9,10,11,13,18,21,24,39

1
R561 R570
+V3.3S 7,13,18,19,20,21,22,23,25,28,30,35,36,39
2.2k_J 2.2k_J
R352 R563 r0402 r0402 R562 R564

2
2.2k_J 2.2k_J 2.2k_J 2.2k_J
r0402 r0402 Q50 r0402 r0402

2
5
D LMBT3904DW1T1G D
SOT363

eDP_BKLT_EN 4 3 DDI1_BKLT_EN 18,23


eDP_BKLT_CTRL 1 6 DDI1_BKLT_CTRL 22,23

2
?
U1C VLV_M_D +V1P8S
+V1P8S +V1P8S HDMI
AV3 AG3
24 DDI0_LANE0_DP AV2 DDI0_TXP_0 DDI1_TXP_0 AG1 EDP_TX0_DP 22,23
24 DDI0_LANE0_DN DDI0_TXN_0 DDI1_TXN_0 EDP_TX0_DN 22,23

2
AT2 AF3 +V1P8S
24 DDI0_LANE1_DP DDI0_TXP_1 DDI1_TXP_1
1

1
Hardware strap AT3 AF2 R450
DDI0 Detect 24 DDI0_LANE1_DN AR3 DDI0_TXN_1 DDI1_TXN_1 AD3
R236 R239 R453 10K_J
0 = DDI0 not detected 24 DDI0_LANE2_DP DDI0_TXP_2 DDI1_TXP_2

2
2.2k_J 2.2k_J AR1 AD2 2.2k_J R0402
1 = DDI0 detected 24 DDI0_LANE2_DN AP3 DDI0_TXN_2 DDI1_TXN_2 AC3 R364
R0402 R0402 24 DDI0_LANE3_DP DDI0_TXP_3 DDI1_TXP_3 R0402
AP2 AC1 10K_J ns

1
24 DDI0_LANE3_DN DDI0_TXN_3 DDI1_TXN_3
R0402
2

2
DDI0_CTRL_DATA DDI0_CTRL_CK AL3 AK3 LVDS DDI1_GEN_R_CLK
DDI0_AUXP DDI1_AUXP EDP_AUX_DP 22,23
AL1 AK2 EDP_VDD_EN_R
EDP_AUX_DN 22,23

1
DDI0_AUXN DDI1_AUXN
1

DDI1_HPD_N
R235 R240 24 DDI0_HPD_Q D27 K30 DDI1_HPD_N
DDI0_HPD DDI1_HPD

3
10K_J 10K_J

1
R0402 C26 P30 DDI1_GEN_R_DAT D
R0402 24 DDI0_CTRL_DATA DDI0_DDCDATA DDI1_DDCDATA
ns 24 DDI0_CTRL_CK C28 G30 DDI1_GEN_R_CLK R11
DDI0_DDCCLK DDI1_DDCCLK R0402 1 EDP_HPD_Q
ns EDP_HPD_Q 22
2

B28 N30 EDP_VDD_EN_R 100K_J S G sot23-3


DDI0_VDDEN DDI1_VDDEN EDP_VDD_EN_R 23
C27 J30 eDP_BKLT_EN eDP L2N7002LT1G

2
B26 DDI0_BKLTEN DDI1_BKLTEN M30 eDP_BKLT_CTRL Q26

2
Follow Ver1.15 CRB DDI0_BKLTCTL DDI1_BKLTCTL LVDS
double check,
C
Ver1.0 EDS:DDI0 RCOMP R4 2 1 402_F DDI0_RCOMP_N AK13 AH14 C
This signal is used for pre-driver slew rate compensation. r0603 DDI0_RCOMP_P AK12 DDI0_RCOMP RESERVED_AH14 AH13
An external precision resistor of 402 Ω ±1% should be connected from this DDI0_RCOMP_P RESERVED_AH13
pin to ground. AM14 AF14
AM13 RESERVED_AM14 RESERVED_AF14 AF13 +V1P8S
AM3 RESERVED_AM13 RESERVED_AF13 AH3
AM2 VSS_AM3 VSS_AH3 AH2
VSS_AM2 VSS_AH2

1
BA3 Hardware strap
VGA_RED AY2 R251 DDI1 Detect
VGA_BLUE BA1 2.2k_J 0 = DDI1 not detected
VGA_GREEN AW1 R0402 1 = DDI1 detected
VGA_IREF AY3
VGA_IRTN

2
BD2 DDI1_GEN_R_DAT
VGA_HSYNC BF2
VGA_VSYNC

1
BC1 R237
VGA_DDCCLK BC2 10K_J
VGA_DDCDATA R0402
T2 T7 ns
T3 RESERVED_T2 RESERVED_T7 T9

2
AB3 RESERVED_T3 RESERVED_T9 AB13
AB2 RESERVED_AB3 RESERVED_AB13 AB12
Y3 RESERVED_AB2 RESERVED_AB12 Y12
Y2 RESERVED_Y3 RESERVED_Y12 Y13
W3 RESERVED_Y2 RESERVED_Y13 V10
W1 RESERVED_W3 RESERVED_V10 V9
V2 RESERVED_W1 RESERVED_V9 T12
V3 RESERVED_V2 RESERVED_T12 T10
+V1P8S R3 RESERVED_V3 RESERVED_T10 V14
R1 RESERVED_R3 RESERVED_V14 V13
AD6 RESERVED_R1 RESERVED_V13 T14
AD4 RESERVED_AD6 RESERVED_T14 T13
RESERVED_AD4 RESERVED_T13
1

AB9 T6
R88 AB7 RESERVED_AB9 RESERVED_T6 T4
Y4 RESERVED_AB7 RESERVED_T4 P14
10K_J RESERVED_Y4 RESERVED_P14
R0402 Y6
V4 RESERVED_Y6
B
V6 RESERVED_V4 K34 B
ns
2

GPIO_NC13 GPIO_NC13 A29 RESERVED_V6 RESERVED_K34 D32


20MIL TP19 1 C29 GPIO_S0_NC13 GPIO_S0_NC26 N32
GPIO_S0_NC14_C29 GPIO_S0_NC25
1

AB14 J34
R87 20MIL TP20 1 B30 RESERVED_AB14 GPIO_S0_NC24 K28
C30 GPIO_S0_NC12 GPIO_S0_NC23 F28
10K_J RESERVED_C30 GPIO_S0_NC22
R0402 F32
GPIO_S0_NC21 D34
GPIO_S0_NC20 J28
2

GPIO_S0_NC18 D28
GPIO_S0_NC17 M32
3 OF 13 GPIO_S0_NC16 F34
GPIO_S0_NC15

VLV_M_D/BGA ?
REV = 1.15

Vinafix.com
A A

Bitland Information Technology Co.,Ltd.

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Page Name

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C <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 6 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

+V_VDDQ_VR 12,15,16,35,36,39

+V3.3A 11,13,18,23,25,28,30,33,34,35,36,37,39

+V3.3S 6,13,18,19,20,21,22,23,25,28,30,35,36,39

+V1P8A 9,10,13,18,34,39

U1A ? VLV_M_D M_A_DQ[63:0] 15


D 15 M_A_A[14:0] D
M_A_A0 K45 M36 M_A_DQ0
M_A_A1 H47 DRAM0_MA_00 DRAM0_DQ_00 J36 M_A_DQ1
M_A_A2 L41 DRAM0_MA_11 DRAM0_DQ_11 P40 M_A_DQ2
M_A_A3 H44 DRAM0_MA_22 DRAM0_DQ_22 M40 M_A_DQ3
M_A_A4 H50 DRAM0_MA_33 DRAM0_DQ_33 P36 M_A_DQ4
M_A_A5 G53 DRAM0_MA_44 DRAM0_DQ_44 N36 M_A_DQ5
M_A_A6 H49 DRAM0_MA_55 DRAM0_DQ_55 K40 M_A_DQ6
M_A_A7 D50 DRAM0_MA_66 DRAM0_DQ_66 K42 M_A_DQ7
M_A_A8 G52 DRAM0_MA_77 DRAM0_DQ_77 B32 M_A_DQ8
M_A_A9 E52 DRAM0_MA_88 DRAM0_DQ_88 C32 M_A_DQ9
M_A_A10 K48 DRAM0_MA_99 DRAM0_DQ09_C32 C36 M_A_DQ10
M_A_A11 E51 DRAM0_MA_1010 DRAM0_DQ_1010 A37 M_A_DQ11
M_A_A12 F47 DRAM0_MA_1111 DRAM0_DQ_1111 C33 M_A_DQ12
M_A_A13 J51 DRAM0_MA_1212 DRAM0_DQ_1212 A33 M_A_DQ13
M_A_A14 B49 DRAM0_MA_1313 DRAM0_DQ_1313 C37 M_A_DQ14
M_A_A15 B50 DRAM0_MA_1414 DRAM0_DQ_1414 B38 M_A_DQ15
15 M_A_A15 DRAM0_MA_1515 DRAM0_DQ_1515 F36 M_A_DQ16
G36 DRAM0_DQ_1616 G38 M_A_DQ17
15 M_A_DM0 DRAM0_DM_00 DRAM0_DQ_1717
15 M_A_DM1 B36 F42 M_A_DQ18
F38 DRAM0_DM_11 DRAM0_DQ_1818 J42 M_A_DQ19
15 M_A_DM2 DRAM0_DM_22 DRAM0_DQ_1919
15 M_A_DM3 B42 G40 M_A_DQ20
P51 DRAM0_DM_33 DRAM0_DQ_2020 C38 M_A_DQ21
15 M_A_DM4 DRAM0_DM_44 DRAM0_DQ_2121
15 M_A_DM5 V42 G44 M_A_DQ22
Y50 DRAM0_DM_55 DRAM0_DQ_2222 D42 M_A_DQ23
15 M_A_DM6 DRAM0_DM_66 DRAM0_DQ_2323
15 M_A_DM7 Y52 A41 M_A_DQ24
DRAM0_DM_77 DRAM0_DQ_2424 C41 M_A_DQ25
M_A_RAS_N M45 DRAM0_DQ_2525 A45 M_A_DQ26
15 M_A_RAS_N DRAM0_RAS DRAM0_DQ_2626
15 M_A_CAS_N M_A_CAS_N M44 B46 M_A_DQ27
M_A_WE_N H51 DRAM0_CAS DRAM0_DQ_2727 C40 M_A_DQ28
15 M_A_WE_N DRAM0_WE DRAM0_DQ_2828 B40 M_A_DQ29
K47 DRAM0_DQ_2929 B48 M_A_DQ30
15 M_A_BS0 DRAM0_BS_00 DRAM0_DQ_3030
15 M_A_BS1 K44 B47 M_A_DQ31
D52 DRAM0_BS_11 DRAM0_DQ_3131 K52 M_A_DQ32
15 M_A_BS2 DRAM0_BS_22 DRAM0_DQ_3232 K51 M_A_DQ33
P44 DRAM0_DQ_3333 T52 M_A_DQ34
15 M_A_DIM0_CS0_N DRAM0_CS_0 DRAM0_DQ_3434 T51 M_A_DQ35
P45 DRAM0_DQ_3535 L51 M_A_DQ36
15 M_A_DIM0_CS1_N DRAM0_CS_2 DRAM0_DQ_3636 L53 M_A_DQ37
DRAM0_DQ_3737 R51 M_A_DQ38
C47 DRAM0_DQ_3838 R53 M_A_DQ39
15 M_A_DIM0_CKE0 DRAM0_CKE_00 DRAM0_DQ_3939
C D48 T47 M_A_DQ40 C
F44 RESERVED_D48 DRAM0_DQ_4040 T45 M_A_DQ41
15 M_A_DIM0_CKE1 DRAM0_CKE_22 DRAM0_DQ_4141
E46 Y40 M_A_DQ42
RESERVED_E46 DRAM0_DQ_4242 V41 M_A_DQ43
T41 DRAM0_DQ_4343 T48 M_A_DQ44
15 M_A_DIM0_ODT0 DRAM0_ODT_0 DRAM0_DQ_4444 T50 M_A_DQ45
P42 DRAM0_DQ_4545 Y42 M_A_DQ46
15 M_A_DIM0_ODT1 DRAM0_ODT_2 DRAM0_DQ_4646 AB40 M_A_DQ47
DRAM0_DQ_4747 V45 M_A_DQ48
M_A_DIM0_CK_DDR0_DP M50 DRAM0_DQ_4848 V47 M_A_DQ49
15 M_A_DIM0_CK_DDR0_DP DRAM0_CKP_0 DRAM0_DQ_4949
15 M_A_DIM0_CK_DDR0_DN M_A_DIM0_CK_DDR0_DN M48 AD48 M_A_DQ50
DRAM0_CKN_0 DRAM0_DQ_5050 AD50 M_A_DQ51
DRAM0_DQ_5151 V48 M_A_DQ52
+V_VDDQ_VR P50 DRAM0_DQ_5252 V50 M_A_DQ53
P48 DRAM0_CKP_2 DRAM0_DQ_5353 AB44 M_A_DQ54
DRAM0_CKN_2 DRAM0_DQ_5454 Y45 M_A_DQ55
DRAM0_DQ_5555
1

V52 M_A_DQ56
R218 DRAM0_DQ_5656 W51 M_A_DQ57
P41 DRAM0_DQ_5757 AC53 M_A_DQ58
4.7K_F 15 DDR3_DRAMRST_R_N DRAM0_DRAMRST DRAM0_DQ_5858
R0402 AC51 M_A_DQ59
DRAM0_DQ_5959 W53 M_A_DQ60
DRAM0_DQ_6060 Y51 M_A_DQ61
2

AF44 DRAM0_DQ_6161 AD52 M_A_DQ62


DRAM_VREF DRAM0_DQ_6262 AD51 M_A_DQ63
DRAM0_DQ_6363
J38 M_A_DQS_P0 M_A_DQS_P0 15
DRAM0_DQSP_00
1

ICLK_DRAM_TERMN_0 AH42 K38 M_A_DQS_N0 M_A_DQS_N0 15


R233 ICLK_DRAM_TERMN_1 AF42 ICLK_DRAM_TERMN DRAM0_DQSN_00 C35 M_A_DQS_P1
ICLK_DRAM_TERMN_AF42 DRAM0_DQSP_11 M_A_DQS_P1 15
2

4.7K_F C286 B34 M_A_DQS_N1 M_A_DQS_N1 15 M_A_DQS_P[7:0] 15


0.1UF/10V,X5R DRAM0_DQSN_11 D40 M_A_DQS_P2
R0402 DRAM0_DQSP_22 M_A_DQS_P2 15
c0402 DDR3_DRAM_S4_PWROK AD42 F40 M_A_DQS_N2 M_A_DQS_N2 15 M_A_DQS_N[7:0] 15
1

DDR3_VCCA_PWROK AB42 DRAM_VDD_S4_PWROK DRAM0_DQSN_22 B44 M_A_DQS_P3 M_A_DQS_P3 15


2

DRAM_CORE_PWROK DRAM0_DQSP_33 C43 M_A_DQS_N3


DRAM0_DQSN_33 M_A_DQS_N3 15
N53 M_A_DQS_P4 M_A_DQS_P4 15
DDR3_RCOMP_0 AD44 DRAM0_DQSP_44 M52 M_A_DQS_N4
DRAM_RCOMP_00 DRAM0_DQSN_44 M_A_DQS_N4 15
DDR3_RCOMP_1 AF45 T42 M_A_DQS_P5 M_A_DQS_P5 15
DDR3_RCOMP_2 AD45 DRAM_RCOMP_11 DRAM0_DQSP_55 T44 M_A_DQS_N5
DRAM_RCOMP_22 DRAM0_DQSN_55 M_A_DQS_N5 15
Y47 M_A_DQS_P6 M_A_DQS_P6 15
DRAM0_DQSP_66 Y48 M_A_DQS_N6
DRAM0_DQSN_66 M_A_DQS_N6 15
AF40 AB52 M_A_DQS_P7 M_A_DQS_P7 15
ICLK_DRAM_TERMN_0 AF41 RESERVED_AF40 DRAM0_DQSP_77 AA51 M_A_DQS_N7
RESERVED_AF41 DRAM0_DQSN_77 M_A_DQS_N7 15
B AD40 B
ICLK_DRAM_TERMN_1 AD41 RESERVED_AD40
RESERVED_AD41
1 OF 13
DDR3_RCOMP_1
VLV_M_D/BGA
DDR3_RCOMP_0 ?
REV = 1.15
DDR3_RCOMP_2
1

R9 R8
R0402 R0402 R232 R589 R590
100K_J 100K_J 29.4_F 23.2_F 162_F
R0402 R0402 R0402
2

+V1P8A +V3.3A +V_VDDQ_VR +V_VDDQ_VR +V3.3S


1

1
2

2
R429 R567 R565
10K_J 2.2k_J 2.2k_J R330 R436
r0402 r0402 r0402 2.2k_J 10K_J

2
r0402 r0402

1
+V3.3A Q4

5
LMBT3904DW1T1G
DDR3_DRAM_S4_PWROK SOT363
1

Q7B 39 DDR3_VCCA_PWROK_3P3 4 3 DDR3_VCCA_PWROK


6

R336 L2N7002DW1T1G
2.2k_J D 1 6
10 PLTRST_N PLT_RST# 18,25,28
r0402
2

2 G 1 +V1P8A
Q7A S C284
3

L2N7002DW1T1G 0.1UF/10V,X5R
1

2
D c0402
2

2
ns
18 SLP_S4_EC_N 5 G R377
S 10K_J
+V_VDDQ_VR r0402
4

EMC add C284 0627

1
A A
1

R571
2.2k_J
r0402
Bitland Information Technology Co.,Ltd.
2

D23 Page Name

18,35,39 DDR3_DRAM_PWROK 2 1 DDR3_DRAM_S4_PWROK Size Project Name Rev


A2 <Doc> Rev1.0
0.37V_30mA_LRB751V-40T1G
Date: Tuesday, March 04, 2014 Sheet 7 of 42
sod323
PROPERTY NOTE: this document contains information confidential and property to

https://vinafix.com
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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D D

?
U1B VLV_M_D M_B_DQ[63:0] 16
16 M_B_A[14:0]
M_B_A0 AY45 BG38 M_B_DQ0
M_B_A1 BB47 DRAM1_MA_00 DRAM1_DQ_00 BC40 M_B_DQ1
M_B_A2 AW41 DRAM1_MA_11 DRAM1_DQ_11 BA42 M_B_DQ2
M_B_A3 BB44 DRAM1_MA_22 DRAM1_DQ_22 BD42 M_B_DQ3
M_B_A4 BB50 DRAM1_MA_33 DRAM1_DQ_33 BC38 M_B_DQ4
M_B_A5 BC53 DRAM1_MA_44 DRAM1_DQ_44 BD36 M_B_DQ5
M_B_A6 BB49 DRAM1_MA_55 DRAM1_DQ_55 BF42 M_B_DQ6
M_B_A7 BF50 DRAM1_MA_66 DRAM1_DQ_66 BC44 M_B_DQ7
M_B_A8 BC52 DRAM1_MA_77 DRAM1_DQ_77 BH32 M_B_DQ8
M_B_A9 BE52 DRAM1_MA_88 DRAM1_DQ_88 BG32 M_B_DQ9
M_B_A10 AY48 DRAM1_MA_99 DRAM1_DQ_99 BG36 M_B_DQ10
M_B_A11 BE51 DRAM1_MA_1010 DRAM1_DQ_1010 BJ37 M_B_DQ11
M_B_A12 BD47 DRAM1_MA_1111 DRAM1_DQ_1111 BG33 M_B_DQ12
M_B_A13 BA51 DRAM1_MA_1212 DRAM1_DQ_1212 BJ33 M_B_DQ13
M_B_A14 BH49 DRAM1_MA_1313 DRAM1_DQ_1313 BG37 M_B_DQ14
BH50 DRAM1_MA_1414 DRAM1_DQ_1414 BH38 M_B_DQ15
16 M_B_A15 DRAM1_MA_1515 DRAM1_DQ_1515 AU36 M_B_DQ16
BD38 DRAM1_DQ_1616 AT36 M_B_DQ17
16 M_B_DM0 DRAM1_DM_00 DRAM1_DQ_1717
C 16 M_B_DM1 BH36 AV40 M_B_DQ18 C
BC36 DRAM1_DM_11 DRAM1_DQ_1818 AT40 M_B_DQ19
16 M_B_DM2 DRAM1_DM_22 DRAM1_DQ_1919
16 M_B_DM3 BH42 BA36 M_B_DQ20
AT51 DRAM1_DM_33 DRAM1_DQ_2020 AV36 M_B_DQ21
16 M_B_DM4 DRAM1_DM_44 DRAM1_DQ_2121
16 M_B_DM5 AM42 AY42 M_B_DQ22
AK50 DRAM1_DM_55 DRAM1_DQ_2222 AY40 M_B_DQ23
16 M_B_DM6 DRAM1_DM_66 DRAM1_DQ_2323
16 M_B_DM7 AK52 BJ41 M_B_DQ24
DRAM1_DM_77 DRAM1_DQ_2424 BG41 M_B_DQ25
AV45 DRAM1_DQ_2525 BJ45 M_B_DQ26
16 M_B_RAS_N DRAM1_RAS DRAM1_DQ_2626
16 M_B_CAS_N AV44 BH46 M_B_DQ27
BB51 DRAM1_CAS DRAM1_DQ_2727 BG40 M_B_DQ28
16 M_B_WE_N DRAM1_WE DRAM1_DQ_2828 BH40 M_B_DQ29
AY47 DRAM1_DQ_2929 BH48 M_B_DQ30
16 M_B_BS0 DRAM1_BS_00 DRAM1_DQ_3030
16 M_B_BS1 AY44 BH47 M_B_DQ31
BF52 DRAM1_BS_11 DRAM1_DQ_3131 AY52 M_B_DQ32
16 M_B_BS2 DRAM1_BS_22 DRAM1_DQ_3232 AY51 M_B_DQ33
AT44 DRAM1_DQ_3333 AP52 M_B_DQ34
16 M_B_CS0_N DRAM1_CS_0 DRAM1_DQ_3434 AP51 M_B_DQ35
AT45 DRAM1_DQ_3535 AW51 M_B_DQ36
16 M_B_CS1_N DRAM1_CS_2 DRAM1_DQ_3636 AW53 M_B_DQ37
DRAM1_DQ_3737 AR51 M_B_DQ38
BG47 DRAM1_DQ_3838 AR53 M_B_DQ39
16 M_B_CKE0 DRAM1_CKE_00 DRAM1_DQ_3939
BE46 AP47 M_B_DQ40
BD44 RESERVED_BE46 DRAM1_DQ_4040 AP45 M_B_DQ41
16 M_B_CKE1 DRAM1_CKE_22 DRAM1_DQ_4141
BF48 AK40 M_B_DQ42
RESERVED_BF48 DRAM1_DQ_4242 AM41 M_B_DQ43
AP41 DRAM1_DQ_4343 AP48 M_B_DQ44
16 M_B_ODT0 DRAM1_ODT_0 DRAM1_DQ_4444 AP50 M_B_DQ45
AT42 DRAM1_DQ_4545 AK42 M_B_DQ46
16 M_B_ODT1 DRAM1_ODT_2 DRAM1_DQ_4646 AH40 M_B_DQ47
DRAM1_DQ_4747 AM45 M_B_DQ48
AV50 DRAM1_DQ_4848 AM47 M_B_DQ49
16 M_B_CK_DDR0 DRAM1_CKP_0 DRAM1_DQ_4949
16 M_B_CK_DDR#0 AV48 AF48 M_B_DQ50
DRAM1_CKN_0 DRAM1_DQ_5050 AF50 M_B_DQ51
DRAM1_DQ_5151 AM48 M_B_DQ52
DRAM1_DQ_5252 AM50 M_B_DQ53
AT50 DRAM1_DQ_5353 AH44 M_B_DQ54
AT48 DRAM1_CKP_2 DRAM1_DQ_5454 AK45 M_B_DQ55
DRAM1_CKN_2 DRAM1_DQ_5555 AM52 M_B_DQ56
DRAM1_DQ_5656 AL51 M_B_DQ57
DRAM1_DQ_5757 AG53 M_B_DQ58
B AT41 DRAM1_DQ_5858 AG51 M_B_DQ59 B
16 DDR3_B_DRAMRST# DRAM1_DRAMRST DRAM1_DQ_5959 AL53 M_B_DQ60
DRAM1_DQ_6060 AK51 M_B_DQ61
DRAM1_DQ_6161 AF52 M_B_DQ62
DRAM1_DQ_6262 AF51 M_B_DQ63
DRAM1_DQ_6363
BF40 M_B_DQS_P0 16
DRAM1_DQSP_00 BD40
DRAM1_DQSN_00 M_B_DQS_N0 16
BG35 M_B_DQS_P1 16
DRAM1_DQSP_11 BH34
DRAM1_DQSN_11 M_B_DQS_N1 16
BA38 M_B_DQS_P2 16
DRAM1_DQSP_22 AY38
DRAM1_DQSN_22 M_B_DQS_N2 16
BH44 M_B_DQS_P3 16
DRAM1_DQSP_33 BG43
DRAM1_DQSN_33 M_B_DQS_N3 16
AU53 M_B_DQS_P4 16
DRAM1_DQSP_44 AV52
DRAM1_DQSN_44 M_B_DQS_N4 16
AP42 M_B_DQS_P5 16
DRAM1_DQSP_55 AP44
DRAM1_DQSN_55 M_B_DQS_N5 16
AK47 M_B_DQS_P6 16
DRAM1_DQSP_66 AK48
DRAM1_DQSN_66 M_B_DQS_N6 16
AH52 M_B_DQS_P7 16
DRAM1_DQSP_77 AJ51
DRAM1_DQSN_77 M_B_DQS_N7 16

2 OF 13

VLV_M_D/BGA
?
REV = 1.15

A A

Bitland Information Technology Co.,Ltd.


Page Name

Size Project Name Rev


A2 <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 8 of 42
PROPERTY NOTE: this document contains information confidential and property to

https://vinafix.com
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

+V1P8A 7,10,13,18,34,39

+V1P8S 6,10,11,13,18,21,24,39

+V3.3A 7,11,13,18,23,25,28,30,33,34,35,36,37,39

+V3.3S 6,7,13,18,19,20,21,22,23,25,28,30,35,36,39

?
U1F VLV_M_D
D D
G2 M10
GPIO_S5_31 RESERVED_M10 M9
RESERVED_M9
P7
M3 RESERVED_P7 P6
L1 GPIO_S5_32 RESERVED_P6
K2 GPIO_S5_33
K3 GPIO_S5_34 M7
+V1P8A M2 GPIO_S5_35 RESERVED_M7 M12 USB_P1_REXT R20 2 1 1.24K_F R0402
N3 GPIO_S5_36 USB3_REXT0
P2 GPIO_S5_37 P10
L3 GPIO_S5_38 RESERVED_P10 P12
GPIO_S5_39 RESERVED_P12

2
R393 M4
10K_J RESERVED_M4 M6
r0402 J3 RESERVED_M6
P3 GPIO_S5_40 D4
ns USB3_RX0_P 27

1
H3 GPIO_S5_41 USB3_RXP0 E3
GPIO_S5_42 USB3_RXN0 USB3_RX0_N 27
R170 1 2 0_J R0402 ns SoC_to_EC_Win8P1_R B12
18 SoC_to_EC_Win8P1 GPIO_S5_43 K6
USB3_TXP0 K7 USB3_TX0_P 27 USB3.0 Port
M16 USB3_TXN0 USB3_TX0_N 27
USB3.0 Port1 27 USB_PP0
K16 USB_DP0
27 USB_PN0 USB_DN0
R254 0_J R0402
23 USB_SOC_PP
R325 0_J R0402 ns J14
30 USB_PP_CD USB_DP1
R321 0_J R0402 ns G14
R253 0_J R0402
TP 30 USB_PN_CD USB_DN1
23 USB_SOC_PN
23 USB_CAM_PP K12
J12 USB_DP2
Camera 23 USB_CAM_PN USB_DN2 H8
R264 0_J R0402 K10 RESERVED_H8 H7
29 USB_HP USB_DP3 RESERVED_H7
29 USB_HN R312 0_J R0402 H10
USB_DN3
H5
USB HUB D10 RESERVED_H5 H4
F10 ICLK_USB_TERMN_D10 RESERVED_H4
ICLK_USB_TERMN
C C
1

R22 R23 27 USB3_OC_N USB3_OC_N C20


1K_J 1K_J R275 0_J R0402 USB_OC# B20 USB_OC_00
30 USB_OC#0 ns USB_OC_11
R0402 R0402 +V1P8S

BD12 GPIO_S0_SC_55
2

R21 2 1 45.3_F r0402 D6 GPIO_S0_SC_55 BC12 GPIO_S0_SC_56


USB_RCOMPO GPIO_S0_SC_56

1
C7 BD14 Add memory ID GPIO61 add the touch_RST 1112
USB_RCOMPI GPIO_S0_SC_57 BC14 GPIO_S0_SC_58 R258
GPIO_S0_SC_58 BF14 GPIO_S0_SC_59 Top Swap (A16 Override) 10K_J
20MIL TP12 1 M13 GPIO_S0_SC_59 BD16 GPIO_S0_SC_60 0 = Top address bit is unchanged R0402
USB_PLL_MON GPIO_S0_SC_60 BC16 GPIO_S0_SC_61 1 = Top address bit is inverted
GPIO_S0_SC_61
ns
+V1P8A

2
GPIO_S0_SC_56
B4 BH12
USB_HSIC0_DATA ILB_8254_SPKR SPKR_R 20

1
B5

teknisi indonesia
USB_HSIC0_STROBE
2

R257
R365 R368 10K_J
10K_J 10K_J E2 R0402
r0402 r0402 D2 USB_HSIC1_DATA BH22
USB_HSIC1_STROBE SIO_I2C0_DATA
ns
BG23
1

2
USB_OC# SIO_I2C0_CLK
R24 2 1 45.3_F r0402 A7
USB3_OC_N USB_HSIC_RCOMP BG24
SIO_I2C1_DATA BH24
SIO_I2C1_CLK
R25 2 1 49.9_F R0402 RCOMP_LPC_HVT BF18
BH16 LPC_RCOMP BG25
18,25 LPC_AD0 ILB_LPC_AD_00 SIO_I2C2_DATA
18,25 LPC_AD1 BJ17 BJ25
BJ13 ILB_LPC_AD_11 SIO_I2C2_CLK
18,25 LPC_AD2 ILB_LPC_AD_22
18,25 LPC_AD3 BG14
+V1P8S BG17 ILB_LPC_AD_33 BG26
18,25 LPC_FRAME_N BG15 ILB_LPC_FRAME SIO_I2C3_DATA BH26
18 L_CLKOUT R837 1R0402 ILB_LPC_CLK_00 SIO_I2C3_CLK
25 L_CLKOUT1
ns2 BH14 ILB_LPC_CLK_11
2

C352 0_J BG16


33pF/50V,X5R 18 L_CLKRUN_N ILB_LPC_CLKRUN
1

BG13 BF27 Top Swap (A16 Override)


c0402 18 ILB_SERIRQ ILB_LPC_SERIRQ SIO_I2C4_DATA BG27 0 = Top address bit is unchanged
1

B
R270 R269 R266 SIO_I2C4_CLK 1 = Top address bit is inverted B
2.2k_J 2.2k_J 2.2k_J for emc 0303 BH28
r0402 r0402 r0402
2

PCU_SMB_DATA BG12 SIO_I2C5_DATA BG28


PCU_SMB_CLK BH10 PCU_SMB_DATA SIO_I2C5_CLK
BG11 PCU_SMB_CLK
PCU_SMB_ALERT BJ29 +V1P8S +V1P8S +V1P8S +V1P8S +V1P8S +V1P8S
SIO_I2C6_DATA BG29
SIO_I2C6_CLK
6 OF 13

1
BH30 GPIO_S0_SC_92
? GPIO_S0_SC_092 BG30 1 pad R286 R287 R290 R292 R293 R331
VLV_M_D/BGA GPIO_S0_SC_093 TP43
1K_J 1K_J 1K_J 1K_J 1K_J 1K_J
REV = 1.15
R0402 R0402 R0402 R0402 R0402 R0402
Memory_ID Memory_ID Memory_ID Memory_ID Memory_ID Memory_ID

2
GPIO_S0_SC_55
GPIO_S0_SC_58
GPIO_S0_SC_59
GPIO_S0_SC_58 GPIO_S0_SC_59GPIO_S0_SC_60 GPIO_S0_SC_61 SDRAM Configuration GPIO_S0_SC_60
GPIO_S0_SC_61
0(R285) 0(R288) 0(R291) 0(R294) Hynix H5TC4G63AFR-PBA GPIO_S0_SC_92

1
1

1
0(R285) 0(R288) 0(R291) 1(R293) Hynix H5TC8G63AMR-PBA R294 R316
R284 R285 R288 R291 1K_J 1K_J
1K_J 1K_J 1K_J 1K_J R0402 R0402
0(R285) 0(R288) 1(R292) 0(R294) Micron MT41K256M16HA-125:E R0402 R0402 R0402 R0402 Memory_ID Memory_ID
Memory_ID Memory_ID Memory_ID Memory_ID

2
2

2
0(R285) 0(R288) 1(R292) 1(R293) Micron MT41K512M16TNA-125:E

0(R285) 1(R290) 0(R291) 0(R294) Elpida EDJ4216EFBG-GN-F

A
0(R285) 1(R290) 0(R291) 1(R293) Elpida EDJ8416E6MB-GN-F A

GPIO_S0_SC_55 Channel Configuration


0(R285) 1(R290) 1(R292) 0(R294) Samsung K4B4G1646Q-HYK0

0(R285) 1(R290) 1(R292) 1(R293) Samsung K4B8G1646Q-MYK0 Bitland Information Technology Co.,Ltd.
1(R286) Single

https://vinafix.com
Page Name
1(R287) 0(R288) 0(R291) 0(R294) Hynix H5TC2G63FFR-PBA
Size Project Name Rev
C <Doc> Rev1.0
1(R287) 0(R288) 0(R291) 1(R293) Micron MT41K128M16JT-125K
Date: Wednesday, April 02, 2014 Sheet 9 of 42
0(R284) Double Samsung K4B2G1646Q-BYK0
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
1(R287) 0(R288) 1(R292) 0(R294) documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

+V3.3A_RTC
+V1P8A

+V1P8A

2
+V3.3A_RTC 13,18

1
R281 1 2 10K_J R0402 PMU_BATLOW_N R451
+V1P8A 7,9,13,18,34,39
R277 R449 1 2 10K_J R0402 PMC_SUS_STAT# N/A
+ECVCC 18,19,30,32,33
10K_J R490 1 2 10K_J R0402 PCIE_WAKE_R_N R0402
+V1P8S 6,9,11,13,18,21,24,39
R0402 R506 1 2 10K_J R0402 SUSPWRDNACK ns
+V3.3S 6,7,13,18,19,20,21,22,23,25,28,30,35,36,39
+V1P0S 11,13,37,39

1
2
GPIO_S514_J20
PMU_BATLOW_N

1
R276 +V1P8S

2
D D
10K_J
R0402 R452
R448 1 2 10K_J R0402 PMU_RSTBTN_N N/A
ns R0402

2
ns

1
+V3.3A_RTC C3 2 1 18PF/50V,NPO
c0402
for emc 0303

3
R447 1 2 20K_J R0402 SRTCRST_N
R446 1 2 20K_J R0402 RTEST_N Y1 2 R27 ?

OPEN_JUMP_OPEN2
25MHZ 4 1M_J U1E VLV_M_D

2
y_4p_smd3225 r0402

1
1

C86 C87 XTAL25_IN AH12 AU34


ICLK_OSCIN SIO_UART1_RXD

GP1
1UF/6.3V,X5R 1UF/6.3V,X5R C4 2 1 18PF/50V,NPO XTAL25_OUT AH10 AV34

Vinafix.com
C0402 C0402 c0402 ICLK_OSCOUT SIO_UART1_TXD BA34
2

AD9 SIO_UART1_RTS AY34


1

RESERVED_AD9 SIO_UART1_CTS
ICLKICOMP AD14 BF34
ICLKRCOMP AD13 ICLK_ICOMP SIO_UART2_RXD BD34
SRTC_RST_N:Low to clear ME RTC register ICLK_RCOMP SIO_UART2_TXD
RTC_RST_N:Low to clear CMOS BD32
1 SIO_UART2_RTS

1
AD10 BF32
R28 R278 AD12 RESERVED_AD10 SIO_UART2_CTS
R0402 R0402 RESERVED_AD12
4.02K_F 47.5_F AF6
AF4 PCIE_CLKN_00 D26 SUSPWRDNACK
PCIE_CLKP_00 PMC_SUSPWRDNACK G24 1 TP10 20MIL
2

2
AF9 PMC_SUSCLK0_G24 F18 PMU_SLP_S0IX_N 1 TP45 pad RSMRST_N
AF7 PCIE_CLKN_11 PMC_SLP_S0IX F22
PCIE_CLKP_11 PMC_SLP_S4 PMU_SLP_S4_N 18
D22 PMU_SLP_S3_N 18
PMC_SLP_S3

2
RN19 0_J RA4_0402 J20 GPIO_S514_J20
2 1 AK4 GPIO_S514_J20 D20 R178
28 CLK_PCIE_LAN# PCIE_CLKN_22 PMC_ACPRESENT PMU_AC_PRESENT 18
+V1P8A 4 3 AK6 F26 100k_J
28 CLK_PCIE_LAN PCIE_CLKP_22 PMC_WAKE_PCIE_0 PCIE_WAKE_R_N 25,28
K26 PMU_BATLOW_N r0402
R26 2 1 51_J R0402 XDP_H_TMS AM4 PMC_BATLOW J26
C C
PMU_PWRBTN_N 18

1
R29 2 1 51_J R0402 XDP_H_TDI RN18 0_J RA4_0402 AM6 PCIE_CLKN_33 PMC_PWRBTN BG9 PMU_RSTBTN_N
R30 2 1 51_J R0402 XDP_H_TDO 2 1 PCIE_CLKP_33 PMC_RSTBTN F20
25 PCIE_REFCLK0_DN PMC_PLTRST PLTRST_N 7
4 3 AM10 J24 GPIO_S517_J24R77 2 1 2.2k_J R0402
R18 1 2 51_J R0402 XDP_H_TCK 25 PCIE_REFCLK0_DP AM9 RESERVED_AM10 GPIO_S517_J24 G18 PMC_SUS_STAT#
R19 1 2 51_J R0402 XDP_H_TRST_N RESERVED_AM9 PMC_SUS_STAT
R31 2 1 0_J RTC_X1_R C5 2 1 15PF/50V,NPO
R0402 C0402
C11 RTEST_N
20MIL TP13 1 BH7 ILB_RTC_TEST
PMC_PLT_CLK_00

2
BH5
BH4 PMC_PLT_CLK_11 R32
BH8 PMC_PLT_CLK_22 B10 R54 1 2 0_J 10M_J
PMC_PLT_CLK_33 PMC_RSMRST RSMRST_N 18
+V1P8A BH6 B7 R0402 R0402
PMC_PLT_CLK_44 PMC_CORE_PWROK COREPWROK 39
BJ9
SRTCRST_N C12 PMC_PLT_CLK_55

1
ILB_RTC_RST C9 RTC_X1
ILB_RTC_X1
1

XDP_H_TCK D14 A9 RTC_X2 C6 2 1 15PF/50V,NPO


R289 XDP_H_TRST_N G12 TAP_TCK ILB_RTC_X2 B8 BVCCRTC_EXTPAD C0402
XDP_H_TMS F14 TAP_TRST ILB_RTC_EXTPAD
200_J TAP_TMS
R0402 XDP_H_TDI F12
XDP_H_TDO G16 TAP_TDI RTC_X2 1 4RTC_X1_R
TAP_TDO

1
pad 1 D18 C7
TP44
2

F16 TAP_PRDY B24 R33 1 2 20.0_J R0402 0.1UF/10V,X5R Y2 2 3


TAP_PREQ SVID_ALERT SVID_ALERT_N 37
AT34 A25 R34 1 2 16.9_F R0402 C0402 32.768KHZ
SVID_DATA 37

2
RESERVED SVID_DATA C25 R35 1 2 0_J R0402 Y_4P_SMD7014
SVID_CLK SVID_CLK 37
SPI_CS0_R_N R56 1 2 22_J R0402 C23
C21 PCU_SPI_CS_00
PCU_SPI_CS_11

1
SPI_MISO B22 AU32
SPI_MOSI R95 1 2 22_J R0402 A21 PCU_SPI_MISO SIO_PWM_00 AT32 R491
SPI_CK_R R96 1 2 22_J R0402 C22 PCU_SPI_MOSI SIO_PWM_11 130.0_F
PCU_SPI_CLK R0402
ns
20MIL TP29 1 B18

2
B16 GPIO_S5_0 K24
20MIL TP17 1 C18 GPIO_S5_1 GPIO_S5_22 N24 1 TP46 20MIL
20MIL TP18 1 A17 GPIO_S5_2 GPIO_S5_23 M20 1 TP47 20MIL Remove the Y13(1018-00143) 1125
C17 GPIO_S5_3 GPIO_S5_24 J18 1 TP48 20MIL +V1P0S
B
C16 GPIO_S5_4 GPIO_S5_25 M18 1 TP49 20MIL B
GPIO_S5_5 GPIO_S5_26
B14
GPIO_S5_6 GPIO_S5_27
K18 Add 130 ohm for power 0115
C15 K20
18 SOC_EXTSMI_N GPIO_S5_7 GPIO_S5_28 M22
GPIO_S5_29 M24
GPIO_S5_30
C13
A13 GPIO_S5_8
C19 GPIO_S5_9 AV32
GPIO_S5_10 SIO_SPI_CS BA28
SIO_SPI_MISO AY28
GPIO_RCOMP18 N26 5 OF 13 SIO_SPI_MOSI AY30
GPIO_RCOMP SIO_SPI_CLK
1

R41 VLV_M_D/BGA ?
+V1P8A R0402 REV = 1.15
+V1P8S_SPI 49.9_F

R51 1 2 0_J R0402 +ECVCC


2

+V1P8S_SPI
Follow S210 1115 D1
BATT1 LBAT54CLT1G
RTCBAT with Cable SOT23-3
+RTC_VCC +V3.3A_RTC
+ RTCBAT1
Pitch=1.25mm_2Pin
1

-
2

cns2_1d25_r_85204 3
R52 R48 3
4.7K_J 10K_J +V1P8S_SPI 1 R838 2 1 1K_J2

1
R0402 R0402 2 R0402 C9 C210
BAT_GLUE1 4 1UF/6.3V,X5R 0.1UF/10V,X5R

SPI ROM 8M
RTC SPONGE C0402 c0402
1

2
1

C8
SPI_WP_N 0.1UF/10V,X5R
SPI_HOLD_N U3 C0402
2

W25Q64DWSSIG
sop8_1d27_8
SPI_CS0_R_N 1 8
SPI_MISO R47 1 2 22_J R0402 SPI_SO0 2 CE# VDD 7 SPI_HOLD_N
A A
SPI_WP_N 3 SO/IO1 HOLD#/IO3 6 SPI_CK_R
4 WP#/IO2 SCK 5 SPI_MOSI
GND SIO/IO0
2

C10
10PF/50V,NPO
C0402 Bitland Information Technology Co.,Ltd.
1

ns

https://vinafix.com
Page Name

Size Project Name Rev


C <Doc> Rev1.0
Date: Tuesday, March 11, 2014 Sheet 10 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

+V1P0S 10,13,37,39

+V3.3A 7,13,18,23,25,28,30,33,34,35,36,37,39

+V1P8S 6,9,10,13,18,21,24,39

+V3.3S 6,7,13,18,19,20,21,22,23,25,28,30,35,36,39

D D

?
U1D
VLV_M_D

26 SATA_TXP0 BF6 AY7 C0402 0.1uF/10V,X5R 2 1 C26 LAN_TXP0 28


BG7 SATA_TXP_0 PCIE_TXP_0 AY6 C0402 0.1uF/10V,X5R 2 1 C146
SATA 26 SATA_TXN0 SATA_TXN_0 PCIE_TXN_0 LAN_TXN0 28
AU16 AT14 LAN_RXP0 28
LAN
26 SATA_RXP0 SATA_RXP_0 PCIE_RXP_0
AV16 AT13 LAN_RXN0 28
26 SATA_RXN0 SATA_RXN_0 PCIE_RXN_0
BD10 AV6 MINI_TXP1_L C0402 0.1uF/10V,X5R 2 1 C12 MINI_TXP1 25
BF10 SATA_TXP1 PCIE_TXP_1 AV4 MINI_TXN1_L C0402 0.1uF/10V,X5R 2 1 C13
SATA_TXN_1 PCIE_TXN_1 MINI_TXN1 25
These pins are used for hardware DEVSLP enabling.
SATA_DEVSLP[0] is multiplexed with SATA_GPI[1], MMC1_RST#. AY16 AT10 MINI_RXP1 25
WIFI
SATA_DEVSLP[1] is multiplexed with LPE_I2S2_CLK. BA16 SATA_RXP_1 PCIE_RXP_1 AT9
SATA_RXN_1 PCIE_RXN_1 MINI_RXN1 25
BB10 AT7
BC10 ICLK_SATA_TERMP PCIE_TXP_2 AT6
ICLK_SATA_TERMN PCIE_TXN_2
R104 2 1 0_J R0402 SATA_GP0 BA12 AP12
18 SOC_RUNTIME_SCI_N SATA_GP0 PCIE_RXP_2 +V1P8S
AY14 AP10
AY12 SATA_GP1 PCIE_RXN_2
SATA_LED AP6
AU18 PCIE_TXP_3 AP4
SATA_RCOMP_P_AU18 PCIE_TXN_3

1
R5 2 1 402_F r0603 AT18
SATA_RCOMP_N_AT18 AP9 LAN_CLK_REQ# R252 R255 R256 R265
PCIE_RXP_3 AP7
PCIE_RXN_3 10K_J 10K_J 10K_J 10K_J
AT22 R0402 R0402 R0402 R0402
21 FLASH_CLK MMC1_CLK BB7
AV20 VSS_BB7 BB5
21 FLASH_D0

2
AU22 MMC1_D0 VSS_BB5 LAN_CLK_REQ0_N
21 FLASH_D1 MMC1_D1
21 FLASH_D2 AV22 BG3 LAN_CLK_REQ0_N LAN_CLK_REQ0_N 28 PCIE_R_CLKREQ1_N
AT20 MMC1_D2 PCIE_CLKREQ_0 BD7 PCIE_R_CLKREQ1_N SOC_PCIE_CLKREQ0_N
21 FLASH_D3 MMC1_D3 PCIE_CLKREQ_1 PCIE_R_CLKREQ1_N 25
21 FLASH_D4 AY24 BG5 SOC_PCIE_CLKREQ0_N PCIE_R_CLKREQ3_N
AU26 MMC1_D4 PCIE_CLKREQ_2 BE3 PCIE_R_CLKREQ3_N
21 FLASH_D5 MMC1_D5 PCIE_CLKREQ_3
21 FLASH_D6 AT26 BD5 1 TP11 20MIL
AU20 MMC1_D6 SD3_WP_BD5
C 21 FLASH_D7 C
MMC1_D7 AP14
Delete R844 AV26 PCIE_RCOMP_P_AP14_AP14 AP13 R6 2 1 402_F r0603
21 FLASH_CMD BA24 MMC1_CMD PCIE_RCOMP_N_AP13_AP13
21 FLASH_RESET MMC1_RST BB4
R57 1 2 49.9_F R0402 AY18 RESERVED_BB4 BB3
MMC1_RCOMP RESERVED_BB3 AV10
RESERVED_AV10 AV9
BA18 RESERVED_AV9
AY20 SD2_CLK
BD20 SD2_D0 BF20 HDA_RCOMP R58 1 2 49.9_F R0402
BA20 SD2_D1 HDA_LPE_RCOMP BG22 HDA_RST_N_SSP_MCLK R0402 33_J 2 1 R59
BD18 SD2_D2 HDA_RST BH20 HDA_SYNC_SSP0_SFRM R0402 33_J 2 1 R60 HDA_RST_N 20
BC18 SD2_D3_CD HDA_SYNC BJ21 R0402 33_J 2 1 R63 HDA_SYNC 20
SD2_CMD HDA_CLK BG20 HDA_SDO_SSP0_TXD_R1 R0402 33_J 2 1 R61 HDA_BIT_CK 20
HDA_SDO BG19 HDA_SDOUT 20
HDA_SDI0 HDA_SDIN 20
BG21
AY26 HDA_SDI1 BH18
AT28 SD3_CLK HDA_DOCKRST BG18 +V1P8S
BD26 SD3_D0 HDA_DOCKEN
AU28 SD3_D1 BF28
BA26 SD3_D2 LPE_I2S2_CLK BA30 I2S_2_FS
SD3_D3 LPE_I2S2_FRM

1
BC24 BC30 I2S_2_TXD
AV28 SD3_CD# LPE_I2S2_DATAOUT BD28 R260
20MIL TP30 1 BF22 SD3_CMD LPE_I2S2_DATAIN
SD3_1P8EN 10K_J
20MIL TP33 1 BD22 P34 R0402
SD3_PWREN RESERVED_P34 N34
SDMMC3_RCOMP BF26 RESERVED_N34

2
SD3_RCOMP AK9 I2S_2_FS
RESERVED_AK9 AK7
RESERVED_AK7

1
C24 PROCHOT_N R259
PROCHOT
1

10K_J
R62 R0402
4 OF 13
R0402 VLV_M_D/BGA ns
49.9_F REV = 1.15 ?

2
2

B B

BIOS Boot Selection


0 = LPC
Vinafix.com +V1P8S
1 = SPI

1
R272
10K_J
R0402
+V3.3A
Q9

2
I2S_2_TXD L2N7002LT1G
2

SOT23-3

3
R10
10K_J R262 D
r0402 10K_J
R0402 1 EC_OVERRIDE 18
1

ns S G
PROCHOT_EC_N 18

2
+V1P0S +V1P0S
2

SOT23-3
2

R15 2 1 1K_J 1 LMBT3904LT1G


Q28
R0402
R64
Security Flash Descriptors
0 = Override
3

73.2_F
R0402
1 = Normal Operation
1

PROCHOT_N
PROCHOT_N 37
1

A CAD Note: Capacitor need to be placed C2 A


47PF/50V,NPO
close to transistor c0402
2

Bitland Information Technology Co.,Ltd.

https://vinafix.com
Page Name

Size Project Name Rev


C <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 11 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

+VCORE 37

+VGFX 37

+V_VDDQ_VR 7,15,16,35,36,39

D D

+VCORE

R524 1 100_J 2 r0402 VCORE_VSNS

+VGFX
? +V_VDDQ_VR
U1G VLV_M_D
R525 1 100_J 2 r0402 VGFX_VSNS
P28 BD49
37 VCORE_VSNS BB8 CORE_VCC_SENSE_P28 DRAM_VDD_S4_BD49 BD52
37 VGFX_VSNS N28 UNCORE_VNN_SENSE DRAM_VDD_S4_BD52 BD53
37 VCORE_GSNS CORE_VSS_SENSE_N28 DRAM_VDD_S4_BD53 BF44
R526 1 100_J 2 r0402 VCORE_GSNS DRAM_VDD_S4_BF44 BG51 +V_VDDQ_VR +V_VDDQ_VR
+V_VDDQ_VR DRAM_VDD_S4_BG51 BJ48
AD38 DRAM_VDD_S4_BJ48 C51
AF38 DRAM_VDD_S4_AD38 DRAM_VDD_S4_C51 D44
DRAM_VDD_S4_AF38 DRAM_VDD_S4_D44

1
A48 F49 C17 C18 C19 C20 C21 C22
DRAM_VDD_S4 DRAM_VDD_S4_F49

1
AK38 F52 C16 1UF/6.3V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R
AM38 DRAM_VDD_S4_AK38 DRAM_VDD_S4_F52 F53 2.2uF/6.3V,X5R 2.2uF/6.3V,X5R 2.2uF/6.3V,X5R 2.2uF/6.3V,X5R C0402_BGA C0402_BGA C0402_BGA

2
AV41 DRAM_VDD_S4_AM38 DRAM_VDD_S4_F53 H46 C0402 C0402 C0402 C0402

2
AV42 DRAM_VDD_S4_AV41 DRAM_VDD_S4_H46 M41
BB46 DRAM_VDD_S4_AV42 DRAM_VDD_S4_M41 M42
+VCORE DRAM_VDD_S4_BB46 DRAM_VDD_S4_M42 V38
DRAM_VDD_S4_V38 Y38
DRAM_VDD_S4_Y38
AA27
+VCORE AA29 CORE_VCC_S0IX_AA27 +VGFX
AA30 CORE_VCC_S0IX_AA29
AC27 CORE_VCC_S0IX_AA30
AC29 CORE_VCC_S0IX_AC27 AA24
CORE_VCC_S0IX_AC29 UNCORE_VNN_S3_AA24
1

1
C23 C24 C25 C27 C131 C132 AC30 AC22
10UF/6.3V,X5R 4.7UF/6.3V,X5R 4.7UF/6.3V,X5R 2.2uF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R AD27 CORE_VCC_S0IX_AC30 UNCORE_VNN_S3_AC22 AC24 +VGFX
C0603 C0603 C0603 C0402 C0402_BGA C0402_BGA AD29 CORE_VCC_S0IX_AD27 UNCORE_VNN_S3_AC24 AD22
2

2
C AD30 CORE_VCC_S0IX_AD29 UNCORE_VNN_S3_AD22 AD24 C
AF27 CORE_VCC_S0IX_AD30 UNCORE_VNN_S3_AD24 AF22
CORE_VCC_S0IX_AF27 UNCORE_VNN_S3_AF22

1
Remove C26 2.2uf 0603 and Add C131 and C132 for layout 1213 AF29 AF24 C28 C29 C30 C31
AG27 CORE_VCC_S0IX_AF29 UNCORE_VNN_S3_AF24 AG22 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R
AG29 CORE_VCC_S0IX_AG27 UNCORE_VNN_S3_AG22 AG24 c0805 c0805 c0805 c0805

2
AG30 CORE_VCC_S0IX_AG29 UNCORE_VNN_S3_AG24 AJ22
+VCORE P26 CORE_VCC_S0IX_AG30 UNCORE_VNN_S3_AJ22 AJ24
P27 CORE_VCC_S0IX_P26 UNCORE_VNN_S3_AJ24 AK22
U27 CORE_VCC_S0IX_P27 UNCORE_VNN_S3_AK22 AK24
U29 CORE_VCC_S0IX_U27 UNCORE_VNN_S3_AK24 AK25 +VGFX
CORE_VCC_S0IX_U29 UNCORE_VNN_S3_AK25
1

C32 C33 C113 V27 AK27


22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R V29 CORE_VCC_S0IX_V27 UNCORE_VNN_S3_AK27 AK29
c0805 c0805 c0805 V30 CORE_VCC_S0IX_V29 UNCORE_VNN_S3_AK29 AK30
2

CORE_VCC_S0IX_V30 UNCORE_VNN_S3_AK30

1
Y27 AK32 C36 C37 C38
Y29 CORE_VCC_S0IX_Y27 UNCORE_VNN_S3_AK32 AM22 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R
Y30 CORE_VCC_S0IX_Y29 UNCORE_VNN_S3_AM22 C0402_BGA C0402_BGA C0402_BGA

2
CORE_VCC_S0IX_Y30

+VCORE 20MIL TP22 1 AF30 AA22 1 TP23 20MIL


TP_CORE_V1P05_S4 TP2_CORE_VCC_S0IX
7 OF 13
+VGFX
VLV_M_D/BGA
1

C34 C35 ?
REV = 1.15
22uF/6.3V,X5R 22uF/6.3V,X5R

1
c0805 c0805 C152 C153 C158
2

10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R


C0603 C0603 C0603

2
checklist Schematic

+VCORE 22μF 7 5
B
10μF 1 1 B

4.7UF 2 2
2.2UF 2 2
+VGFX 22μF 4 4
10μF 3 3 Vinafix.com
1μF 3 3
+V_VDDQ_VR 2.2UF 4 4

A A

Bitland Information Technology Co.,Ltd.


Page Name

Size Project Name Rev


A2 <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 12 of 42
PROPERTY NOTE: this document contains information confidential and property to

https://vinafix.com
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

+V1P8A 7,9,10,18,34,39

+V1P0S 10,11,37,39 +V3.3S 6,7,18,19,20,21,22,23,25,28,30,35,36,39

+V1P05S 36,39 +V3.3A 7,11,18,23,25,28,30,33,34,35,36,37,39

+V1P35S 39 +V3.3A_RTC 10,18

+V1P0A 34,39

+V1P5S 20,36,39

+V1P8S 6,9,10,11,18,21,24,39
D D

for DRAM_V1P35_S0Ix_F1
+V1P35S
BA1
2 1

1
DG Page52 : C39
1UF/6.3V,X5R
C40
1UF/6.3V,X5R 180ohm/100MHZ

S0iX is not supported. The S0iX rails are equivalent to S0-only rails on the C0402_BGA C0402_BGA FB0603

2
platform.
?
+V1P0S U1H VLV_M_D +V1P5S +V1P8S +V3.3S

V32 AD36
BJ6 SVID_V1P0_S3_V32 DRAM_V1P35_S0IX_F1_AD36 AM32 LPC_AD[0:3]/LPC_FRAME#/LPC_CLK
AD35 VGA_V1P0_S3_BJ6 HDA_LPE_V1P5V1P8_S3_AM32 AM30 +V3.3A Signal can operate at 3.3 V if SoC LPC_V1P8V3P3_S3 power ball is connected to a 3.3V supply
AF35 DRAM_V1P0_S0IX_AD35 UNCORE_V1P8_S3_AM30 AN32
AF36 DRAM_V1P0_S0IX_AF35 UNCORE_V1P8_S3_AN32 AM27
AA36 DRAM_V1P0_S0IX_AF36 LPC_V1P8V3P3_S3_AM27 U24 +VSDIO +V3.3S
AJ36 DRAM_V1P0_S0IX_AA36 UNCORE_V1P8_G3_U24 N18
AK35 DRAM_V1P0_S0IX_AJ36 USB_V3P3_G3_N18 P18
AK36 DRAM_V1P0_S0IX_AK35 USB_V3P3_G3_P18 U38 R65 1 2 0_J R0603
Y35 DRAM_V1P0_S0IX_AK36 UNCORE_V1P8_S3_U38 AN24 +V1P8S
Y36 DRAM_V1P0_S0IX_Y35 VGA_V3P3_S3_AN24 V25 +VSDIO USB_HSIC_V1P2_G3_V18 +V3.3A_RTC
AK19 DRAM_V1P0_S0IX_Y36 PCU_V1P8_G3_V25 N22 R66 1 2 0_J R0603
DDI_V1P0_S0IX_AK19 PCU_V3P3_G3_N22
ns
AK21 AN27
AJ18 DDI_V1P0_S0IX_AK21 SD3_V1P8V3P3_S3_AN27 AD16
AM16 DDI_V1P0_S0IX_AJ18 VSS_AD16 AD18
U22 DDI_V1P0_S0IX_AM16 VSS_AD18 V18 USB_HSIC_V1P2_G3_V18
V22 UNCORE_V1P0_G3_U22 USB_HSIC_V1P2_G3_V18 AA18
AN29 UNCORE_V1P0_G3_V22 UNCORE_V1P8_G3_AA18 P22 +V1P8A USB_HSIC_V1P2_G3_V18 +V1P0A
AN30 VIS_V1P0_S0IX_AN29 RTC_VCC_P22 N20
AF16 VIS_V1P0_S0IX_AN30 USB_V1P8_G3_N20 U25
AF18 UNCORE_V1P0_S3_AF16 PMU_V1P8_G3_U25 AF33 R68 1 2 0_J R0402
Y18 UNCORE_V1P0_S3_AF18 CORE_V1P05_S3_AF33 AG33
G1 UNCORE_V1P0_S3_Y18 CORE_V1P05_S3_AG33 AG35
C AM21 UNCORE_V1P0_S3_G1 CORE_V1P05_S3_AG35 U33 +V1P05S C
AN21 PCIE_V1P0_S3_AM21 CORE_V1P05_S3_U33 U35
PCIE_V1P0_S3_AN21 CORE_V1P05_S3_U35 V33
+V1P05S AN18 CORE_V1P05_S3_V33 A3
AN19 PCIE_GBE_SATA_V1P0_S3_AN18 VSS_A3_A3 A49
AA33 SATA_V1P0_S3_AN19 VSS_A49_A49 A5
AF21 CORE_V1P05_S3_AA33 VSS_A5_A5 A51
AG21 UNCORE_V1P0_S0IX_AF21 VSS_A51_A51 A52
V24 UNCORE_V1P0_S0IX_AG21 VSS_A52_A52 A6
Y22 VIS_V1P0_S0IX_V24 VSS_A6_A6 B2
Y24 VIS_V1P0_S0IX_Y22 VSS_B2_B2 B52
M14 VIS_V1P0_S0IX_Y24 VSS_B52_B52 B53
U18 USB_V1P0_S3_M14 VSS_B53_B53 BE1 USB_HSIC_V1P2_G3_V18 +V3.3A +V1P8A +V3.3S +V1P5S
U19 USB_V1P0_S3_U18 VSS_BE1_BE1 BE53
AN25 USB_V1P0_S3_U19 VSS_BE53_BE53 BG1
Y19 GPIO_V1P0_S3_AN25 VSS_BG1_BG1 BG53
USB3_V1P0_G3_Y19 VSS_BG53_BG53

1
+V1P0A C3 BH1 C44 C45 C46 C47 C48 C49
C5 USB3_V1P0_G3_C3 VSS_BH1_BH1 BH2 1UF/6.3V,X5R 0.1UF/10V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R
+V1P35S B6 UNCORE_V1P0_G3_C5 VSS_BH2_BH2 BH52 C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA

2
BA2 AC32 UNCORE_V1P0_G3_B6 VSS_BH52_BH52 BH53
180ohm/100MHZ C50 Y32 CORE_V1P0_S3_AC32 VSS_BH53_BH53 BJ2
FB0603 1UF/6.3V,X5R U36 CORE_V1P0_S3_Y32 VSS_BJ2_BJ2 BJ3
2 1 C0402_BGA AA25 UNCORE_V1P35_S0IX_F4_U36 VSS_BJ3_BJ3 BJ5
1 2 AG32 UNCORE_V1P35_S0IX_F5_AA25 VSS_BJ5_BJ5 BJ49
V36 UNCORE_V1P35_S0IX_F2_AG32 VSS_BJ49_BJ49 BJ51
2 1 BD1 UNCORE_V1P35_S0IX_F3_V36 VSS_BJ51_BJ51 BJ52 +V1P8S
AF19 VGA_V1P35_S3_F1_BD1 VSS_BJ52_BJ52 C1
UNCORE_V1P35_S0IX_F6 VSS_C1_C1
1

BA3 CA2 AG19 C53


+V1P35S 180ohm/100MHZ 10UF/6.3V,X5R AJ19 UNCORE_V1P35_S0IX_F1_AG19 VSS_C53_C53 E1 +V1P0S
ICLK_V1P35_S3_F1_AJ19 VSS_E1_E1

1
FB0603 C0603 E53 C51 C52 C53 C54 C55
BA4
2

VSS_E53_E53 F1 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R


2 1 AG18 RESERVED_F1 AK18 C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA

2
AN16 ICLK_V1P35_S3_F2 PCIE_V1P0_S3_AK18 AM18
VSSA_AN16 PCIE_V1P0_S3_AM18
1

CA3 C56 C57 U16 8 OF 13


180ohm/100MHZ 10uF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R USB_VSSA_U16
FB0603 C0603 C0402_BGA C0402_BGA VLV_M_D/BGA
2

REV = 1.15 ?

B B

+V1P0S +V1P0A
1

1
C58 C59 C60 C61 C62 C63 C64 C66 C67 C68 C69 C70 C71 C203 C201 C199
0.01UF/25V,X7R 1UF/6.3V,X5R 0.1UF/10V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 0.01UF/25V,X7R 1UF/6.3V,X5R 1UF/6.3V,X5R
C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA
2

2
+V1P0S +V1P8S
1

1
C72 C73 C74 C75 C76 C77 C78 C79 C80 C81
1UF/6.3V,X5R 1UF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 0.01UF/25V,X7R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R
C0402_BGA C0402_BGA c0805 c0805 c0805 C0402_BGA C0402_BGA C0402_BGA C0402_BGA C0402_BGA
2

+V1P05S
+V1P35S
1

Vinafix.com
C82 C83
1

C84 C85 1UF/6.3V,X5R 1UF/6.3V,X5R


1UF/6.3V,X5R 1UF/6.3V,X5R C0402_BGA C0402_BGA
2

C0402_BGA C0402_BGA
2

A A

Bitland Information Technology Co.,Ltd.


Page Name

Size Project Name Rev


A2 <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 13 of 42
PROPERTY NOTE: this document contains information confidential and property to

https://vinafix.com
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
5 4 3 2 1

D D

? ? ? ? ?
VLV_M_D VLV_M_D VLV_M_D VLV_M_D VLV_M_D
U1I U1J U1K U1L U1M

A11 AC36 AG38 AH47 AT24 AY36 BF30 E8 K9 U3


A15 VSS1 VSS36 AC38 AH4 VSS71 VSS106 AH48 AT27 VSS141 VSS176 AY4 BF36 VSS211 VSS246 F19 L13 VSS281 VSS316 U30
A19 VSS2 VSS37 AD19 AH41 VSS72 VSS107 AH50 AT30 VSS142 VSS177 AY50 BF4 VSS212 VSS247 F2 L19 VSS282 VSS317 U32
A23 VSS3 VSS38 AD21 AH45 VSS73 VSS108 AH51 AT35 VSS143 VSS178 AY9 BG31 VSS213 VSS248 F24 L27 VSS283 VSS318 U40
A27 VSS4 VSS39 AD25 AH7 VSS74 VSS109 AH6 AT38 VSS144 VSS179 BA14 BG34 VSS214 VSS249 F27 L35 VSS284 VSS319 U42
A31 VSS5 VSS40 AD32 AH9 VSS75 VSS110 AM44 AT4 VSS145 VSS180 BA19 BG39 VSS215 VSS250 F30 M19 VSS285 VSS320 U43
A35 VSS6 VSS41 AD33 AJ1 VSS76 VSS111 AM51 AT47 VSS146 VSS181 BA22 BG42 VSS216 VSS251 F35 M26 VSS286 VSS321 U45
A39 VSS7 VSS42 AD47 AJ16 VSS77 VSS112 AM7 AT52 VSS147 VSS182 BA27 BG45 VSS217 VSS252 F5 M27 VSS287 VSS322 U46
A43 VSS8 VSS43 AD7 AJ21 VSS78 VSS113 AN1 AU1 VSS148 VSS183 BA32 BG49 VSS218 VSS253 F7 M34 VSS288 VSS323 U48
A47 VSS9 VSS44 AE1 AJ25 VSS79 VSS114 AN11 AU24 VSS149 VSS184 BA35 BJ11 VSS219 VSS254 G10 M35 VSS289 VSS324 U49
AA1 VSS10 VSS45 AE11 AJ27 VSS80 VSS115 AN12 AU3 VSS150 VSS185 BA40 BJ15 VSS220 VSS255 G20 M38 VSS290 VSS325 U5
AA16 VSS11 VSS46 AE12 AJ29 VSS81 VSS116 AN14 AU30 VSS151 VSS186 BA53 BJ19 VSS221 VSS256 G22 M47 VSS291 VSS326 U51
C AA19 VSS12 VSS47 AE14 AJ3 VSS82 VSS117 AN22 AU38 VSS152 VSS187 BB19 BJ23 VSS222 VSS257 G26 M51 VSS292 VSS327 U53 C
AA21 VSS13 VSS48 AE3 AJ30 VSS83 VSS118 AN3 AU51 VSS153 VSS188 BB27 BJ27 VSS223 VSS258 G28 N1 VSS293 VSS328 U6
AA3 VSS14 VSS49 AE4 AJ32 VSS84 VSS119 AN33 AV12 VSS154 VSS189 BB35 BJ31 VSS224 VSS259 G32 N16 VSS294 VSS329 U8
AA32 VSS15 VSS50 AE40 AJ33 VSS85 VSS120 AN35 AV13 VSS155 VSS190 BC20 BJ35 VSS225 VSS260 G34 N38 VSS295 VSS330 U9
AA35 VSS16 VSS51 AE42 AJ35 VSS86 VSS121 AN36 AV14 VSS156 VSS191 BC22 BJ39 VSS226 VSS261 G42 N51 VSS296 VSS331 V12
AA38 VSS17 VSS52 AE43 AJ38 VSS87 VSS122 AN38 AV18 VSS157 VSS192 BC26 BJ43 VSS227 VSS262 H19 P13 VSS297 VSS332 V16
AA53 VSS18 VSS53 AE45 AJ53 VSS88 VSS123 AN40 AV19 VSS158 VSS193 BC28 BJ47 VSS228 VSS263 H27 P16 VSS298 VSS333 V19
AB10 VSS19 VSS54 AE46 AK10 VSS89 VSS124 AN42 AV24 VSS159 VSS194 BC32 BJ7 VSS229 VSS264 H35 P19 VSS299 VSS334 V21
AB4 VSS20 VSS55 AE48 AK14 VSS90 VSS125 AN43 AV27 VSS160 VSS195 BC34 C14 VSS230 VSS265 J1 P20 VSS300 VSS335 V35
AB41 VSS21 VSS56 AE50 AK16 VSS91 VSS126 AN45 AV30 VSS161 VSS196 BC42 C31 VSS231 VSS266 J16 P24 VSS301 VSS336 V40
AB45 VSS22 VSS57 AE51 AK33 VSS92 VSS127 AN46 AV35 VSS162 VSS197 BD19 C34 VSS232 VSS267 J19 P32 VSS302 VSS337 V44
AB47 VSS23 VSS58 AE53 AK41 VSS93 VSS128 AN48 AV38 VSS163 VSS198 BD24 C39 VSS233 VSS268 J22 P35 VSS303 VSS338 V51
AB48 VSS24 VSS59 AE6 AK44 VSS94 VSS129 AN49 AV47 VSS164 VSS199 BD27 C42 VSS234 VSS269 J27 P38 VSS304 VSS339 V7
AB50 VSS25 VSS60 AE8 AM12 VSS95 VSS130 AN5 AV51 VSS165 VSS200 BD30 C45 VSS235 VSS270 J32 P4 VSS305 VSS340 Y10
AB51 VSS26 VSS61 AE9 AM19 VSS96 VSS131 AN51 AV7 VSS166 VSS201 BD35 C49 VSS236 VSS271 J35 P47 VSS306 VSS341 Y14
AB6 VSS27 VSS62 AF10 AM24 VSS97 VSS132 AN53 AW13 VSS167 VSS202 BE19 D12 VSS237 VSS272 J40 P52 VSS307 VSS342 Y16
AC16 VSS28 VSS63 AF12 AM25 VSS98 VSS133 AN6 AW19 VSS168 VSS203 BE2 D16 VSS238 VSS273 J53 P9 VSS308 VSS343 Y21
AC18 VSS29 VSS64 AF25 AM29 VSS99 VSS134 AN8 AW27 VSS169 VSS204 BE35 D24 VSS239 VSS274 K14 T40 VSS309 VSS344 Y25
AC19 VSS30 VSS65 AF32 AM33 VSS100 VSS135 AN9 AW3 VSS170 VSS205 BE8 D30 VSS240 VSS275 K22 U1 VSS310 VSS345 Y33
AC21 VSS31 VSS66 AF47 AM35 VSS101 VSS136 AP40 AW35 VSS171 VSS206 BF12 D36 VSS241 VSS276 K32 U11 VSS311 VSS346 Y41
AC25 VSS32 VSS67 AG16 AM36 VSS102 VSS137 AT12 AY10 VSS172 VSS207 BF16 D38 VSS242 VSS277 K36 U12 VSS312 VSS347 Y44
AC33 VSS33 VSS68 AG25 AM40 VSS103 VSS138 AT16 AY22 VSS173 VSS208 BF24 E19 VSS243 VSS278 K4 U14 VSS313 VSS348 Y7
AC35 VSS34 VSS69 AG36 M28 VSS104 VSS139 AT19 AY32 VSS174 VSS209 BF38 E35 VSS244 VSS279 K50 U21 VSS314 VSS349 Y9
VSS35 VSS70 VSS105 VSS140 VSS175 11 OF 13 VSS210 VSS245 12 OF 13 VSS280 VSS315 VSS350
9 OF 13 10 OF 13 13 OF 13
VLV_M_D/BGA VLV_M_D/BGA VLV_M_D/BGA VLV_M_D/BGA ? VLV_M_D/BGA ?
REV = 1.15 ? REV = 1.15 ? REV = 1.15 ? REV = 1.15 REV = 1.15

B B

A A

Bitland Information Technology Co.,Ltd.


Page Name

Size Project Name Rev


A3 <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 14 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

https://vinafix.com
5 4 3 2 1
5 4 3 2 1

+V_VDDQ_VR 7,12,16,35,36,39

+V_VDDQ_VTT 16,35

+V_VDDQ_VR
U5 +V_VDDQ_VR
U6
M_A_DQ2 E3 B2
M_A_DQ0 F7 DQL0 VDD D9 M_A_DQ19 E3 B2
M_A_DQ6 F2 DQL1 VDD G7 M_A_DQ17 F7 DQL0 VDD D9
M_A_DQ5 F8 DQL2 VDD K2 M_A_DQ23 F2 DQL1 VDD G7
M_A_DQ7 H3 DQL3 VDD K8 M_A_DQ16 F8 DQL2 VDD K2
M_A_DQ3 H8 DQL4 VDD N1 M_A_DQ18 H3 DQL3 VDD K8
M_A_DQ4 G2 DQL5 VDD N9 M_A_DQ21 H8 DQL4 VDD N1
M_A_DQ[63:0] 7 DQL6 VDD DQL5 VDD
M_A_DQ1 H7 R1 M_A_DQ22 G2 N9
DQL7 VDD R9 M_A_DQ20 H7 DQL6 VDD R1
M_A_DQS_P[7:0] 7 M_A_DQ13 D7 VDD DQL7 VDD R9
M_A_DQ11 C3 DQU0 A1 M_A_DQ29 D7 VDD
D M_A_DQS_N[7:0] 7 M_A_DQ9 C8 DQU1 VDDQ A8 M_A_DQ26 C3 DQU0 A1 D
M_A_DQ10 C2 DQU2 VDDQ C1 M_A_DQ28 C8 DQU1 VDDQ A8
M_A_DQ12 A7 DQU3 VDDQ C9 M_A_DQ31 C2 DQU2 VDDQ C1
M_A_DQ15 A2 DQU4 VDDQ D2 M_A_DQ25 A7 DQU3 VDDQ C9
M_A_DQ8 B8 DQU5 VDDQ E9 M_A_DQ30 A2 DQU4 VDDQ D2
M_A_DQ14 A3 DQU6 VDDQ F1 M_A_DQ24 B8 DQU5 VDDQ E9
DQU7 VDDQ H2 M_A_DQ27 A3 DQU6 VDDQ F1 +V_VDDQ_VTT
M_A_DQS_P0 F3 VDDQ H9 DQU7 VDDQ H2
7 M_A_DQS_P0 DQSL VDDQ VDDQ
M_A_DQS_N0 G3 M_A_DQS_P2 F3 H9
7 M_A_DQS_N0 DQSL 7 M_A_DQS_P2 DQSL VDDQ
M_A_DQS_N2 G3 R268 1 2 35.7_F R0402
7 M_A_DQS_N2 DQSL 7 M_A_A0
M_A_DQS_P1 C7 H1 +V_VREF_DQ_DIMM0 R392 1 2 35.7_F R0402
7 M_A_DQS_P1 DQSU VREFDQ +V_VREF_DQ_DIMM0 15 7 M_A_A1
M_A_DQS_N1 B7 M_A_DQS_P3 C7 H1 +V_VREF_DQ_DIMM0 R384 1 2 35.7_F R0402
7 M_A_DQS_N1 DQSU 7 M_A_DQS_P3 DQSU VREFDQ +V_VREF_DQ_DIMM0 15 7 M_A_A2
M8 +V_VREF_CA_DIMM0 M_A_DQS_N3 B7 R428 1 2 35.7_F R0402
VREFCA +V_VREF_CA_DIMM0 15 7 M_A_DQS_N3 DQSU 7 M_A_A3
M8 +V_VREF_CA_DIMM0 R386 1 2 35.7_F R0402
VREFCA +V_VREF_CA_DIMM0 15 7 M_A_A4
E7 L8 DQA_ZQ1 R249 1 2 35.7_F R0402
7 M_A_DM0 DML ZQ DQA_ZQ1 15 7 M_A_A5
D3 E7 L8 DQA_ZQ2 R433 1 2 35.7_F R0402
7 M_A_DM1 DNU 7 M_A_DM2 DML ZQ DQA_ZQ2 15 7 M_A_A6
J1 M_A_DIM0_ODT1 D3 R380 1 2 35.7_F R0402
NC0 M_A_DIM0_ODT1 7,15 7 M_A_DM3 DNU 7 M_A_A7
T2 J9 M_A_DIM0_CKE1 J1 M_A_DIM0_ODT1 R267 1 2 35.7_F R0402
7 DDR3_DRAMRST_R_N RESET NC1 M_A_DIM0_CKE1 7,15 NC0 7 M_A_A8
L1 M_A_DIM0_CS1_N DDR3_DRAMRST_R_N T2 J9 M_A_DIM0_CKE1 R430 1 2 35.7_F R0402
NC2 M_A_DIM0_CS1_N 7,15 RESET NC1 M_A_DIM0_CKE1 7,15 7 M_A_A9
M_A_DIM0_CK_DDR0_DP J7 L9 DQA_ZQ5 L1 M_A_DIM0_CS1_N R419 1 2 35.7_F R0402
7,15 M_A_DIM0_CK_DDR0_DP CK NC3 DQA_ZQ5 15 NC2 M_A_DIM0_CS1_N 7,15 7 M_A_A10
M_A_DIM0_CK_DDR0_DN K7 M7 M_A_A15 M_A_DIM0_CK_DDR0_DP J7 L9 DQA_ZQ6 R379 1 2 35.7_F R0402
7,15 M_A_DIM0_CK_DDR0_DN CK NC4 M_A_A15 7,15 7,15 M_A_DIM0_CK_DDR0_DP CK NC3 DQA_ZQ6 15 7 M_A_A11
M_A_DIM0_CK_DDR0_DN K7 M7 M_A_A15 R385 1 2 35.7_F R0402
7,15 M_A_DIM0_CK_DDR0_DN CK NC4 M_A_A15 7,15 7 M_A_A12
M_A_DIM0_CKE0 K9 R250 1 2 35.7_F R0402
7,15 M_A_DIM0_CKE0 CKE 7 M_A_A13
M_A_DIM0_CKE0 K9 R280 1 2 35.7_F R0402
7,15 M_A_DIM0_CKE0 CKE 7 M_A_A14
M_A_DIM0_CS0_N L2 R279 1 2 35.7_F R0402
7,15 M_A_DIM0_CS0_N CS 7,15 M_A_A15
M_A_DIM0_CS0_N L2
7,15 M_A_DIM0_CS0_N CS
M_A_CAS_N K3 R383 1 2 35.7_F R0402
7,15 M_A_CAS_N CAS 7,15 M_A_DIM0_CKE0
M_A_RAS_N J3 M_A_CAS_N K3 R378 1 2 35.7_F R0402
7,15 M_A_RAS_N RAS 7,15 M_A_CAS_N CAS 7,15 M_A_DIM0_CKE1
M_A_WE_N L3 A9 M_A_RAS_N J3
7,15 M_A_WE_N WE VSS 7,15 M_A_RAS_N RAS
B3 M_A_WE_N L3 A9 R388 1 2 35.7_F R0402
VSS 7,15 M_A_WE_N WE VSS 7,15 M_A_DIM0_CS0_N
E1 B3 R376 1 2 35.7_F R0402
7,15 M_A_A[14:0] VSS VSS 7,15 M_A_DIM0_CS1_N
M_A_A0 N3 G8 E1
A0 VSS 7,15 M_A_A[14:0] VSS
M_A_A1 P7 J2 M_A_A0 N3 G8 R390 1 2 35.7_F R0402
A1 VSS A0 VSS 7,15 M_A_RAS_N
M_A_A2 P3 J8 M_A_A1 P7 J2 R417 1 2 35.7_F R0402
A2 VSS A1 VSS 7,15 M_A_CAS_N
M_A_A3 N2 M1 M_A_A2 P3 J8 R391 1 2 35.7_F R0402
A3 VSS A2 VSS 7,15 M_A_WE_N
M_A_A4 P8 M9 M_A_A3 N2 M1
M_A_A5 P2 A4 VSS P1 M_A_A4 P8 A3 VSS M9 R418 1 2 35.7_F R0402
A5 VSS A4 VSS 7,15 M_A_BS0
M_A_A6 R8 P9 M_A_A5 P2 P1 R389 1 2 35.7_F R0402
A6 VSS A5 VSS 7,15 M_A_BS1
M_A_A7 R2 T1 M_A_A6 R8 P9 R427 1 2 35.7_F R0402
A7 VSS A6 VSS 7,15 M_A_BS2
M_A_A8 T8 T9 M_A_A7 R2 T1
M_A_A9 R3 A8 VSS M_A_A8 T8 A7 VSS T9
M_A_A10 L7 A9 B1 M_A_A9 R3 A8 VSS R401 1 2 240_F R0402
A10/AP VSSQ A9 15 DQA_ZQ1
M_A_A11 R7 B9 M_A_A10 L7 B1 R402 1 2 240_F R0402
A11 VSSQ A10/AP VSSQ 15 DQA_ZQ2
M_A_A12 N7 D1 M_A_A11 R7 B9 R403 1 2 240_F R0402
A12/BC* VSSQ A11 VSSQ 15 DQA_ZQ3
M_A_A13 T3 D8 M_A_A12 N7 D1 R404 1 2 240_F R0402
A13 VSSQ A12/BC* VSSQ 15 DQA_ZQ4
M_A_A14 T7 E2 M_A_A13 T3 D8 R406 1 2 240_F R0402
A14 VSSQ A13 VSSQ 15 DQA_ZQ5
E8 M_A_A14 T7 E2 R405 1 2 240_F R0402
VSSQ A14 VSSQ 15 DQA_ZQ6
M_A_BS0 M2 F9 E8 R407 1 2 240_F R0402
7,15 M_A_BS0 BA0 VSSQ VSSQ 15 DQA_ZQ7
M_A_BS1 N8 G1 M_A_BS0 M2 F9 R408 1 2 240_F R0402
7,15 M_A_BS1 BA1 VSSQ 7,15 M_A_BS0 BA0 VSSQ 15 DQA_ZQ8
M_A_BS2 M3 G9 M_A_BS1 N8 G1
C
7,15 M_A_BS2 BA2 VSSQ 7,15 M_A_BS1 BA1 VSSQ
M_A_BS2 M3 G9 C
7,15 M_A_BS2 BA2 VSSQ
M_A_DIM0_ODT0 K1
7,15 M_A_DIM0_ODT0 ODT +V_VDDQ_VTT
M_A_DIM0_ODT0 K1
ODT
NT5CB64M16DP-CF 7,15 M_A_DIM0_ODT0 R411 1 2 35.7_F R0402
NT5CB64M16DP-CF 7,15 M_A_DIM0_ODT1 R412 1 2 35.7_F R0402

+V_VDDQ_VTT
C270
0.1UF/10V,X5R
+V_VDDQ_VR C0402
U8 +V_VDDQ_VR R409 1 2 39_J R0402 1 2
7,15 M_A_DIM0_CK_DDR0_DP
U9

2
M_A_DQ36 E3 B2 C271
M_A_DQ37 F7 DQL0 VDD D9 M_A_DQ54 E3 B2 10PF/50V,NPO
M_A_DQ39 F2 DQL1 VDD G7 M_A_DQ51 F7 DQL0 VDD D9 C0402

1
M_A_DQ33 F8 DQL2 VDD K2 M_A_DQ55 F2 DQL1 VDD G7 R410 1 2 39_J R0402
DQL3 VDD DQL2 VDD 7,15 M_A_DIM0_CK_DDR0_DN
M_A_DQ34 H3 K8 M_A_DQ53 F8 K2
M_A_DQ32 H8 DQL4 VDD N1 M_A_DQ49 H3 DQL3 VDD K8
M_A_DQ38 G2 DQL5 VDD N9 M_A_DQ52 H8 DQL4 VDD N1
M_A_DQ35 H7 DQL6 VDD R1 M_A_DQ48 G2 DQL5 VDD N9
DQL7 VDD R9 M_A_DQ50 H7 DQL6 VDD R1
M_A_DQ40 D7 VDD DQL7 VDD R9 +V_VDDQ_VTT
M_A_DQ44 C3 DQU0 A1 M_A_DQ56 D7 VDD
M_A_DQ47 C8 DQU1 VDDQ A8 M_A_DQ63 C3 DQU0 A1
M_A_DQ43 C2 DQU2 VDDQ C1 M_A_DQ57 C8 DQU1 VDDQ A8
M_A_DQ41 A7 DQU3 VDDQ C9 M_A_DQ59 C2 DQU2 VDDQ C1
DQU4 VDDQ DQU3 VDDQ

1
M_A_DQ45 A2 D2 M_A_DQ60 A7 C9 C241 C242
M_A_DQ42 B8 DQU5 VDDQ E9 M_A_DQ62 A2 DQU4 VDDQ D2 10UF/6.3V,X5R 10UF/6.3V,X5R
M_A_DQ46 A3 DQU6 VDDQ F1 M_A_DQ61 B8 DQU5 VDDQ E9 C0603 C0603

2
DQU7 VDDQ H2 M_A_DQ58 A3 DQU6 VDDQ F1
VDDQ DQU7 VDDQ
ns
M_A_DQS_P4 F3 H9 H2
7 M_A_DQS_P4 DQSL VDDQ VDDQ
M_A_DQS_N4 G3 M_A_DQS_P6 F3 H9
7 M_A_DQS_N4 DQSL 7 M_A_DQS_P6 DQSL VDDQ
M_A_DQS_N6 G3
7 M_A_DQS_N6 DQSL
M_A_DQS_P5 C7 H1 +V_VREF_DQ_DIMM0
7 M_A_DQS_P5 DQSU VREFDQ +V_VREF_DQ_DIMM0 15
M_A_DQS_N5 B7 M_A_DQS_P7 C7 H1 +V_VREF_DQ_DIMM0
7 M_A_DQS_N5 DQSU 7 M_A_DQS_P7 DQSU VREFDQ +V_VREF_DQ_DIMM0 15
M8 +V_VREF_CA_DIMM0 M_A_DQS_N7 B7
VREFCA +V_VREF_CA_DIMM0 15 7 M_A_DQS_N7 DQSU

1
M8 +V_VREF_CA_DIMM0 C243 C244 C245 C246 C212 C247
E7 L8 DQA_ZQ3 VREFCA +V_VREF_CA_DIMM0 15
7 M_A_DM4 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
D3 DML ZQ DQA_ZQ3 15 E7 L8 DQA_ZQ4
7 M_A_DM5 7 M_A_DM6 C0402 C0402 C0402 C0402 C0402 C0402

2
DNU J1 M_A_DIM0_ODT1 D3 DML ZQ DQA_ZQ4 15
NC0 7 M_A_DM7 DNU
DDR3_DRAMRST_R_N T2 J9 M_A_DIM0_CKE1 J1 M_A_DIM0_ODT1
RESET NC1 L1 M_A_DIM0_CS1_N M_A_DIM0_CKE1 7,15 DDR3_DRAMRST_R_N T2 NC0 J9 M_A_DIM0_CKE1
M_A_DIM0_CK_DDR0_DP J7 NC2 L9 DQA_ZQ7 M_A_DIM0_CS1_N 7,15 RESET NC1 L1 M_A_DIM0_CS1_N M_A_DIM0_CKE1 7,15
7,15 M_A_DIM0_CK_DDR0_DP CK NC3 DQA_ZQ7 15 NC2 M_A_DIM0_CS1_N 7,15
M_A_DIM0_CK_DDR0_DN K7 M7 M_A_A15 M_A_DIM0_CK_DDR0_DP J7 L9 DQA_ZQ8
7,15 M_A_DIM0_CK_DDR0_DN CK NC4 M_A_A15 7,15 7,15 M_A_DIM0_CK_DDR0_DP CK NC3 DQA_ZQ8 15
M_A_DIM0_CK_DDR0_DN K7 M7 M_A_A15
7,15 M_A_DIM0_CK_DDR0_DN CK NC4 M_A_A15 7,15
M_A_DIM0_CKE0 K9
7,15 M_A_DIM0_CKE0 CKE
B
7,15 M_A_DIM0_CKE0
M_A_DIM0_CKE0 K9
CKE
Note: Place these Caps near to respective DIMM Pins B
M_A_DIM0_CS0_N L2
7,15 M_A_DIM0_CS0_N CS M_A_DIM0_CS0_N L2
7,15 M_A_DIM0_CS0_N CS 15 +V_VREF_DQ_DIMM0
M_A_CAS_N K3
7,15 M_A_CAS_N CAS
M_A_RAS_N J3 M_A_CAS_N K3
7,15 M_A_RAS_N RAS 7,15 M_A_CAS_N CAS

1
M_A_WE_N L3 A9 M_A_RAS_N J3 C255 C256 C258 C257
7,15 M_A_WE_N WE VSS 7,15 M_A_RAS_N RAS
B3 M_A_WE_N L3 A9 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
VSS 7,15 M_A_WE_N WE VSS
E1 B3 c0402 c0402 c0402 c0402
7,15 M_A_A[14:0]

2
M_A_A0 N3 VSS G8 VSS E1
A0 VSS 7,15 M_A_A[14:0] VSS
M_A_A1 P7 J2 M_A_A0 N3 G8
M_A_A2 P3 A1 VSS J8 M_A_A1 P7 A0 VSS J2
M_A_A3 N2 A2 VSS M1 M_A_A2 P3 A1 VSS J8
M_A_A4 P8 A3 VSS M9 M_A_A3 N2 A2 VSS M1
A4 VSS A3 VSS 15 +V_VREF_CA_DIMM0
M_A_A5 P2 P1 M_A_A4 P8 M9
M_A_A6 R8 A5 VSS P9 M_A_A5 P2 A4 VSS P1
A6 VSS A5 VSS

1
M_A_A7 R2 T1 M_A_A6 R8 P9 C259 C260 C262 C261
M_A_A8 T8 A7 VSS T9 M_A_A7 R2 A6 VSS T1 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
M_A_A9 R3 A8 VSS M_A_A8 T8 A7 VSS T9 c0402 c0402 c0402 c0402

2
M_A_A10 L7 A9 B1 M_A_A9 R3 A8 VSS
M_A_A11 R7 A10/AP VSSQ B9 M_A_A10 L7 A9 B1
M_A_A12 N7 A11 VSSQ D1 M_A_A11 R7 A10/AP VSSQ B9
M_A_A13 T3 A12/BC* VSSQ D8 M_A_A12 N7 A11 VSSQ D1
M_A_A14 T7 A13 VSSQ E2 M_A_A13 T3 A12/BC* VSSQ D8
A14 VSSQ E8 M_A_A14 T7 A13 VSSQ E2
M_A_BS0 M2 VSSQ F9 A14 VSSQ E8
7,15 M_A_BS0 BA0 VSSQ VSSQ +V_VDDQ_VR +V_VDDQ_VR
M_A_BS1 N8 G1 M_A_BS0 M2 F9
7,15 M_A_BS1 BA1 VSSQ 7,15 M_A_BS0 BA0 VSSQ
M_A_BS2 M3 G9 M_A_BS1 N8 G1
7,15 M_A_BS2 BA2 VSSQ 7,15 M_A_BS1 BA1 VSSQ
M_A_BS2 M3 G9
7,15 M_A_BS2 BA2 VSSQ

1
M_A_DIM0_ODT0 K1
ODT M_A_DIM0_ODT0 K1 R297 R299
ODT
4.7K_F 4.7K_F
NT5CB64M16DP-CF R0402 R0402
NT5CB64M16DP-CF

2
+V_VREF_DQ_DIMM0 +V_VREF_CA_DIMM0

1
R298 R300

1
4.7K_F C106 C217 4.7K_F C112 C248
R0402 0.1UF/10V,X5R 10UF/6.3V,X5R R0402 0.1UF/10V,X5R 10UF/6.3V,X5R
+V_VDDQ_VR c0402 C0603 c0402 C0603

Vinafix.com

2
ns ns

2
1

C213 C215 C216 C218 C229 C230 C231 C232


10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603
2

A A
change filter cap to 0.1uF
divider res change to 4.7K_F
add C217 C248
1

C233 C234 C235 C236 C237 C238 C239 C240


1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 Bitland Information Technology Co.,Ltd.
2

Page Name
Size Project Name Rev
D <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 15 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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5 4 3 2 1

+V_VDDQ_VR 7,12,15,35,36,39

+V_VDDQ_VTT 15,35

M_B_DQ[63:0] 8

+V_VDDQ_VR
U72 +V_VDDQ_VR
U73
M_B_DQ20 E3 B2
M_B_DQ19 F7 DQL0 VDD D9 M_B_DQ4 E3 B2
M_B_DQ21 F2 DQL1 VDD G7 M_B_DQ2 F7 DQL0 VDD D9
M_B_DQ23 F8 DQL2 VDD K2 M_B_DQ5 F2 DQL1 VDD G7
M_B_DQ16 H3 DQL3 VDD K8 M_B_DQ7 F8 DQL2 VDD K2
M_B_DQ22 H8 DQL4 VDD N1 M_B_DQ1 H3 DQL3 VDD K8
M_B_DQ18 G2 DQL5 VDD N9 M_B_DQ6 H8 DQL4 VDD N1
M_B_DQ17 H7 DQL6 VDD R1 M_B_DQ0 G2 DQL5 VDD N9
DQL7 VDD R9 M_B_DQ3 H7 DQL6 VDD R1
M_B_DQ11 D7 VDD DQL7 VDD R9
D M_B_DQ12 C3 DQU0 A1 M_B_DQ30 D7 VDD D
M_B_DQ10 C8 DQU1 VDDQ A8 M_B_DQ25 C3 DQU0 A1
M_B_DQ9 C2 DQU2 VDDQ C1 M_B_DQ31 C8 DQU1 VDDQ A8
M_B_DQ14 A7 DQU3 VDDQ C9 M_B_DQ29 C2 DQU2 VDDQ C1
M_B_DQ13 A2 DQU4 VDDQ D2 M_B_DQ26 A7 DQU3 VDDQ C9
M_B_DQ15 B8 DQU5 VDDQ E9 M_B_DQ28 A2 DQU4 VDDQ D2
M_B_DQ8 A3 DQU6 VDDQ F1 M_B_DQ27 B8 DQU5 VDDQ E9
DQU7 VDDQ H2 M_B_DQ24 A3 DQU6 VDDQ F1
F3 VDDQ H9 DQU7 VDDQ H2
8 M_B_DQS_P2 G3 DQSL VDDQ F3 VDDQ H9
8 M_B_DQS_N2 DQSL 8 M_B_DQS_P0 G3 DQSL VDDQ
C7 H1 8 M_B_DQS_N0 DQSL
8 M_B_DQS_P1 B7 DQSU VREFDQ +V_VREF_DQ_DIMM1 16 C7 H1
8 M_B_DQS_N1 DQSU M8 8 M_B_DQS_P3 B7 DQSU VREFDQ +V_VREF_DQ_DIMM1 16
VREFCA +V_VREF_CA_DIMM1 16 8 M_B_DQS_N3 DQSU M8
E7 L8 VREFCA +V_VREF_CA_DIMM1 16 +V_VDDQ_VTT
8 M_B_DM2 DML ZQ DQB_ZQ1 16
D3 E7 L8
8 M_B_DM1 DNU 8 M_B_DM0 DML ZQ DQB_ZQ2 16
J1 D3
NC0 M_B_ODT1 8,16 8 M_B_DM3 DNU
T2 J9 J1 R273 1 2 35.7_F R0402
8,16 DDR3_B_DRAMRST# RESET NC1 L1 M_B_CKE1 8,16 T2 NC0 J9 M_B_ODT1 8,16 8 M_B_A0 1 2
R394 35.7_F R0402
J7 NC2 L9 M_B_CS1_N 8,16 8,16 DDR3_B_DRAMRST# RESET NC1 L1 M_B_CKE1 8,16 8 M_B_A1 1 2
8,16 M_B_CK_DDR0 R399 35.7_F R0402
K7 CK NC3 M7 DQB_ZQ5 16 J7 NC2 L9 M_B_CS1_N 8,16 8 M_B_A2 1 2
8,16 M_B_CK_DDR#0 8,16 M_B_CK_DDR0 R431 35.7_F R0402
CK NC4 M_B_A15 8,16 K7 CK NC3 M7 DQB_ZQ6 16 8 M_B_A3 1 2
8,16 M_B_CK_DDR#0 R440 35.7_F R0402
K9 CK NC4 M_B_A15 8,16 8 M_B_A4 1 2
R261 35.7_F R0402
8,16 M_B_CKE0 CKE K9 8 M_B_A5 R438 1 2 35.7_F R0402
L2 8,16 M_B_CKE0 CKE 8 M_B_A6 R398 1 2 35.7_F R0402
8,16 M_B_CS0_N CS L2 8 M_B_A7 R271 1 2 35.7_F R0402
K3 8,16 M_B_CS0_N CS 8 M_B_A8 R437 1 2 35.7_F R0402
8,16 M_B_CAS_N J3 CAS K3 8 M_B_A9 R422 1 2 35.7_F R0402
8,16 M_B_RAS_N L3 RAS A9 8,16 M_B_CAS_N J3 CAS 8 M_B_A10 R396 1 2 35.7_F R0402
8,16 M_B_WE_N WE VSS B3 8,16 M_B_RAS_N L3 RAS A9 8 M_B_A11 R400 1 2 35.7_F R0402
VSS E1 8,16 M_B_WE_N WE VSS B3 8 M_B_A12 R263 1 2 35.7_F R0402
8,16 M_B_A[14:0] VSS VSS 8 M_B_A13
M_B_A0 N3 G8 E1 R283 1 2 35.7_F R0402
A0 VSS 8,16 M_B_A[14:0] VSS 8 M_B_A14
M_B_A1 P7 J2 M_B_A0 N3 G8 R282 1 2 35.7_F R0402
M_B_A2 P3 A1 VSS J8 M_B_A1 P7 A0 VSS J2 8,16 M_B_A15
M_B_A3 N2 A2 VSS M1 M_B_A2 P3 A1 VSS J8 R397 1 2 35.7_F R0402
M_B_A4 P8 A3 VSS M9 M_B_A3 N2 A2 VSS M1 8,16 M_B_CKE0 R381 1 2 35.7_F R0402
M_B_A5 P2 A4 VSS P1 M_B_A4 P8 A3 VSS M9 8,16 M_B_CKE1
M_B_A6 R8 A5 VSS P9 M_B_A5 P2 A4 VSS P1 R441 1 2 35.7_F R0402
M_B_A7 R2 A6 VSS T1 M_B_A6 R8 A5 VSS P9 8,16 M_B_CS0_N R395 1 2 35.7_F R0402
M_B_A8 T8 A7 VSS T9 M_B_A7 R2 A6 VSS T1 8,16 M_B_CS1_N
M_B_A9 R3 A8 VSS M_B_A8 T8 A7 VSS T9 R443 1 2 35.7_F R0402
M_B_A10 L7 A9 B1 M_B_A9 R3 A8 VSS 8,16 M_B_RAS_N R420 1 2 35.7_F R0402
M_B_A11 R7 A10/AP VSSQ B9 M_B_A10 L7 A9 B1 8,16 M_B_CAS_N R444 1 2 35.7_F R0402
M_B_A12 N7 A11 VSSQ D1 M_B_A11 R7 A10/AP VSSQ B9 8,16 M_B_WE_N
M_B_A13 T3 A12/BC* VSSQ D8 M_B_A12 N7 A11 VSSQ D1 R421 1 2 35.7_F R0402
M_B_A14 T7 A13 VSSQ E2 M_B_A13 T3 A12/BC* VSSQ D8 8,16 M_B_BS0 R442 1 2 35.7_F R0402
A14 VSSQ E8 M_B_A14 T7 A13 VSSQ E2 8,16 M_B_BS1 R434 1 2 35.7_F R0402
M2 VSSQ F9 A14 VSSQ E8 8,16 M_B_BS2
8,16 M_B_BS0 N8 BA0 VSSQ G1 M2 VSSQ F9
C 8,16 M_B_BS1 M3 BA1 VSSQ G9 8,16 M_B_BS0 N8 BA0 VSSQ G1 R413 1 2 240_F R0402 C
8,16 M_B_BS2 BA2 VSSQ 8,16 M_B_BS1 M3 BA1 VSSQ G9 16 DQB_ZQ1 R414 1 2 240_F R0402
K1 8,16 M_B_BS2 BA2 VSSQ 16 DQB_ZQ2 R416 1 2 240_F R0402
8,16 M_B_ODT0 ODT K1 16 DQB_ZQ3 R415 1 2 240_F R0402
8,16 M_B_ODT0 ODT 16 DQB_ZQ4 R423 1 2 240_F R0402
NT5CB64M16DP-CF 16 DQB_ZQ5 R424 1 2 240_F R0402
NT5CB64M16DP-CF 16 DQB_ZQ6 R425 1 2 240_F R0402
16 DQB_ZQ7 R439 1 2 240_F R0402
16 DQB_ZQ8

+V_VDDQ_VTT

R455 1 2 35.7_F R0402


+V_VDDQ_VR 8,16 M_B_ODT0 R445 1 2 35.7_F R0402
U74 +V_VDDQ_VR 8,16 M_B_ODT1 +V_VDDQ_VTT
U75 C273
M_B_DQ43 E3 B2 0.1UF/10V,X5R
M_B_DQ44 F7 DQL0 VDD D9 M_B_DQ53 E3 B2 C0402
M_B_DQ47 F2 DQL1 VDD G7 M_B_DQ55 F7 DQL0 VDD D9 R457 1 2 39_J R0402 1 2
M_B_DQ45 F8 DQL2 VDD K2 M_B_DQ52 F2 DQL1 VDD G7 8,16 M_B_CK_DDR0
DQL3 VDD DQL2 VDD

2
M_B_DQ41 H3 K8 M_B_DQ50 F8 K2 C276
M_B_DQ46 H8 DQL4 VDD N1 M_B_DQ49 H3 DQL3 VDD K8 10PF/50V,NPO
M_B_DQ42 G2 DQL5 VDD N9 M_B_DQ54 H8 DQL4 VDD N1 C0402

1
M_B_DQ40 H7 DQL6 VDD R1 M_B_DQ48 G2 DQL5 VDD N9 R456 1 2 39_J R0402
DQL7 VDD R9 M_B_DQ51 H7 DQL6 VDD R1 8,16 M_B_CK_DDR#0
M_B_DQ35 D7 VDD DQL7 VDD R9
M_B_DQ36 C3 DQU0 A1 M_B_DQ62 D7 VDD
M_B_DQ34 C8 DQU1 VDDQ A8 M_B_DQ63 C3 DQU0 A1
M_B_DQ33 C2 DQU2 VDDQ C1 M_B_DQ59 C8 DQU1 VDDQ A8
M_B_DQ39 A7 DQU3 VDDQ C9 M_B_DQ56 C2 DQU2 VDDQ C1
M_B_DQ32 A2 DQU4 VDDQ D2 M_B_DQ58 A7 DQU3 VDDQ C9
M_B_DQ38 B8 DQU5 VDDQ E9 M_B_DQ60 A2 DQU4 VDDQ D2
M_B_DQ37 A3 DQU6 VDDQ F1 M_B_DQ57 B8 DQU5 VDDQ E9
DQU7 VDDQ H2 M_B_DQ61 A3 DQU6 VDDQ F1
F3 VDDQ H9 DQU7 VDDQ H2
8 M_B_DQS_P5 G3 DQSL VDDQ F3 VDDQ H9 +V_VDDQ_VTT
8 M_B_DQS_N5 DQSL 8 M_B_DQS_P6 G3 DQSL VDDQ
C7 H1 8 M_B_DQS_N6 DQSL
8 M_B_DQS_P4 B7 DQSU VREFDQ +V_VREF_DQ_DIMM1 16 C7 H1
8 M_B_DQS_N4 DQSU M8 8 M_B_DQS_P7 B7 DQSU VREFDQ +V_VREF_DQ_DIMM1 16
VREFCA +V_VREF_CA_DIMM1 16 DQSU

1
8 M_B_DQS_N7 M8 C265 C264
E7 L8 VREFCA +V_VREF_CA_DIMM1 16
8 M_B_DM5 10UF/6.3V,X5R 10UF/6.3V,X5R
D3 DML ZQ DQB_ZQ3 16 E7 L8
8 M_B_DM4 8 M_B_DM6 C0603 C0603

2
DNU J1 D3 DML ZQ DQB_ZQ4 16
NC0 M_B_ODT1 8,16 8 M_B_DM7 DNU
ns
T2 J9 J1
8,16 DDR3_B_DRAMRST# RESET NC1 L1 M_B_CKE1 8,16 T2 NC0 J9 M_B_ODT1 8,16
J7 NC2 L9 M_B_CS1_N 8,16 8,16 DDR3_B_DRAMRST# RESET NC1 L1 M_B_CKE1 8,16
8,16 M_B_CK_DDR0 CK NC3 DQB_ZQ7 16 NC2 M_B_CS1_N 8,16
K7 M7 J7 L9
8,16 M_B_CK_DDR#0 CK NC4 M_B_A15 8,16 8,16 M_B_CK_DDR0 CK NC3 DQB_ZQ8 16
K7 M7
B
8,16 M_B_CK_DDR#0 CK NC4 M_B_A15 8,16
K9 B
CKE

1
8,16 M_B_CKE0 K9 C266 C267 C277 C269 C219 C252
L2 8,16 M_B_CKE0 CKE 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
8,16 M_B_CS0_N CS L2 C0402 C0402 C0402 C0402 C0402 C0402

2
K3 8,16 M_B_CS0_N CS
8,16 M_B_CAS_N J3 CAS K3
8,16 M_B_RAS_N L3 RAS A9 8,16 M_B_CAS_N J3 CAS
8,16 M_B_WE_N WE VSS B3 8,16 M_B_RAS_N L3 RAS A9
VSS E1 8,16 M_B_WE_N WE VSS B3
8,16 M_B_A[14:0] VSS VSS
M_B_A0 N3 G8 E1
A0 VSS 8,16 M_B_A[14:0] VSS
M_B_A1 P7 J2 M_B_A0 N3 G8
M_B_A2 P3 A1 VSS J8 M_B_A1 P7 A0 VSS J2
M_B_A3 N2 A2 VSS M1 M_B_A2 P3 A1 VSS J8
M_B_A4 P8 A3 VSS M9 M_B_A3 N2 A2 VSS M1
A4 VSS A3 VSS
M_B_A5 P2
A5 VSS
P1 M_B_A4 P8
A4 VSS
M9 Note: Place these Caps near to respective DIMM Pins
M_B_A6 R8 P9 M_B_A5 P2 P1
M_B_A7 R2 A6 VSS T1 M_B_A6 R8 A5 VSS P9
A7 VSS A6 VSS 16 +V_VREF_DQ_DIMM1
M_B_A8 T8 T9 M_B_A7 R2 T1
M_B_A9 R3 A8 VSS M_B_A8 T8 A7 VSS T9
A9 A8 VSS

1
M_B_A10 L7 B1 M_B_A9 R3 C278 C282 C344 C345
M_B_A11 R7 A10/AP VSSQ B9 M_B_A10 L7 A9 B1 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
M_B_A12 N7 A11 VSSQ D1 M_B_A11 R7 A10/AP VSSQ B9 c0402 c0402 c0402 c0402

2
M_B_A13 T3 A12/BC* VSSQ D8 M_B_A12 N7 A11 VSSQ D1
M_B_A14 T7 A13 VSSQ E2 M_B_A13 T3 A12/BC* VSSQ D8
A14 VSSQ E8 M_B_A14 T7 A13 VSSQ E2
M2 VSSQ F9 A14 VSSQ E8
8,16 M_B_BS0 N8 BA0 VSSQ G1 M2 VSSQ F9
8,16 M_B_BS1 BA1 VSSQ 8,16 M_B_BS0 BA0 VSSQ 16 +V_VREF_CA_DIMM1
M3 G9 N8 G1
8,16 M_B_BS2 BA2 VSSQ 8,16 M_B_BS1 M3 BA1 VSSQ G9
BA2 VSSQ

1
K1 8,16 M_B_BS2 C346 C347 C348 C349
8,16 M_B_ODT0 ODT K1 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
8,16 M_B_ODT0 ODT c0402 c0402 c0402 c0402

2
NT5CB64M16DP-CF
NT5CB64M16DP-CF

+V_VDDQ_VR +V_VDDQ_VR

1
R301 R308
4.7K_F 4.7K_F
R0402 R0402
+V_VDDQ_VR

2
+V_VREF_DQ_DIMM1 +V_VREF_CA_DIMM1

A A
1

1
C956 C957 C958 C959 C960 C961 C962 C963
10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R 10UF/6.3V,X5R R304 R311

1
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 4.7K_F C114 C253 4.7K_F C116 C254
2

R0402 0.1UF/10V,X5R 10UF/6.3V,X5R R0402 0.1UF/10V,X5R 10UF/6.3V,X5R


c0402 C0603 c0402 C0603

2
ns ns

2
Bitland Information Technology Co.,Ltd.
Page Name
1

C964 C965 C966 C967 C968 C969 C970 C971 change filter cap to 0.1uF
1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R divider res change to 4.7K_F Size Project Name Rev
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 D
add C217 C248 <Doc>
2

Rev1.0
Date: Tuesday, March 04, 2014 Sheet 16 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

https://vinafix.com
5 4 3 2 1

D D

C C

B B

A A

Bitland Information Technology Co.,Ltd.


Page Name

Size Project Name Rev


A3 <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 17 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

https://vinafix.com
5 4 3 2 1
1 2 3 4 5 6 7 8

+ECVCC

+ECVCC 10,19,30,32,33

2
UR1
+V3.3A_RTC 10,13
100K_J
r0402
+V3.3S 6,7,13,19,20,21,22,23,25,28,30,35,36,39

1
ECRST#
+V1P8A 7,9,10,13,18,34,39
+V3.3A

1
C328
+V5S 19,20,24,26,29,39
1UF/6.3V,X5R
C0402
+V3.3A 7,11,13,23,25,28,30,33,34,35,36,37,39

1
+V1P8A 7,9,10,13,18,34,39
R538 R539
+V1P8S 6,9,10,11,13,21,24,39
2.2k_J 2.2k_J
r0402 r0402

2
+V3.3A_RTC

CLK_SMB R107 2 1 0_J R0402


DAT_SMB R167 2 1 0_J R0402 OZ8296_CLK 37
OZ8296_DAT 37

A A
+ECVCC R71 2 1 0.1UF/10V,X5R C0402
L1
2 1
+V1P8A +V1P8S

1
C88 C89 C90 C91 C92 C93 C94
10UF/6.3V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 120ohm/100MHZ C0402 +V1P8A +V1P8S
C0603 C0402 C0402 C0402 C0402 C0402 FB0603 0.1UF/10V,X5R

1
R497 1 2

+ECVCC_L
EC_AVCC
10K_J
R0402 +V3.3S R559 R566

1
U36 2.2k_J 2.2k_J
+V1P8S TXB0101 +V3.3S r0402 r0402

2
sot363 U10 R303 R549

1
1 6 C95 IT828E 2.2k_J 2.2k_J

114
121

127
VCCA VCCB 0.1UF/10V,X5R LQFP128_0D4_16X16 r0402 r0402

11
26
50
92

74

2
1

3
C306 2 5 C304 C0402

2
0.1UF/10V,X5R GND OE 0.1UF/10V,X5R 110 CLK_SMB_R R355 1 100_J 2 r0402 Q44

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5

VSTBY
VCC

VBAT

AVCC
CLK_SMB 22,32

5
SMCLK0/GPB3
C0402 9,18 ILB_SERIRQ
3 4 SERIRQ C0402 111 DAT_SMB_R R488 1 100_J 2 r0402
DAT_SMB 22,32 battery/Charge/VG Core LMBT3904DW1T1G
2

2
A B SMDAT0/GPB4 115 SOT363
SMCLK1/GPC1 PBAT_SMBCLK_R 19
SM BUS SMDAT1/GPC2
116
PBAT_SMBDAT_R 19 Thermal
117 10 SOC_EXTSMI_N
3 4 SMC_EXTSMI_N_R
PECI/SMCLK2/GPF6(3) +V1P5S_EN 36
118 PROCHOT_EC_N 11
SMDAT2/GPF7(3) 6 1 SMC_RUNTIME_SCI_N_R
11 SOC_RUNTIME_SCI_N
9,25 LPC_AD0
10
9 LAD0/GPM0(3) 85 1 pad
9,25 LPC_AD1 LAD1/GPM1(3) PS2CLK0/TMB0/CEC/GPF0 TP38
9,25 LPC_AD2
8 86
LAD2/GPM2(3) PS2DAT0/TMB1/GPF1 WLAN_EN 25
9,25 LPC_AD3 7 87 EC_BLT_OFF_N 23

2
22 LAD3/GPM3(3) PS2CLK1/DTR0#/GPF2 88 AC_PRESENT
7,25,28 PLT_RST# LPCRST#/GPD2 PS2DAT1/RTS0#/GPF3
change the option from bss138 to ns 0308 LPC_CLKOUT 13 89 CLK_TP

PS/2
LPCCLK/GPM4(3) PS2CLK2/GPF4 CLK_TP 18
9,25 LPC_FRAME_N
6
LFRAME#/GPM5(3) LPC PS2DAT2/GPF5
90 DAT_TP
DAT_TP 18 TPad
+V1P8S +V3.3S 20MIL TP31 1 17
+V1P8S LPCPD#/GPE6 24
PWM0/GPA0 POWER_LED# 30
20MIL TP32 1 126 25
SERIRQ 5 GA20/GPB5(3) PWM1/GPA1 28 1 TP55 20MIL Button_LED# 30 +V1P8A +V3.3A
1

SMC_EXTSMI_N_R 15 SERIRQ/GPM6(3) PWM2/GPA2 29


ECSMI#/GPD4(3) PWM3/GPA3 BEEP_EC 20
R578 SMC_RUNTIME_SCI_N_R 23 PWM 30
1

0_J R579 14 ECSCI#/GPD3 PWM4/GPA4 31


19 ECRST# CHARGE_LED# 30

1
r0402 2.2k_J 4 WRST# PWM5/GPA5 32 BATTERY_LED# 30

1
R307 r0402 16 KBRST#/GPB6(3) PWM6/SSCK/GPA6 34
2

2.2k_J 34 +V1P8A_EN PWUREQ#/BBO/SMCLK2ALT/GPC7(3) PWM7/RIG1#/GPA7 FAN1_PWM 19


ns R558 R568
r0402 2.2k_J 2.2k_J R550 R553
2

ns ns 39 DELAY_ALL_SYS_PWRGD
119 r0402 r0402 2.2k_J 2.2k_J

5 2

2
CRX0/GPC0 Q45
G

123 47 FAN1_TACH FAN1_TACH 19 r0402 r0402

2
2 3 SERIRQ CTX0/TMA0/GPB2(3) TACH0A/GPD6(3) 48 PM_PWRBTN_N LMBT3904DW1T1G
9,18 ILB_SERIRQ TACH1A/TMA1/GPD7(3)
D
S

106 SOT363
Q27 SPI_ROM_CLK_R 105 SSCE1#/GPG0(Up) 120
FSCK TMRI0/GPC4(3) ACIN_EC 32
BSS138-7 GPG6 104 124 SLP_S4_EC_N 10 PMU_SLP_S3_N
4 3 SLP_S3_EC_N
FDIO3/DSR0#/GPG6 TMRI1/GPC6(3)
SOT23-3 for emc 0303 SPI_ROM_SDI 103 FLASH

2
C351 SPI_ROM_SDO_R 102 FMISO 1 6 SLP_S4_EC_N
FMOSI 10 PMU_SLP_S4_N SLP_S4_EC_N 7
33pF/50V,X5R SPI_ROM_CS# 101
ns +V3.3A 1 c0402 100 FSCE# 125 PWRSW#_R
10 RSMRST_N SSCE0#/GPG2 PWRSW/GPE4(3) 18
RI1#/GPD0(3) BATT_PRS# 32
WAKE UP 21 RUN_ON 39
1

2
RI2#/GPD1

1
ns Please do not place any pull-up resistor 35 Novo_SW#_R C101
RTS1#/GPE5
B
SOT23-3 R576
on GPG0, GPG2, and GPG6 (Reserved RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7
112
BT_ON 25
0.1UF/10V,X5R for emc 0303 B
LMBT3904LT1G 2.2k_J C0402

2
Q87 r0402 hardware strapping).
2

2 3 ns SoC_to_EC_Win8P1_Q 109 1 TP52 20MIL +V1P8A +V1P8A


9 SoC_to_EC_Win8P1

IT8528
TXD/SOUT0/GPB1
UART RXD/SIN0/GPB0
108 1 TP53 20MIL
UART Port +ECVCC +V3.3A
KSI0 58
KSI1 59 KSI0/STB#
1

KSI2 60 KSI1/AFD#

1
KSI3 61 KSI2/INIT# 84 ALW_ON_R R92 1 2 2.2k_J R0402
ALW_ON 33
1

KSI4 62 KSI3/SLIN# EGCLK/GPE3 83 R169 R173


KSI4 EGCS#/GPE2 SUS_ON 35,39
R575 KSI5 63 82 47K_J 47K_J R305 R555 R560 R569
KSI5 EGAD/GPE1 BATT_OFF 32
2.2k_J KSI6 64 R0402 R0402 2.2k_J 2.2k_J 2.2k_J 2.2k_J
KSI7 65 KSI6 56 Caps_LED_R#
r0402 ns r0402 r0402 r0402 r0402

2
KSI7 KSO16/SMOSI/GPC3(3) 57
ns ns
2

2
KSO17/SMISO/GPC5(3) 33 Q49
EC_IMVP_VR_ON 37

5
GINT/CTS0#/GPD5 19 1 TP41 20MIL LMBT3904DW1T1G

1
+V1P8A KSO0 36 L80HLAT/BAO/GPE0 20 C296 LIDIN# SOT363
KSO0/PD0 L80LLAT/GPE7 LIDIN# 30
KSO1 37
KSO1/PD1 GPIO 0.1UF/10V,X5R
KSO2 38 107 c0402 3 4 AC_PRESENT
10 PMU_AC_PRESENT

2
KSO2/PD2 FDIO2/DTR1#/SBUSY/GPG1/ID7(Dn) +V1P0A_EN 34
KSO3 39
KSO3/PD3 for emc 0303
KSO4/PD4 KBMX
9 L_CLKOUT R110 1 2 12_F R0603 LPC_CLKOUT KSO4 40 10 PMU_PWRBTN_N 6 1 PM_PWRBTN_N
KSO5 41 99 add eDP_bklt_on signal 1102
KSO6 42 KSO5/PD5 HMOSI/GPH6/ID6 98 R815 1 0_J 2R0402 EC_OVERRIDE 11
DDI1_BKLT_EN 6,23
1

C107 KSO7 43 KSO6/PD6 HMISO/GPH5/ID5 97 1 TP36 20MIL


22PF/50V,NPO KSO8 44 KSO7/PD7 HSCK/GPH4/ID4 96 1 TP37 20MIL

2
C0402 KSO9 45 KSO8/ACK# HSCE#/GPH3/ID3 95 +V1P8A_PWRGD 34
2

ns KSO10 46 KSO9/BUSY CTX1/SOUT1/GPH2/SMDAT3/ID2 94 1 TP39 20MIL


KSO11 51 KSO10/PE CRX1/SIN1/SMCLK3/GPH1/ID1 93 PM_CKRUN_EC_N R101 1 2 0_J R0402
KSO11/ERR# CLKRUN#/GPH0/ID0 L_CLKRUN_N 9
KSO12 52
KSO13 53 KSO12/SLCT
KSO14 54 KSO13
+ECVCC KSO15 55 KSO14
KSO15 66 SLP_S3_EC_N
ADC0/GPI0(3) SLP_S3_EC_N 39
C552 1 2 1000PF/50V,X7R ns 67 ALL_SYS_PWRGD ALL_SYS_PWRGD 39
c0402 ADC1/GPI1(3) 68 SoC_to_EC_Win8P1_Q

Vinafix.com
ADC2/GPI2(3) 69
R577 1 330_J 2 r0402 ADC3/GPI3(3) 70
26 ADC4/GPI4(3) DDR3_DRAM_PWROK 7,35,39
Caps_LED_R# 32KXCLKI 128 71 GPI5 R113 1 2 0_J R0402 V1P0A_PWRGD 34
25 CK32K/GPJ6(3) ADC5/DCD1#/GPI5(3)
CK32KE/GPJ7(3) CLOCK
KSI0 20MIL TP15 1 2 72 BOARD ID
24 KSI1 ADC6/DSR1#/GPI6(3) 73 GPI7 R545 1 2 1K_J r0402
ADP_ID 32
2

23 KSI2 ADC7/CTS1#/GPI7(3)
22
21
KSI3 R108 A/D D/A
KSI4 0_J 76
20 TACH2/HDIO2/GPJ0(3) +V1P05S_EN 36
KSI5 R0402
77
19 HDIO3/GPJ1(3) HW_POP_MUTE_EC# 20
KSI6 78 V5A_V3P3A_VR_PWRGD 33
18 KSI7 DAC2/TACH0B/GPJ2(3) 79 1 TP50 20MIL
1

1
17 KSO15 VCORE DAC3/TACH1B/GPJ3(3) 80 1 TP40 20MIL C288 C279
16 DAC4/DCD0#/GPJ4(3)

AVSS
81
VSS1

VSS3
VSS4
VSS5
VSS6
VSS7
KSO14 0.1UF/10V,X5R 0.1UF/10V,X5R
15 DAC5/RIG0#/GPJ5(3) WWAN_EN 30
KSO13 c0402 c0402

2
14 KSO12
13 KSO11
1
VCORE_C 12
27
49
91
113
122

EC_AGND 75
12
11
KSO10
TP
10
KSO9 for emc 0303 +V3.3S
KSO8
9 KSO7 CLK_TP R309 2 1 10K_J r0402
8 KSO6 DAT_TP R310 2 1 10K_J r0402
7 KSO5
6 KSO4
28 5 KSO3
1

C 27 4 KSO2 C109 C
3 KSO1 0.1UF/10V,X5R
2 KSO0 C0402 +V5S
2

1
KBCON1
50565-02601-001

1
1011-01278 C384 C385
cns26_0d8_r_50565 0.1UF/10V,X5R 1uF/6.3V,X5R CN3
CONN FPC R/A 26Pin Pitch=0.8mm Black L26.6×W7.1×H1.9mm SMT RoHS c0402 c0402 88513-0641

2
+ECVCC ns cns6_1d0_r_88513
1011-00446
+ECVCC 6 8
CLK_TP R459 1 2 22_J R0402 5
18 CLK_TP

1
DAT_TP R461 1 2 22_J R0402 4
18 DAT_TP
PR5 LEFT# 3

1
4.7K_J RIGHT# 2
R0402 R166 1 7

1
4.7K_J C386 C387
R0402 100PF/50V,NPO 100PF/50V,NPO

2
C0402 C0402

2
Novo_SW#_R R485 1K_J r0402
Novo_SW# 30

2
PWRSW#_R R825 1K_J r0402 PWRSW# PWRSW# 30

1
VRA3

2
ns C305 AZ5725-01F
1

C214 r0402 0.1UF/10V,X5R


AZ5725-01F r0402
0.1UF/10V,X5R c0402

1
c0402 VRA4 ns
2

2
TLSW6 TLSW5
+ECVCC +ECVCC 3.3V 5% TSKB-1PHF TSKB-1PHF
1 3 sw_1bt002 1 R274 1 2 1K_J r0402 RIGHT# 3 sw_1bt002 1 R238 1 2 1K_J r0402 LEFT#
R386 100K 5% 1012-00119 1012-00119
2

+ECVCC

1
R114 4 2 4 2

1
L2 1 2 120ohm/100MHZ FB0603 EC_AVCC 8.2K_J smdfix2 smdfix1 smdfix2 smdfix1
C357 VR23
Board ID R387 V min V typ V max Phase

1
R0402 C358 VR21 100PF/50V,NPO ESD9B5V-2

5
ns 100PF/50V,NPO ESD9B5V-2 c0402 WBFBP-02C

2
c0402 WBFBP-02C ns
0 0 0V 0V 0V REV1.0
1

2
1

C110 C111 BOARD ID ns


0.1UF/10V,X5R 1000PF/50V,X7R
1

C0402 C0402
1 8.2K 5% 0.216V 0.250V 0.289V REV1.1
2

R119
L3 1 2 120ohm/100MHZ FB0603 EC_AGND 100K_J
R0402
2 18K 5% 0.436V 0.503V 0.538V REV1.2
2

3 33K 5% 0.712V 0.819V 0.875V REV1.3


+ECVCC
U11 GPG6 R335 1 2 100k_J r0402 ns
W25X80AVSS1G CO-LAY
SOP8_1D27_8 +ECVCC +ECVCC GPI5 R458 1 2 100k_J r0402
SPI_ROM_CS# 1 8
SPI_ROM_SDI_R 2 CE# VDD 7 HOLD# GPI7 R462 1 2 100k_J r0402

1
+ECVCC SPI_ROM_WP# 3 SO/IO1 HOLD#/IO3 6 SPI_ROM_CLK
4 WP#/IO2 SCK 5 SPI_ROM_SDO R158
Lenovo Adapter ID Communication

1
GND SIO/IO0 C206 4.7K_J

1
D R460 1 2 100k_J D
ns C0402 R0402 SUS_ON r0402
R112 0.1UF/10V,X5R ALW_ON R432 1 2 100k_J r0402

2
1K_J
Non

2
R0402 R115 U13
AC adapter connection Reserved 170W 135W 90W 65W 45W Reserved 22_J SPI_ROM_CS# 1 8
SPI_ROM_SDI1 R0402 2SPI_ROM_SDI_R 2 CS# VCC 7HOLD#
2

SPI_ROM_WP# 3 DO/IO1 HOLD#/IO3 6SPI_ROM_CLK R116 1 0_J 2 R0402 SPI_ROM_CLK_R


4 WP#/IO2 CLK 5SPI_ROM_SDO R117 1 22_J 2 R0402 SPI_ROM_SDO_R
ID pin resistor
1

GND DI/IO0
Open 4640 1910 1000 549 287 118 0(short) R118 W25X512Kbit
(ohm,1%)

1
1K_J sop8_1d27_6d0 C115
R0402 ns C0402
EC detection ns
<=3.056 <=2.590 <=2.109 <=1.618 <=1.134 <=0.663 10PF/50V,NPO
SPI ROM

2
voltage >3.093 <=0.207
2

@3.3 VREF >2.626 >2.149 >1.663 >1.172 >0.693 >0.234


Bitland Information Technology Co.,Ltd.
Indication by Non support Non support 170W 135W 90W 65W 45W Non support Page Name
power manager AC message AC message adapter adapter adapter adapter adapter AC message
Size Project Name Rev
A1 <Doc> Rev1.0
Date: Tuesday, April 01, 2014 Sheet 18 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

1 2 3 4 5 6 7 8

https://vinafix.com
A B C D E

+ECVCC 10,18,30,32,33
+V3.3S 6,7,13,18,20,21,22,23,25,28,30,35,36,39
+V5S 18,20,24,26,29,39

+ECVCC

4 4

1
C771
0.1UF/10V,X5R +ECVCC

2
C0402

2
R804 R805
ADM1032ARMZ 0X4C
4.7K_J 4.7K_J
R0402 R0402 EMC1412-1-ACZL 1001-100xb
U58
C772

1
EMC1412-1-ACZL-TR
msop8_0d65_5d0 1 2
PBAT_SMBCLK_R 8 1 2200PF/50V,X7R
18 PBAT_SMBCLK_R SCLK VDD

3
C0402 Place to hotest area
PBAT_SMBDAT_R 7 2 1 Q79
18 PBAT_SMBDAT_R SDATA D+ LMBT3904LT1G
6 3 SOT23-3

2
ALERT D-
5 4
GND THERM HW_OT# 33
3 3
R809 1 2 ECRST# 18
0_J R0402
ns

2
External Thermal Sensor(required for sun)

2
R807
4.7K_J R806
R0402 4.7K_J
R0402

1
+ECVCC

change power from +3.3s to +ECVCC


10-8

Vinafix.com
2 2
+V3.3S

1
R465
10K_J

FAN Conn
r0402 FAN_CN1
50208-00401-001
2

18 FAN1_TACH Cns4_0d8_r_50208
1011-01397
+V5S 1 5
18 FAN1_PWM
2
3
4 6

OK
1

C379 C380 C381 C382


0.1UF/10V,X5R 4.7uF/6.3V,X5R 1000PF/50V,X7R 0.1UF/10V,X5R Bitland Information Technology Co.,Ltd.
c0402 c0603 c0402 c0402
2

ns Page Name
1 1
Size Project Name Rev
A4 <Doc> Rev1.0
Date: Tuesday, April 01, 2014 Sheet 19 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

https://vinafix.com
A B C D E
5 4 3 2 1

AVDD should place near the IC +V5S 18,19,24,26,29,39


+V5A 27,29,30,33,34,35,36,37,39
+V1P5S 13,36,39
+V3.3S 6,7,13,18,19,21,22,23,25,28,30,35,36,39
DIGITAL
ANALOG
BA9 120ohm/100MHZ
+5VA +V5S
l0603

1
1
CA56 D5

1
D 10uF/6.3V,X5R AZ5125-01H CA57 C43 C127 C100 C130 D
C0603 SOD-523 10uF/6.3V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R

2
ns ns C0603 C0402 C0402 C0402 C0402

2
2
Add C43,C127,C100,C130 for EMC 1211
1011-00537--> 1011-01790 Follow melon 1122
MIC-VREFO LINE1-R FRH5D28-8R2N 1.6A INTSPK1
50271-00401-001
30 HPOUT-L HPOUT-L LINE1-L cns4_1d25_r_85204
SPK-R+ INT_SPK_R+_CN 1 5
30 HPOUT-R HPOUT-R SPK-R- INT_SPK_R-_CN 2
+5VA
SPK-L+ INT_SPK_L+_CN 3
SPK-L- INT_SPK_L-_CN 4 6

2
CA49 CA46
CA50
2.2UF/6.3V,X5R
C0402
0.1UF/10V,X5R
c0402
4.7uF/6.3V,X5R Demodulation Filter
c0603
Placement near

1
2 1
CA51
2.2UF/6.3V,X5R Audio Codec
C0402
2 1 SPK L+ L- R+ R- trace width
Speaker 4 ohm ==> 40 mils

1
CA47 CA48 CA66 CA68 CA69 CA64
2.2UF/6.3V,X5R 0.1UF/10V,X5R Speaker 8 ohm ==> 20 mils 1000PF/50V,X7R 1000PF/50V,X7R 1000PF/50V,X7R 1000PF/50V,X7R
C0402 c0402 c0402 c0402 c0402 c0402

36

35

34

33

32

31

30

29

28

27

26

25

2
C C

CBP

CPVEE

AVSS2

HP-OUT-L

MIC1-VREFO

LINE1-L

AVDD1

AVSS1
CBN

HP-OUT-R

LINE1-R

VREF
+5VA
2

CA75 CA53
4.7uF/6.3V,X5R 0.1UF/10V,X5R
c0603 c0402 37 24 MIC1-VREFO
1

MONO-OUT NC4
Change to 1000pf stuff For EMC 0115
38 23 MIC1-VREFO
AVDD2 LINE1-VREFO

1
39 22 R690 2 1 20K_F R0402 R159
LINE2-L JDREF
2.2k_J
40 21 CA63 2 1 10uF/6.3V,X5RC0603 R130 R0402
LINE2-R LDO-CAP
Close to Pin 41 c0603
FB37 120ohm/100MHZ 2A 41 20 MIC1-R LINE1-R CA74 1 2 4.7uF/6.3V,X5R 1 ns 1K_J2 R0402 FB15 1 2 120ohm/100MHZ
+V5S

2
PVDD1 MIC1-R

2
l0603 FB0603
1

1
CA55 CA54 SPK-L+ 42 UA2 19 MIC1-L R102 C188 C187
10uF/6.3V,X5R 0.1UF/10V,X5R SPK-L+ MIC1-L 100PF/50V,NPO 100PF/50V,NPO
C0603 c0402 SPK-L- 43 ALC280-GR 18 LINE1-L CA73 1 2 4.7uF/6.3V,X5R c0603
22K_J
r0402 C0402 C0402
2

2
SPK-L- mqfn48_0d4_6x6 NC3

1
SPK-R- 44 17

teknisi indonesia
SPK-R- NC2
SPK-R+ 45 16
SPK-R+ NC1
46 15
GPIO1/DMIC-DATA12

PVDD2 AUX_CLK_In
1

CA58 Conn to Pin7 Vendor suggestion 1128


0.1UF/10V,X5R Combo_Jack 47 14
靠近音效芯片放置
PIO0/DMIC-CLK

GPIO2/DMIC-DATA34 Sense B
GPIO3/SPDIFO

c0402 Combo_Jack R467 1 2 22K_J r0402 MIC1_JACK


2

PD# 48 13 RA19 1 2 39.2K_F r0402 HPOUT-JD MIC1_JACK 30


SDATA-OUT

EAPD+PD# Sense A HPOUT-JD 30


SDATA-IN
DVDD-IO

PCBEEP

1
RESET#
BIT-CLK

49 CA60
GPIO4

THRM_PAD
DVDD

SYNC
ANALOG 10uF/6.3V,X5R

1
C190 C0603

2
100PF/50V,NPO
B C0402 B
1

10

11

12

2
DIGITAL Moat
1

+V1P5S CA44 1 2 0.1UF/10V,X5R c0402 RA15 2 1 10K_J r0402


SPKR_R 9
DVDD1

CA45 1 2 0.1UF/10V,X5R c0402 RA17 2 1 10K_J r0402


BEEP_EC 18
TP21
1

1
CA43
1

CA70 20MIL 100PF/50V,NPO RA16 RA34 MIC-VREFO RA5 2 0_J 1 r0402 RA6 1 2.2k_J 2 R0402
0.1UF/10V,X5R c0402 4.7K_J 4.7K_J
2

c0402 r0402 r0402


2

MIC1-R CA10 1 2 2.2UF/6.3V,X5R C0402 ns RA7 2 1K_J 1 R0402 INT_MIC


INT_MIC 30

2
+V3.3S
HDA_RST_N 11 MIC1-L CA11 1 2 2.2UF/6.3V,X5R C0402
RA39 1 2 0_J r0603 DVDD1 R0402 33_J 2 1 R595 HDA_SYNC 11
HDA_SDIN 11
CA72 HDA_SDOUT 11
HDA_BIT_CK 11
2

1uF/6.3V,X5R CA71 CA59


c0402 0.1UF/10V,X5R 22PF/50V,NPO
c0402 C0402
1

+V3.3S
1

A RA38 A
10K_J
r0402 R111 2 1 0_J R0402
Bitland Information Technology Co.,Ltd.
2

R148 2 1 0_J R0402 PD# Page Name


18 HW_POP_MUTE_EC#
Size Project Name Rev
Custom <Doc> Rev1.0
Date: Friday, April 25, 2014 Sheet 20 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

https://vinafix.com
5 4 3 2 1

+V1P8S 6,9,10,11,13,18,24,39
+V3.3S 6,7,13,18,19,20,22,23,25,28,30,35,36,39

U52B
D eMMC-SDIN7DU2-16G D

R1 A4
+V1P8S +V3.3S R2 NC_R1 NC_A4 A6
R3 NC_R2 NC_A6 A9
R5 NC_R3 NC_A9 A11
R751 1 R0603 2 0_J R12 NC_R5 NC_A11 B2
U52A EMMC R13 NC_R12 NC_B2 B13
eMMC-SDIN7DU2-16G R752 1 R0603 2 0_J R14 NC_R13 NC_B13 D1
ns NC_R14 NC_D1
Add R13,R14,R16,R17,R43,R55,R67,R73,C15 for EMC 121 C713 T1 D14
T2 NC_T1 NC_D14 H1
0.1uF/10V,X5R C714
T3 NC_T2 NC_H1 H2 FLASH_D4_IC
C0402 10uF/6.3V,X5R
1 R13 2 R0402 0_JFLASH_D0_IC H3 AA5 EMMC T5 NC_T3 NC_H2 A10走线走不出来,所以删掉一个pin
11 FLASH_D0 DAT0 VCCQ2 C0603 NC_T5
11 FLASH_D1
1 R14 2 R0402 0_JFLASH_D1_IC H4 AA3 T12 H7 FLASH_D7_IC
1 R16 2 R0402 0_JFLASH_D2_IC H5 DAT1 VCCQ1 Y4 T13 NC_T12 NC_H7 H8
11 FLASH_D2 DAT2 VCCQ5 +V3.3S NC_T13 NC_H8
11 FLASH_D3
1 R17 2 R0402 0_JFLASH_D3_IC J2 W4 EMMC T14 H9
1 R43 2 R0402 0_JFLASH_D4_IC J3 DAT3 VCCQ4 K6 U1 NC_T14 NC_H9 H10
11 FLASH_D4 DAT4 VCCQ3 NC_U1 NC_H10
11 FLASH_D5 1 R55 2 R0402 0_JFLASH_D5_IC J4 U2 H11
1 R67 2 R0402 0_JFLASH_D6_IC J5 DAT5 U9 R753 1 R0603 2 0_J U3 NC_U2 NC_H11 H12
11 FLASH_D6 DAT6 VCC4 NC_U3 NC_H12
11 FLASH_D7 1 R73 2 R0402 0_JFLASH_D7_IC J6 T10 U6 H13
DAT7 VCC3 N5 U7 NC_U6 NC_H13 H14
VCC2 C715 C716 EMMC NC_U7 NC_H14
11 FLASH_CMD FLASH_CMD W5 M6 0.1uF/10V,X5R 10uF/6.3V,X5R U10 J1 FLASH_D3_IC
CMD VCC1 C0402 U12 NC_U10 NC_J1 J7
C0603 NC_U12 NC_J7
11 FLASH_CLK FLASH_CLK W6 U8 EMMC EMMC U13 J8
CLK VSS4 R10 U14 NC_U13 NC_J8 J9
1 R76 R0402 2 0_JFLASH_RESET_IC U5 VSS3 P5 V1 NC_U14 NC_J9 J10
11 FLASH_RESET RESET VSS2 NC_V1 NC_J10
M7 V2 J11
C717 K2 VSS1 V3 NC_V2 NC_J11 J12
VDDI NC_V3 NC_J12
2

C15 0.1uF/10V,X5R AA6 V12 J13


C 10PF/50V,NPO C0402 VSSQ2 AA4 V13 NC_V12 NC_J13 J14 C
C0402 EMMC VSSQ1 Y5 V14 NC_V13 NC_J14 K1 U9_K2
1

ns Add R76 vendor suggestion 1214 VSSQ5 Y2 W1 NC_V14 NC_K1 K3


VSSQ4 K4 W2 NC_W1 NC_K3 K5 FLASH_D5_IC
U9_K2 VSSQ3 W3 NC_W2 NC_K5 K7
W7 NC_W3 NC_K7 K8
bga169_0d5_14x14 W8 NC_W7 NC_K8 K9
W9 NC_W8 NC_K9 K10
1010-01979 NC_W9 NC_K10
EMMC W10 K11
W11 NC_W10 NC_K11 K12
W12 NC_W11 NC_K12 K13
W13 NC_W12 NC_K13 K14
W14 NC_W13 NC_K14 L1
Y1 NC_W14 NC_L1 L2
Y3 NC_Y1 NC_L2 L3
Y6 NC_Y3 NC_L3 L4
Y7 NC_Y6 NC_L4 L12
Y8 NC_Y7 NC_L12 L13
Y9 NC_Y8 NC_L13 L14
Y10 NC_Y9 NC_L14 M1
Y11 NC_Y10 NC_M1 M2
+V1P8S Y12 NC_Y11 NC_M2 M3
Y13 NC_Y12 NC_M3 M5
Y14 NC_Y13 NC_M5 M8
RP1 10K_J ra8_0402 AA1 NC_Y14 NC_M8 M9
1 2 FLASH_D1_IC AA2 NC_AA1 NC_M9 M10
3 4 FLASH_D0_IC AA7 NC_AA2 NC_M10 M12
5 6 FLASH_D4_IC AA8 NC_AA7 NC_M12 M13
7 8 FLASH_D3_IC AA9 NC_AA8 NC_M13 M14
B AA10 NC_AA9 NC_M14 N1 B
ns NC_AA10 NC_N1
RP2 10K_J ra8_0402 AA11 N2
1 2 FLASH_D7_IC AA12 NC_AA11 NC_N2 N3
3 4 FLASH_D6_IC AA13 NC_AA12 NC_N3 N10
5 6 FLASH_D2_IC AA14 NC_AA13 NC_N10 N12
7 8 FLASH_D5_IC AE1 NC_AA14 NC_N12 N13
AE14 NC_AE1 NC_N13 N14
ns NC_AE14 NC_N14
R754 10K_J ns FLASH_CMD AG2 P1
R0402 AG13 NC_AG2 NC_P1 P2
AH4 NC_AG13 NC_P2 P3
AH6 NC_AH4 NC_P3 P10
R755 10K_J ns FLASH_CLK NC_AH6 NC_P10
R0402 AH9 P12
AH11 NC_AH9 NC_P12 P13
NC_AH11 NC_P13 P14
NC_P14

bga169_0d5_14x14
EMMC

COPY from A10

A A

Vinafix.com Page Name


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A3 <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 21 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

https://vinafix.com
5 4 3 2 1
5 4 3 2 1

VDDIO

VDDIO
1

1
PR56 PR57
+V3.3S 6,7,13,18,19,20,21,23,25,28,30,35,36,39
10K_J 10K_J
+V5S 18,19,20,24,26,29,39 r0402 r0402
LVDS LVDS

PD1#
2

RST# 2
D D

1
C41 C42
1UF/6.3V,X5R
C0402 2.2uF/6.3V,X5R

2
LVDS C0402
VDDIO LVDS

1
C251
0.1UF/10V,X5R
C207 1 2 0.1UF/10V,X5R C0402 LVDS DAUXn C0402

2
6,23 EDP_AUX_DN
C185 1 2 0.1UF/10V,X5R C0402 LVDS DAUXp LVDS
6,23 EDP_AUX_DP

TCK0n
TC0n
TC0p
TA0n
TA0p
TB0n
TB0p
C183 1 2 0.1UF/10V,X5R C0402 LVDS DRX0p

46
45
44
43
42
41
40
39
38
6,23 EDP_TX0_DP
C184 1 2 0.1UF/10V,X5R C0402 LVDS DRX0n
6,23 EDP_TX0_DN To connector TA0n LVDS_DATA0-

NC2
TA0n
TA0p
TB0n
TB0p
VDDIO1
TC0n
TC0p
TCK0n
eDP_TXN1_C 23
TA0p eDP_TXP1_C 23 LVDS_DATA0+

1 37 TCK0p
DAUXn 2 NC0 TCK0p 36 PWMI TB0n LVDS_DATA1-
DAUXn PWMI eDP_TXN2_C 23
DAUXp 3 U7 35 TB0p LVDS_DATA1+
DAUXp TD0n eDP_TXP2_C 23
4 34
DRX0p 5 GND0 PS8622 TD0p 33
DRX0n 6 DRX0p qfn46_0d4_4d5x6d5 NC1 32 VDDIO

1
VDDRX 7 DRX0n LVDS VDDIO0_1 31 ENPVCC/I2C_ADDR C205 TC0n LVDS_DATA2-
VDDRX ENPVCC/I2C_ADDR ENPVCC/I2C_ADDR 23 eDP_TXN3_C 23
RST# 8 30 PWMO 0.1UF/10V,X5R TC0p LVDS_DATA2+
RST# PWMO eDP_TXP3_C 23
PD1# 9 29 ENBLT C0402

2
1

2
R207 1 2 0_J R0402 R208 1 1K_J 2 R0402 HPD C200 C196 HPD 10 PD# ENBLT 28 VDD12
6 EDP_HPD_Q
LVDS LVDS HPD VDD12 LVDS
0.1UF/10V,X5R 0.01UF/25V,X7R I2C_CFG 11 27 DDC_SDA 0_J

2
C0402 VDDIOX 12 I2C_CFG DDC_SDA 26 DDC_SCL TCK0n R582 1 2 r0402 LVDS LVDS_CLK-
c0402 eDP_TXN0_C 23

1
R209 LVDS VDDIOX 13 VDDIOX0 DDC_SCL 25 TCK0p R583 1 0_J 2 r0402 LVDS LVDS_CLK+
LVDS VDDIOX1 GND1 eDP_TXP0_C 23

1
CSDA/MSDA
100K_J SW_OUT 14 24 RLV_AMP C209 C250

CSCL/MSCL
TESTMODE
C R0402 SW_OUT BLV_AMP 0.1UF/10V,X5R C

RLV_CFG
RLV_SSC
0.01UF/25V,X7R

VDD12_0

1
LVDS c0402 C0402

2
GPIO0
GNDX

REXT
47 R484 LVDS LVDS 1 2

1
EPAD 4 3
4.99K_F
R0402 L4_0805
LVDS

15
16
17
18
19
20
21
22
23
CH3

2
6,23 DDI1_BKLT_CTRL R212 1 2 0_J R0402 PWMI [email protected]
2 ns
LVDS

RLV_CFG
RLV_SSC
R214 ENBLT BL_EN 23 BKLT_ON

VDD12
100K_J PWMO 23 BKLT_PWM

1 REXT
PWM_OUT

GND
R0402
ns

CIICSDA
CIICSCL
1

R474
4.99K_F
R0402
LVDS

2
2

1
C202 C204
0.01UF/25V,X7R 0.1UF/10V,X5R
c0402 C0402

2
LVDS
LVDS

+V3.3S +V3.3S +V3.3S +V3.3S


2

2
+V3.3S
R5948 R5949 R219 R220
4.7K_J 4.7K_J 4.7K_J 4.7K_J
R0402 R0402 R0402 R0402
5

LVDS LVDS L9 LVDS LVDS RN11


2.2uH_3.3X3.0X1.5 0_J
G

1
3 4 CIICSDA L_2p_3x3 RA4_0402
18,32 DAT_SMB
1004-00504 DDC_SCL 3 4 EDID_SCL
D

eDP_AUXP_C 23
2

LVDS SW_OUT 1 2 VDD12 FB6 1 2 FB0603 VDDRX DDC_SDA 1 2 eDP_AUXN_C EDID_SDA


23
From EC Q8A 80ohm/100MHZ
G

6
L2N7002DW1T1G 1 CIICSCL
18,32 CLK_SMB

1
B SOT363 C191 C192 B
D

LVDS 4.7uF/6.3V,X5R 1UF/6.3V,X5R


Q8B c0603 C0402

2
L2N7002DW1T1G LVDS LVDS
SOT363
Vendor suggestion 0.1uf to 1uf 0116 VDDIO

2
R476
4.7K_J
VDDIO VDDIO VDDIO +V3.3S R0402 Change to stuff 0122

1
FB9 1 2 FB0603 VDDIOX ENPVCC/I2C_ADDR
2

80ohm/100MHZ
R224 R225 R317 FB8 1 2 FB0603 VDDIO
4.7K_J 4.7K_J 4.7K_J 80ohm/100MHZ
R0402 R0402 R0402 Vendor suggestion 0116

1
LVDS ns 2 C197 C198

1
C193 C195 4.7uF/6.3V,X5R 0.1UF/10V,X5R
1

I2C_CFG 4.7uF/6.3V,X5R 0.1UF/10V,X5R c0603 C0402

2
c0603 C0402 LVDS LVDS
1

2
RLV_SSC LVDS LVDS

RLV_CFG

1. Entire trace of Panel VCC should be wider than 80-mil


2

R230 R231 R318


4.7K_J 4.7K_J 4.7K_J
R0402 R0402 R0402
LVDS ns ns
1

A A

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Custom <Doc> Rev1.0
Date: Saturday, August 16, 2014 Sheet 22 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

https://vinafix.com
5 4 3 2 1

+V3.3S 6,7,13,18,19,20,21,22,25,28,30,35,36,39

+VDC 32,33,34,35,37,39

+V5A 27,29,30,33,34,35,36,37,39

+V3.3A 7,11,13,18,25,28,30,33,34,35,36,37,39

+ECVCC 10,18,19,30,32,33

+V5S 18,19,20,24,26,29,39

eDP_VDD
+VDC
V_LED
Colay
D 500mA FB5 1 2 FB0603
80ohm/100MHZ
500mA D

1 2 V_AUX +V3.3S

1
R171 0_J R0603
ns
C154
1UF/25V,X5R
C155
33PF/50V,NPO
C156
0.1uF/25V,X7R
LVDS_CN1
88242-3001 EDID R172 1 0_J 2 R0402 LVDS
C0603 C0402 c0603 cns30_1_lcd

2
C157 C159
1 2 eDP_VDD 0.1UF/10V,X5R 4.7uF/6.3V,X5R
1 2 C0402 c0603

1
3 4 LVDS LVDS
3 4
5 6
5 6 +V3.3S
6,22 EDP_TX0_DN C164 1 2 0.1UF/10V,X5R C0402 EDP 1 2 eDP_TXN0_C 7 8
AUX Channel LVDS_CLK- 3 4 7 8

6,22 EDP_TX0_DP C161 1 2 0.1UF/10V,X5R C0402 EDP eDP_TXP0_C 9 10 R581 1 2 0_J r0402
LVDS_CLK+ RA4_0402 9 10

2
+V3.3S 0_J 11 12 BKLT_PWM C536
RN10 11 12
eDP_TXN1_C 13 14 TP 0.1UF/10V,X5R
c0402

1
2 LVDS_DATA0- 13 14
R174 LVDS_DATA0+ eDP_TXP1_C 15 16 USB_TP_HN
100K_F 15 16
R0402 17 18 USB_TP_HP
Touch panel
RN1 17 18
ns LVDS_DATA1-
0_J LVDS_DATA1+ eDP_TXP2_C 19 20 BKLT_ON
1

RA4_0402 19 20
C165 1 2 0.1UF/10V,X5R C0402 EDP 3 4 eDP_AUXN_C eDP_TXN2_C 21 22 eDP_AUXP_C USB_TP_HN 1 2 USB_TP_HN4 29
6,22 EDP_AUX_DN 21 22
C166 1 2 0.1UF/10V,X5R C0402 EDP 1 2 eDP_AUXP_C USB_TP_HP 3 4 USB_TP_HP4 29
6,22 EDP_AUX_DP
LVDS_DATA2- 23 24 eDP_AUXN_C
23 24 RA4_0402
EDP LVDS_DATA2+
2

eDP_TXN3_C 25 26 RN2
R176 +V3.3A_camera 25 26 0_J
100K_F +V3.3A eDP_TXP3_C 27 28 CAM_DATA-
27 28 ns
R0402 0_J
ns R200 0_J R0603
20mils 29 30 CAM_DATA+
Camera RN9
CRB v1.0 unstuff 29 30 RA4_0402

32
31
1

3 4 USB_SOC_PN 9

1
C177 1011-00495 1 2 USB_SOC_PP 9

32
31
2
C178 0.1UF/10V,X5R
4.7uF/6.3V,X5R c0402

2
C c0603 C

1
Backlight control

+V3.3S
2

R182
10K_J eDP_TXP0_C 22
From EC R0402 LVDS_CLK+
eDP_TXN0_C 22
18 EC_BLT_OFF_N 2 LVDS_CLK-
eDP_TXP1_C 22
1

From SOC 3 BKLT_ON LVDS_DATA0+


eDP_TXN1_C 22
6,18 DDI1_BKLT_EN R185 1 2 0_J R0402 eDP D10 LVDS_DATA0-
1

1 LBAT54ALT1G C168 eDP_TXP2_C 22


From IC SOT23-3 100PF/50V,NPO LVDS_DATA1+
eDP_TXN2_C 22

Vinafix.com
22 BL_EN R211 1 2 0_J R0402 LVDS C0402 LVDS_DATA1-
2

ns eDP_TXP3_C 22
1

eDP_TXN3_C 22 LVDS_DATA2+
R186 LVDS_DATA2-
100K_J
R0402 BKLT_ON
+V3.3S BKLT_PWM
eDP_AUXP_C 22
eDP_AUXN_C 22 EDID_SCL
2

EDID_SDA
2

R187
1K_J LVDS EDP colay
R0402
ns
From SOC +V3.3S eDP_VDD
1

6,22 DDI1_BKLT_CTRL R188 1 2 0_J R0402 eDP BKLT_PWM


500mA 500mA
2

2 3 R192 1 2 0_J R0805

D
1

R191 C169 Q13


10K_J 100PF/50V,NPO LP2301LT1G

1 G
1

1
From IC R0402 C0402 C170 SOT23-3 +V3.3A C182 C179 C180
2

2
22 PWM_OUT R213 1 2 0_J R0402 LVDS eDP ns 1UF/6.3V,X5R C171 4.7uF/6.3V,X5R 0.1UF/10V,X5R 33PF/50V,NPO
B C0402 +V3.3A 0.1UF/10V,X5R R193 c0603 C0402 C0402 B
1

2
2
C0402 62_J

2
R195 R0402
R196 2 1 100K_J R194 2 1 10K_J 100K_J ns
R0402 R0402 R0402

1
ns

1
3

6
3
D D
D Q6
L2N7002LT1G 5 G G 2
R201 2 1 1K_J EDP 1 SOT23-3 S S
6 EDP_VDD_EN_R
R0402 G S Q14A Q14B

1
2
L2N7002DW1T1G L2N7002DW1T1G

2
R202 SOT363 SOT363
22 ENPVCC/I2C_ADDR R203 2 1 1K_J LVDS 100K_J ns ns
R0402 R0402

1
0_J
RN3
RA4_0402
3 4
1 2

L4_0805
CAM_DATA+ 4 3 USB_CAM_PP 9
CAM_DATA- 1 2 USB_CAM_PN 9 Camera
A CH2 A
[email protected]
ns

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A2 <Doc> Rev1.0
Date: Saturday, August 16, 2014 Sheet 23 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other

https://vinafix.com
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

HDMI RECEPTABLE A

TYPE A
+V1P8S 6,9,10,11,13,18,21,39
JTMDS_D2+ 1
+V5S 18,19,20,26,29,39 D2+
2
GND
JTMDS_D2- 3
JTMDS_D1+ 4 D2- 20
D1+
5
GND
D JTMDS_D1- 6 21 D
D1-
JTMDS_D0+ 7
D0+
8
GND
JTMDS_D0- 9
JTMDS_TXC+ 10 D0-
11 CK+
GND
JTMDS_TXC- 12
CK-
HDMI_CEC 13
CEC
R121 1 2 0_J R0402 14 22
RSD
DDC3CLK 15
L4 HDMI_+5VRUN DDC3DATA 16 SCL 23
SDA
L4_0805 17
GND
[email protected] ns 18
+5V
6 DDI0_LANE0_DP C124 1 2 0.1UF/10V,X5R C0402 TMDS_D2+ 1 2 JTMDS_D2+ HDMI_DET_HPD 19
HPD
6 DDI0_LANE0_DN C117 1 2 0.1UF/10V,X5R C0402 TMDS_D2- 4 3 JTMDS_D2-

2
C147 C211

2
470PF/50V,X7R 0.1UF/10V,X5R C14 C11 R145
R122 1 2 0_J R0402 C0402 c0402 10PF/50V,NPO 10PF/50V,NPO 100K_J

2
C0402 C0402 R0402 HDMI_CN1

1
R123 1 2 0_J R0402 ns ns ABA-HDM-022-K01
hdmi_099a7ac19nbxcnf

1
L5
L4_0805 AddC147 C211For EMC 0115
90ohm/100M,0.4A ns
C118 1 2 0.1UF/10V,X5R C0402 TMDS_D1+ 1 2 JTMDS_D1+ ns ns

0.1UF/10V,X5R

0.1UF/10V,X5R
6 DDI0_LANE1_DP

1
1 2 0.1UF/10V,X5R 4 3

C1011

c0402

C1012

c0402
6 DDI0_LANE1_DN C119 C0402 TMDS_D1- JTMDS_D1-

Q46

2
R124 1 2 0_J R0402 +V5S LP2301LT1G
SOT23-3 HDMI_+5VRUN
R125 1 2 0_J R0402
3 2 F2 1 2 16V/0.35A FUSE_1206 ns

S
L6
90ohm/100M,0.4A Add C14,C11,C1011,C1012 for EMC 1211 R302 0_J r0603

G
1

1
L4_0805

1
6 DDI0_LANE2_DP C120 1 2 0.1UF/10V,X5R C0402 TMDS_D0+ 1 2 ns JTMDS_D0+ R598 R599 C592
6 DDI0_LANE2_DN C121 1 2 0.1UF/10V,X5R C0402 TMDS_D0- 4 3 JTMDS_D0- 4.7K_J 4.7K_J 0.1UF/10V,X5R
r0402 r0402 C0402

2
3
2

2
R128 1 2 0_J R0402 1 Q47
LMBT3904LT1G

1
C sot23-3 C

2
R133 1 2 0_J R0402
R600
L7 2.2k_J
L4_0805 r0402

2
90ohm/100M,0.4A ns R0402
6 DDI0_LANE3_DP C122 1 2 0.1UF/10V,X5R C0402 TMDS_TXC+ 1 2 JTMDS_TXC+
6 DDI0_LANE3_DN C123 1 2 0.1UF/10V,X5R C0402 TMDS_TXC- 4 3 JTMDS_TXC-

R131 1 2 0_J R134 1 2 619_F r0402 TMDS_D2+


R135 1 2 619_F r0402 TMDS_D2-

R136 1 2 619_F r0402 TMDS_D0+


R137 1 2 619_F r0402 TMDS_D0-

R138 1 2 619_F r0402 TMDS_D1+


R139 1 2 619_F r0402 TMDS_D1-

R140 1 2 619_F r0402 TMDS_TXC+


R141 1 2 619_F r0402 TMDS_TXC-

3
Q3 D
L2N7002LT1G
sot23-3 1 R165 1 2 0_J R0402 +V5S
S G

1
2
R146
100K_J
R0402
ns +V1P8S

2
HDMI_+5VRUN R319
+V1P8S 10K_J
R0402
1

1
B R295 R296 B
6 DDI0_HPD_Q
2.2k_J 2.2k_J LD2

3
Q90A R0402 R0402 HDMI_DET_HPD SOT23_6 DDC3CLK
LBSS138DW1T1G AZC199-04S D
5

1
Q90B sot363 C593
2

6
G

LBSS138DW1T1G 0.1UF/10V,X5R 1 HDMI_DET_HPD


2

sot363 4 3 DDC3DATA C0402 S G


6 DDI0_CTRL_DATA

2
G

Q2

2
6 DDI0_CTRL_CK 1 6 DDC3CLK L2N7002LT1G
S

sot23-3

EMC add C593 0627

1
HDMI_CEC DDC3DATA

D7 D8 HDMI
ESDA6V8UD ESDA6V8UD
DFN10_0D5_2D5X1D0 DFN10_0D5_2D5X1D0

JTMDS_D2- 5 6 JTMDS_D2- JTMDS_D0- 1 10 JTMDS_D0-

JTMDS_D2+ 4 7 JTMDS_D2+ JTMDS_D0+ 2 9 JTMDS_D0+

3 3

JTMDS_D1- 2 9 JTMDS_D1- JTMDS_TXC- 4 7 JTMDS_TXC-

A A
JTMDS_D1+ 1 10 JTMDS_D1+ JTMDS_TXC+ 5 6 JTMDS_TXC+

Bitland Information Technology Co.,Ltd.


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A2 <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 24 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other

https://vinafix.com
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

+V3.3A 7,11,13,18,23,28,30,33,34,35,36,37,39

+V3.3S 6,7,13,18,19,20,21,22,23,28,30,35,36,39

+V1P8A 7,9,10,13,18,34,39

3.3V is available during the system’s stand-by/suspend state to


support wake event processing on the communications card.
D
+V3.3A WLAN_+3_3V D
LPC_AD2 R822 1 2 0_J R0402 LPC_AD2_DG +V3.3S
9,18 LPC_AD2
ns place near Pin2 Pin72
1 R74 2 0_J
LPC_AD1 R830 1 2 0_J R0402 LPC_AD1_DG r0805
9,18 LPC_AD1
ns

1
1 R75 2 0_J C303 C287 C290 C289 C294 C291
LPC_AD0 R832 1 2 0_J R0402 LPC_AD0_DG r0805ns 10UF/6.3V,X5R 0.1UF/10V,X5R 10UF/6.3V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R
10UF/6.3V,X5R
9,18 LPC_AD0
ns C0603 c0402 C0603 c0402 c0402 C0603

2
R834 1
LPC_FRAME_N 2 0_J R0402 LPC_FRAME_N_DG
9,18 LPC_FRAME_N
ns
LPC_AD3 R836 1 2 0_J R0402 LPC_AD3_DG
9,18 LPC_AD3
ns
WLAN_+3_3V

CN28
NGFF SlotA-SD KeyE
PLACE near signal devided ngff_conn_213eaaa32fa
10-15
change to X211 NGFF_CONN footprint follow E10 1127
NGFF SlotA-SD
75
74 GND1 73 LPC_FRAME_N_DG
72 3.3Vaux3 RESERVED1 71 LPC_AD3_DG
LPC_AD2_DG 70 3.3Vaux2 RESERVED2 69
LPC_AD1_DG 68 RESERVED3 GND2 67
RESERVED4 Reserved6/PERn1 L_CLKOUT1 9
C LPC_AD0_DG 66 65 R908 1 2 WLAN_+3_3V
C
64 RESERVED5 Reserved7/PERp1 63
NFC Reset# (MGPIO7)/RESERVED GND3
ns 10K_J R0402
62 61 R909 1 2 WLAN_+3_3V
60 NFC I2C IRQ (MGPIO5)/ALERT Reserved8/PETn1 59
NFC I2C SM CLK/I2C CLK Reserved9/PETp1
ns 10K_J R0402
58 57
56 NFC I2C SM DATA/I2C DATA GND4 55 R846 1 2 R0402 0_J ns
18 WLAN_EN W_DISABLE#1(WIFI) PEWake0# PCIE_WAKE_R_N 10,28
18 BT_ON R426 1 1K_J 2 R0402 BT_DIABLE 54 53 R840 1 2 R0402 ns
Reserved/W_DISABLE#2(BT) CLKRQ0# PCIE_R_CLKREQ1_N 11
7,18,28 PLT_RST# PLT_RST# R454 2 0_J 1 R0402 PCIE_RST#_S 52 51 0_J
50 PERST0# GND5 49 CLK_PCIE_MINI_N
SUSCLK REFCLKN0 PCIE_REFCLK0_DN 10
48 47 CLK_PCIE_MINI_P
COEX1 REFCLKP0 PCIE_REFCLK0_DP 10
46 45
COEX2 GND6
44
COEX3 PERn0
43
MINI_RXN1 11 pcie_RXN
42
CLINK_CLK/RESERVED PERp0
41
MINI_RXP1 11 pcie_RXP
40 39
38 CLINK_DATA/RESERVED GND7 37
CLINK_RST/RESERVED PETn0 MINI_TXN1 11
36
UART RTS PETp0
35
MINI_TXP1 11 pcie_TXN
34
UART CTS GND8
33 pcie_TXP
32
UART Tx Tonny 0625
WIFI

teknisi indonesia KEY E


23
22 SDIO_RST 21
20 UART Rx SDIOWAKE 19
18 UART Wake SDIODAT3 17
16 GND9 SDIODAT2 15
14 LED#2 SDIODAT1 13
12 PCM_OUT SDIODAT0 11
B 10 PCM_IN SDIOCMD 9 B
8 PCM_SYNC SDIOCLK 7
6 PCM_CLK GND10 5 USB_BT_N 0_J Colay
4 LED#1 USB_D- 3 USB_BT_P RN8
2 3.3Vaux1 USB_D+ 1 RA4_0402
3.3Vaux0 GND11 USB_BT_N 3 4
GND12

GND13

USB_BT_PN 29
USB_BT_P 1 2 USB_BT_PP 29

P0

P1
CH4
76

77

78

79
3 4
2 1

L4_0805
90ohm/100M,0.4A
ns

A A

Bitland Information Technology Co.,Ltd.


Page Name

Size Project Name Rev


A3 <Doc> Rev1.0
Date: Tuesday, April 01, 2014 Sheet 25 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

https://vinafix.com
5 4 3 2 1
5 4 3 2 1

D D

SATA_B1 SATA_B2
M2*4mm M2*4mm
1101-00096 1101-00096
+V5S 18,19,20,24,29,39

SATA HDD CONN


HDD_CN1
S1
C1044 1 2 0.01UF/25V,X7R c0402 SATA_TXP0_C S2 GND1
11 SATA_TXP0 RX+
C1045 1 2 0.01UF/25V,X7R c0402 SATA_TXN0_C S3
11 SATA_TXN0 RX-
S4
C1046 1 2 0.01UF/25V,X7R c0402 SATA_RXN0_C S5 GND2
11 SATA_RXN0 C1047 1 2 0.01UF/25V,X7R c0402 SATA_RXP0_C S6 TX-
11 SATA_RXP0 S7 TX+
GND3
P1
C 3.3V_1 C
P2
+V5S P3 3.3V_2
P4 3.3V_3
P5 GND4
GND5
1.5A
P6
RA40 1 2 0_J r0603 P7 GND6
P8 5V_1
P9 5V_2
P10 5V_3
GND7
1

1
C1048 C1049 C1050 C1051 P11 G1
10uF/6.3V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 33PF/50V,NPO P12 Reserved GND9 G2
C0603 c0402 c0402 c0402 P13 GND8 GND10
2

2
P14 12V_1
R922 P15 12V_2
12V_3
0_J
r0402 LD2122F-S8EL6H
sata_saf-01n1bb-41-55
ns 1011-01276

OK

B B

A
Bitland Information Technology Co.,Ltd. A
Page Name

Size Project Name Rev


B <Doc> Rev1.0
Date: Thursday, April 10, 2014 Sheet 26 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

https://vinafix.com

Vinafix.com
5 4 3 2 1

+V5A 29,30,33,34,35,36,37,39

USB5V

1
CHK1

1
D [email protected] C220 + PC1 C221 C222 C225 C249 CE4 D
L4_0805 0.1UF/10V,X5R 100uF/6.3V 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R + 220uF/6.3V
4 3 c0402 tc3528 c0805 c0805 c0805 c0805 cap6d3x6d6

2
1 2
colayns ns ns ns ns

2
R241 0_J R0402 ns
9 USB3_RX0_N R242 0_J R0402
9 USB3_RX0_P ns

2
CHK2 SSRX0- USB30_CN1 C1038
[email protected] SSRX0+ PUBAU1-09FNLS1NN4H2 1000pF/2KV,X7R
L4_0805 usb_pubau1-09flbscnn4h0 c1206

1
4 3 5 ns
1 2 4 RX-
6 PGND 13
R244 0_J R0402 USBD8P 3 RX+ GND4 12
9 USB_PP0 ns D+ GND3
9 USB_PN0 R243 0_J R0402 ns 7 11
USBD8N 2 GND GND2 10
SSTX0- 8 D- GND1
C223 2 1 0.1UF/10V,X5R c0402 R245 0_J R0402 1 TX-
9 USB3_TX0_N ns Vbus
9 USB3_TX0_P C224 2 1 0.1UF/10V,X5R c0402 R246 0_J R0402 ns SSTX0+ 9
TX+
C C
CHK3
[email protected]
L4_0805
4 3
1 2

+V5A USB5V
D11
U21 ESDA6V8UD
1 8 DFN10_0D5_2D5X1D0
2 GND OUT_3 7
3 IN_1 OUT_2 6 SSTX0+ 1 10 SSTX0+
IN_2 OUT_1
2

4 5 USB3_OC_N 9
R247 EN(EN#) OC#
10K_J G547F2P81U
r0402 MSOP8_0D65_2D54 SSTX0- 2 9 SSTX0-
1

C226 C227 ns C594


1

B 0.1UF/10V,X5R 10uF/6.3V,X5R 0.1UF/10V,X5R B


c0402 C0603 C0402
2

2
2

3
R248
1

10K_J C228
r0402 0.1UF/10V,X5R
c0402 SSRX0+ 4 7SSRX0+
1

EMC add C594 0627

C228 NC->stuff SSRX0- 5 6SSRX0-

LD6 1006-00812
SOT23_6 Intel recommends each USB3.0 slot be
USBD8P AZC199-04S capable of supplying a minimum of 0.9 A
4

Bitland Information Technology Co.,Ltd.


Page Name
A A
Size Project Name Rev
A4 <Doc> Rev1.0
Date: Tuesday, April 01, 2014 Sheet 27 of 42
3

PROPERTY NOTE: this document contains information confidential and property to


USBD8N Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

https://vinafix.com
5 4 3 2 1
5 4 3 2 1

+V3.3A 7,11,13,18,23,25,30,33,34,35,36,37,39
1
+V3.3S 6,7,13,18,19,20,21,22,23,25,30,35,36,39 TP107 20MIL ictpad_c20
1
TP108 20MIL ictpad_c20
R910 1 2.49K_F 2 r0402RSET 1
TP109 20MIL ictpad_c20

VDD33

VDD10
XTAL2
XTAL1
Place close to VDD33_LAN PINS.
VDD33

R911 0_J r0603 60MIL U12


RTL8106EUL
+V3.3A
1010-02032

32
31
30
29
28
27
26
25
2

2
C1015 C1016 qfn32_0d4_4X4

2
C1014 0.1UF/10V,X5R 0.1UF/10V,X5R 33

LED1/GPO
AVDD33_2
RSET
AVDD10_4
CKXTAL2
CKXTAL1
LED0

LED2(LED1)
D GND1 D
C1032 C1013 0.1UF/10V,X5R c0402 c0402

1
4.7uF/6.3V,X5R 4.7uF/6.3V,X5R c0402
1

1
c0603 c0603 P11 P32
AVDD33_REG
MDI0+ 1 24 REGOUT
R912 0_J r0603 MDI0- 2 MDIP0 REGOUT(NC) 23 AVDD33_REG +V3.3S
VDD10 3 MDIN0 VDDREG(DVDD33) 22 VDD10
AVDD10_1 DVDD10_1(NC)

2
C1017 C1018 MDI1+ 4 21 PCIE_WAKE#
0.1UF/10V,X5R MDI1- 5 MDIP1 LANWAKEB 20 ISOLATEB R913 1 2 1K_J r0402
4.7uF/6.3V,X5R MDIN1 ISOLATEB
c0603 c0402 6 19 LAN_PLT_RST#

1
7 MDIP2(NC) PERSTB 18 R914 1 2 15K_J R0402
MDIN2(NC) HSON
P23 VDD10 8
AVDD10_3(NC) HSOP
17

L8
2.2uH_3.0X3.0X1.5 PCIE_WAKE_R_N 10,25
L_2p_3x3 VDD10

AVDD33_1(NC)
1004-00504
60MIL R915 0_J r0402
PLT_RST# 7,18,25

MDIN3(NC)

REFCLK_N
MDIP3(NC)

REFCLK_P
1 2

CLKREQB
REGOUT

2
C1019 C1020 C1021 C1022

HSIN
HSIP
0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R
2

2
c0402 c0402 c0402 c0402

1
C1023 C1024 C1025

9
10
11
12
13
14
15
16
C 0.1UF/10V,X5R
P3
4.7uF/6.3V,X5R 0.1UF/10V,X5R P8 P22 P30 P30 C
1

1
c0402 c0603 c0402

LAN_CLK_REQ#
ns

PCIE_TXN0_LAN
PCIE_TXP0_LAN

CLK_PCIE_LAN#
P24

CLK_PCIE_LAN
VDD33

PCIE_RXN0
PCIE_RXP0
C1026 C1027 XTAL1

2
1uF/6.3V,X5R
c0402
0.1UF/10V,X5R
c0402 <=+/-50ppm, ESR<30ohm

1
11 LAN_CLK_REQ0_N 2 4
3 1 XTAL2
P30 10 CLK_PCIE_LAN
Y3 25MHZ y_4p_smd3225

2
C1028 C1029
10 CLK_PCIE_LAN#
18PF/50V,NPO 18PF/50V,NPO
11 LAN_TXP0
U77 c0402 c0402
11 LAN_TXN0

1
HSC-1622-R C1030 c0402 0.1UF/10V,X5R
TRANSFORMER16_1D27_9D65 11 LAN_RXP0 C1031 c0402 0.1UF/10V,X5R
1014-00025 11 LAN_RXN0
4

MDI0+ 1 RD+ RX+ 16 TX0+ BIOS通过关闭相应的PCIE LANE来关闭PCIE LAN。


MDI0- 2 15 TX0-
3 RD- RX- 14 RXCT1
CT1 CT2
6 CT3 CT4 11 TXCT1
MDI1+ 7 TD+ TX+ 10 TX1+ RXCT1 R921 1 75_J 2 r0603
B B
MDI1- 8 9 TX1-
TD- TX- TXCT1 PF2
2

1
P4200SC C1036 C1037
12

13

C1034 C1035 d_smb 1000pF/2KV,X7R 0.1uF/25V,X7R


0.01uF/25V,X7R 0.01uF/25V,X7R RXCT2 c1206 C0603
1

2
C0402 C0402 ns
ns
TXCT2 LD8
SOT23_6
MDI0- AZC199-04S MDI1-

6
Vinafix.com CN12
130470-2

1
Rj45_130470-02 MDI0+ MDI1+

OK
1011-01396
11

TX0+ 1 10 Bitland Information Technology Co.,Ltd.


NPTH2

A 1A GND2 A
TX0- 2
TX1+ 3 2A
3A Page Name
4
RXCT2 5 4A Size Project Name
5A Rev
TX1- 6 Custom <Doc>
NPTH1

7 6A Rev1.0
TXCT2 8 7A 9 Date: Saturday, August 16, 2014 Sheet 28 of 42
8A GND1
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
12

documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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5 4 3 2 1

+V5_HUB

+V5_HUB

1
+V5S 18,19,20,24,26,39

1
R486
R468 100K_J
+V5A 27,30,33,34,35,36,37,39
10K_J R0402
R0402 ns

2
D PGANG D
+V5_HUB

1
+V5_HUB R157 1 2 0_J ns
+V5_HUB

OVCUR#
OVCUR#
R0402

PGANG
PSELF
R812 1 2 R0603 R371

DVDD
+V5A

SDA
+V5S R813 1 0_J 2 R0603 100K_J

1
0_J ns R0402
change power supply to +V5A 0906 U22

2
GL852G DVDD R475

28
27
26
25
24
23
22
qfn28_0d5_5x5 100K_J
R0402

SDA
V33
V5

PGANG
PSELF
OVCUR1#
OVCUR2#

2
1 21 FB10 2 1 100ohm/100MHZ FB0603
SOC 9 USB_HN
2 DM0 DVDD 20 R162 1 2 0_J R0402 OVCUR3# OVCUR3#
9 USB_HP DP0 OVCUR3# OVCUR3# 30
3 19 OVCUR# R163 1 2 0_J R0402 ns
30 USB_3G_PN DM1 OVCUR4#

1
4 18 TEST/SCL
3G 30 USB_3G_PP
AVDD 5 DP1 GL852G TEST/SCL 17 RESET#
6 AVDD1 RESET# 16 USB_HUB_HP4 1 2 R483
25 USB_BT_PN DM2 DP4 USB_TP_HP4 23
7 15 USB_HUB_HN4 3 4 100K_J
BT TP

AVDD2
25 USB_BT_PP DP2 DM4 USB_TP_HN4 23

AVDD
RREF
R0402

DM3
DP3
RA4_0402

G1
X1
X2

2
QFN28 RN6 DVDD
0_J

8
9
10
11
12
13
14

29
C C
ns
Option:

AVDD

AVDD
RREF

1
Customized VID, PID,

X1
X2
+V5_HUB R469 R473
String, Configuration. 10K_J 10K_J
R0402 R0402
1

2
R471 ns

2
10K_J R306
R0402 680_F +V5_HUB
R0402
SDA

USB_PN1
USB_PP1
2

1
RESET# TEST/SCL

1
R370
R160 100K_J
1

C150 47K_J R0402


1UF/6.3V,X5R r0402 USB_HUB_HN4 1 2 USB_HUB_PN_CD 30

2
30

USB_PN1_C
USB_PP1_C

30
C0402 OVCUR# USB_HUB_HP4 3 4 USB_HUB_PP_CD 30
2

1
RA4_0402
RN5
B R472 0_J B
100K_J
R0402
USB 2.0

2
DVDD AVDD
Y9
12MHZ <=+/-50ppm, ESR<30ohm
y_4p_smd3225 X1
2 4 R161 2 1 0_J R0603
3 1

1
C148 C263 C149 C274
1

C275 C151 1UF/6.3V,X5R 0.1UF/10V,X5R 1UF/6.3V,X5R 0.1UF/10V,X5R


2

C543 C538 0.1UF/10V,X5R 4.7UF/6.3V,X5R C0402 C0402 C0402 C0402

2
22PF/50V,NPO 22PF/50V,NPO R470 C0402 C0603
2

C0402 C0402 1M_J


1

R0402
2

X2

A
Bitland Information Technology Co.,Ltd. A
Page Name

Size Project Name Rev


B <Doc> Rev1.0
Date: Wednesday, April 02, 2014 Sheet 29 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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5 4 3 2 1

+V5A 27,29,33,34,35,36,37,39
+V5S 18,19,20,24,26,29,39
+V3.3A 7,11,13,18,23,25,28,33,34,35,36,37,39
+V3.3S 6,7,13,18,19,20,21,22,23,25,28,35,36,39
+ECVCC 10,18,19,32,33

D D

CN6
88511-1841
+V3.3S cns18_0d5_r_88511
1011-00719
1 19
2

1
+ECVCC C390 3
C0402 4
CN4 0.1UF/10V,X5R 5

2
88511-0641 3G 6
1

PC7 cns6_0d5_r_88511 7 USB_PN_CD1 1 2 USB_PN_CD 9


18 WWAN_EN
0.1UF/10V,X5R 1011-00552 8 USB_PP_CD1 3 4 USB_PP_CD 9
c0402 1 7 9
2

2 10 RA4_0402
3 11 RN4
18 Novo_SW# 4 12 0_J
18 PWRSW# 5 13
18 Button_LED# ns
6 8 14 0_J
C 15 RN12 C
1

C562 C561 29 USB_3G_PN 16 RA4_0402


0.1UF/10V,X5R 0.1UF/10V,X5R 17 3 4
c0402 c0402
3G 29 USB_3G_PP
18 20 1 2
USB_HUB_PN_CD 29
USB_HUB_PP_CD 29
2

ns C563
0.1UF/10V,X5R 3G Card: 2.75A;
c0402 3G
2

Add C562 C563 For EMC 0115

+V3.3A +V3.3A

C391 1 2 0.1UF/10V,X5R CN5


c0402 88242-3001
2

cns30_1d0_r_88242
2

2
0_J
OK
R852 R234 1 2 R0402 1011-00495

32
29 OVCUR3#
R853 R854
330_J
r0402 330_J 330_J
+V3.3S 9 USB_OC#0
1
3
2
4
端子线实际值走2根线
r0402 r0402 18 LIDIN# HPOUT-JD 20
1

5 6
1

PR88 1 0_J 2 r0603 ns 7 8


POWER LED
1

2
0.1UF/10V,X5R 9 10
CHARGE LED BATTERY LED
1

B LED3 PR89 1
+V3.3A 0_J 2 r0603 C389 USB_PN_CD1 11 12 MIC1_JACK 20 B
AS-F196BP LED1 LED2 c0402 USB_PP_CD1 13 14

1
led_0603 BL-HJC36A-TRB AS-F196BP 15 16
led_0603 led_0603 USB_PN1_C R487 1 0_J 2 R0402 17 18
+V5A 29 USB_PN1_C
USB_PP1_C R489 1 0_J 2 R0402 19 20
29 USB_PP1_C INT_MIC 20
2

Place Charge LED&Battery LED Together 21 22


2

23 24 HPOUT-L 20
POWER_LED# +ECVCC 25 26
18 POWER_LED#

2
18 CHARGE_LED# CHARGE_LED# BATTERY_LED# C388 27 28 HPOUT-R 20
1

BATTERY_LED# 18 0.1UF/10V,X5R 29 30
1

c0402

2
VR1 C542

31
AZ5125-01H VR2 VR3 0.1UF/10V,X5R
SOD-523 AZ5125-01H AZ5125-01H c0402

1
ns SOD-523 SOD-523
2
2

C1003 ns ns
2

2
2

0.1UF/10V,X5R C1004 C1005 Add R487 R489 For EMC Colse to Conn 0115
c0402 0.1UF/10V,X5R 0.1UF/10V,X5R
1

c0402 c0402
1

1000pf to 0.1uf For EMC 0115


Bitland Information Technology Co.,Ltd.
A A
Page Name

Size Project Name Rev


Custom <Doc> Rev1.0
Date: Saturday, August 16, 2014 Sheet 30 of 42
Vinafix.com PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

https://vinafix.com
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

Bitland Information Technology Co.,Ltd.


Page Name

A Size Project Name Rev A


A <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 31 of 42

https://vinafix.com
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

D Vinafix.com D

ACIN

2
C341 C342
+VDC 23,33,34,35,37,39
0.1uF/25V,X7R 0.1uF/25V,X7R
+ECVCC 10,18,19,30,33
C0603 C0603

1
EMC add C341 C342 0627
ACIN colay
VPJ1 AD+ +VDC BATT+
85204-05001 VPF1 1 32V/5A 2 fuse_0603 Stuff 5A Fuse 1113 PQ48 PQ49 PQ47
cns5_1d25_r_85204 EMB20N03V EMB20N03V EMB20N03V
1011-00535 dfn8_0d65_3x3 dfn8_0d65_3x3 dfn8_0d65_3x3
7 5 VPF2 1 24V/7A 2 fuse_1206 ns PFB4 2 1 100ohm/100MHZ FB0603 1 1 R106 1 2 15m_F R1206 1
4 PFB5 2 1 100ohm/100MHZ FB0603 2 2 2
3 3 3 3

2
2 5 S S 5 5 S
6 1 R659 D D D

1
PC247 PC263 PC236 PC269 C327 22K_J C143 G C283 G G

2
1000PF/50V,X7R 100PF/50V,NPO 4.7uF/25V,X5R 1000PF/50V,X7R 0.1uF/25V,X7R r0402 0.01UF/25V,X7R 0.1uF/25V,X7R

4
c0402 c0402 c0805 c0402 c0603 c0402 C0603 C142

2
0.01UF/25V,X7R

1
c0402
BAT_EN

Change to 4.7uf C0805 1114

2
R83 R42
ADP_ID 18 4.7K_J 4.7K_J
1

C272 R0402 R0402


0.1UF/10V,X5R
c0402
2

1
C C139 C140 C
R90
0.1uF/25V,X7R 0.1uF/25V,X7R
VMB C0603 C0603 2 1

2
18 BATT_OFF

3
1K_J
R89
1

PC50 PC51 R0402 C SOT23-3


2200PF/50V,X7R 0.1uF/25V,X7R 2 3 2 1 1 LMBT3906LT1G
B E Q62
c0402 c0603 GND_CHR
2

colay +ECVCC sot23-3 1K_J

2
BATT+ C138 D2 AD+ LMBT3904LT1G R0402
VMB 0.1uF/25V,X7R LBAT54CLT1G Q52

2
VPF3 1 32V/5A 2 fuse_0603 PFB1 1 2 100ohm/100MHZ FB0603 C0603 SOT23-3
4A
PFB2 1 2 100ohm/100MHZ FB0603 R39 1 2 1
PF1 2 24V/7A 1 fuse_1206 ns VBT+ PFB3 1 2 100ohm/100MHZ FB0603 10K_J
BATCON1 3
R0402
BT41710701-41-50-XXX
1

1
bat_bt4101070b-41-55-021 PC53 PC54 2

1
1

1011-01262 PC52 0.1uF/25V,X7R 0.1uF/25V,X7R AD+


18 ACIN_EC +VDC
2200PF/50V,X7R C0603 C0603
2

2
c0402 R82 change to 0805 1112

GND_CHR
2

1
9 7 R81 10_J
GND1 7 6 R40 301K_F R0805

ACOK

ACDRV

ACP
CMSRC

ACN
6 5 BATT_CLK R315 1 2 100_F r0402 49.9K_F R0402 21
5 CLK_SMB 18,22,32 PAD C268 1UF/25V,X5R

1
4
4 BATT_DAT R314 1 2 100_F r0402
DAT_SMB 18,22,32
R0402 2.4--3.15V C129 C141
3 BATT_PRS#_R 6 20 1 2 C0603 10uF/25V,X5R 0.1uF/25V,X7R
3 GND_CHR ACDET VCC GND_CHR

5
8 2 C0805 C0603

2
GND 2
1

D
1 PC55 PC56 CA42 1 2 100PF/50V,NPO c0402 I_OUT 7 19 Charger_PHASE Q29
1 5.6PF/50V 5.6PF/50V IOUT U24 PHASE
EMB20N03V
c0402 c0402 R98 1 2 0_J R0402 SMB_CH_DAT 8 Bq24735 18 4
dfn8_0d65_3x3
2

18,22,32 DAT_SMB SDA qfn20_0d5_3d5x3d5HDRV

G
ns ns
BATT+
OC:3A

S
R97 1 2 0_J R0402 SMB_CH_CLK 9 17
18,22,32 CLK_SMB SCL BTST C340 PL10

3
2
1
R72 2 1 100K_J R0402 10 16 16V 2 1 2 0.1uF/25V,X7R C0603 Charger_PHASE1 2 R109 1 2 15m_F
GND_CHR ILIM REGN

BATDRV
PD5 4.7uH/5.5A R1206

5
LDRV
L_2P_6D6X7D3

GND
SRN

SRP
1.0V_0.2A_LMDL914T1G
+ECVCC
750KHz

D
Q38
SOD323 EMB20N03V

1
0.9V-3A R38 C128 4
dfn8_0d65_3x3 C99 C125

11

12

13

14

15
2

G
412K_F 1uF/10V,X5R 10uF/25V,X5R 10uF/25V,X5R

S
R0402 C0402 C0805 C0805

2
PR32

3
2
1
301K_F

2
r0402 +ECVCC
R36
1

4.7K_J
PR33 1 2 1K_J
BATT_PRS# 18 R0402
R0402
R37 2 1 0_J

1
B BAT_EN R0402 B

GND_CHR

1
+ECVCC +ECVCC C280
0.1uF/25V,X7R
C0603

2
2
2
1

PC57 3 CLK_SMB
1

1
0.1UF/10V,X5R PC58 3 DAT_SMB C108 C281
c0402 1 0.1UF/10V,X5R 0.1uF/25V,X7R 0.1uF/25V,X7R
2

c0402 1 C0603 C0603


2

2
PZD1 close to IC as possible to the
LBAT54SLT1G PZD2 decouple high frequency noise
sot23-3 LBAT54SLT1G
sot23-3

GND_CHR

A A

Bitland Information Technology Co.,Ltd.


Page Name
Size Project Name Rev
D <Doc> Rev1.0
Date: Thursday, April 17, 2014 Sheet 32 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

https://vinafix.com
5 4 3 2 1

+VDC 23,32,34,35,37,39
+V3.3A 7,11,13,18,23,25,28,30,34,35,36,37,39
+V5A 27,29,30,34,35,36,37,39
+ECVCC 10,18,19,30,32
+VDC

CAD NOTE:PC62 place close to pin16

VREF

1
PC148

1
0.1uF/25V,X7R PC70
C0603 1uF/6.3V,X5R

2
D c0402 D

2
+3VALW_LDO +5VALW_LDO

16

3
PU6 AGND_51125
+VDC PC59 C133 Clolay

VIN

VREF

1
+VDC
C399 C400
SKIPSEL 14 4.7uF/6.3V,X5R 4.7uF/6.3V,X5R

2
SKIPSEL 8 c0603 c0603
VREG3

1
C401 C134 PC150 PC74 PC75

1
1000PF/50V,X7R 10uF/25V,X5R 4.7uF/25V,X5R 4.7uF/25V,X5R 0.1uF/25V,X7R TONSEL 4 PC149 PC60 PC59 C133 C402
c0402 C0805 c0805 c0805 C0603 TONSEL 17 0.1uF/25V,X7R 4.7uF/25V,X5R 4.7uF/25V,X5R 10uF/25V,X5R 1000PF/50V,X7R
2

2
VREG5 C0603 c0805 c0805 C0805 c0402
ns

2
PR34 ns
0_J
+5VBST1 r0603 +5V_BST 22 9 +3V_BST PR35 0_J +3VBST1
VBST1 VBST2

5
PC150 C134 Clolay PQ3 r0603

D
EMB20N03V PQ15

D
dfn8_0d65_3x3 EMB20N03V
4 +5V_DH 21 10 +3V_DH 4 dfn8_0d65_3x3
+V5A DRVH1 DRVH2

G
6A

2
+V3.3A
5A

S
C403 C404

S
OCP=11A
PL9 0.1uF/25V,X7R 0.1uF/25V,X7R PL8

1
2
3

3
2
1
OCP=8.4A
C0603 C0603

1
+5VALW_PWM 1 2 +5V_LX 20 11 +3V_LX 1 2 +3VALW_PWM
LL1 LLS

1
4.7uH/5.5A 4.7uH/5.5A

1
l_2p_6d6x7d3 PQ14 l_2p_6d6x7d3

D
PR36 EMB20N03V PQ16

D
1

1
C405 PC65 1_J dfn8_0d65_3x3 EMB20N03V PR37
1

1
1000PF/50V,X7R 0.1UF/10V,X5RCT2 CE2 r0805 4 1 2+5V_DL 19 12 +3V_DL 1 2 4 dfn8_0d65_3x3 1_J + PC152 CE3 CT1 PC63 C406

1 2
DRVL1 DRVL2

1
T + 150uF/6.3V + 220uF/6.3V + 220uF/6.3V T + 150uF/6.3V 0.1UF/10V,X5R

G
c0402 c0402 + PC151 PR40 PC71 PC66 PR38 0_J r0603 PR39 0_J r0603 r0805 PR41 PC69 220uF/6.3V 1000PF/50V,X7R

G
2

1 2
S
TC3528 cap6d3x6d6 220uF/6.3V 30K_F 1000PF/50V,X7R 13K_F 1000PF/50V,X7R tc7343 cap6d3x6d6 TC3528 c0402 c0402

2
tc7343 r0402 c0402 1500PF/50V,X7R PC67 r0402 c0402 ns
2

1
2
3

3
2
1

2
ns ns C0402 1500PF/50V,X7R ns
2

2
C0402

2
ns ns
+5VALW_PWM 24 7
VO1 VO2

C C
+5V_FB 2 5 +3V_FB
VFB1 VFB2

teknisi indonesia

1
1

PR42
R478 20K_F
20K_F r0402
r0402 6 +3V_EN

2
ENTRIP2
2

20MIL TP106 1 18
VCLK AGND_51125

1
AGND_51125 PR86
169K_F
r0402

2
+5V_EN +V3.3A
+5V_EN 1 AGND_51125
ENTRIP1
3

D Q25A 23 PR83 1 2 10K_J r0402


L2N7002DW1T1G PGOOD
5 G sot363

1
S PR84 1 2 0_J r0402
PR85 V5A_V3P3A_VR_PWRGD 18
4

169K_F
+3VALW_LDO r0402
13

2
EN0
2

1
+3V_EN

GND1
PR82 R477

GND
6

100k_J 620K_J +3VALW_LDO +ECVCC


r0402 D Q25B AGND_51125 r0402
L2N7002DW1T1G RT8205MGQW ns PR79 1 0_J 2 r0402
1

15

25

2
2 G sot363 qfn24_0d5_4x4
S
3

1
AGND_51125 PC62 PC68 PC112
1
1

D PQ17 PC61 0.1UF/10V,X5R 1uF/6.3V,X5R 0.1UF/10V,X5R


L2N7002LT1G 22PF/50V,NPO PR80 1 0_J 2 r0603 c0402 c0402 c0402

2
+3V_+5V_EN_R 1 SOT23-3 C0402 ns
2

B G S ns B
2

AGND_51125

SKIPSEL
TONSEL

Auto skip mode


OA Auto skip mode PR81 1 2 1K_J r0402

+5VALW_LDO PR74 1 0_J 2 r0402 2 1 VREF +3VALW_LDO 2 1 2 1 VREF +3V_+5V_EN_R D22 2 1 LMDL914T1G ns
ALW_ON 18
PR73 0_J ns PR78 0_J ns PR76 0_J SOD323

2
5V --365K 5V --245K r0402 r0402
3.3V---460K r0402 3.3V---305K PR77

1
0_J PC64
1

PR75 r0402 0.1UF/10V,X5R


0_J ns c0402 D27 1 2 LMDL914T1G

2
PWM mode HW_OT# 19
r0402 SOD323
ns
AGND_51125
2 +3VALW_LDO

5V --300K
3.3V---375K

A A

Bitland Information Technology Co.,Ltd.


Page Name

Size Project Name Rev


A2 <Doc> Rev1.0
Date: Tuesday, April 08, 2014 Sheet 33 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other

https://vinafix.com
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

+V1P0A 13,39
+V1P8A 7,9,10,13,18,39
+VDC 23,32,33,35,37,39
+V3.3A 7,11,13,18,23,25,28,30,33,35,36,37,39
+V5A 27,29,30,33,35,36,37,39

D D

+VDC

1
R143 C160 PC76 PC77 C136
0.1uF/25V,X7R 4.7uF/25V,X5R 4.7uF/25V,X5R 10uF/25V,X5R

21

22

23

24

34
340K_F
R0402 C0603 c0805 c0805 C0805

2
+V5A ns

VIN1

VIN2

VIN3

VIN4

VIN5
7
R127

1
+V3.3A TON
PC77 C136 Clolay
BOOT
27 2 30mil
1
9
VCC

1
26 C175
NC 2.2_F

1
PC113 0.1uF/25V,X7R
2

1
1UF/6.3V,X5R 25 R0603 C0603

2
PHASE5

1
R144 C97 PR64 C0402 35

2
0.01UF/25V,X7R 32 PHASE6 PL11 +V1P0A
100K_J 10K_F GND
R0402 C0402 R0402 20 1 2 +V1P0_F

2
PHASE4 0.68uh
19 PR55 l_2p_6d6x7d3
1

2
PHASE3

1
1_J PC143 PC94 PC93 PC92 PC91 PC85 PC115

1
10 18 r0805 0.1UF/10V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R 0.1UF/10V,X5R
CS PHASE2 c0402 C0805 C0805 C0805 C0805 C0805 c0402
ns

2
17 ns

2
8 U4 PHASE1
18 V1P0A_PWRGD POK

1
uP1741P PC105
4700pF/50V,X7R
C0402

2
R103 ns
2 R142 1 2 0_J R0603
2 1 6 VDDQ
18 +V1P0A_EN 1
EN

2
PC107 3
100K_J 0.1UF/10V,X5R FB R132
C R0402 c0402 178K_F C
2

5 28 R0402
GND6 GND5 C126
1 2

1
29 470PF/50V,X7R
GND4 C0402
1
INTREF 31 1
R552 r0402 2 3.3k_F
GND3
1

PC117

1
0.1UF/10V,X5R 33

PGND1

PGND2

PGND3

PGND4

PGND5

PGND6
c0402 GND7 30 PR61
2

GND2

1
4 10K_F PC116
GND1 0.1UF/10V,X5R
R0402
c0402
11

12

13

14

15

16

2
ns

2
Vinafix.com

B B

PU9 +V1P8A
UP0111AMA5-00
SOT23-5
0.2A
+V3.3A 1 5
VIN VOUT
2

1
C419 PC178 18 +V1P8A_EN R320 1 2 1K_J R0402 3 4 PC179
SHDN# BP

1
4.7uF/6.3V,X5R 0.1UF/10V,X5R PR101 0.1UF/10V,X5R PC182 PC180 PC181
1

c0603 c0402 PC109 GND 150K_F c0402 10uF/6.3V,X5R 10uF/6.3V,X5R 0.1UF/10V,X5R


1

2
0.1UF/10V,X5R r0402 ns C0603 C0603 c0402

2
c0402 2 ns
2

1
1
PR104 0.8v
120K_F
r0402
2

+V3.3A
2

PR60
+V3.3A 10K_F
R0402
2

3 1

PR151 +V1P8A_PWRGD 18
51K_J D PQ32
1

r0402 L2N7002LT1G PC111


1 SOT23-3 0.1UF/10V,X5R
1

G S c0402
2

+V1P8A
2
3

A A
C
PR143 1 2 1K_J r0402 1 B
E
Q37
LMBT3904LT1G
2

SOT23-3 Bitland Information Technology Co.,Ltd.

https://vinafix.com
Page Name
Size Project Name Rev
C <Doc> Rev1.0
Date: Friday, April 11, 2014 Sheet 34 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

+V_VDDQ_VR 7,12,15,16,36,39

+VDC 23,32,33,34,37,39

+V_VDDQ_VTT 15,16

+V3.3S 6,7,13,18,19,20,21,22,23,25,28,30,36,39

+V3.3A 7,11,13,18,23,25,28,30,33,34,36,37,39

+V5A 27,29,30,33,34,36,37,39

D D

+VDC

1
R49 C96 PC78 PC79 C137
0.1uF/25V,X7R 4.7uF/25V,X5R 4.7uF/25V,X5R 10uF/25V,X5R

21

22

23

24

34
340K_F
R0402 C0603 c0805 c0805 C0805

2
ns

VIN1

VIN2

VIN3

VIN4

VIN5
+V3.3A +V5A 7

1
TON
30mil PC99 C137 Clolay
27
R53 1 2 0_J R0603
9 BOOT
VCC

1
26 C135
NC

1
PC108 0.1uF/25V,X7R

2
1UF/6.3V,X5R 25 C0603

2
PHASE5
1

1
C98 R50 C0402 35 +V_VDDQ_VR

2
R129 0.01UF/25V,X7R 32 PHASE6 PL12
8.2k_F GND
100K_J C0402 R0402 20 1 2 +V1.35_OUT_J

2
PHASE4

2
R0402 0.68uh
19 PR62 l_2p_6d6x7d3

1
PHASE3

1
1_J PC90 PC154
2

1
10 18 r0805 PC153 22UF/6.3V,X5R PC89 PC88 PC87 PC86 0.1UF/10V,X5R
CS PHASE2 0.1UF/10V,X5R C0805 22UF/6.3V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R 22UF/6.3V,X5R c0402
ns

2
C 17 c0402 C0805 C0805 C0805 C0805 C

2
8 U2 PHASE1
7,18,39 DDR3_DRAM_PWROK POK ns

1
uP1740P/Q PC110
4700pF/50V,X7R
C0402

2
ns
2 R46 1 2 0_J R0603
PR43 2 1 1K_J R0402 uP1740_S5 6 VDDQ
18,39 SUS_ON S5

2
uP1740_S3 5 3
S3 FB
2

R45
R313 1 40mil 178K_F
100k_J 28 +V1.35_OUT_J R0402
R120 VTTIN
R0402 C65

1
100K_J PC114
1

1
R0402 29 1UF/6.3V,X5R 1 2
VTT C0402 150pF/50V,NPO

2
1 C0402
2

VTTREF 31 R100 8.2k_F R0402


VTTSNS
1
PC119 2 1
0.1UF/10V,X5R 33

PGND1

PGND2

PGND3

PGND4

PGND5

PGND6
VTTGND3

1
c0402 30 PC127
2
VTTGND2 4 PR63 0.1UF/10V,X5R

teknisi indonesia
VTTGND1 c0402
10K_F

2
R0402 ns

11

12

13

14

15

16

2
+V_VDDQ_VTT
+V_VDDQ_VTT_F
B B
+V3.3S

1
PC120 PC97 PC95
0.1UF/10V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
1

c0402 C0603 C0603

2
PR53 ns
10K_J
r0402
2

PR71 2 1 0_J R0402 uP1740_S3


39 +1P0_1P35_1P5_1P8_PWRGD
1
1

PC96 PR54
1uF/6.3V,X5R 1M_J
c0402 R0402
2

ns ns
2

A A

Bitland Information Technology Co.,Ltd.


Page Name

Size Project Name Rev


Custom <Doc> Rev1.0
Date: Friday, April 11, 2014 Sheet 35 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

https://vinafix.com
5 4 3 2 1

+V5A 27,29,30,33,34,35,37,39

+V3.3S 6,7,13,18,19,20,21,22,23,25,28,30,35,39

+V_VDDQ_VR 7,12,15,16,35,39
D +V1P5S 13,20,39 D

+V1P05S 13,39

+V3.3A 7,11,13,18,23,25,28,30,33,34,35,37,39

rsvd C295 C302 EMC request


+V5A +V3.3S

R493 10_J r0402 1003-01048

2
1

1
C421 PR66 C295 C302
1uF/6.3V,X5R 10K_J 0.1UF/10V,X5R 0.1UF/10V,X5R
c0402 r0402 c0402 c0402

2
ns ns ns

8
PU11

1
PR106 2 1 0_J R0402 2 1 R322 2 1 R0402 0_J

CTNL

GND
18 +V1P05S_EN EN PG +V1P05S_PWRGD 39 +V1P05S
5
NC

2
700mA

2
PR107 C423 6 +V1P05S
VOUT
22K_J 0.1UF/10V,X5R

1
r0402 c0402

1
7 PR93 PC184 PC187 PC185 PC186

1
FB 0.1UF/10V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 0.1UF/10V,X5R
4.7K_F

1
+V_VDDQ_VR R494 0_J r0603 3 9 R0402 c0402 C0603 C0603 c0402 C292 C293

2
VIN TGND ns 0.1UF/10V,X5R 0.1UF/10V,X5R
C ns C

1
FB2 120ohm/100MHZ c0402 c0402

2
l0603 ns C422 PC183 uP0104SSW8
4.7uF/6.3V,X5R 0.1UF/10V,X5R
0.8v

2
c0603 c0402
PR92 del PJ17 lihong 0729
EMC add FB2 0628 15K_F EMC add C293 C292 0627
r0402

1
PU8 +V1P5S
UP0111AMA5-00
SOT23-5 100mA
+V3.3A R843 1 2 1 5
0_J VIN VOUT
2

2
C416 PC163 R0603 3 4
SHDN# BP PR98

1
4.7uF/6.3V,X5R 0.1UF/10V,X5R PC164 PC167 PC165 PC166
c0603 c0402 GND 100K_F 0.1UF/10V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 0.1UF/10V,X5R
1

r0402 c0402 C0603 C0603 c0402

2
2 ns ns

1
1
PR95 0.8v
B 18 +V1P5S_EN
PR108 2 1 0_J R0402 115K_F del PJ18 lihong 0729 B
r0402
2

2
2

PR109 C424
22K_J 0.1UF/10V,X5R
r0402 c0402
1
1

Vinafix.com

A A

Bitland Information Technology Co.,Ltd.


Page Name

Size Project Name Rev


A3 <Doc> Rev1.0
Date: Tuesday, April 08, 2014 Sheet 36 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

https://vinafix.com
5 4 3 2 1
5 4 3 2 1

add +V5A for vcore should ramp first lihong 0605


+V5S 18,19,20,24,26,29,39

+V1P0S 10,11,13,39

+VDC 23,32,33,34,35,39
+V5A
+VCORE 12

2
+VGFX 12
R508
0_J
+V5A 27,29,30,33,34,35,36,39
R0402
+V3.3A 7,11,13,18,23,25,28,30,33,34,35,36,39

1
D D

+VDC
PC124 C144 Clolay
+VDC
R324
22_J

1
IMVP change 20130628 r0402 PC121 PC122 PC123 PC124 C144
+VCORE
R323 PQ5 D 0.1uF/25V,X7R 1000PF/50V,X7R 4.7uF/25V,X5R 4.7uF/25V,X5R 10uF/25V,X5R
R344 1.5k->2.61k -> 1.37K EMB12N03V C0603 c0402 c0805 c0805 C0805
51K_J
R345 1K->1.1k -> 1.37K

2
R0402 dfn8_0d65_3x3 ns

1
PR68 1.65K->0.75k C307 4 G
S VHCORE_OZ8296
R338 2.55K->1.78K -> 1.5K +V3.3A VDDA VDDA 1uF/25V,X5R

1
c0603
PQ5,PQ7 QM3002N3->EMB12N03V 1 1

1
2
3
1
PQ6,PQ8 QM3014N3->EMB06N03V 2
C308 PL6
RLL_CPU: -5.9mOhm CPU Iccmax: 15A

1
1UF/6.3V,X5R PC125 PD2 PD3 1 2
R509 C0402 1000PF/50V,X7R LMDL914T1G LMDL914T1G 0.68uh

2
10K_J C0402 sod323 sod323 PQ6 l_2p_6d6x7d3

1
EMB06N03V D R326 PC128 PC129 C309 C310

32

22
r0402 ns ns

1
GND_OZ8296 dfn8_0d65_3x3 51K_J 0.1UF/10V,X5R 1000PF/50V,X7R 10UF/6.3V,X5R 10UF/6.3V,X5R
1

GND_OZ8296 2 2 R0402 c0402 c0402 C0603 C0603

VIN
VDDA

VDDP

2
R327 1 0_J 2 R0402 VH_PWROK26 PR67 0_J r0603 4 G
39 IMVP_OK 1 15
GFX_PWROK PGA S
TP8

1
+V1P0S 20MIL PGB 23 PC130 0.22uF/25V,X7R 1 2 2 1

1
2
3
BSTA c0603 R328 RT1
24 71.5K_F 100k NTC
HDRA

2
R0402 R0402
1

2
25V/0603-->6.3V/0402 1122 C311
LXA
25 R329

1
1UF/6.3V,X5R R333 C779

teknisi indonesia
51_J
C0402 R332 100k_J 21 T + PC159 + PC126 + 330uF/2.5V
R0402
2

75_J r0402 LDRA 330UF/2.5V 330uF/2V cap6d3x6d6


R0402 ns GND_OZ8296 TC3528 tc7343

2
GND_OZ8296 ns
1

18 EC_IMVP_VR_ON R334 1 2 0_J R0402 VR_ON 2 27 CSPA C312 1 2 3300pF/50V,X7R


VR_SVID_ALERT_N 5 VR_EN CSPA C0402
ALRTb
ns
ns
C
VR_SVID_DATA
VR_SVID_CLK
6
7 VDIO CSNA
28 PR68 2 1 750_F r0402 CSNA
Co-lay C
VCLK

1
R337 1 2 0_J R0402 VR_HOT# 8 C313 PC131
11 PROCHOT_N VRTTb 22PF/50V,NPO 1000PF/50V,X7R
2

C314 C0402 C0402

2
47PF/50V,NPO +VDC
C0402 PC137 C145 Clolay
1

ns
3 GND_OZ8296 GND_OZ8296
18 OZ8296_CLK SCL

5
GND_OZ8296 +VGFX

1
4 PQ7 D PC133 PC134 PC136 PC137 C145
18 OZ8296_DAT SDA 18 PC132 0.22uF/25V,X7R EMB12N03V 0.1uF/25V,X7R 1000PF/50V,X7R 4.7uF/25V,X5R 4.7uF/25V,X5R 10uF/25V,X5R
BSTB c0603 dfn8_0d65_3x3 C0603 c0402 c0805 c0805 C0805

2
29 17 4 G ns
12 VCORE_VSNS RSPA HDRB S
PC139 1 2 1000PF/50V,X7R R338 2 1.5K_F 1 R0402 16 GFXCORE_OZ8296 del PJ14 PJ15 lihong 0729

1
2
3
C0402 LXB
C3152
RLL_GFX: -5.9mOhm GFX Iccmax: 10A
1 470PF/50V,X7R 30 20 PL7
12 VCORE_GSNS RSP_LLA LDRB
C0402 1 2

2
0.68uh
R339 1 0_J 2 R0402 14 l_2p_6d6x7d3
CSPB

5
PQ8 R340

1
RSN 9 13 EMB06N03V D 51K_J C780 PC141 PC142
RSN CSNB dfn8_0d65_3x3 + PC140 T + PC160 + 330uF/2.5V 0.1UF/10V,X5R 1000PF/50V,X7R
R0402
R341 1 0_J 2 R0402 330uF/2V 330UF/2.5V cap6d3x6d6 c0402 c0402

2
PR69 0_J r0603 4 G 1 2 2 1 tc7343 TC3528

2
S R342 RT2

2
12 31 71.5K_F 100k NTC
12 VGFX_VSNS

1
2
3
RSPB TEMPA
R344 2 1.37K_F 1 R0402 10
R0402 R0402 R343
51_J
Co-lay
ns
ns
TEMPB
R0402
PC144 1 2 C316 2 1470PF/50V,X7R 11 delate PC161
1000PF/50V,X7R C0402 RSP_LLB CSPB C317 1 2 3300pF/50V,X7R 10-17

1
C0402 C0402
GNDA

GNDP

R345 2 1 1.37K_F R0402 CSNB

VDDA

1
U26 C318 PC145
33

19

stuff PR120 PR121 PR122 PR124 for debug only


OZ8296 TEMPA R346 2 4.99K_F 1 R0402 22PF/50V,NPO 1000PF/50V,X7R
B B
PR70 0_J r0603 qfn32_0d4_4X4 C0402 C0402

2
1

1
PC146 RT3
1000PF/50V,X7R 100k NTC GND_OZ8296 GND_OZ8296
2

C0402 R0402
GND_OZ8296 2

4.87K
GND_OZ8296
have change the P/N from 1010-01531 to 1010-02033---0331 TEMPB R347 2 4.99K_F 1 R0402
GND_OZ8296
2
1

PC147 RT4
1000PF/50V,X7R 100k NTC
C0402 R0402
2

GND_OZ8296 GND_OZ8296

+V1P0S
1

R363 R366 R367


73.2_F 73.2_F 73.2_F
R0402 R0402 R0402
2

R86 1 2 0_J R0402 VR_SVID_ALERT_N


10 SVID_ALERT_N
R84 1 2 16.9_F R0402 VR_SVID_DATA
10 SVID_DATA
R85 1 2 20.0_J R0402 VR_SVID_CLK
10 SVID_CLK

A A

Bitland Information Technology Co.,Ltd.

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C <Doc> Rev1.0
Date: Tuesday, April 08, 2014 Sheet 37 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

D D

H8 H5
HOLE HOLE
HOLE2D4_7D5 HOLE5D4_3D4

1
MK1 MK2 MK3

1 1 1
1 1 1
FMARKS FMARKS FMARKS
fmarks fmarks fmarks
C ns ns ns C

MK4 MK5 MK6

1 1 1 H12 H6 H7 H9
1 1 1 HOLE HOLE HOLE HOLE
FMARKS FMARKS FMARKS HOLE5D0_2D3 HOLE5D0_2D3 HOLE5D0_2D3 HOLE5D0_2D3
fmarks fmarks fmarks
ns ns ns

MK7 MK8

1 1

1
1 1
FMARKS FMARKS
fmarks fmarks
ns ns

H13
HOLE
HOLE5T7D5B_2D2

SW2
PCB1
SW1

1
B B

MB
BIOS code
EC code N/A H15 H16
BM5338 N/A HOLE HOLE
N/A SHAPE196X137 SHAPE196X137

U30
U29

1
Barcode2
Barcode1

BOSS2 BOSS4 BOSS3

A A

Bitland Information Technology Co.,Ltd.

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hole-c6d3p2-b
Hole+Dowel
hole-c6d3p2-b
Hole+Dowel
hole-c6d3p2-b
Page Name

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1

A3 <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 38 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

https://vinafix.com
5 4 3 2 1
5 4 3 2 1

+V1P0S 10,11,13,37 +V3.3A 7,11,13,18,23,25,28,30,33,34,35,36,37


+V1P0A 13,34
+VDC 23,32,33,34,35,37 +V3.3S 6,7,13,18,19,20,21,22,23,25,28,30,35,36
+V_VDDQ_VR 7,12,15,16,35,36
+V1P35S 13 +V1P05S 13,36
+V1P8A 7,9,10,13,18,34
+V1P8S 6,9,10,11,13,18,21,24 +V1P5S 13,20,36
+V5A 27,29,30,33,34,35,36,37
+V5S 18,19,20,24,26,29

+V1P0A +V1P0S
PQ18
+VDC EMB12N03V
+VDC dfn8_0d65_3x3 +V5A

1
C331 1
D 0.1UF/10V,X5R 2 6A D

2
C0402 3

2
1

1
C353 C354 C355 5 S
0.1uF/25V,X7R 0.1uF/25V,X7R 0.1uF/25V,X7R D PR140
C0603 C0603 C0603 G 51K_J +1P0_1P35_1P5_1P8_PWRGD 35
2

3
C332 C330 r0402

4
2
R373 2 1 10K_F R0402 10UF/6.3V,X5R 0.1UF/10V,X5R D PQ31

1
1
R348 C321 C0603 C0402 L2N7002LT1G

2
100K_J 0.01UF/25V,X7R 1 SOT23-3
R464

1
C0402 C329 G S
R0402

2
1

C356 C359 2 1 2 1 0.1uF/25V,X7R

2
2
0.1uF/25V,X7R 0.1uF/25V,X7R D18 LMDL914T1G C0603

2
C0603 C0603 SOD323
2

1 B E Q20 71.5K_F
C LDTB114ELT1G R0402 +V1P8S
Q36

2
SOT23-3 +V1P5S

6
R350 LMBT3904DW1T1G

3
+V_VDDQ_VR +V1P35S PR146
1K_J SOT363
for emc 0303 R0402 PQ19 PR144 1 2 1K_J 5 2 2 1
EMB20N03V r0402
3RUN_DISCHAGE#

2
dfn8_0d65_3x3
1

1K_J

1
R351 C334 1
1A

1
30K_F 0.1UF/10V,X5R 2 r0402
R0402 C0402 3

2
5 S
D

1
G

1
C336 C335

4
D Q21 R374 2 1 33K_J R0402 10UF/6.3V,X5R 0.1UF/10V,X5R
L2N7002LT1G C0603 C0402 +V1P0S Q34

6
R353 1 2 1K_J R0402 RUN_DISCHAGE#_L 1 sot23-3 LMBT3904DW1T1G +V1P35S
18 RUN_ON PR142

1
G S R463 2 151K_J r04022 1 C333 SOT363
2

D19 LMDL914T1G 0.1uF/25V,X7R PR145 1 2 680_F 5 2 2 1


2

R354 SOD323 C0603 r0402

2
100K_J
R0402 1K_J

1
r0402
1

LMBT3904LT1G
C Saturation Voltage:Type=0.2V C
+V3.3S

+V1P8A Q51 +V1P8S +V1P0S +V1P05S


QM3010K 100mA

1
sot23-3 PR87 1 0_J 2 r0603 ns
3 2 R479

S
D
+V1P8A 10K_J
r0402

G
1

2
1

1
R356 1 2 33K_J R0402 C339 C338
10UF/6.3V,X5R 0.1UF/10V,X5R
R357
1

C608 C610 C612 C613 C0603 C0402 +1P0_1P35_1P5_1P8_PWRGD PR147 1 2 1K_J r0402 R480 0_J r0402

2
0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 2 1 2 1 ALL_SYS_PWRGD 18

1
C0402 C0402 C0402 C0402 D20 LMDL914T1G C337
2

SOD323 0.1uF/25V,X7R
33K_J C0603 PR148 1 2 1K_J r0402
2
36 +V1P05S_PWRGD

1
R0402
for emc 0303 PR152
100k_J
PR149 1 2 1K_J r0402 ns r0402
37 IMVP_OK
ns

2
+V1P8A PQ9 D24 2 1 LMDL914T1G SOD323
EMB20N03V +V5S
+V1P0S +V5A dfn8_0d65_3x3 2A
1
2
1

C604 C601 C602 C603 C609 3


0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 5 S 2
18 SLP_S3_EC_N
C0402 C0402 C0402 C0402 C0402 D
2

ns G 3
4

1
R349 1 2 47K_J R0402 C319 C320 1
7,18,35 DDR3_DRAM_PWROK
10UF/6.3V,X5R 0.1UF/10V,X5R PD11
+V5A R466
C0603 C0402 BAT54A
2

2
1

1 2 2 1 C322 sot23-3
D21 LMDL914T1G 0.1uF/25V,X7R
SOD323 C0603
2

22K_J
Add For EMC 0115 +V3.3A
1

C595 C605 C606 r0402


0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R
B C0402 C0402 C0402 +V3.3A +V3.3S B
2

1
PQ10 C442
EMB20N03V 0.1UF/10V,X5R
dfn8_0d65_3x3 c0402

2
1

C323 1

+V1P35S
0.1UF/10V,X5R 2 1A
C0402 3
2

5
5 S ALL_SYS_PWRGD 1
D 4
G 2 DDR3_VCCA_PWROK_3P3 7
18 DELAY_ALL_SYS_PWRGD
1

C597 C598 C599 C600 C611 C324 C325 U20


4

3
0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R R372 1 2 71.5K_F R0402 10UF/6.3V,X5R 0.1UF/10V,X5R 74AHC1G08GW

2
C0402 C0402 C0402 C0402 C0402 C0603 C0402 sot353 R105 1 2 0_J R0402 COREPWROK 10
2

R435
2

ns R482
1

1 2 2 1 C326 10K_J
D17 LMDL914T1G 0.1uF/25V,X7R R168 1 2 0_J r0402
SOD323 C0603 R0402 ns
2

1
10K_F

1
C285
R0402 0.1UF/10V,X5R
c0402

2
1

C343 ns
0.1uF/25V,X7R
C0603 EMC add C343 0729
2

+VDC +V_VDDQ_VR EMC add C285 0627

1
PR137 PR138
+V1P5S +V5S +V3.3S +V1P8S +V1P35S +V1P0S +V1P05S 510K_J 330_J
r0402 r0603
ns ns

6 2
2

+VDC

2
R358 R359 R360 R369 R375 R382 R387
330_J 330_J 330_J 330_J 330_J 330_J 330_J D Q32B
2

r0603 r0603 r0603 r0603 r0603 r0603 r0603 L2N7002DW1T1G


R361 SUS_ON# 2 G SOT363
510K_J S ns
6 1

3 1

6 1

3 1

6 1

3 1

6 1

R0402 Q23B Q5A Q5B Q22A Q22B

1
3
L2N7002DW1T1G L2N7002DW1T1G L2N7002DW1T1G L2N7002DW1T1G L2N7002DW1T1G
D D D D D D D D Q32A
1

1
A L2N7002DW1T1G A
2 G 5 G 2 G 5 G 2 G 5 G 2 G 5 G SOT363 R481
S S S S S S S 18,35 SUS_ON S ns 200K_J
3

Q24B Q23A r0402


1

4
D Q24A R362 L2N7002DW1T1G L2N7002DW1T1G ns

2
L2N7002DW1T1G 200K_J SOT363 SOT363
RUN_DISCHAGE#_L 5 G SOT363 r0402
S
Bitland Information Technology Co.,Ltd.
1
4

Page Name
1

C596 C607 Size


0.1UF/10V,X5R 0.1UF/10V,X5R Project Name Rev
A2 <Doc>
C0402 C0402 Rev1.0
2

ns ns Date: Thursday, April 10, 2014 Sheet 39 of 42


PROPERTY NOTE: this document contains information confidential and property to

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Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
EMC add C596 0627, add C607 0729 was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

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A <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 40 of 42

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PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
5 4 3 2 1

Power On/Off Sequence Specification(Battery Mode) G3-S5-S4-S3-S0


E E

PLTRST_N SB output

SUS_STAT#

COREPWROK EC output
>100mS
DDR3_VCCA_PWROK_3P3 EC output

ALL_SYS_PWRGD Input EC

+V_VDDQ_VTT

+1P0_1P35_1P5_1P8_PWRGD

RUN_ON EC output
Ttype=3~4mS
D D

EC_IMVP_VR_ON EC output
Ttype=1~2mS

SLP_S3_EC_N SB to EC

DDR3_DRAM_PWROK Input EC & SOC

+V_VDDQ_VR

SUS_ON output EC

SUSPWRDNACK SB to EC
Ttype=1~2mS
SLP_S4_EC_N SB to EC
TB_min>=0mS:5mS
TD_type=50ms
RSMRST_N EC to SB
Ttype=10mS
C C

PM_PWRBTN_N EC to SB
Tmin>=0mS
TA_min>=5mS:97mS
TC_Min>=100ms:155mS
PWRSW#_R External Power Botton TO EC
Press Power Button

+V1P8A_1P2A_PWRGD Input EC

+V1P2A_EN output EC
T2 10~2000us

+V1P8A_EN output EC

+V1P0A_EN output EC
Ttype=1~2mS
B B
V5A_V3P3A_VR_PWRGD Input EC

+V5AL/ +V3.3AL

ALW_ON EC output Ttype=1~2mS

ECRST#

EC_RTC

+VDC NO Request

>9mS
RTCRST#

VCCRTC
A A

G3 G3 S5 S3/S4/S5 S0 S0 Bitland Information Technology Co.,Ltd.

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条纹填充区域表示在这段时间任意一个时间点达到要求电平都OK Custom <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 41 of 42
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1
5 4 3 2 1

D D

C C

B B

Bitland Information Technology Co.,Ltd.


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A <Doc> Rev1.0
Date: Tuesday, March 04, 2014 Sheet 42 of 42

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PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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