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    Two-Phase Clock Generator For BBD's V3102: 1. Description

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    Stef LNA
    This document provides information about the V3102, a CMOS LSI chip that generates a two-phase clock signal suitable for driving BBDs up to 4096 stages. It can self-oscillate or be externally excited, and provides two 50% duty cycle clock outputs. The document includes details on pin configuration, electrical characteristics, an application circuit, and mechanical drawing.

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    © All Rights Reserved
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    Two-Phase Clock Generator For BBD's V3102: 1. Description

    Uploaded by

    Stef LNA
    59 views3 pages
    This document provides information about the V3102, a CMOS LSI chip that generates a two-phase clock signal suitable for driving BBDs up to 4096 stages. It can self-oscillate or be externally excited, and provides two 50% duty cycle clock outputs. The document includes details on pin configuration, electrical characteristics, an application circuit, and mechanical drawing.

    Original Title

    COOLAUDIO_V3102_DATASHEET

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    This document provides information about the V3102, a CMOS LSI chip that generates a two-phase clock signal suitable for driving BBDs up to 4096 stages. It can self-oscillate or be externally excited, and provides two 50% duty cycle clock outputs. The document includes details on pin configuration, electrical characteristics, an application circuit, and mechanical drawing.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    59 views3 pages

    Two-Phase Clock Generator For BBD's V3102: 1. Description

    Uploaded by

    Stef LNA
    This document provides information about the V3102, a CMOS LSI chip that generates a two-phase clock signal suitable for driving BBDs up to 4096 stages. It can self-oscillate or be externally excited, and provides two 50% duty cycle clock outputs. The document includes details on pin configuration, electrical characteristics, an application circuit, and mechanical drawing.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    Two-Phase Clock Generator for BBD’s

    V3102
    1. Description
    The V3102 is a universal CMOS LSI to generate a two-phase clock signal of low output impedance, perfectly suitable
    to drive BBDs up to 4096 stages, such as V3207, V3208, V3205, etc.

    2. Features
    • Direct driving capability of up to 4096-stage BBD’s
    • Self-oscillation or separate excitation possible
    • Two phase clock output (duty: 1/2)
    • Incorporates a diode to protect the IGBT gate at power on
    • Package outline: DIL-8 (V3102D)
    • ROHS compliant (PB-free)

    3. Pin Configuration

    VDD 1 8 VGG

    CP1 2 7 RCext1

    VSS 3 6 RCext2

    CP2 4 5 RCext3

    Information furnished by CoolAudio is believed to be accurate and


    reliable. However, no responsibility is assumed by CoolAudio for its
    use, nor for any infringements of patents or other rights of third parties
    which may result from its use. No license is granted by implication or
    otherwise under any patent or patent rights of CoolAudio.

    Rev. 1.0

    1
    V3102
    4. Absolute Maximum Ratings (Tamb = 250 °C)

    Parameter Symbol Min Max Unit


    Collector Supply Voltage VCC -0.3 12 V
    Input Voltage VI, VO -0.3 VCC+0.3 V
    Power Dissipation PD 200 mW
    Operating Temperature Tamb -10 70 °C
    Storage Temperature Tstg -30 125 °C

    5. Electrical Characteristics (Ta = 250 °C, VCC = 20 V, Unless otherwise specified)

    Parameter Symbol Test Condition Min Typ Max Unit


    Drain Supply Current I cc 0.5 mA
    RL = ∞, F0 = 40 KHZ
    Total Power Dissipation Ptot 2.5 mW
    Input Current “H” Level VIH VCC = 5 V, 10 V VCC-1 VCC V
    Input Current “L” Level VIL VCC = 5 V, 10 V 0 1 V
    Input High Leakage Current IIH(L) VI = 10 V 30 µA
    Input Low Leakage Current IIL(L) VI = 10 V 30 µA
    Output Current “H” Level IOH(1) VCC = 5 V, VO = 4 V 0.5 mA
    Output Current “L” Level IOL(1) VCC = 5 V, VO = 1 V 0.4 mA
    Output Leakage Current “H” Level IOH(L1) VCC = 10 V, VO = VCC 30 µA
    Output Leakage Current “L” Level IOL(L1) VCC = 10 V, VO = VSS 30 µA
    Output Current “H” Level IOH(L2) VCC = 5 V, VO = 4 V 0.7 mA
    Output Current “L” Level IOL(L2) VCC = 5 V, VO = 1 V 1 mA
    Output Leakage Current “H” Level IOH(L2) VCC = 10 V, VO = VCC 30 µA
    Output Leakage Current “L” Level IOL(L2) VCC = 10 V, VO = VSS 30 µA
    Output Current “H” Level IOH(3) VCC = 5 V, VO = 4 V 5 mA
    Output Current “L” Level IOL(3) VCC = 5 V, VO = 1 V 5 mA
    Output Leakage Current “H” Level IOH(L3) VCC = 10 V, VO = VCC 30 µA
    Output Leakage Current “L” Level IOL(L3) VCC = 10 V, VO = VSS 30 µA

    2
    V3102
    6. Application Circuit

    vcc1

    10u/50v
    104 104
    47k

    1 5 SG
    6 4 6 3
    10u/16v
    47k
    180k

    7 2 2 7
    5.6k
    68P ACout
    100k
    10u/16v

    5 8 4 8 0.22u
    3 1 5.6k
    100k

    7. Mechanical Drawing

    DIP-8 unit : mm

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