Military Institute of Science and Technology

Department of Electrical, Electronic and Communication Engineering

EECE – 458: VLSI –II Sessional

Experiment No. 1: Drawing the schematic of a 2-input NAND Gate, creating a Symbol
and Performing Simulation.

Learning Objectives:
✓ To log in to the Cadence Server shell and start the Cadence virtuoso software
✓ To create a working library and schematic cellview
✓ To draw the schematic of a 2-input NAND gate in Cadence Virtuoso Schematic Editor
✓ To create a symbol view of the NAND gate from the schematic
✓ To simulate the NAND gate using Spectre.

1-1. Getting started

a. The first step is to run Cadence
b. After successful login, open terminal and type

cd /Cadence/license
csh
source cshrc
“welcome to cadence tools”
cd
cd EECE-458
mkdir (here give any name you want)
“when your folder is created, copy cds.lib file from desktop and paste to
the folder”
cd
cd EECE-458/dir name
pwd
virtuoso –log /home/mist2018/EECE-458/dirname/mycds.log

c. Virtuoso Command Interpreter Window (CIW) appears at the bottom of the screen.

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1-2. Creation of library

a. In the CIW, execute File – New – Library. The new library form appears.

b. In the “New Library” form, type “your library name” in the Name section.

c. In “Technology File” field, select option “Attach to an existing technology library

and click OK.

d. A ―Attach library to Technology Library form appears, select option ―gpdk090 from
the cyclic field and click OK

e. After creating a new library, we can verify it from the “Library Manager Window (Tools
–Library Manager)

1-3. Creating the schematic of a 2 input NAND Gate

a. In the Command Interpreter Window (CIW) or Library manger execute

File→New→Cellview.

b. Set up the create new file.

c. Click Ok when done.

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A blank schematic window for the NAND2 design appears. In the schematic window execute
Create→Instance. Make sure that the View name field in the form is set to symbol. You will
update the Library Name, Cell Name, and the property values given in the table below as you place
each component. After you complete the Create instance form, move your cursor to the schematic
window and click left to place the component. The nand2 design contains the
following cells from the following library.

Library Name Cell Name Properties

gpdk090 nmos1v Total Width = 240n
gpdk090 pmos1v Total Width = 240n

If you place a component with wrong parameter values, use the Edit→Properties→Objects
command to change the parameters. Use the Edit→Move command if you placed components in the
wrong location.

d. After entering the components, click Cancel in the Create Instance form or press Esc with
your cursor in the schematic window.

e. Execute Create→ Pin. Enter the Pin Names Ain Bin Vdd Gnd, Select Direction to be input. Place
the pins and then follow the same process to create and place a pin name of out with
direction to be output.

f. Use Create →Wire to create the wire connections between pins and
instances.

g. File →Check and save when your schematic looks like the
following:

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1-4. Creating the Symbol View of a 2 input NAND Gate
a. In the nand2 schematic window execute Create → Cellview → From Cellview.

b. The Cellview From Cellview form appears. With the edit options function active, you
can control the appearance of the symbol to generate.

c. Verify that the From View Name field is set to schematic, and the To view Name field is set
to symbol, with the Tool/Data Type set as schematicSymbol.

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d. Click OK in the Cellview From Cellview form. The Symbol Generation Form appears. Change
the values such that Ain & Bin is at the left, Out is at the right, Vdd is at the top and Gnd at
the bottom:

e. Click OK and the default box-shaped symbol view is created as shown below:

f. Move your cursor over the symbol, until entire green rectangle is highlighted (selected). Click
left to select it.

g. Click the delete icon in the symbol window.

h. Execute Create → Shape → Line/Arc/Circle to draw the symbol shown in the final picture.

i. Move the labels to the desired location.

j. To save your edited symbol view to disk, click the Save icon in the symbol editor window.
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10. Now we can instantiate this symbol to build other circuits.

1-5. Simulation of a the 2 input NAND Gate

Open a new schematic window in your library and build the NAND2_test design.
In the Command Interpreter Window (CIW) or Library manger execute File →New→ Cellview.
1. Set up the create new file form.

2. Click Ok when done.

A blank schematic window for the NAND2_test design appears. In the schematic window execute
Create →Instance. Make sure that the View name field in the form is set to symbol. You will
update the Library Name, Cell Name, and the property values given in the table below as you
place each component.

Library Name Cell Name Properties

mylib nand2
analogLib vdc DC voltage = 1V
analogLib gnd
analogLib vpulse Voltage1 = 0V, Voltage 2 = 1V, Delay time = 3ns, Rise time =
3ns, Fall time = 3ns, *Period = 40ns/50ns, *Pulse width =
20ns/25ns
analogLib cap Capacitance = 0.1pF

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4. After entering the components, click Cancel in the Create Instance form or press Esc with
your cursor in the schematic window.
5. Execute Create → Pin. Enter the Pin Names A & B, Select Direction to be input. Place the
pins and then follow the same process to create and place a pin name of O with direction to be
output.
6. Use Create →Wire to create the wire connections between pins and instances.
7. File → Check and save when your schematic looks like the following:

8. In the Schematic window execute Launch → ADE L. Analog Design Environment (ADE)
window will open.

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9. Now choose the analysis to be done by Analysis → Choose. Select transient analysis to be done.
Provide stop time as 200ns.

10. Select the output to be plotted by executing Outputs → To be plotted → Select on

schematic in the ADE window. Select A, B and O from the schematic to plot and save. The
ADE window should appear to be something like the following:

11. We will create the netlistand run the simulation by executing the following in the ADE
environment Simulation → Netlist and Run. A netlist file will be created. The netlist is saved
in your simulation directory with name input.scs. The simulation will run and the output will appear
as shown below.

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12. Next we measure the falling propagation delay for input port B. To start it we go to Tools →
Calculator. The calculator window appears. Click on vt. Next select the pins B and O from the
schematic. Next click on the Enter symbol. You will see the expression related to the transient
voltages of the selected entities being stacked in the calculator.

13. Next select delay under the Special Functions tab in the Function Panel of the Calculator.
The parameters corresponding to the delay function appears on the screen.

14. Clear the Signal 1 and Signal 2 lines if there is any expression already present on those lines.
After that, Drag and drop VT(“/B”) from stack or simply type it on the Signal 1 line. Next do the
same for VT(“/O”). Enter the threshold value for both 1 and 2 to be 0.5. Choose Edge Number
1 and 2 to be 2. Choose rising for Edge Number 1 and falling for Edge Number 2. Click on
Apply and then go to Tools → Plot. This will calculate the falling propagation delay for input
port B.

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Report :
All the Reports relating to EEE-458 have to be submitted in the form of the standard lab report
template for EEE-458. In addition to the requirements in the template answer the following
questions:
(1) Observe the different MOS transistors available in the gpdk090 technology library and try to
understand the meaning of different parameters. In a Table summarize the values of the critical
parameters for different types of MOS transistors and make comment about the difference.
(2) Measure the rise time, fall time and propagation delay of the NAND gate for all four
different combinations of input waveforms.
(3) Make the worst case rise time and fall time approximately equal by changing the transistor
width and hence comment on the mobility ratio of the NMOS and PMOS transistors in the
technology library. Repeat the above for the best case also.
(4) Re-simulate the circuit using Fast Fast (FF) corner. For this purpose execute Setup →
Model Libraries. Go to section and select FF_s1v. This will select the fast coroner model.
Re-simulate the circuit and find the rise time, fall time and propagation delay.
(5) Repeat the above procedure using the Slow Slow (SS) and Fast Slow (FS) corners also.
(6) The delay of a technology is usually measured in terms of Fan-Out of 4 (FO4) inverter.
Measure the 50% delay, rise time and fall time of a FO4 inverter. Compare the FO4 delay
with that of the best case and worst case NAND gate delay.
(7) Submit the report in the form of the standard lab report template for EEE-458.

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