5 4 3 2 1

D D

+V3.3AL +V3.3A +V1.1A

2 +1.1VEN
SWITCH
PQ31 APL5930
+V3.3AL

+V5A

EC SN0608098RHBT
1
ITE8502 EC_ALW_EN

EC_PWRBTN# 3
+V1.5

SLP_S5#
4 TPS51117
C
SB820M 4 & G2997F6U +V0.75S
C
SLP_S3#
+V1.8S

4 4
NB634
+V5A +V5S PWRGD V1.8S_PWRGD
SWITCH
SLP_S3# PQ42 6
CPU_VDDA_RUN

+V3.3A +V3.3S
5 APL5930 +VCC_CORE +V1.5 +V1.5S
PQ39 LDO VDDA_PWRGD
7 8
EN MAX 17480
+VDDNB_CPU SWITCH
PWRGD
8 PQ17
Power on Sequence required:

SB820M: VRM_PWRGD
1, +V3.3A ramp before +V1.1A +VDDR_CPU
2, +V3.3S ramp before +V1.8S 8 +V1.1S
3, +V1.8S ramp before +V1.1S NB634
B 4, +V3.3S ramp before +V1.1S B
TPS51117 VLDT
RS880M: 9 VRM_PWRGD
1, 0 <(+V3.3S) - (+V1.8S) < 2.1
2, +V1.8S ramp before +V1.1S
3. +V1.1S ramp before VCC_NB VCC_NB
9 VRM_PWRGD
TPS51217

A A

Hon Hai Precision Industry Co. Ltd.

Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111

Title
POWER SEQUENCY DIAGRAM
Size Document Number Rev
Custom Safina MV
Page Modified: Wednesday, April 07, 2010 18:49:16 (UTC/GMT) Sheet 5 of 39
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 5 4 3 2 1

LDT_RST#
(SB to CPU)

LDT_PG
(SB to CPU) >1 mS Req.

CPU_CLKP/N running
D D

>1 mS Req.

running

>1 mS Req. VCC_NB(all NB power) valid before NB_PWRGD.

NB_PWRGD
(SB to NB)
SLP_S3#_3R V1.1A_PWRGD
SB_PWRGD V1.8S_PWRGD VRM_PWRGD
(VRM_PWRGD to SB)

0.95V - 1.1V RC=~22ms VCC_NB should not ramp before +V1.1S

+VCC_NB

1.1V
+VLDT
GROUP B

VRM_PWRGD AND V1.8S_PWRGD

+V1.1S

VRM_PWRGD
(from +VCC_CORE IC)
0.9V(DDR3-1066) 1.05V(DDR3-1333) RC=0
+VDDR_CPU

0.8V - 1.1V RC=0

+VCC_CORE

0.9V RC=0
+VDDNB_CPU
C C

VDDA_PWRGD
GROUP A

2.5V
+VDDA_CPU

V1.8S_PWRGD

RC=0
+V1.8S

+V5S/+V3.3S

+V12S

to S3
SLP_S3#_3R (SB to EC)

CPU MEM CTL &

DDR3 SODIMM PWRS +V0.75S +V0.75S only will be shut down in S3 mode
M_VREF
+V1.5

SLP_S5#_3R (SB to EC)

B B
Power button from EC to SB
EC_PWRBTN#

CPU_THM/SB/SB_SCL1/2 20mS
delay
SB_KB/SPI/LPC ROM PWRS RSMRST# (EC to SB)

+V12A/+V5A/+V3.3A/+V1.1A
ALW RAILS When IMC, always on at all time( always PWR)

EC_ALW_EN (from EC)

Power button pressed

PWR_SWIN#

KBC is ready
AC not present scenario = LOW AC present= high
ACPRES
(ACIN detect)
KBC is powered by
+V3.3AL +V5AL/+V3.3AL

M31ALDO
(from DCIN)
Battery inserted/AC IN
Power on Sequence required: +VBAT

SB820: +VCC_RTC
A A
1, +V3.3A ramp before +V1.1A
2, +V3.3S ramp before +V1.8S
3, +V1.8S ramp before +V1.1S
5, +V3.3A ramping down time > 300us
6, 50uS <= All power rails except +V3.3A <= 40mS
Hon Hai Precision Industry Co. Ltd.
7, 100uS <= +V3.3A <= 40mS
Foxconn eMS Inc.
HNBD R&D phone: +886-2-2799-6111
RS880M:
1, 0 <(+V3.3S) - (+V1.8S) < 2.1 Title
2, +V1.8S ramp before +V1.1S POWER SEQUENCY TIMING
3. +V1.1S ramp before +VCC_NB Size Document Number Rev
Custom Safina MV
Page Modified: Wednesday, April 07, 2010 18:49:16 (UTC/GMT) Sheet 6 of 39
5 4 3 2 1