214446: Logic Design & Computer organization Laboratory

SEIT (2019 Course)

Semester - I
Teaching Scheme Examination Scheme
Practical : 2 Hrs. / Week Term work : 25 Marks

Practical 25 Marks

LABORATORY MANUAL V 1.0

DEPARTMENT OF INFORMATION TECHNOLOGY

Sinhgad College of Engineering, Pune
2020-2021
 VISION

To provide excellent Information Technology education by building strong teaching and research environment.

MISSION

1) To transform the students into innovative, competent and high quality IT professionals to meet the
growing global challenges.
2) To achieve and impart quality education with an emphasis on practical skills and social relevance.
3) To endeavor for continuous up-gradation of technical expertise of students to cater to the needs of
the society.
4) To achieve an effective interaction with industry for mutual benefits.
 PROGRAM EDUCATIONAL OBJECTIVES

The students of Information Technology course after passing out will

1. Possess strong fundamental concepts in mathematics, science, engineering and Technology

to address technological challenges.

2. Possess knowledge and skills in the field of Computer Science and Information Technology
for analyzing, designing and implementing complex engineering problems of any domain
with innovative approaches.

3. Possess an attitude and aptitude for research, entrepreneurship and higher studies in the
field of Computer Science and Information Technology.

4. Have commitment to ethical practices, societal contributions through communities and life-
long learning.

5. Possess better communication, presentation, time management and teamwork skills

leading to responsible & competent professionals and will be able to address challenges in
the field of IT at global level.
 PROGRAM OUTCOMES

The students in the Information Technology course will attain:

PO1 Engineering knowledge An ability to apply knowledge of mathematics,

computing, science, engineering and technology.
PO2 Problem analysis An ability to define a problem and provide a systematic
solution with the help of conducting experiments,
analyzing the problem and interpreting the data.
PO3 Design / Development of An ability to design, implement, and evaluate a software
Solutions or a software/hardware system, component, or process
to meet desired needs within realistic constraints.
PO4 Conduct Investigations of An ability to identify, formulates, and provides
Complex Problems systematic solutions to complex engineering/Technology
problems.
PO5 Modern Tool Usage An ability to use the techniques, skills, and modern
engineering technology tools, standard processes
necessary for practice as a IT professional.
PO6 The Engineer and Society An ability to apply mathematical foundations,
algorithmic principles, and computer science theory in
the modeling and design of computer-based systems
with necessary constraints and assumptions.
PO7 Environment and An ability to analyze and provide solution for the local
Sustainability and global impact of information technology on
individuals, organizations and society.
PO8 Ethics An ability to understand professional, ethical, legal,
security and social issues and responsibilities.
PO9 Individual and Team Work An ability to function effectively as an individual or as a
team member to accomplish a desired goal(s).
PO10 Communication Skills An ability to engage in life-long learning and continuing
professional development to cope up with fast changes
in the technologies/tools with the help of electives,
professional organizations and extra-curricular activities.
PO11 Project Management and An ability to communicate effectively in engineering
Finance community at large by means of effective presentations,
report writing, paper publications, demonstrations.
PO12 Life-long Learning An ability to understand engineering, management,
financial aspects, performance, optimizations and time
complexity necessary for professional practice.
 Compliance
Document Control

Reference Code SCOE-IT / Lab Manual Procedures

Version No. 1.0

Compliance Status Complete

Revision Date 17th June 2020

Security Classification Department Specific

Document Status Definitive

Review Period Yearly

Document History

Revision
Revision Date Reason For Change
No.

1.0 17th June 2020 University syllabus modification - course 2019

Summary of Changes to Digital Laboratory Manual

Sr. No Changes Change type

 PREFACE

Every day digital concepts are being applied to problems that could only be solved by analog
methods several years ago. Fast and reliable solutions using digital techniques proved the
tremendous power and usefulness of digital electronics. Nowadays digital circuits are used in
wide variety of industrial and consumer products such as automated industrial machinery, pocket
calculators, digital computers, digital watches and TV games.

This laboratory deals with the basic understanding of the digital electronics and provides thorough
understanding of principles and design of digital applications.

In the next stage of the manual computer organization simulations are discussed. Virtual lab
simulator developed by IIT Kharagpur is a tool that can be used to model CPU components.

In this laboratory theory comes alive and practical hands-on skills are learnt; a balance is struck
between theory and practice.

This laboratory manual is prepared by referring to various standard books which help the students
to perform the experiments. Students are not expected to copy the contents of the manual as it is.
They must understand the concepts given in the manual and write journal on their own. The
manual is prepared as per Savitribai Phule Pune University syllabus and accordingly the practical
assignments are discussed in the manual. However students can go beyond this set and perform
extra practical assignments.
 Syllabus 2019 Course

214446: Logic Design & Computer organization Laboratory

Teaching Scheme Credit Scheme : 1 Examination scheme
Practical: 2 hrs / week Term Work: 25 Marks
Practical: 25 Marks

Prerequisites: Basic Electronics Engineering

Course Objectives :

1. To design & implement combinational and sequential circuits.

2. To learn simulation of digital systems.

Course Outcomes :
On completion of the course, students will be able to–
CO1: Use logic function representation for simplification with K-Maps and design
Combinational logic circuits using SSI & MSI chips.
CO2: Design Sequential Logic circuits: MOD counters using synchronous counters.
CO3: Understand the basics of simulator tool & to simulate basic blocks such as ALU & memory.

List of Laboratory Assignments

Group A
Combinational Logic Design – CO1
1. Design and implement 4-bit BCD to Excess-3 code
2. Design and implement 1 digit BCD adder usingIC7483
3. Design and implement following using multiplexer IC 74153 1) full adder 2) Any three variable
function ( cascade method)
4. Design and implement full subtractor using decoder IC 74138

Group B
Sequential Logic Design - CO2
1. Design and implement 3 bit Up and 3 bit Down Asynchronous Counters using master slave JK
flip-flop IC 7476
2. Design and implement 3 bit Up and 3 bit Down Synchronous Counters using master slave JK
flip-flop IC 7476
3. Design and implement Modulo ‘N’ counter using IC7490. ( N= 100 max)

Group C
Computer organization– CO 3
Any two of following , using virtual lab simulator
1. Design& simulate single bit RAM cell OR 4 address*2bit memory using 8 single bit RAM cells.
2. Design& simulate single bit ALU with four functions(AND, OR, XOR, ADD).
3. Design& simulation of single instruction CPU.
Student should submit term work in the form of a journal based on the above assignments
(Group A, B and C). Practical examination will be based on the term work. Questions will be
asked during the examination to judge the understanding of the practical performed in the
examination. Candidate is expected to know the theory involved in the experiment.
Note - Instructor should take care that datasheets of all the required ICs are available

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 INDEX

Sr. No. Title Page No.

Group A : Combinational circuit design

1 Design & implement 4 bit Code Converter 4

a. BCD to Excess-3
b. Excess-3 to BCD
2 Design & implement BCD Adder using IC 7483 15
3 Study of Multiplexer 23
a. Verification of IC 74153
b. Realization of Boolean Expressions.
c. Combinational circuit design (Full adder and Any 3 variable function).
4 Study of Decoder 31
a. Verification of IC 74138.
b. Realization of Boolean Expressions.
c. Combinational circuit design (Full subtractor).

Group B : Sequential Logic Design

5 Design & implement 3 bit Asynchronous counter 37

a. 3 bit up Asynchronous counter
b. 3 bit down Asynchronous counter
6 Design & implement 3 bit Synchronous counter 43
a. 3 bit up Synchronous counter
b. 3 bit down Synchronous counter
7 Design & implement Modulus- N counter 51
a. Using IC 7490 (BCD counter)

Group C : Computer organization

8 Design& simulate single bit RAM cell 60

9 Design& simulate single bit ALU with four functions(AND, OR, XOR, ADD). 65

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 SCHEDULE

Sr. Title No. Of

Week
No. Hrs.
Introduction to digital laboratory & demonstration of
1. 2 1
digital trainer kit, IC tester
2. Design & implement 4 bit Code Converter. 2 2
3 Design & implement BCD Adder using IC 7483 2 3
4 Study of Multiplexer 2 4
5 Study of Decoder 2 5
6 Design & implement Asynchronous counter 2 6
7 Design & implement Synchronous counter 2 7
8 Design & implement Modulus- N counter 2 8
9 Repeat turn for Assignments 2 to 7 2 9
10 Mid-term Mock & Partial Submission 2 10
11 Demonstration of Virtual Laboratory 2 11
12 Design& simulate single bit RAM cell 2 12
Design& simulate single bit ALU with four
13 2 13
functions(AND, OR, XOR, ADD).
14 Final Mock & submission 2 14

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 1. Code Converter
Title: Code Converter

Aim: Design and implementation of 4-bit Code convertors.

i) BCD to Excess – 3 Code

ii) Excess-3 to BCD Code
IC’s Used:

IC 7404(Hex INV), 7432 (OR-gate), 7408 (AND-gate), 7486 (Ex-or gate)

Theory:
There is a wide variety of binary codes used in digital systems. Some of these codes are binary-
coded -decimal (BCD), Excess-3, Gray, octal, hexadecimal, etc. Often it is required to convert
from one code to another. For example, the input to a digital system may be in natural BCD and
output may be 7-segment LEDs. The digital system used may be capable of processing the data
in straight binary format. Therefore, the data has to be converted from one type of code to another
type for different purpose. The various code converters can be designed using gates.

1. BCD Code:

Binary Coded Decimal (BCD) is used to represent each of decimal digits (0 to 9) with a 4-bit
binary code. For example (23)10 is represented by 0010 0011 using BCD code rather than(10111)2
This code is also known as 8-4-2-1 code as 8421 indicates the binary weights of four bits(2 3, 22,
21, 20). It is easy to convert between BCD code numbers and the familiar decimal numbers. It is
the main advantage of this code. With four bits, sixteen numbers (0000 to 1111) can be
represented, but in BCD code only 10 of these are used. The six code combinations (1010 to 1111)
are not used and are invalid.

Applications: Some early computers processed BCD numbers. Arithmetic operations can be
performed using this code. Input to a digital system may be in natural BCD and output may be 7-
segment LEDs.

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It is observed that more number of bits are required to code a decimal number using BCD code
than using the straight binary code. However, in spite of this disadvantage it is very convenient
and useful code for input and output operations in digital systems.

Fig. 3 BCD Coded Decimal Representation

2. EXCESS-3 Code:

Excess-3, also called XS3, is a non-weighted code used to express decimal numbers. It can be
used for the representation of multi-digit decimal numbers as can BCD.The code for each decimal
number is obtained by adding decimal 3 and then converting it to a 4-bit binary number. For e.g.
decimal 2 is coded as 0010 + 0011 = 0101 in Excess-3 code.

This is self-complementing code which means 1’s complement of the coded number yields 9’s
complement of the number itself. Self-complementing property of this helps considerably in
performing subtraction operation in digital systems, so this code is used for certain arithmetic
operations.

BCD to Excess – 3 Code Conversion:

Convert BCD 2 i. e. 0010 to Excess – 3 code

For converting 4 bit BCD code to Excess – 3, add 0011 i. e. decimal 3 to the respective code using
rules of binary addition.
0010 + 0011 = 0101 – Excess – 3 code for BCD 2

Excess – 3 Code to BCD Conversion:

The 4-bit Excess-3 coded digit can be converted into BCD code by subtracting decimal value 3
i.e. 0011 from 4 bit Excess-3 digit.
e.g. Convert 4-bit Excess-3 value 0101 to equivalent BCD code.
0101-0011= 0010- BCD for 2

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A. BCD To Excess-3 Code Conversion: Truth Table:

INPUT (BCD CODE) OUTPUT (EXCESS-3 CODE)

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x X x x

1 0 1 1 x X x x

1 1 0 0 x X x x

1 1 0 1 x X x x

1 1 1 0 x X x x

1 1 1 1 x X x x

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2) K-Map For Reduced Boolean Expressions Of Each Output:

Fig. 8 K-Map For Reduced Boolean Expressions Of Each Output (Excess-3 Code)

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3) Circuit Diagram:

BCD TO EXCESS-3 CONVERTER

Fig.9 Logic Diagram for BCD to Excess-3 Code Conversion

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4) Hardware Requirements Table:

GATE Quantity IC Quantity

XOR 1 7486 1

NOT 4 7404 1

AND 4 7408 1

OR 3 7432 1

Table 5 Hardware Requirement Table

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B. Excess-3 To BCD Conversion: Truth Table:

INPUT (EXCESS-3 CODE) OUTPUT (BCD CODE)

E3 E2 E1 E0 B3 B2 B1 B0

0 0 0 0 X X X X

0 0 0 1 X X X X

0 0 1 0 X X X X

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

1 1 0 1 X X X X

1 1 1 0 X X X X

1 1 1 1 X X X X

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Fig 10 K-Map For Reduced Boolean Expressions Of Each Output (BCD Code)

3) Circuit Diagram: EXCESS-3 TO BCD CONVERTER

B2 = E2’E0’+E2’E1’+E2E1E0

=E2’(E1’+E0’)+E2E1E0

=E2’(E1E0)’+E2(E1E0)

B2 = E2 XNOR E1E0

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 Fig.11 Logic Diagram for Excess-3 to BCD Conversion

4) Hardware Requirements Table:

GATE Quantity IC Quantity

XOR 2 7486 1

NOT 2 7404 1

AND 4 7408 1

OR 1 7432 1

Table 5 Hardware Requirement Table

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Test the circuit for all possible combinations of input and output codes.

Conclusion:

Thus, we studied different codes and their conversions including applications.

The truth tables have been verified using IC 7486, 7432, 7408, and 7404.
FAQ’s with answers:

Q.1) What is the need of code converters?

There is a wide variety of binary codes used in digital systems. Often it is required to convert
from one code to another. For example the input to a digital system may be in natural BCD and
output may be 7-segment LEDs. The digital system used may be capable of processing the data
in straight binary format. Therefore, the data has to be converted from one type of code to another
type for different purpose.

Q.2) What is Gray code?

It is a modified binary code in which a decimal number is represented in binary form in such a
way that each Gray- Code number differs from the preceding and the succeeding number by a
single bit.

(e.g. for decimal number 5 the equivalent Gray code is 0111 and for 6 it is 0101. These two codes
differ by only one bit position i. e. third from the left.) It is non weighted code.

Q.3) What is the significance of Gray code?

Important feature of Gray code is it exhibits only a single bit change from one code word to the
next in sequence. Whereas by using binary code there is a possibility of change of all bits if we
move from one number to other in sequence (e.g. binary code for 7 is 0111 and for 8 it is 1000).
Therefore it is more useful to use Gray code in some applications than binary code.

Q.4) What are applications of Gray code?

1. Important feature of Gray code is it exhibits only a single bit change from one code word to
the next in sequence. This property is important in many applications such as Shaft encoders

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where error susceptibility increases with number of bit changes between adjacent numbers in
sequence.

2. It is sometimes convenient to use the Gray code to represent the digital data converted from
the analog data (Outputs of ADC).

3. Gray codes are used in angle-measuring devices in preference to straight forward binary
encoding.

4. Gray codes are widely used in K-map

Q.5) What are weighted codes and non-weighted codes?

In weighted codes each digit position of number represents a specific weight. The codes 8421,
2421, and 5211 are weighted codes. Non weighted codes are not assigned with any weight to each
digit position i.e. each digit position within the number is not assigned a fixed value. Gray code,
Excess-3 code are non-weighted code.

Q.6) Why Excess-3code is called as self-complementing code?

Excess-3 code is called self-complementing code because 9’s complement of a coded number
can be obtained by just complementing each bit.

Q.7) What is invalid BCD?

With four bits, sixteen numbers (0000 to 1111) can be represented, but in BCD code only 10 of
these are used as decimal numbers have only 10 digits from 0 to 9. The six code combinations
(1010 to 1111) are not used and are invalid.

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 2. BCD Adder

AIM: To design & implement of single digit BCD adder using IC 7483.

OBJECTIVE: 1. To study the BCD arithmetic rules.

2. Comparison between binary and BCD codes.

IC’s USED:

IC 7483 (4 bit Binary adder), IC 7404(Hex INV), 7432 (OR-gate), 7408 (AND-gate), 7486 (EX-
OR gate)

THEORY:

BCD Adder:
BCD adder is a circuit that adds two BCD digits & produces a sum of digits also inBCD.
Rules for BCD addition:
1. Add two numbers using rules of Binary addition.
2. If the 4 bit sum is greater than 9 or if carry is generated then the sum is invalid. To correct
the sum add 0110 i.e. (6)10 to sum. If carry is generated from this addition add it to next
higher order BCD digit.
3. If the 4 bit sum is less than 9 or equal to 9 then sum is in proper form.
CASE I : Sum <= 9 & carry = 0.

Add BCD digits 3 & 4

1. 0011
+ 0100
---------
0111
Answer is valid BCD number = (7) BCD& so 0110 is not added.

CASE II : Sum > 9 & carry = 0.

Add BCD digits 6 & 5
1. 0110
+ 0101
-----------
10 1 1

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Invalid BCD (since sum > 9) so 0110 is to be added

2. 1011

+0 1 1 0

-----------

1 0001

(1 1)BCD

Valid BCD result = (11) BCD

CASE III : Sum < = 9 & carry = 1.

Add BCD digits 9 & 9

1. 1001

+ 1001

-----------

10010

Invalid BCD (since Carry = 1) so 0110 is to be added

2. 1 0010
+0 1 1 0

------------

11000

(1 8)
Valid BCD result = (18) BCD

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Design of BCD adder :

1. To execute first step i.e. binary addition of two 4 bit numbers we will use IC 7483
( with Cin = 0 ), which is 4 bit binary adder.
2. We need to design a digital circuit which will sense sum & carry of IC 7483 & if sum
exceeds 9 or carry = 1, this digital circuit will produce high output otherwise its output
will be zero.

Circuit to check invalid BCD :

First we will design circuit to check sum & then we will logically OR output of this circuit
to carry output of IC 7483
For digital circuit which we are going to design we will have 4 inputs
( S3, S2, S1, S0) & only 1 output Y.
a) Y output of this circuit. Will be ORed with carry output of first adder IC
7483.
b) If BCD result is invalid i e. sum output of first 7483 we have to add
(6)10 i.e. (0110)2 that means we need one more binary adder IC 7483.

c) If BCD result is valid (i.e. final output of the circuit to check validity is 0) we
will make an arrangement that second adder IC 7483 adds (0)10 i.e. ( 0000 )2
to the sum of the first adder IC 7483. The output of the combinational circuit is
used as final output carry & carry output of second adder IC is ignored.

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i) Truth Table for design of combinational circuit for BCD adder to check invalid
BCD:

INPUT OUTPUT

S3 S2 S1 S0 Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

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 ii) K-map for reduced Boolean expressions of output :

S3S2
S1S0 00 01 11 10
0 0 1 0
00
0 0 1 0
01
0 0 1 1
11
0 0 1 1
10
Y = S3S2 + S3S1

iii) Circuit diagram:

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iv) Circuit diagram for BCD adder :

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v) Hardware Requirements:

GATE Quantity IC Quantity

Binary adder 2 7483 2

AND 2 7408 1

OR 2 7432 1

OBSERVATION :

BCD adder :

INPUT OUTPUT

1st Operand 2nd Operand MSD LSD

A0 B3 B0 S3 S0
A3 S S
A2 A1 (LSB (MS B2 B1 (LSB Cout (MS (LSB
(MSB) 2 1
) B) ) B) )

CONCLUSION :
BCD adder is designed & tested for all possible combinations.

FAQ’s:
1. Explain and Write the significance of. BCD number system
2. Write the applications of BCD & Excess 3 code.
3. Explain the rules of BCD & Excess 3 arithmetic.

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4. What is the difference between BCD and binary codes?
5. What do you mean by unpacked and packed BCD nos.?

PRACTISE ASSIGNMENTS / EXERCISE / MODIFICATIONS:

1. Design & implement two digit BCD adder using IC 7483.
2. Design & implement single digit BCD subtractor using 10’s complement method.
3. Design & implement 9’s complementer.

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 3. Study of Multiplexer

AIM: MUX IC 74153

1) Verification of IC.
2) Implementation of 8:1 Mux by cascading 2, 4:1 mux in IC 74153
3) Boolean function implementation
4) Full adder implementation using hardware reduction table.

OBJECTIVES:
1. To study the multiplexer.
2. To study the applications of multiplexer.
IC’s USED :
IC 74153, 74138, 7404, 7432.
THEORY :
Digital Multiplexer:
Multiplexer are combinational digital circuits equating as controlled switches
with several data inputs (I0, I1, I2 …) & one single data output (“out”). At any time one of the I/p
is transmitted to output, according to binary signals applied on select inputs. Usually the number
of data inputs is a power of two. Multiplexing is the process of transmitting a large no. of
information units over a small no. of channel / digital multiplexer is a combinational logic circuit
which performs the operation of multiplexing. Multiplexer is called a data selector or
multiposition switch because it selects one of the many inputs. Selection of a particular line is
controlled by a set of a selection lines or selects inputs. Block diagram of MUX is shown, it
contains ‘2m’ data input lines, ‘m’ select lines & one enable input which is used to activate or
deactivate MUX. Depending upon the no. of I/P & O/P lines various types of multiplexers are
available. We have 2:1, 4:1, 8:1, 16:1 MUX. Here the first no. indicates the no. of input lines &
second no. indicates the no. of output lines.
Demultiplexer:
Demultiplexer is a logic used to perform exactly reverse function performed by
multiplexer. It accepts a single input and distributes among several outputs. The selection of a
particular output line is controlled by a set of selection line. There are n input lines & 2 m is the
number of selection line whose bit combinations determine which output to be selected.

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Difference between Multiplexer, De-multiplexer& Decoder
Point Multiplexer Demultiplexer Decoder
Input Many input lines Single input line Many input line also Acts
as select line
Output Single output line Many output lines Many output line, Active
low output
Select line 2m = n n = 2m Enable inputs used

Uses of Mux. :
1) Used for Boolean function implementation
2) Construct a common bus system.
3) To select between multiple sources & single destination.
4) Inter register transfer.
Advantages :
1) Simplification of logic expression not required.
2) Logic design is simplified.

Disadvantages :
To implement Boolean function with multiple outputs, multiple multiplexers are
required
(IC 74153)
1. VERIFICATION OF IC 74153 :
IC 74153 is a dual layer 4:1 MUX. It has four input lines for (I 0D-I3D) for second MUX & active
high output. ‘Ya’, ‘Yb’ (1Y or 2Y). It has select lines S1S0 common to both MUX. The Enable
inputs are active low, Ea&Eb(1G and 2G). The MUX is activated when they are at logic o.

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Pin out of IC 74153:

Function table of IC 74153: (X= Don’t Care Condition)

Inputs (I or II) Output

S1 Select
S0 EInput
(I or II) D0 D1 D2 D3 Y
X X 1 X X X X 0
0 0 0 0 X X X 0
0 0 0 1 X X X 1
0 1 0 X 0 X X 0
0 1 0 X 1 X X 1
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1
1 1 0 X X X 0 0
1 1 0 X X X 1 1

2.CASCADING OF IC 74153:
Cascading is done to expand two or more MUX IC’s to a digital multiplexer with larger no. of
inputs i.e. multiplexer stocks or tress is designed. The enable input is used for cascading. In case
of IC 74153 we have only two select lines. But for certain applications, 3 select lines are
required then it can be obtained by cascading using enable. Now with 3 select lines we have
8 combinations. Out of this combination the MSB is O. MSB is 1 for last four combination so

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we can use these MSB to select any 1 MUX out of two by connecting it to E pin of first 4:1
MUX .

Logic Diagram

Function table of IC 74153 as 8: 1 Mux by cascading 2, 4:1 Mux :

Select Input Output

C (1G / 2G ) B (S1) A (S0) Y

0 0 0 D0

0 0 1 D1

0 1 0 D2

0 1 1 D3

1 0 0 D4

1 0 1 D5

1 1 0 D6

1 1 1 D7

3.FUNCTION IMPLEMENTATION:
Y= ∑ m (1, 3, 5, 6)
This expression is in Standard SOP form and it is three variable function. So, we need to use mux
with three select inputs i.e. 8:1 Mux. Already we have implemented 8:1 Mux using IC 74153. For
Boolean function in Standard SOP form we connect data inputs corresponding to the minterms
present in the given function to Vcc and remaining data inputs to ground.

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Truth table :

Inputs Output
C B A Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1

1 1 0 1

1 1 1 0

LOGIC DIAGRAM :

Hardware Requirements :

GATE Quantity IC Quantity

Mux. 1 74153 1

NOT 1 7404 1

OR 1 7432 1

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4. IMPLEMENTATION OF FULL ADDER USING IC 74153:

A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists
of three inputs and two outputs. Two of these variables denoted by A and B represent the two
significant bits to be added. The third input represents the carry from previous lower significant
position.

Truth Table for Design of full adder:

Input Output

A B C Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Sum= ∑m (1, 2, 4, 7), Carry=∑m (3, 5, 6, 7)

Hardware reduction table for Sum:

D0 D1 D2 D3
A 0 1 2 3

A 4 5 6 7

i/p to MUX A A A A

LDCO Laboratory SCOEIT 28 / 87

Hardware reduction table for Carry:

D0 D1 D2 D3
A 0 1 2 3

A 4 5 6 7

i/p to MUX 0 A A 1

Logic Diagram of Full Adder using IC 74153:

Hardware Requirements :

GATE Quantity IC Quantity

Mux. 1 74153 1

NOT 1 7404 1

Conclusion :In this way multiplexer applications are studied , implemented &
tested.

LDCO Laboratory SCOEIT 29 / 87

FAQ’s:
1. What is a multiplexer?
2. What is a Demultiplexer?
3. Enlist applications of multiplexer.
4. What is the difference between multiplexer &demultiplexer?

PRACTICE ASSIGNMENTS / EXERCISE / MODIFICATIONS:

1. Implement 16:1 mux by cascading 4, 4:1 mux using IC 74153.
2. Implement full subtractor using hardware reduction table.

LDCO Laboratory SCOEIT 30 / 87

 4. Study of Decoder

AIM:
Decoder IC 74138
1) Verification of IC.
2) Decoder Cascading
3) Boolean function implementation.

OBJECTIVE:
1. To study the difference between multiplexer, de-multiplexer and decoder.
2. To study the applications of decoder.
IC’s USED :
IC 74138, 7404, 7432.
THEORY :

Decoder (IC 74138)

Discrete quantities of information are requested in digital system with binary codes. A binary
code of n bits is capable of representing into 2n distinct elements of the coded information.
Decoder converts coded input to coded outputs accepts one of the code.
There are different types of decoders such as 3:8 decoder, 4:16 line decoders etc. These are in
general called as n: m line decoder where m=2 n and n= no. of input lines and m=no. of output
lines.
Demux also takes one input data line source and selectively distributes it to one of n output
channels. The only difference between demux and decoder is that demux has Din (data i/p) line
whereas decoder does not have.

ADVANTAGES:
1) The decoder provides best implementation whenever there are many outputs of the
combinational circuit and each o/p of the function (or its complement) is required to be
expressed with a small no. of minterms.
2) The decoder can function as demux. If the Enable i/p line is taken as Din (data i/p) .

DISADVANTAGES:
Since decoder method requires an OR gate for each o/p function, so there is new hardware used.
And it is always advisable to use minimum hardware as we come across problems like
propagation delay of gates.

LDCO Laboratory SCOEIT 31 / 87

APPLICATIONS:
Decoder is worthily used for decoding binary information and memory interfacing. It is used for
the implementation of Boolean function.

A) Verification of IC 74138:
We use IC 74138 which accepts 3 binary weighted inputs (A0, A1, A2) and when enabled
provides mutually exclusive active low outputs (y0-y7). It features 3 Enable i/ps. Two active low
(G2A, G2B) and one active high (G1). Every output will be high unless G2A, G2B are low and
G1 is high. It has demultiplexing capability and multiple enable i/ps for easy expansion.

Function Table of 3:8 decoder:

Input Output

Enable Data
G2A G2B G1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

0 0 0 X X X 1 1 1 1 1 1 1 1

0 1 1 X X X 1 1 1 1 1 1 1 1

1 0 1 X X X 1 1 1 1 1 1 1 1

1 1 1 X X X 1 1 1 1 1 1 1 1

0 0 1 0 0 0 0 1 1 1 1 1 1 1

0 0 1 0 0 1 1 0 1 1 1 1 1 1

0 0 1 0 1 0 1 1 0 1 1 1 1 1

0 0 1 0 1 1 1 1 1 0 1 1 1 1

0 0 1 1 0 0 1 1 1 1 0 1 1 1

0 0 1 1 0 1 1 1 1 1 1 0 1 1

0 0 1 1 1 0 1 1 1 1 1 1 0 1

0 0 1 1 1 1 1 1 1 1 1 1 1 0

B) Cascading of IC 74138:
The enable i/p G1 active high of IC 74138 is used for cascading. For cascading 2 IC’s, the enable
i/p G1 of first IC is connected to G1 enable i/p of second IC through a NOT gate. This enable i/p
is used as MSB select i/p line A3. the other three select input lines of both IC’s (A0, A1, A2) are
also shorted to select input lines of second IC to get single i/p select lines (A0,A1,A2).
The i/p line A3 is used to enable /disable the 2 IC 74138 decoders. When A3=0, first IC is enabled
and second is disabled. Thus the first decoder will generate minterms from 0000 to 0111 as o/p
and the second decoder will generate nothing. When A3=1, the enable conditions are reversed
and thus second decoder IC will generate minterms 1000 to 1111.

LDCO Laboratory SCOEIT 32 / 87

Function Table of 4:16 decoder using IC 74138 (3:8 decoder):

Input Output

Enable Data
G2A G2B A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15

0 1 X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 0 X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

0 0 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1

0 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1

0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1

0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1

0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1

0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1

0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1

0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1

0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1

0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1

0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

LDCO Laboratory SCOEIT 33 / 87

C) Implementation of Boolean function:
The procedure for implementation of combinational circuit by means of a decoder and ‘OR’ gates
requires that the Boolean function fir the circuit be expressed in Sum of Minterms. These forms
can be obtained by expanding the function. A decoder is then chosen which generates all the
minterms of n i/p variables. The i/p to each OR gate are selected from the decoder outputs
according to the minterms list in each function.
For example, F1=∑m (1, 3, 5, 7) and F2=∑m (2, 3, 6, 7)

LDCO Laboratory SCOEIT 34 / 87

D) Implementation of Full Subtractor:
First of all we need to decide on which type of decoder the above Boolean function can be
implemented. The highest minterm is 7 and minimum no. of bits required to represent it in binary
form are 3. So we have 3 select lines in 3:8 decoders so we can use IC 74138.
To implement the function, we require NOT and OR or AND and NAND gate (7408 & 7400).
As the o/p of the decoder IC 74138 are active low and we need to get o/p active high at the o/p
pin of the function DIFFERENCE and BORROW when respective minterms are selected.
Truth Table for design of Full Subtractor:

INPUT OUTPUT

A2 A1 A0 DIFFERENCE BORROW

A B C
0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

DIFFERENCE=∑m (1, 2, 4, 7), BORROW=∑m (1, 2, 3, 7)

LDCO Laboratory SCOEIT 35 / 87

Conclusion :In this way Decoder & its applications are studied , implemented &
tested.
FAQ’s:
1. What is a Decoder?
2. Enlist applications of Decoder.
3. Define the terms Encoder and Decoder.
4. What is the difference between decoder &demultiplexer?

PRACTICE ASSIGNMENTS / EXERCISE / MODIFICATIONS:

1. Implement 4 bit BCD to EXCESS 3 code converter using decoder IC 74138.
2. Implement full adder using decoder IC 74138.

LDCO Laboratory SCOEIT 36 / 87

 5. Asynchronous Counter

AIM: To design and implement 3 bit UP, Down Asynchronous Counter using MS-JK Flip-flop.

OBJECTIVE: To understand design procedure of asynchronous counter.

ICs USED : IC 7476 (MS-JK Flip-flop),

THEORY:

Counters : counters are logical device or registers capable of counting the no. of states or no.
of clock pulses arriving at its clock input where clock is a timing parameter arriving at regular
intervals of time, so counters can be also used to measure time & frequencies. They are made
up of flip flops. Where the pulse is counted to be made of it goes up step by step & the o/p of
counter in the flip flop is decoded to read the count to its starting step after counting n pulse in
case of module counters.
Types of Counters:

Counter are of two types:

1) Asynchronous counter.

2) Synchronous counter.

Asynchronous counter:

A digital counter is a set of flip flop. The flip flops are connected such that their combined state
at any time is binary equivalent of total no. of pulses that have occurred up to that time. Thus its
name implies a counter is used to count pulse. A counter is used as frequency dividers. To obtain
waveform with frequency that is specific fraction of clock frequency.
Counter may be Asynchronous or synchronous. The Asynchronous counter is also
called as ripple counter. An Asynchronous counter uses T flip flop to perform a counting function.
The actual hardware used is usually J-K flip flop with J & K connected to logic1.Even D flip
flops may be used here.
In asynchronous counter commonly called ripple counter, the first flip-flop is clocked by the
external clock pulse & then each successive flip-flop is clocked by the Q or Q’ output of the
previous flip-flop. Therefore, in an asynchronous counter the flip-flops are not clocked
simultaneously. The input of MS-JK is connected to VCC because when both inputs are one

LDCO Laboratory SCOEIT 37 / 87

output is toggled. As MS-JK is negative edge triggered at each high to low transition the next
flip-flop is triggered.
Synchronous Counter:

When counter is clocked such that each flip flop in the counter is
triggered at the same time, the counter is called as synchronous counter.
The gates propagation delay at reset time will not be present or we may say will not occur.
1) Asynchronous Up Counter:

Fig. 1 shows 3bit Asynchronous Up Counter. Here Flip-flop 2 act as a MSB Flip-flop and Flip-
flop 0 act as a LSB Flip-flop. Clock pulse is connected to the Clock of Flip-flop 0. Output of Flip-
flop 0(Q0) is connected to clock of next flip-flop (i.e Flip-flop 1) and so on. As soon as clock
pulse changes output is going to change (at the negative edge of clock pulse) as a Up count
sequence. For 3 bit Up counter state table is as shown below.
State Table:

Counter States Count

Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0

LDCO Laboratory SCOEIT 38 / 87

Logic diagram :

Fig 1: 3 Bit Asynchronous Up Counter

Hardware requirements :

Gate /
IC Quantity
Flip flop Quantity

MS JK 3 7476 2

Waveforms:

LDCO Laboratory SCOEIT 39 / 87

2) Down Counter:

Fig. 2 shows 2-bit Asynchronous Down Counter. Here Flip-flop 2 act as a MSB Flip-flop and
Flip-flop 0 act as a LSB Flip-flop. Clock pulse is connected to the Clock of Flip-flop 0. Output of
Flip-flop 0 (Q0’) is connected to clock of next flip-flop (i.e Flip-flop 1) and so on. As soon as
clock pulse changes output is going to change (at the negative edge of clock pulse) as a down
count sequence. For 3 bit down counter sate table is as shown below.
In both the counters Inputs J and K are connected to Vcc, hence J-K Flip flop work in toggle
mode. Preset and Clear both are connected to logic 1.

State Table:

Counter States Count

Q2 Q1 Q0
7 1 1 1
6 1 1 0
5 1 0 1
4 1 0 0
3 0 1 1
2 0 1 0
1 0 0 1
0 0 0 0
7 1 1 1

Logic diagram :

Fig 2: 3 Bit Asynchronous Down Counter

LDCO Laboratory SCOEIT 40 / 87

Hardware requirements :

Gate /
IC Quantity
Flip flop Quantity

MS JK 3 7476 2

Waveforms:

Applications :

The asynchronous counters are specially used as the counting devices.

They are also used to count number of pulses applied.
It also works as frequency divider.
It helps in counting the number of product coming out of the machinery where product is coming
out at equal interval of time.

Conclusion:

Asynchronous up and down counters are successfully implemented, the counters are studied &
o/p are checked. The state table is verified.

LDCO Laboratory SCOEIT 41 / 87

PRACTICE ASSIGNMENTS / EXERCISE / MODIFICATIONS:

1. Design & implement 2 bit controlled Asynchronous counter.

2. Design& implement 4 bit controlled Asynchronous counter.
3. Design& implement truncated Asynchronous up or down counter.
FAQ’s with answers:

1. What do you mean by Counter?

A Counter is a register capable of counting the no. of clock pulses arriving at its
clock inputs. Count represents the no. of clock pulses arrived. A specified
sequence of states appears as the counter output.

2. What are the types of Counters? Explain each.

There are two types of counters as Asynchronous Counter and Synchronous Counter.
Asynchronous Counter: In this counter, the first flip-flop is clocked by the external clock
pulse and then each successive flip-flop is clocked by the Q or Q’ o/p of the previous flip-
flop. Hence in Asynchronous Counter flip-flops are not clocked simultaneously and hence
called as Ripple Counter. Synchronous Counter: In this counter, the common clock input
is connected to all the flip-flops simultaneously.

3. What do you mean by pre-settable counters?

A counter in which starting state is not zero can be designed by making use of the
preset inputs of the flip flops. This is referred to as loading the counter
asynchronously. This is referred to as pre-settable counter.

4. What are the advantages of synchronous counters over asynchronous counters?

Propagation delay time is reduced.
Can operate at a much higher frequency than the asynchronous counters.

LDCO Laboratory SCOEIT 42 / 87

 6. Synchronous Counter

AIM: To design and implement 3 bit UP, Down Synchronous Counter using MS-JK Flip-flop.

OBJECTIVE: To understand design procedure of Synchronous counter.

ICs USED : IC 7476 (MS-JK Flip-flop), IC 7408(Quad 2 i/p AND Gate),

IC 7432 (Quad 2 i/p OR Gate) and IC 7404 (Hex Inverter).

THEORY: Types of synchronous counter:

1) Up counter.

2) Down counter.

1. 3 bit Synchronous up counter:

The up counter counts from 0 to7 i.e.(000 to 111).for this we are using MS JK
flip flop. In IC 74LS76, 2 MS J-K flip flops are present. The clock pulse is given at pin 1 & 6 of
the 1st IC & pin 1 of 2nd IC. Next state decoder logic is designed with the help of state table.

State table for synchronous up counter:

Present state Next state Flip flop 3 Flip flop 2 flip flop 1

Q2 Q1 Q0 Q2 Q2 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0 x 0 X 1 x

0 0 1 0 1 0 0 x 1 X x 1

0 1 0 0 1 1 0 x x 0 1 x

0 1 1 1 0 0 1 x x 1 x 1

1 0 0 1 0 1 x 0 0 X 1 X

1 0 1 1 1 0 x 0 1 X x 1

1 1 0 1 1 1 x 0 x 0 1 X

1 1 1 0 0 0 x 1 x 1 x 1

LDCO Laboratory SCOEIT 43 / 87

K-Map :

Q1Q0 00 01 11 10

Q2

0 0 0 1 0

1 X X X X

J2= Q1Q0

Q1Q0 00 01 11 10

Q2

0 X X X X

1 0 0 1 0

K2= Q1Q0

Q1Q0 00 01 11 10

Q2

0 0 1 X X

1 0 1 X X

J1= Q0

Q1Q0 00 01 11 10

Q2

0 X X 1 0

1 X X 1 0

K1= Q0

LDCO Laboratory SCOEIT 44 / 87

 Q1Q0 00 01 11 10

Q2

0 1 X X 1

1 1 X X 1

J0= 1

Q1Q0 00 01 11 10

Q2

0 X 1 1 X

1 X 1 1 X

K 0= 1

Logic Diagram:

Fig 1: 3 bit Synchronous up counter

LDCO Laboratory SCOEIT 45 / 87

 2. 3 bit Synchronous down counter:

This is used to count from 7-0 i.e.(111-000).for this also 2 IC’s of 74LS76 are required & hence
we use 3 MS JK flip flops. Here also clock is given to 1st& 6th pin of 1st IC &1st pin of 2nd IC
enabling to apply clock to all flip flop at a time. Next state decoder logic is designed with the help
of state table.
State table for synchronous down counter :

Present state Next state Flip flop 3 Flip flop 2 Flip flop 1

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

1 1 1 1 1 0 X 0 X 0 X 1

1 1 0 1 0 1 X 0 X 1 1 X

1 0 1 1 0 0 X 0 0 X X 1

1 0 0 0 1 1 X 1 1 X 1 X

0 1 1 0 1 0 0 X X 0 X 1

0 1 0 0 0 1 0 X X 1 1 X

0 0 1 0 0 0 0 X 0 X X 1

0 0 0 1 1 1 1 X 1 X 1 X

K-Map :

Q1Q0 00 01 11 10

Q2

0 1 0 0 0

1 X X X X

J2= Q1Q0

LDCO Laboratory SCOEIT 46 / 87

 Q1Q0 00 01 11 10

Q2

0 X X X X

1 1 0 0 0

K2= Q1Q0

Q1Q0 00 01 11 10

Q2

0 1 0 X X

1 1 0 X X

J1= Q0

Q1Q0 00 01 11 10

Q2

0 X X 0 1

1 X X 0 1

K1= Q0

Q1Q0 00 01 11 10

Q2

0 1 X X 1

1 1 X X 1

J0= 1

LDCO Laboratory SCOEIT 47 / 87

 Q1Q0 00 01 11 10

Q2

0 X 1 1 X

1 X 1 1 X

K 0= 1

Logic Diagram :

Fig 2: 3 bit Synchronous down counter

Uses:

1. Specially used as the counting devices.

2. Used in frequency divider circuit.
3. Used in digital voltmeter.
4. Used in counter type A to D converter.

LDCO Laboratory SCOEIT 48 / 87

 5. Used for time measurement..
6. It helps in counting the no of product coming out from machinery where product is
coming out at equal interval of time.
Conclusion:

Up and down counters are successfully implemented, the counters are studied & o/p are
checked. The state table is verified.

PRACTICE ASSIGNMENTS / EXERCISE / MODIFICATIONS:

1. Design & implement 2 bit controlled synchronous counter.

2. Design& implement 4 bit controlled synchronous counter.
3. Design& implement truncated synchronous up or down counter.
FAQ’s with answers:

1. What are the applications of synchronous counters?

Digital clock
Frequency divider circuits
Frequency counters
Used in analog to digital converters
2. What are the advantages of synchronous counters over asynchronous counters?
Propagation delay time is reduced.
Can operate at a much higher frequency than the asynchronous counters.
3. Ring counter is an example of synchronous counters or asynchronous counter?
Synchronous counter. Since all the flip flops are clocked simultaneously.

4. Twisted Ring (Johnson’s) counter is an example of synchronous counters or asynchronous

counter?
Synchronous counter. Since all the flip flops are clocked simultaneously.

5. What is the difference between ring counter and twisted ring counter?
In ring counter pulses to be counted are applied to a counter , it goes from state to state
and the output of the flip flop s in the counter is decoded to read the count. Here the

LDCO Laboratory SCOEIT 49 / 87

 uncomplimentary output (Q) of last flip flop is fed back as an input to first flip flop. Ring
counters are referred as MOD ‘N’ counters.

But in Twisted ring counter the complimentary output (Q bar) of last flip flop is fed back
as an input to first flip flop. Twisted Ring counters are referred as MOD ‘2N’ counters.

6. What are the applications of ring counters?

Ring counter outputs are sequential non-overlapping pulses which are useful for control
state counters, Used in stepper motor, this requires pulses to rotate it from one position to
the next. Used as divide by ‘N’ ((MOD ‘N’) counters.

7. What are the applications of ring counter twisted ring counters?

Used as divide by ‘2N’ ((MOD ‘2N’) counters.
Used for control state counters.
Used for generation of multiphase clock.
8. List the Synchronous Counter ICs.
IC 74160 : Decade Up Counter
IC 74161 : 4 bit binary Up Counter
IC 74162 : Decade Up Counter
IC 74163 : 4 bit binary Up Counter
IC 74168 : Decade Up/Down Counter
IC 74169 : 4 bit Binary Up/Down Counter
IC 74190 : Decade Up/Down Counter
IC 74191 : 4 bit Binary Up/Down Counter
IC 74192 : Decade Up/Down Counter
IC 74193 : 4 bit Binary Up/Down Counter

LDCO Laboratory SCOEIT 50 / 87

 7. Modulus n Counter

AIM: To design and implement mod - 10, mod – 7, mod - 99 asynchronous BCD counter using
IC 7490.
OBJECTIVE: To know difference between regular & truncated counter as well as binary &BCD
Counter

IC’s USED: IC 7490, basic gates.

THEORY: IC 7490

IC 7490 is a TTL MSI (medium scale integration) decade counter. It contains 4 master
slave flip flops internally connected to provide MOD-2 i.e. divide by 2 and MOD-5 i.e. divide by
5 counters. MOD-2 and Mod-5 counters can be used independently or in cascading.
It is a 4-bit ripple type decade counter. The device consists of 4-master slave flip flops
internally connected to provide a divide by two and divide by 5 sections. Each section has a
separate clock i/p to initiate state changes of the counter on the high to low clock transition.
Since the o/p from the divide by 2 section is not internally connected to the succeeding
stages. The device may be operated in various counting modes. In a BCD counter the CP 1 input
must be externally connected to QA o/p. The CP0 i/p receives the incoming count producing a BCD
count sequence. It is also provided with additional gating to provide a divide by 2 counter and
binary counter for which the count cycle length is divide by 5. The device may be operated in
various counting modes.
There are 2 reset inputs R0(1) and R0(2) both of which need to be connected to the ‘logic
1’ for clearing all flip flops. Two set inputs Rg(1) and Rg(2) when connected to logic 1 are used
for setting counter to 1001 (BCD 9).

LDCO Laboratory SCOEIT 51 / 87

Pin out of IC 7490:

U1

14 INA QA 12
1 INB QB 9
QC 8
2 R01 QD 11
3 R02
6 R91
7 R92

7490N

Basic internal Structure of IC 7490:

LDCO Laboratory SCOEIT 52 / 87

Function Table of MOD-2 counter:

Input A clock Output Count

0 0

1 1

Function Table of MOD-5 counter:

InputB clock Output

QD QC QB Count

0 0 0 0

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 4

Design of MOD-10 counter using IC 7490:

The QA o/p the first flip flop is connected to the input B which is clock i/p of internal
MOD-5 ripple counter. Due to cascading of Mod-2 and Mod-5 counters, the overall configuration
the decade counters count from 0000 to 1001. After 1001 mod-5 resets to 0000 and next count
after 1001 is 0000.
When QA o/p is connected to B i/p, we have the Mod-2 counter followed by Mod-5
counter. The count sequence obtained is shown in the table. It may be noted that QA changes

LDCO Laboratory SCOEIT 53 / 87

from 0 to 1 the state of Mod-5 counter doesn’t change, whereas when QA changes from 1 to 0
the Mod-5 counter goes to the next state.

Logic DiagramMOD-10 counter using IC 7490:

LDCO Laboratory SCOEIT 54 / 87

Function table:

I/p clock Output

QD QC QB QA Count

0 0 0 0 0

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 7

1 0 0 0 8

1 0 0 1 9

LDCO Laboratory SCOEIT 55 / 87

 Timing diagram of mod10:

CLK

0 1 0 0 1 0 1 0 1 0
1
QA

0 0 0 0 1 0 0 0
1 1 1
QB

0 0 0 0 1 1 1 1 0 0 0
QC

0 0 0 0 0 0 0 0 0
1 1
QD

Design of Mod-7 Counter using IC 7490:

Mod-7 counter counts through seven states from 0 to 6 counters and it should reset as soon
as the count becomes 7. The o/p of reset logic should be 1 corresponding to invalid states. The
reset logic o/p should be applied to pin 2 and 3.
Truth Table of Reset Logic:

QD QC QB QA Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

LDCO Laboratory SCOEIT 56 / 87

 0 1 1 1 1

1 0 0 0 1

1 0 0 1 1

Logic Diagram Mod 7 Counter using IC 7490:

LDCO Laboratory SCOEIT 57 / 87

 Function table:

I/p clock Output

QD QC QB QA Count

0 0 0 0 0

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

Timing diagram of mod7:

CLK

0 0 0 0 0
1 1 1
QAA

0 0 0 0 0
QBA 1 1 1

0 0 0 0 0
QCA 1 1 1

LDCO Laboratory SCOEIT 58 / 87

Design of Mod-99 using IC 7490:

For Mod-99 two IC 7490’s will be required. Hence to implement a divide by 99 counter
we have to use two decade counters IC’s. A divide by 99 counter counts 99 states from 0 to 98
and the counter should reset as soon as the count becomes 99. So in order to reset the counter of
99 connect the Q o/p which are equal to 1 in the count of 99 to an ‘And’ gate & then connect and
o/p to the reset i/p of both IC’s.

Conclusion:

FAQs:

1. What do you mean modulus counter?

It represents the number of possible states of counter.

2. How will you use the 7490 IC to design symmetrical divide by 10 frequency counter?

The divide by 5 circuit followed by divide by 2 circuit will give symmetrical output.

LDCO Laboratory SCOEIT 59 / 87

 8. Single bit RAM Cell

AIM: To design memory units and understand how it operates during read and write operation.

OBJECTIVES:

Understanding behavior of memory from working module

THEORY: Design of Memory:

A memory unit is a collection of storage cells together with associated circuits needed to
transform information in and out of the device. Memory cells which can be accessed for
information transfer to or from any desired random location is called random access
memory(RAM). The block diagram of a memory unit-

Internal Construction: The internal construction of a random-access memory of m words with n

bits per word consists of m*n binary storage cells and associated decoding circuits for selecting
individual words. The binary cell is the basic building block of a memory unit.

RAM Design: Design of a RAM cell :

The binary cell has three inputs and one output. The select input enables the cell for reading or
writing and the reda/write input determines the cell operation when it is selected. A 1 in the
read/write input provides the read operation by forming a path from the flip-flop to the output
terminal. A 0 in the read/write input provides the write operation by forming a path from the
input terminal to the flip-flop. the logic diagram is-

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Design of a 4X4 RAM :

The logical construction of a small RAM 4X3 is shown below. It consists of 4 words of 3 bits
each and has a total of 12 binary cells. Each block labeled BC represents the binary cell with its
3 inputs and 1 output. The block diagram of a binary cell-

A memory with 4 words needs two address lines. The two address inputs go through a 2*4
decoder to select one of the four words. The decoder is enabled with the memory enable input.
When the memory enable is 0, all outputs of the decoder are 0 and none of the memory words
are selected. With the memory enable at 1, one of the four words is selected, dictated by the
value in the two address lines. Once a word has been selected, the read/write input determines
the operation. the logic diagram is-

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PROCEDURE:

General guideline to use the Virtual Laboratory simulator for performing the experiment:

1. Start the simulator as directed. For more detail please refer to the manual for using the
simulator
2. The simulator supports 5-valued logic
3. To add the logic components to the editor or canvas (where you build the circuit) select
any component and click on the position of the canvas where you want to add the
component
4. The pin configuration is shown when you select the component and press the 'show
pinconfig' button in the left toolbar or whenever the mouse is hovered on any canned
component of palette
5. To connect any two components, select the connection tool of palette, and then click on
the source terminal and then click on the the target terminal

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 6. To move any component, select the component using the selection tool and drag the
component to the desired position
7. To give a toggle input to the circuit, use 'Bit Switch' which will toggle its value with a
double click
8. Use 'Bit Display' component to see any single bit value. 'Digital Display' will show the
output in digital format
9. undo/redo, delete, zoom in/zoom out, and other functionalities have been given in the
top toolbar for ease of circuit building
10. Use start/stop clock pulse to start or stop the clock input of the circuit. Clock period can
be set from the given 'set clock' button in the left toolbar
11. Use 'plot graph' button to see input-output wave forms
12. Users can save their circuits with .logic extension and reuse them
13. After building the circuit press the simulate button in the top toolbar to get the output
14. If the circuit contains a clock pulse input, then the 'start clock' button will start the
simulation of the whole circuit. Then there is no need to again press the 'simulate' button

PIN CNFIGURATION of RAM cell (Single bit memory):

Upper Terminals: Inputs
Bottom Terminals: Outputs
Bottom Left Corner: Circle Represents pin-1
Pin Numbering: Anticlockwise
I/P : 5, select : 8, R/W' : 6, O/P : 4
Read Operation: R/W' : 1
Write Operation: R/W' : 0

Examining behaviour of memory for the working module

examining the write behaviour:
initialization:
select=1
R/W'=0
Loading data in the memory
input(i/p)=1
examining the read behaviour:
initialization:
select=1
R/W'=1
check output:
output(o/p)=1
it will give the value which was previously written

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SIMUATION OUTPUT

select=1
R/W'=0
Loading data in the memory
input(i/p)=1

Examining the read behaviour:

select=1
R/W'=1
Check output = 1

Conclusion:

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 9 Single bit ALU

AIM: To design ALU and understand how it operates.

OBJECTIVES:

Understanding behaviour of arithmetic logic unit from working module

THEORY: Design of ALU:

ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,
subtraction, division, multiplication and logical operations like AND, OR, XOR, NAND, NOR
etc. A simple block diagram of a 4 bit ALU for operations AND, OR, XOR and ADD is shown
here :

The 4-bit ALU block is combined using 4 1-bit ALU block

The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal S1
and S0 the circuit operates as follows:

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for Control signal S1 = 0 , S0 = 0, the output is A AND B,

for Control signal S1 = 0 , S0 = 1, the output is A OR B,

for Control signal S1 = 1 , S0 = 0, the output is A XOR B,

for Control signal S1 = 1 , S0 = 1, the output is A ADD B.

PROCEDURE:

General guideline to use the Virtual Laboratory simulator for performing the experiment:

1. Start the simulator as directed. For more detail please refer to the manual for using the
simulator
2. The simulator supports 5-valued logic
3. To add the logic components to the editor or canvas (where you build the circuit) select
any component and click on the position of the canvas where you want to add the
component
4. The pin configuration is shown when you select the component and press the 'show
pinconfig' button in the left toolbar or whenever the mouse is hovered on any canned
component of palette
5. To connect any two components, select the connection tool of palette, and then click on
the source terminal and then click on the the target terminal
6. To move any component, select the component using the selection tool and drag the
component to the desired position
7. To give a toggle input to the circuit, use 'Bit Switch' which will toggle its value with a
double click
8. Use 'Bit Display' component to see any single bit value. 'Digital Display' will show the
output in digital format
9. undo/redo, delete, zoom in/zoom out, and other functionalities have been given in the
top toolbar for ease of circuit building
10. Use start/stop clock pulse to start or stop the clock input of the circuit. Clock period can
be set from the given 'set clock' button in the left toolbar
11. Use 'plot graph' button to see input-output wave forms
12. Users can save their circuits with .logic extension and reuse them
13. After building the circuit press the simulate button in the top toolbar to get the output
14. If the circuit contains a clock pulse input, then the 'start clock' button will start the
simulation of the whole circuit. Then there is no need to again press the 'simulate' button

LDCO Laboratory SCOEIT 66 / 87

PIN CNFIGURATION of 1 bit ALU:

Upper Terminals: Inputs

Bottom Terminals: Outputs
Bottom Left Corner: Circle Represents pin-1
Pin Numbering: Anticlockwise
I/P: A0 : 9, B0 : 10, C0 : 11
S0 : 12,S1 : 13
O/P: F : 8, Cout : 7
00 : AND
01 : OR
10 : XOR
11 : ADD

Examining behaviour of arithmetic logic unit for the working module:

Loading data in the arithmetic logic unit

load the two input numbers as:

A0=0
B0=1
carry in(C0)=0

SIMUATION OUTPUT

Examining the AND behaviour:

load data in select input as:
S1=0, S0=0 `
check output:
F=0
Cout=0 `

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Examining the OR behaviour:
load data in select input as:
S1=0, S0=1 `
check output:
F=1
Cout=0 `

Examining the XOR behaviour:

load data in select input as:
S1=1, S0=0 `
check output:
F=1
Cout=0 `

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Examining the ADD behaviour:
load data in select input as:
S1=1, S0=1 `
check output:
F=1
Cout=1 `

Conclusion:

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 APPENDIX

A. Assignment separator for the student’s Journal.

Assignment No.: Date:

Title :

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B. Pin Diagrams
7400: Quad 2-Input NAND Gate

7402: Quad 2-Input NOR Gate

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7404: Hex Inverting Gates

7408: Quad 2-Input AND Gates

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7410: Triple 3-Input NAND Gate

7432: Quad 2-Input OR Gate

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7474: Dual Positive Edge Triggered D Flip-Flop

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7476: Dual Master-Slave J-K Flip-Flops

7483: 4 bit Binary Adder:

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(PIN 13- Cin, PIN 14- Cout)

7486: Quad 2-Input Exclusive-OR Gate

7490: Decade and Binary Counters :

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( R01 & R02- RESET I/PS, Rg1 & Rg2- SET I/PS, QD- MSB O/P)

74138: 3:8 Decoder:(A -LSB SELECT I/P, C-MSB SELECT I/P )

74151: 8:1 Multiplexer:

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74153: Dual 4:1 Multiplexer:

(A - LSB SELECT I/P, B - MSB SELECT I/P)

74180: 8 bit Parity Generator/Checker

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74191: Synchronous Up/Down 4 bit Binary counter with Mode Control

(A-LSB PARALLEL I/P, QA- LSB O/P)

74194: Universal Shift Register :

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(A –MSB PARALLEL I/P, QA – MSB O/P)

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