IS2083

IS2083
IS2083 Bluetooth® Stereo Audio SoC Data Sheet
Introduction
The IS2083 is a System-on-Chip (SoC) for dual mode Bluetooth stereo audio applications. It contains an on-board
Bluetooth stack, audio profiles and supports 24-bit/96 kHz high-resolution (Hi-Res) audio formats to enable high-
fidelity wireless audio. An integrated Digital Signal Processor (DSP) decodes (LDAC, Advanced Audio Codec (AAC),
and Sub-band Codec (SBC) codecs) and executes advanced audio and voice processing (wideband speech,
Acoustic Echo Cancellation (AEC), and Noise Reduction (NR)). This platform provides a Microcontroller (MCU) core
for application implementation via Software Development Kit (SDK) with debug support and a GUI (Config Tool) tool
for easy customization of peripheral settings and DSP functionality.
Note: Contact your local sales representative for more information about the Software Development Kit (SDK).
The IS2083 SoC is offered in a BGA package and contains in-package Flash, and is referred to as IS2083BM.
The IS2083BM supports Over-the-Air (OTA) firmware upgrade and controls the end-application via Bluetooth Low
Energy using the Microchip Bluetooth Audio (MBA) mobile app.
Features
• Qualified for Bluetooth v5.0 specification
– Hands-free Profile (HFP) 1.7, Headset Profile (HSP) 1.2, Advanced Audio Distribution Profile (A2DP) 1.3,
Serial Port Profile (SPP) 1.2, Audio/Video Remote Control Profile (AVRCP) 1.6, and Phone Book Access
Profile (PBAP) 1.2
– Bluetooth classic (BR/EDR) and Bluetooth Low Energy
– General Attribute Profile (GATT) and General Access Profile (GAP)
– Bluetooth Low Energy Data Length Extension (DLE) and secure connection
• Software Development Kit
– 8051 microcontroller debugging
– 24-bit program counter and Data Pointer modes
• Audio interfaces
– Stereo line input
– Two analog microphones
– One stereo digital microphone
– Stereo audio Digital-to-Analog Converter (DAC)
– I2S input/output
– I2S Master clock (MCLK)/reference clock
• USB, UART, and Over-the-Air (OTA) firmware upgrade
• Built-in lithium-ion and lithium polymer battery charger (up to 350 mA)
• Integrated 3V and 1.8V configurable switching regulator and Low-Dropout (LDO)
Radio Frequency (RF)/Analog

• Bluetooth 5.0 dual mode RF radio
• Receive sensitivity: –90 dBm (2 Mbps EDR)
• Programmable transmit output power:
© 2019 Microchip Technology Inc. Datasheet DS70005403B-page 1

IS2083
– Up to +11 dBm (typical) for Basic Data Rate (BDR)

– Up to +9.5 dBm (typical) for Enhanced Data Rate (EDR)
• Integrated Medium Power Amplifier (MPA) and Low Power Amplifier (LPA)
MCU Features
• 8051 8-bit core
• 8-bit data
• 24-bit program counter (PC24) mode
• 24-bit data pointer (DPTR24) mode
• Operating speed:
– DC – 48 MHz clock input
– 0.33-1 MIPS/MHz, depending on instruction
DSP Voice and Audio Processing

• 16/32-bit DSP core with enhanced 32-bit precision, single cycle multiplier
• Synchronous Connection-Oriented (SCO) channel operation
• Modified Sub-Band Coding (mSBC) decoder for wideband speech
• Built-in High-definition Clean Audio (HCA) algorithms for both narrowband and wideband speech processing
• Built-in audio effect algorithms to enhance audio streaming
• 64 Kbps A-Law, μ-Law Pulse Code Modulation (PCM), or Continuous Variable Slope Delta (CVSD) modulation
for SCO channel operation
• 8/16 kHz Noise Reduction (NR)
• 8/16 kHz Acoustic Echo Cancellation (AEC)
• Packet Loss Concealment (PLC) for SBC and mSBC codecs only
Audio Codec
• Sub-band Codec (SBC), Advanced Audio Codec (AAC), and LDAC Decoding (IS2083BM-2L2 only)
• 20-bit audio stereo DAC with SNR 95 dB
• 16-bit audio stereo ADC with SNR 90 dB
• 24-bit, I2S digital audio:
– 96 kHz output sampling frequency
– 48 kHz input sampling frequency
Peripherals
• Successive Approximation Register Analog-to-Digital Converter (SAR ADC) with dedicated channels:
– Battery voltage detection and adapter voltage detection
– Charger thermal protection and ambient temperature detection
• UART (with hardware flow control)
• USB (full-speed USB 1.1 interface)
• I2C™ Master
• One Pulse Width Modulation (PWM) channel
• Two LED drivers
• Up to 19 General Purpose Inputs/Outputs (GPIOs)
8051 MCU Debug Features

• 2-wire 8051 MCU Joint Test Action Group (JTAG) debug/program
• CPU registers to write Flash for software downloading
• Debug features supported
– Run/Stop control
– Single Step mode

IS2083
– Software breakpoint
– Debug program
– Hardware breakpoint
– Program trace
– Access to ACC
Operating Condition
• Operating voltage: 3.2V to 4.2V
• Operating temperature: -40ºC to +85ºC
Applications
• Portable speakers
• Multiple speakers
• Headphones
• Bluetooth audio transmitter

IS2083
Table of Contents
Introduction.....................................................................................................................................................1
Features......................................................................................................................................................... 1
1. Quick References....................................................................................................................................6
1.1. Reference Documentation............................................................................................................6
1.2. Acronyms/Abbreviations...............................................................................................................6
2. Device Overview..................................................................................................................................... 9
2.1. IS2083BM Device Ball Diagram................................................................................................. 10
2.2. IS2083BM Device Ball Description.............................................................................................11
3. Audio Subsystem.................................................................................................................................. 17
3.1. Digital Signal Processor............................................................................................................. 18
3.2. Codec......................................................................................................................................... 19
3.3. Auxiliary Port.............................................................................................................................. 27
3.4. Microphone Inputs......................................................................................................................27
3.5. Analog Speaker Output.............................................................................................................. 28
4. Bluetooth Transceiver........................................................................................................................... 29
4.1. Transmitter................................................................................................................................. 29
4.2. Receiver..................................................................................................................................... 29
4.3. Synthesizer.................................................................................................................................30
4.4. Modulator-Demodulator..............................................................................................................30
4.5. Adaptive Frequency Hopping..................................................................................................... 30
5. Microcontroller.......................................................................................................................................31
5.1. Memory...................................................................................................................................... 32
5.2. Clock.......................................................................................................................................... 32
6. Power Management Unit.......................................................................................................................34

6.1. Device Operation........................................................................................................................34
6.2. Power Supply............................................................................................................................. 34
6.3. Adapter Input..............................................................................................................................34
6.4. Buck1 (BK1) Switching Regulator.............................................................................................. 35
6.5. Buck2 (BK2) Switching Regulator.............................................................................................. 35
6.6. Low-Droput Regulator................................................................................................................ 35
6.7. Battery Charging........................................................................................................................ 35
6.8. SAR ADC................................................................................................................................... 36
6.9. LED Driver..................................................................................................................................38
7. Application Information..........................................................................................................................39
7.1. Power On/Off Sequence............................................................................................................ 39
7.2. Reset.......................................................................................................................................... 40
7.3. Programming and Debugging.................................................................................................... 41
7.4. General Purpose I/O Pins.......................................................................................................... 45
7.5. I2S Mode Application..................................................................................................................45
7.6. Host MCU Interface....................................................................................................................46

IS2083
8. Electrical Specifications........................................................................................................................ 48
8.1. Timing Specifications..................................................................................................................54
9. Package Information............................................................................................................................. 57
10. Ordering Information............................................................................................................................. 61
11. Document Revision History...................................................................................................................62
The Microchip Website.................................................................................................................................63
Product Change Notification Service............................................................................................................63
Customer Support........................................................................................................................................ 63
Microchip Devices Code Protection Feature................................................................................................ 63
Legal Notice................................................................................................................................................. 63
Trademarks.................................................................................................................................................. 64
Quality Management System....................................................................................................................... 64
Worldwide Sales and Service.......................................................................................................................65

IS2083
Quick References
1. Quick References
1.1 Reference Documentation

For further study, refer to the following:
• BM83 Bluetooth® Stereo Audio Module Data Sheet (DS70005402)
• BM83 Bluetooth® Audio Development Board User's Guide (DS50002902)
• IS2083 SDK User Guide (DS50002894)
• BM83 Host MCU Firmware Development Guide (DS50002896)
• IS2083 Bluetooth® Audio Application Design Guide (DS00003118)
• IS2083 SDK Debugger User’s Guide (DS50002892)
• IS2083 Reference Design Application Note
• Serial Quad Interface (SQI) Family Reference Manual (DS60001244)
Note:
1. For a complete list of development support tools and documents, visit:
– http://www.microchip.com/BM83
– https://www.microchip.com/IS2083
2. Contact your local sales representative for more information about the Software Development Kit (SDK).
1.2 Acronyms/Abbreviations
Table 1-1. Acronyms/Abbreviations
Acronyms/Abbreviations Description
A2DP Advanced Audio Distribution Profile
AAC Advanced Audio Codec
ADC Analog-to-Digital Converter
AEC Acoustic Echo Cancellation
AFH Adaptive Frequency Hopping
ANCS Apple Notification Center Service
API Application Programming Interfaces
AVRCP Audio/Video Remote Control Profile
AW Audio Widening
BDR Basic Data Rate
BER Bit Error Rate
BLE Bluetooth Low Energy
BOM Bill of Materials
BPF Band Pass Filter
BR Basic Rate
CVSD Continuous Variable Slope Delta
DAC Digital-to-Analog Converter
DFU Device Firmware Upgrade
DIS Device Information Service
DLE Data Length Extension

IS2083
Quick References
...........continued
DPSK Differential Phase Shift Keying
DQPSK Differential Quadrature Phase Shift Keying
DR Receive Data
DSP Digital Signal Processor
DT Transmit Data
EDR Enhanced Data Rate
EMC Electromagnetic Compatibility
EVB Evaluation Board
FET Field Effect Transistor
GAP General Access Profile
GATT General Attribute Profile
GFSK Gaussian Frequency Shift Keying
GPIO General Purpose Input Output
GUI Graphical User Interface
HFP Hands-free Profile
HPF High Pass Filter
HSP Headset Profile
HW Hardware
I2C Inter-Integrated Circuit
I2S Inter-IC Sound
IC Integrated Circuit
ICSP In-Circuit Serial Programming
IDE Integrated Development Environment
IF Intermediate Frequency
IPE Integrated Programming Environment
JTAG Joint Test Action Group
LDO Low-Dropout
LED Light Emitting Diode
LNA Low-Noise Amplifier
LPA Linear Power Amplifier
LSB Least Significant Bit
MAC Medium Access Control
MB DRC Multiband Dynamic Range Compression
MCLK Master Clock
MCU Microcontroller
MEMS Micro-Electro-Mechanical Systems
MFB Multi-function Button
Modem Modulator-demodulator
MPA Medium Power Amplifier
mSBC Modified Sub-band Coding

IS2083
Quick References
MSPK Multi-speaker
NR Noise Reduction
OTA Over-the-Air
PBAP Phone Book Access Profile
PCB Printed Circuit Board
PCM Pulse Code Modulation
PDM Pulse Density Modulation
PIM Plug-in Module
PLC Packet Loss Concealment
PMU Power Management Unit
POR Power-on Reset
PWM Pulse Width Modulation
RF Radio Frequency
RFS Receive Frame Sync
RoHS Restriction of Hazardous Substances
RSSI Received Signal Strength Indicator
RX Receiver
SAR Successive Approximation Register
SBC Sub-band Coding
SCO Synchronous Connection-oriented
SDK Software Development Kit
SIG Special Interest Group
SNR Signal-to-Noise Ratio
SoC System-on-Chip
SPP Serial Port Profile
SW Software
TX Transmitter
UART Universal Asynchronous Receiver-Transmitter
UI User Interface
USB Universal Serial Bus
VB Virtual Bass Enhancement
VCO Voltage-controlled Oscillator
WDT Watchdog Timer

IS2083
Device Overview
2. Device Overview
The IS2083BM uses a single-cycle 8-bit 8051 MCU core connected to the system components via an MCU system
bus. The MCU system bus provides interface memory map address decode for the Read Only Memory (ROM), Static
Random Access Memory (SRAM), and peripherals.
IS2083BM contains the following major blocks:
• Bluetooth Link Controller (BTLC) – Bluetooth clock, task scheduler, and Bluetooth hopping
• Bluetooth modulator-demodulator (modem) – TX/RX baseband, and RF
• DSP audio subsystem – DSP with audio codec
• Program ROM Memory
• Bluetooth DMA – Common Memory Access
• Power Management Unit (PMU)
• Clock/Reset – Low power logic
Figure 2-1. IS2083BM SoC Architecture
CPU Subsystem To Memories

Interrupt
Controller Program
Debug OCI Patch ROM 2 MB
8-bit 8051 MMU WDT I 2C PWM GPIO SQI
Host Debug CPU Core Logic Flash
Patch RAM
CPU Program/Data Bus
Mailbox
Baseband
IO Bus
Hopping Bluetooth
DSP Subsystem
Task Bluetooth
Sequence Clock DSP Core
Controller Baseband Core
Controller Timer
External
DMA Codec
RF SPORT0
Controller
Program Data
RAM RAM
CLDO RFLDO Coeff. Patch

TX path RAM RAM
Controller
+ Memory
TX modem
Bluetooth 5.0 IO Bus
Dual Mode Radio
RX path
+ Audio MIC
288 MHz RX modem Stereo
XTAL ULPC BG Subsystem
PLL Audio Codec SPK
16 MHz UART RS-232

32 kHz
CLKGEN Common
0-48 MHz
Memory USB USB
0-96 MHz
The IS2083BM device variants are:

• IS2083BM variant supports analog output from the internal DAC
• IS2083BM-2L2 variant supports LDAC and does not support analog output
The following table provides the features of IS2083BM SoC variants.

IS2083
Device Overview
Table 2-1. IS2083BM Features
Features IS2083BM IS2083BM-2L2
Application • Headset/Speaker Headset / Speaker

• Bluetooth Audio Transmitter
Memory Flash Flash
Stereo/Concert mode Yes Yes
Package BGA BGA
Pin/Ball count 82 82
Dimensions 5.5 mm x 5.5 mm 5.5 mm x 5.5 mm
Audio DAC output 2 channel —
DAC (single-ended) SNR 95 dB —
DAC (cap-less) SNR 95 dB —
ADC SNR at 1.8V –88 dB –88 dB
I2S audio input Yes Yes
I2S digital output Yes Yes
MCLK output Yes Yes
Analog output Yes —
Analog Line-In Yes Yes
Analog microphone 2 channel 2 channel
Digital microphone 2 channel 2 channel
External audio amplifier interface Yes Yes
UART with hardware flow control 1 1
USB (Full-speed USB 1.1 interface and Yes Yes

battery charging)
I2C 1 1
PWM 1 channel 1 channel
LED driver 2 2
Battery charger (350 mA maximum) Yes Yes
ADC for battery voltage and Yes Yes

temperature monitoring
GPIO Up to 19 Up to 19
Multitone Yes Yes
Integrated MPA and LPA Yes Yes
2.1 IS2083BM Device Ball Diagram

The following figure illustrates the ball diagram of the IS2083BM and IS2083BM-2L2.

IS2083
Device Overview
Figure 2-2. IS2083BM and IS2083BM-2L2 Ball Diagram
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
MIC_N2 AOHPL AOHPM VDDA_CODEC AOHPR PA1OP GND RTX VCC_BTPA VCC_RF
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
MIC_P2 SCLK1 RFS1 VCOM P1_3/ P1_2/ VCC_PA1 P0_1 P2_3 XO_P
TCK_CPU/ TDI_CPU/
SDA SCL
C1 C2 C3 C6 C8 C9 C10
MIC_N1 DT1 DR1 NC VDD_IO P1_6/ XO_N

PWM1
D1 D2 D3 D8 D9 D10
MIC_P1 MCLK1 VDD_IO RST_N P0_5 ULPC_VSUS
E1 E2 E3 E5 E6 E8 E9 E10
MICBIAS DMIC_CLK DMIC1_L GND P0_7 P0_2 P2_7 VBG
F1 F2 F3 F5 F6 F8 F9 F10
ADAP_IN DMIC1_R AIR GND GND P0_0/ P0_3 RFLDO_O

UART_TX_IND
G1 G2 G3 G8 G9 G10
BAT_IN P3_2 AIL USB_1V2/ P3_5 PMIC_IN

VDD_CORE
H1 H2 H3 H5 H8 H9 H10
SARVDD P0_6 P2_6 VDD_CORE AVDD_USB/ P3_7/ CLDO_O/

VDD_IO_10 UART_CTS VDD_PLL
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
SYS_POWER P8_6/ P8_5/ SK1 SK2 VDD_CORE P3_4/ LED1 LED2 USB_DP
UART_RXD UART_TXD UART_RTS
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
BK1_VDDC BK1_LX1 BK1_VOUT MFB LDO31_VO LDO31_VIN BK2_VOUT BK2_LX BK2_VDD USB_DM
Note: The IS2083BM-2L2 does not support an analog output from the internal DAC. The AOHPR, AOHPM and
AOHPL are affected pins.
2.2 IS2083BM Device Ball Description

Table 2-2. IS2083BM and IS2083BM-2L2 Ball Description
IS2083BM Ball IS2083BM-2L2 Ball Ball Name Ball Description

Number Number Type
A1 A1 MIC_N2 I MIC2 mono differential analog negative

input
A2 - AOHPL(1) O Left channel, analog headphone output
A3 - AOHPM(1) O Headphone common mode output/sense
input

IS2083
Device Overview
Number Number Type
A4 A4 VDDA_CODEC P • Analog audio codec power supply

(1.8V)
• Connect to BK2_VOUT pin
A5 - AOHPR(1) O Right channel, analog headphone output

A6 A6 PA1OP I/O RF output pin for MPA
A7 A7 GND P Ground reference
A8 A8 RTX I/O • RF path (transmit/receive)
• TX LPA output multiplexed with RX
LNA input
A9 A9 VCC_BTPA P • Power supply for RF power amplifier

• Connect to BK1_VOUT
A10 A10 VCC_RF P • RF power input (1.28V) for both

synthesizer and TX/RX block
• Connect to RFLDO_O
B1 B1 MIC_P2 I MIC2 mono differential analog positive input

B2 B2 SCLK1 I/O I2S interface for bit clock
B3 B3 RFS1 I/O I2S interface for DAC digital left/right clock
B4 B4 VCOM P • Internal biasing voltage for codec
• Connect a 4.7 μF capacitor to ground
B5 B5 P1_3/ I/O • General purpose I/O port P1_3

TCK_CPU/ SDA • CPU 2-wire debug clock
• I2C SDA
B6 B6 P1_2/ TDI_CPU/ I/O • General purpose I/O port P1_2

SCL • CPU 2-wire debug data
• I2C SCL
B7 B7 VCC_PA1 P • Power supply for MPA

B8 B8 P0_1 I/O • General purpose I/O port P0_1

• By default, this is configured as forward
button (user configurable button)
B9 B9 P2_3 I/O General purpose I/O port P2_3

B10 B10 XO_P I 16 MHz crystal positive input
C1 C1 MIC_N1 I MIC1 mono differential analog negative
input
C2 C2 DT1 O I2S interface: ADC digital left/right data
C3 C3 DR1 I/O I2S interface: DAC digital left/right data
C6 C6 NC — Not connected

IS2083
Device Overview
Number Number Type
C8 C8 VDD_IO P • I/O power supply input

• Connect to ground through a 1 μF
(X5R/X7R) capacitor
C9 C9 P1_6/ PWM1 I/O • General purpose I/O port P1_6

• PWM1 output
C10 C10 XO_N I 16 MHz crystal negative input

D1 D1 MIC_P1 I MIC1 mono differential analog positive input
D2 D2 MCLK1 O Master clock output provided to an external
I2S device/codec
D3 D3 VDD_IO P • I/O power supply input
• Connect to LDO31_VO and ground
through a 1 μF (X5R/X7R) capacitor
D8 D8 RST_N I System Reset pin (active-low)

D9 D9 P0_5 I/O • General purpose I/O port P0_5
• By default, this is configured as volume
down button (user configurable button)
D10 D10 ULPC_VSUS P • 1.2V ULPC output power

• Maximum loading 1 mA
capacitor
E1 E1 MICBIAS P Electric microphone biasing voltage

E2 E2 DMIC_CLK O Digital microphone clock
E3 E3 DMIC1_L I Digital microphone left channel
E5 E5 GND P Ground reference
E6 E6 P0_7 I/O General purpose I/O port P0_7
E8 E8 P0_2 I/O • General purpose I/O port P0_2
• By default, this is configured as play/
pause button (user configurable button)
E9 E9 P2_7 I/O • General purpose I/O port P2_7

• By default, this is configured as volume
up button (user configurable button)
E10 E10 VBG P • Bandgap output reference for

decoupling interference
capacitor
F1 F1 ADAP_IN P 5V power adapter input to charge the

battery in the battery powered applications
F2 F2 DMIC1_R I Digital microphone right channel
F3 F3 AIR I Right channel, single-ended analog input

IS2083
Device Overview
Number Number Type
F5 F5 GND P Ground reference

F6 F6 GND P Ground reference
F8 F8 P0_0/ I/O • General purpose I/O port P0_0
UART_TX_IND • By default, this is configured as an
external codec reset (Embedded
mode)
• UART_TX_IND (active-high); used to
wake-up host MCU (Host mode)
F9 F9 P0_3 I/O • General purpose I/O port P0_3

• By default, this is configured as reverse
button (user configurable button)
F10 F10 RFLDO_O P • 1.28V RF LDO output for internal use

only
capacitor
G1 G1 BAT_IN P • Input power supply

• Source can either be a battery or any
other power rail on the host board
G2 G2 P3_2 I/O • General purpose I/O port P3_2

• By default, this is configured as
AUX_IN DETECT
G3 G3 AIL I Left channel, single-ended analog input

G8 G8 USB_1V2/ P • 1.2V core power input
VDD_CORE • Connect to ground through a 1 μF
(X5R/X7R) capacitor
G9 G9 P3_5 I/O General purpose I/O port P3_5

G10 G10 PMIC_IN P • 1.8V power input for internal blocks
H1 H1 SARVDD P • SAR ADC 1.8V input

• Connect to BK2_O pin
H2 H2 P0_6 I/0 General purpose I/O port P0_6

H3 H3 P2_6 I/O General purpose I/O port P2_6
H5 H5 VDD_CORE P • Core 1.2V power input
• Connect to CLDO_O pin
H8 H8 AVDD_USB/ P • USB power input

VDD_IO_10 • Connect to LDO31_VO pin
• Do not connect if USB functionality is
not required

IS2083
Device Overview
Number Number Type
H9 H9 P3_7/ I/O • General purpose I/O port P3_7 (this pin

UART_CTS should not be pulled low during start-
up)
• UART CTS
H10 H10 CLDO_O/ P • 1.2V core LDO output for internal use
VDD_PLL only
capacitor
J1 J1 SYS_POWER P • System power output derived from the

ADAP_IN or BAT_IN input
• Do not connect to any other devices
• Only for internal use
J2 J2 P8_6/ I/O • General purpose I/O port P8_6

UART_RXD • UART data input

UART_TXD • UART data output
J4 J4 SK1 I ADC channel 1

J5 J5 SK2 I ADC channel 2
J6 J6 VDD_CORE P • 1.2V core input power supply
(X5R/X7R) capacitor

UART_RTS • System configuration pin (Application
mode or Test mode)
• UART RTS
J8 J8 LED1 O LED driver 1

J9 J9 LED2 O LED driver 2
J10 J10 USB_DP I/O Differential data-plus USB
K1 K1 BK1_VDDC P • 1.5V buck VDD power input
• Connect to SYS_POWER pin
K2 K2 BK1_LX1 P 1.5V buck regulator feedback path

K3 K3 BK1_VOUT P • 1.5V buck regulator output
• Do not connect to other devices
K4 K4 MFB I Multifunction push button and Power On key

K5 K5 LDO31_VO P • 3V LDO output for VDD_IO power
• Do not calibrate
K6 K6 LDO31_VIN P • LDO input

• Connect to SYS_POWER

IS2083
Device Overview
Number Number Type
K7 K7 BK2_VOUT P • 1.8V buck regulator output

• Do not connect to other devices
K8 K8 BK2_LX P 1.8V buck regulator feedback path

K9 K9 BK2_VDD P • 1.8V buck VDD power input
• Connect to SYS_POWER pin
K10 K10 USB_DM I/O Differential data-minus USB
Note:
1. The AOHPR, AOHPM, and AOHPL pins are not available in the IS2083BM-2L2 variant as it does not support
an analog output from the internal DAC.
2. The conventions used in the preceding table are indicated as follows:
– I = Input pin
– O = Output pin
– I/O = Input/Output pin
– P = Power pin

IS2083
Audio Subsystem
3. Audio Subsystem
The input and output audio have different stages and each stage can be programmed to vary the gain response
characteristics. For microphones, both single-ended inputs and differential inputs are supported. To maintain a high-
quality signal, a stable bias voltage source to the condenser microphone’s FET is provided. The DC blocking
capacitors can be used at both positive and negative sides of the input. Internally, this analog signal is converted to
16-bit, 8/16 kHz linear PCM data.
The following figure shows the audio subsystem.
Figure 3-1. Audio Subsystem
RSTGEN reset Analog Audio Codec
CLKGEN clk
CPU registers
DSP
DSP registers
AOHPL
DAC Audio
DT0 AOHPM
Controller DAC
AOHPR
ADC_SDATA AIL
ADC
Controller AIR
ADC_LRO
Audio MICN1
ADC MICP1
MICN2
DMIC_CLK digmic_mclk_out
MICP2
DMIC1_L digmic1_l_data_in
DMIC1_R digmic1_r_data_in VREF MICBIAS
Note: The AOHPL, AOHPM, AOHPR pins are not available in the IS2083BM-2L2 variant.

IS2083
Audio Subsystem
3.1 Digital Signal Processor

A Digital Signal Processor (DSP) is used to perform speech and audio processing. The advanced speech features,
such as AES and NR are inbuilt. To reduce nonlinear distortion and to help echo cancellation, an outgoing signal level
to the speaker is monitored and adjusted to avoid saturation of speaker output or microphone input. In addition,
adaptive filtering is applied to track the echo path impulse in response to provide echo free and full-duplex user
experience.
The embedded noise reduction algorithm helps to extract clean speech signals from the noisy inputs captured by the
microphones and improves mutual understanding in communication. The advanced audio features, such as
multiband dynamic range control, parametric multiband equalizer, audio widening and virtual bass are inbuilt. The
audio effect algorithms improve the user’s audio listening experience in terms of better-quality audio after audio
signal processing.
Note: DSP parameters can be configured using the Config Tool.
The following figures illustrate the processing flow of speaker phone applications for speech and audio signal
processing.
Figure 3-2. Speech Signal Processing
IS2083BM
DSP
CVSD/A-Law/
Antenna Far-end Audio
μ-Law/MSBC Equaliser HPF SRC DAC
NR Amplifier
Decoders Speaker
MCU
CVSD/A-Law/
Near-end
μ-Law/MSBC Equaliser AEC HPF SRC ADC
NR/AES
Encoders
Digital Microphones
Additive MIC Gain
Background Noise
Figure 3-3. Audio Signal Processing
IS2083BM
Antenna DSP
External Audio
Line-In ADC
Source
MCU SBC/AAC DAC Audio

Audio Equaliser (speaker
SRC Amplifier
Decoders Effect gain) Speaker
LDAC I2S Output

Decoders
Note: LDAC is supported only in the IS2083BM-2L2 device.

The DSP core consists of three computational units (ALU, MAC, and Barrel Shifter), two data address generators,
PMD-DMD bus exchanger, program sequencer, bi-directional serial ports (SPORT), DMA controller, interrupt
controller, programmable I/O, on-chip program, and on-chip data memory.
The DSP memory subsystem defines the address ranges for the following addressable memory regions:

IS2083
Audio Subsystem
• Program space
– 96 KB of Program RAM
– 12 KB of Patch RAM
– 64 KB of Coefficient RAM
• Data space
– 96 KB of Data RAM
• I/O Space
– Memory-mapped registers
The DSP core implements a modified Harvard architecture in which data memory stores data and program memory
stores both instructions and data (coefficients).
3.2 Codec
The built-in codec has a high signal-to-noise ratio (SNR) performance and it consists of an Analog-to-Digital
Converter (ADC), a Digital-to-Analog Converter (DAC), and an additional analog circuitry.
• Interfaces
– Two mono differential or single-ended microphone inputs
– One stereo single-ended line input
– One stereo single-ended line output
– One stereo single-ended earphone output (capacitor-less connection)
• Built-in circuit
– Microphone bias (MICBIAS)
– Reference and biasing circuitry
• Optional digital High Pass Filter (HPF) on ADC path
• Silence detection
– Typically, used for Line-In inputs. For some applications, the Line-In input has high priority. After the Line-In
input source is plugged in and before streaming out an audio, the Line-In noise cannot be ignored. So, the
silence detection feature is used to mute this background noise.
• Anti-pop function to reduce audible glitches
– Pop reduction system
– Soft Mute mode
– Typically used when the codec analog gain is changed suddenly (for example, turning OFF the power or
switching the volume dial very quickly), in which case the RCL circuits in the external audio amplifier would
cause "pop" noise. The anti-pop function is used to lower or increase the gain in many small steps, 1- or 2-
dB change for each step, rather than a single large gain decrease or increase.
• ADC supports 8 kHz, 16 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz sampling rates.
3.2.1 Audio Performance

This section provides characteristics of the internal codec in the IS2083BM device.
Table 3-1. Test Conditions
Parameter (Condition) Value

FS 48 kHz
Analog gain setting for ADC 0 dB
Digital gain setting for ADC 0 dB
Analog gain setting for DAC -3 dB
Digital gain setting for DAC 0 dB

IS2083
Audio Subsystem
Figure 3-4. ADC Signal Quality – THD
Note: Analog Gain = 0 dB, Digital Gain = 0 dB, Sweep Vin= -60 dbV to 5 dbV@1 kHz.
Figure 3-5. ADC Signal Quality – THD+N

IS2083
Audio Subsystem
Figure 3-6. ADC Dynamic Range
Figure 3-7. ADC Frequency Response
Note: Analog Gain = 0 dB, Digital Gain = 0 dB Sweep Fin= 20 Hz to 20 kHz @ -3 dbV.

IS2083
Audio Subsystem
Figure 3-8. ADC Crosstalk – Line-In
Figure 3-9. ADC Crosstalk – Mic-in

IS2083
Audio Subsystem
Figure 3-10. DAC Signal Quality – THD (Single-ended)
Note: Analog gain = −3 dB, digital gain = 0 dB, sweep Vin = −60 dBFS to 0 dBFS@ 1 kHz.
Figure 3-11. DAC Signal Quality – THD (Capless)
Note: Analog gain = −3 dB, digital gain = 0 dB, sweep Vin = −60 dBFS to 0 dBFS @1 kHz.

IS2083
Audio Subsystem
Figure 3-12. DAC Signal Quality − THD+N (Single-ended)
Note: Analog gain = −3 dB, digital gain = 0 dB, sweep Vin = −60 dBFS to 0 dbFS @1 kHz.
Figure 3-13. DAC Signal Quality − THD+N (Capless)
Note: Analog gain = −3 dB, digital gain = 0 dB, sweep Vin = −60 dBFS to 0 dBFS @1 kHz.

IS2083
Audio Subsystem
Figure 3-14. DAC Dynamic Range (Single-ended)
Note: Analog gain = 3 dB, digital gain = 0 dB, sweep Vin = −100 dBFS to 0 dBFS @1 kHz.
Figure 3-15. DAC Dynamic Range (Capless)
Note: Analog gain = 3 dB, digital gain = 0 dB, sweep Vin = −100 dBFS to 0 dBFS @1 kHz.

IS2083
Audio Subsystem
Figure 3-16. DAC Frequency Response (Single-ended)
Note: Analog gain = −3 dB, sweep fin = 20 Hz to 20 kHz @ -3 dBFS.

Figure 3-17. DAC Frequency Response (Capless)
Note: Analog gain = −3 dB, sweep fin = 20 Hz to 20 kHz @ −3 dBFS.

IS2083
Audio Subsystem
Figure 3-18. DAC Crosstalk (Single-ended)

Figure 3-19. DAC Crosstalk (Capless)
3.3 Auxiliary Port

The IS2083BM SoC supports one analog (Line-In, also called as Aux-In) signal from the external audio source. The
analog (Line-In) signal can be processed by the DSP to generate different sound effects (multiband dynamic range
compression and audio widening), which can be configured by using the Config Tool.
3.4 Microphone Inputs

The IS2083BM SoC supports:
• One digital microphone with one (mono) or two channels (stereo L and R)
• Two analog microphones (left and right)
Note: Do not use analog and digital microphones simultaneously.

IS2083
Audio Subsystem
The DIGMIC interfaces should only be used for PDM digital microphones (typically, MEMS microphones) up to 4 MHz
of clock frequency. I2S-based digital microphones should use the external I2S port.
3.5 Analog Speaker Output

The IS2083BM SoC supports the following speaker output modes:
• Capless mode − Used for headphone applications in which capacitor less (capless) output connection helps to
save the Bill of Material (BoM) cost by avoiding a large DC blocking capacitor. The following figure illustrates the
Capless mode analog speaker output.
Figure 3-20. Capless Mode Analog Speaker Output
IS2083BM
AOHPR
AOHPM
AOHPL
16/32 Ohm Speaker
• Single-Ended mode − Used for driving an external audio amplifier where a DC blocking capacitor is required.
The following figure illustrates the Single-Ended mode analog speaker output.
Figure 3-21. Single-ended Mode Analog Speaker Output
IS2083BM
AOHPR
Audio Amplifier
AOHPL

IS2083
Bluetooth Transceiver
4. Bluetooth Transceiver
The IS2083BM SoC is designed and optimized for Bluetooth 2.4 GHz systems. It contains a complete radio
frequency transmitter (TX)/receiver (RX) section. An internal synthesizer generates a stable clock for synchronizing
with another device.
4.1 Transmitter
The IS2083BM has Lower Power Amplifier (LPA) and Medium Power Amplifier (MPA). The MPA supports up to +11
dBm power level for Bluetooth Class1 configuration and LPA supports up to about +1 dBm power level for Bluetooth
Class2 configuration. The MPA output is connected to the PA1OP pin of the SoC. The LPA output and LNA input are
multiplexed and connected to the RTX pin of the device.
The IS2083BM supports shared port configuration, in which the MPA and LPA pins are wired together as shown in
the following figure. In shared port configuration, the external series capacitors on RTX, PA1OP pins and PI filter
circuit implements a low BoM cost solution to combine the MPA and LPA/LNA signals. Typical value of these
components are C1 = 2 pF, C2 = 3 pF, C3 = 1.3 pF/1.4 pF, L1 = 2.7 nH/2.8 nH, C4 = 3 pF (use the BM83 RF
schematics as it is to achieve the desired RF performance).
Note: For more details, refer to the IS2083 Reference Design Application Note.
Figure 4-1. Shared Port Configuration
4.2 Receiver
The Low-Noise Amplifier (LNA) operates in a TR-combined mode for a single port application. It saves a pin on the
package without having an external TX/RX switch.
The ADC is used to sample the analog input signal and convert it into a digital signal for demodulator analysis. A
channel filter is integrated into the receiver channel before the ADC to reduce the external component count and
increase the anti-interference capability.
The image rejection filter is used to reject the image frequency for the low-IF architecture, and it also intended to
reduce the external Band Pass Filter (BPF) component for a super heterodyne architecture.
The Received Signal Strength Indicator (RSSI) signal feedback to the processor is used to control the RF output
power to make a good trade-off for effective distance and current consumption.

IS2083
Bluetooth Transceiver
4.3 Synthesizer
A synthesizer generates a clock for radio transceiver operation. There is a Voltage Controlled Oscillator (VCO) inside
with a tunable internal LC tank that can reduce components variation. A crystal oscillator with an internal digital
trimming circuit provides a stable clock for the synthesizer.
4.4 Modulator-Demodulator
For Bluetooth 1.2 specification and below, 1 Mbps is the standard data rate based on the Gaussian Frequency Shift
Keying (GFSK) modulation scheme. This basic rate modulator-demodulator (Modem) meets Basic Data Rate (BDR)
requirements of Bluetooth 2.0 with Enhanced Data Rate (EDR) specifications.
For Bluetooth 2.0 and above specifications, EDR is introduced to provide the data rates of 1/2/3 Mbps. For baseband,
both BDR and EDR utilize the same 1 MHz symbol rate and 1.6 kHz slot rate. For BDR, symbol 1 represents 1-bit.
However, each symbol in the payload part of the EDR packet represents 2 or 3 bits. This is achieved by using two
different modulations, π/4 DQPSK and 8 DPSK.
4.5 Adaptive Frequency Hopping

The IS2083BM SoC has an Adaptive Frequency Hopping (AFH) function to avoid RF interference. It has an algorithm
to check the nearby interference and to choose a clear channel for transceiver Bluetooth signal.

IS2083
Microcontroller
5. Microcontroller
A 8051 microcontroller is built into the SoC to execute the Bluetooth protocols. It operates from 16 MHz to higher
frequencies where the firmware can dynamically adjust the trade-off between the computing power and the power
consumption.
Figure 5-1. IS2083BM SoC Block Diagram
Antenna
Audio Bluetooth Classic

I2S (digital signal) Codec and Low Energy
External and MCLK Transceiver
Digital 16 MHz
DSP
Core Crystal
RF
Speaker 1 32-bit DSP Core
2-Channel
DAC RF Controller
Speaker 2
MAC Modem
ANAMIC1 2-Channel
ANAMIC2 ADC
DIGMIC1 PMU
IS2083BM Battery Charger Battery
AUX_In
MCU
(Analog signal) Battery Monitor
Core
Flash Power Switch
Memory JTAG Debug
16 Mbit 1.5V
512 B Internal Buck Regulator
832 KB Prog 1.8V
ROM Buck Regulator
512 KB Prog/ 3.1V
USB 1.1 Patch/Data RAM LDO
UART LED Drivers

LED
I2C PWM IO Ports
The MCU core contains Bluetooth stack and profiles, which are hard-coded into ROM to minimize power
consumption for the firmware execution and to save the external Flash cost. This core is responsible for the following
system functions:
• Boot-up
• On-the-Air Device Firmware Upgrade (OTA DFU)
• Executing the Bluetooth stack and Bluetooth profiles
• Sending the packets to DSP core for audio processing
• Loading audio codec registers with values read the Flash
• Managing low-power modes
• Executing UART commands

IS2083
Microcontroller
• Device programming
• GPIO button control
• PWM control
• LED control
• Bluetooth role swap for multi-speakers
• Adjusting the Bluetooth clock
• External audio codec control/configuration, if needed
• USB battery charge detection and configuration of the PMU battery charger
• Configuration of PMU power regulation
• Changing the audio subsystem clocks On-the-Fly (OTF) for different audio sampling rates
5.1 Memory
A synchronous single port RAM interface is used to fulfill the ROM and RAM requirements of the processor. The
register bank, dedicated single port memory and Flash memory are connected to the processor bus. The processor
coordinates with all link control procedures and the data movement happens using a set of pointer registers.
5.2 Clock
The IS2083BM SoC is composed of an integrated crystal oscillator that uses a 16 MHz ±10 ppm external crystal and
two specified loading capacitors to provide a high-quality system reference timer source. This feature is typically used
to remove the initial tolerance frequency errors, which are associated with the crystal and its equivalent loading
capacitance in the mass production. Frequency trim is achieved by adjusting the crystal loading capacitance through
the on-chip trim capacitors (Ctrim).
The crystal trimming can be done using manufacturing tools provided by Microchip. The following figure illustrates the
crystal oscillator connection of the IS2083BM SoC with two capacitors.
Figure 5-2. Crystal Oscillator in the IS2083BM
IS2083BM
XO_N XO_P
CL1 CL2
The clock module controls switching and synchronization of clock sources. Clock sources include:
• System Phase-locked Loop (PLL)
• Primary oscillator
• External clock oscillator
• Ultra Low-power internal RC oscillator (UPLC) with nominal frequency as 32 kHz.

IS2083
Microcontroller
The clock module provides gated clock output for 8051 and its peripheral modules, gated clock output for Bluetooth
modules as well as DSP audio subsystem. The system enters low power mode by switching OFF clocks driven from
the PLL and external oscillator. Only ULPC is operated to maintain Bluetooth timing.

IS2083
Power Management Unit
6. Power Management Unit

The IS2083BM SoC has an integrated Power Management Unit (PMU). The PMU includes buck switching regulator,
LDO, battery charger, SAR ADC for voltage sensing, and LED drivers. The power switch is provided to switch
between battery and adapter. It also provides current to the LED drivers.
6.1 Device Operation

The IS2083BM SoC is powered through the BAT_IN input pin. The external 5V power adapter can be connected to
the ADAP_IN pin to charge the battery.
For normal operation, it is recommend to use the BAT_IN pin to power the IS2083BM SoC and ADAP_IN only for
charging the battery. The following figure illustrates the connection from the BAT_IN pin to other voltage supply pins
of the IS2083BM. The IS2083BM has two buck switching regulators:
• Buck1 DC/DC regulator provides 1.5V and is used to supply power to RF and baseband.
• Buck2 DC/DC regulator provides 1.8V and is used to supply power to I/O pads and internal codec.
Figure 6-1. Power Tree Diagram
1.8V Buck BK_O

Switching
(1.8V)
BK_VDD Regulator BK_LX
(Buck2)
VDDA/
LDO31_VIN VDDAO
(3.2 to 4.2V) 3V LDO
Li-Ion BAT_IN
Battery Power LDO31_VO VDD_IO
SYS_PWR (3.0 to 3.6V)
(4.5 to 5.5V) Switch
ADAP_IN (4.2 to 3.2V)
1.5V Buck BK_O

5V Switching (1.5V) (1.2V)
Adapter BK_VDD Regulator BK_LX PMIC_IN CLDO_O VDD_CORE
(Buck1)
1.2V LDO
(1.28V)
RFLDO_O VCC_RF
SAR_VDD
6.2 Power Supply

Typically, the PWR (MFB) pin is connected to a mechanical button on the device. When pressed, it connects the
BAT_IN pin to the power detection block of the PMU. The PMU keeps the VBAT_IN connected once the PWR pin is
released.
6.3 Adapter Input

The adapter input (ADAP_IN) is used for charging the battery. If the total power consumed by IS2083BM SoC is less
than 120 mA, ADAP_IN pin can also be used as power supply input. If the current to be driven is more than 120 mA,
it is recommended to use the BAT_IN pin as the power supply input and the ADAP_IN pin can be left floating.

IS2083
6.4 Buck1 (BK1) Switching Regulator

The IS2083BM includes a built-in programmable output voltage regulator which converts the battery voltage to 1.5V
to supply the RF and baseband power supply. This converter has high conversion efficiency and fast transient
response.
Note: Do not connect any other devices to buck1 regulator output pin (BK1_VOUT).
6.5 Buck2 (BK2) Switching Regulator

The IS2083BM includes a second build in programmable output voltage regulator which converts the battery voltage
to 1.8V, to supply the PMU ADC and to optionally supply stereo audio codec and/or I/O’s. This converter has a high
conversion efficiency and a fast-transient response.
Note: Do not connect any other devices to buck2 regulator output pin (BK2_VOUT).
6.6 Low-Droput Regulator

The built-in Low-Dropout (LDO) regulator is used to convert the battery or adapter power to 3.3V to supply the USB
transceiver and to supply the I/O’s.
6.7 Battery Charging

The IS2083BM SoC has built-in battery charger which is optimized for lithium-ion and lithium polymer batteries. The
battery charger includes a current sensor for charging control, user programmable current regulator and high
accuracy voltage regulator. The charging current parameters are configured by using the Config Tool. The maximum
charging current is 350 mA. Whenever the adapter is plugged in, the charging circuit is activated.
Figure 6-2. Battery Charging Curve
Constant Current Constant Voltage Stop Recharge Stop

Icharge
VBatt
Mode Mode Charging Mode Charging (back

V5 = 0.1V drop to re-charge if
Stage Stage Stage Stage
1 2 3 4 voltage drop > V5)
I4 V4
I3 V3
I5
Icomp
I2 V2
I1 V1
T1 T2 T3 T4 T5 Time
6.7.1 Battery Charger Detection

The IS2083BM USB transceiver includes built-in battery charger detection that is compatible with the following:
USB BC 1.2 Standard Downstream Port (SDP): This is the same port defined by the USB 2.0 spec and is the
typical form found in desktop and laptop computers. The maximum load current is 2.5 mA when suspended, 100mA
when connected and not suspended, and 500 mA (max) when connected and configured for higher power.
USB BC 1.2 Dedicated Charger Port (DCP): BC 1.2 describes power sources like wall warts and auto adapters that
do not enumerate so that charging can occur with no digital communication at all. DCPs can supply up to 1.5A and
are identified by a short between D+ to D-. This port does not support any data transfer, but is capable of supplying
charge current beyond 1.5A.

IS2083
Any device (such as the IS2083BM) that connects to any USB receptacle and uses that power to run itself or charge
a battery, must know how much current is appropriate to draw. Attempting to draw 1A from a source capable of
supplying only 500mA would not be good. An overloaded USB port will likely shut down or blow a fuse. Even with
resettable protection, it will often not restart until the device is unplugged and reconnected. In ports with less rigorous
protection, an overloaded port can cause the entire system to Reset. Once the USB transceiver determines the
battery charger profile and port type (SDP, CDP, DCP), it interrupts the CPU, which then reads the battery charger
profile and port type information out of the USB registers. It uses this information to program the PMU (via the 3-wire
PMU interface) with the configuration corresponding to the battery charger profile and port type.
Figure 6-3. USB Battery Charger 1.2 DCP/SDP/CDP Signaling
6.8 SAR ADC

The IS2083BM SoC has a 10-bit Successive Approximation Register (SAR) ADC with ENOB (Effective Number of
Bits) of 8-bits; used for battery voltage detection, adapter voltage detection, charger thermal protection, and ambient
temperature detection. The input power of the SAR ADC is supplied by the 1.8V output of Buck2. The warning level
can be programmed by using the Config Tool or the SDK.
The SK1 and SK2 are the ADC channel pins. The SK1 is used for charger thermal protection. The following figure
illustrates the suggested circuit and thermistor, Murata NCP15WF104F. The charger thermal protection can avoid
battery charge in a restricted temperature range. The upper and lower limits for temperature values can be
configured by using the Config Tool.

IS2083
Figure 6-4. Ambient Detection Circuit

VDD_IO
R1
1M/1%
SK1
C1
1 µ F, 16V R2
86.6k/1%
TR1
100k
Thermistor: Murata NCP15WF104F
Note: The thermistor must be placed close to the battery in the user application for accurate temperature
measurements and to enable the thermal shutdown feature.
The following figures show SK1 and SK2 channel behavior.
Figure 6-5. SK1 Channel

IS2083
Figure 6-6. SK2 Channel
6.9 LED Driver

The IS2083BM has two LED drivers to control external LEDs. The LED drivers provide enough sink current (16-step
control and 0.35 mA for each step) and the LED can be connected directly to the IS2083BM. The LED settings can
be configured by using the Config Tool. The following figure illustrates the LED drivers in the IS2083BM.
Figure 6-7. LED Driver
IS2083BM
SYS_PWR
LED1
LED2

IS2083
Application Information
7. Application Information
7.1 Power On/Off Sequence

In Embedded mode, the BM83 module utilizes the MFB button to turn on and turn off the system. For Host mode,
refer to 7.6 Host MCU Interface. The following figure illustrates the system behavior (Embedded mode) upon a MFB
press event to turn on and turn off the system.
Figure 7-1. Timing Sequence of Power On/Off in Embedded Mode
BAT_IN
SYS_PWR Turn On Turn Off
MFB
VDD_IO
RST_N
BK1
BK2
LDO31
The following figure illustrates the system behavior (Embedded mode) upon a MFB press event to turn on the system
and then trigger a Reset event.
Figure 7-2. Timing Sequence of Power On and Reset Trigger in Embedded Mode
BAT_IN
SYS_PWR Turn On
MFB
VDD_IO Reset Trigger
RST_N
BK1
BK2
LDO31

IS2083
7.2 Reset
The Reset logic generates proper sequence to the device during Reset events. The Reset sources include external
Reset, power-up Reset, and Watchdog Timer (WDT). The IS2083 SoC provides a WDT to Reset the chip. In addition,
it has an integrated Power-on Reset (POR) circuit that resets all circuits to a known Power On state. This action can
also be driven by an external Reset signal, which is used to control the device externally by forcing it into a POR
state. The following figure illustrates the system behavior upon a RST_N event.
Note: The Reset (RST_N) is an active-low signal and can be utilized based on the application needs, otherwise, it
can be left floating.
Figure 7-3. Timing Sequence of Reset Trigger
BAT_IN
SYS_PWR
MFB
VDD_IO
RST_N
0 ms 200 ms
BK1
BK2
LDO31
Note: RST_N pin has an internal pull-up, thus, RST_N signal will transition to high again upon releasing the RST_N
button. This is an expected behavior of RST_N signal.
Figure 7-4. Timing Sequence of Power Drop Protection
Power
2.93V
SYS_PWR
2.7V
SYS_PWR
IS2083
Reset IC
RST_N from Reset IC Reset OUT VDD
GND
MCU Reset
Timing sequence of power drop protection:

• It is recommended to use the battery to provide the power supply at BAT_IN.
• If an external power source or a power adapter is utilized to provide power to BAT_IN, it is recommended to use
a voltage supervisor Integrated Circuit (IC).
• The Reset IC output pin, RST_N, must be open drain type and threshold voltage as 2.93V.
• The RST_N signal must be fully pulled low before SYS_PWR power drop to 2.7V.

IS2083
7.3 Programming and Debugging

The IS2083BM devices contain 2 MB of Flash memory which is interfaced using Serial Quad Interface (SQI). The
below section defines the external SQI (Serial Quad Interface) Flash programming specification for the IS2083BM
family of 8-bit microcontrollers to support external Flash programming. The following figure illustrates a typical
programming setup which contains an external programmer tool and a target device (IS2083BM). The programmer
tool is responsible for executing necessary programming steps and completing the operations.
Figure 7-5. Programming Setup
External Programmer IS2083BM

JTAG
or
SQI
ICSPTM
Interface
Interface
In-Package Serial
Flash
7.3.1 Test Mode

The Test mode allows an external UART host to communicate with the device using Bluetooth vendor commands
over the UART interface. The host can interface with the driver firmware on the device to perform TX/RX operations
and to collect/report Bit Error Rate (BER) and other RF performance parameters. These values can then be used to
accept/reject the device and/or calibrate the module.
Test mode is entered by pulling the PORT3_4 pin to low during start-up/Reset. The pin PORT3_4 can be used as
GPIO pin, if the pin level is high during start-up/Reset. The boot code residing in the boot ROM is responsible for
identifying this event, setting the CFGMODE [TEST_MODE] bit, and then performing a Reset of the device using the
RST_N pin.
The following table provides the configurations required to set the Test mode or Application mode.
Table 7-1. Test Mode Configuration Settings
Pins Status Mode
P3_4 Low Test mode

Floating Application mode
To exit from Test mode (regardless of how it is entered), firmware can clear the Test mode bit, and perform a device
Reset, either by asserting RST_N pin or by a Software Reset.
7.3.2 Flash Memory and SQI Controller

This section covers various aspects of SQI controller and Flash memory, which are essential for programming.
The SQI module is a synchronous serial interface that provides access to serial Flash memories and other serial
devices. The SQI module supports Single Lane (identical to SPI), Dual Lane, and Quad Lane interface modes. Refer
to the Serial Quad Interface (SQI) Documentation for more information: http://ww1.microchip.com/downloads/en/
DeviceDoc/60001244C.pdf.
7.3.2.1 SQI Controller

1. SQI controller is used to control the In-package serial Flash. It provides following functions:
– Command mode
– Memory mapped read

IS2083
– Memory mapped write

The SQI controller provides both SPI and SQI mode. The device’s initial state after a POR is SPI mode. A command
instruction configures the device to SQI mode. The data flow in the SQI mode is similar to the SPI mode, except it
uses four multiplexed I/O signals for command, address, and data sequence. Users are responsible to switch the
mode. The SQI mode is overridden by next usage; users must set to the right mode before using it.
7.3.3 2-wire Interface

The IS2083BM devices provide physical interface for connecting and programming the memory contents, see the
following figure. For all programming interfaces, the target device must be powered, and all required signals must be
connected. In addition, the interface must be enabled through a special initialization sequence.
Figure 7-6. 2-wire ICSP Interface
Programmer/ 2-Wire
IS283BM
IS2083BM
SoC
Debugger ICSP TM
The 2-wire ICSP port is used as interface to connect a Programmer/Debugger in IS2083BM device. The following
table provides the required pin connections. This interface uses the following two communication lines to transfer
data to and from the IS2083BM device being programmed:
• Serial Program Clock (TCK_CPU)
• Serial Program Data (TDI_CPU)
These signals are described in the following two sections. Refer to the specific device data sheet for the connection
of the signals to the chip pins. The following table describes the 2-wire interface pins.
Table 7-2. 2-wire Interface Pin Description
Pin Name Pin Type Description

RST_N I Reset pin
VDD_IO, ADAP_IN, BAT_IN P Power supply pins
GND P Ground pin
TCK_CPU I Primary programming pin pair: Serial Clock
TDI_CPU I/O Primary programming pin pair: Serial Data
Note: For more details, refer to the IS2083 SDK Debugger User's Guide.
7.3.3.1 Serial Program Clock

Serial Program Clock (TCK_CPU) is the clock that controls the updating of the TAP controller and the shifting of data
through the Instruction or selected data registers. TCK_CPU is independent of the processor clock, with respect to
both frequency and phase.
7.3.3.2 Serial Program Data

Serial Program Data (TDI_CPU) is the data input/output to the instruction or selected data registers. In addition, it is
the control signal for the TAP controller. This signal is sampled on the falling edge of TDI_CPU for some TAP
controller states.

IS2083
7.3.4 Enabling Programming Interface

On the IS2083BM, programming interfaces are enabled using the standard Microchip test patterns. Once RST_N is
asserted (low), the user may provide an entry sequence on any TSTC2ENTRY and TSTD2ENTRY pin pair on the
device. Once RST_N is de-asserted (high), the corresponding programming interface is enabled as per the entry
sequence.
The TSTC2ENTRY/TSTD2ENTRY pin pairs are mapped on top of the CPU JTAG interface, so that 2-wire
programming and debug interface may be enabled by controlling only 3 device pins (RST_N and 2 entry pins).
The programming/debugging mode is entry sequence for 2-wire mode is shown in the following table and the timing
diagram is shown in the following figure.
Table 7-3. CPU Programming/Debugging Mode Entry
Debug Mode Entry Sequence Mode
TSTC 4D43 4851 “MCHQ” CPU/DSP 2-wire Debug mode

TSTD
Vdd
RST_N
Figure 7-7. CPU Programming/Debug Mode Entry
RST_N
32 clock pulses
TSTCnENTRY
TSTDnENTRY 1 2 3 ..... 31 32
Device State Reset TMODn
tst_pat_tmod[3:0] Reset value TMODn
7.3.5 On-chip Instrumentation

The OCI unit serves as an interface for On-chip Instrumentation. The OCI provides following functions for
communication with On-chip Instrumentation.
• Run/Stop control
• Single Step mode
• Software breakpoint
• Debug program
• Hardware breakpoint
• Program trace
• Access to ACC
7.3.5.1 Enabling OCI Functionality

Enabling the OCI is done by clearing the OCI_OFF bit in the OCI_DEBUG SFR register. By default, OCI is enabled
after a device POR.
7.3.5.2 Entering Debug Mode

Debug mode is entered by using the CPU 2-wire Test Mode Entry interface. On entry into Debug mode, the OCI
holds the CPU and Watchdog Timer in the Reset state using JReset until the external debugger asserts DebugReq
using the DebugReqOn JTAG instruction. This allows the debugger to configure the device before the CPU boots-up.

IS2083
7.3.5.3 Reading the Debug Status

There is no explicit status data register, rather, the status value is shifted out when a new JTAG Instruction Register
(IR) value is shifted in.
7.3.5.4 Reading the Program Counter

The current value of the CPU program counter may be read using the Get PC JTAG instruction. In PC16 mode, only
the least significant 16 bits (PC[15:0]) are valid.
7.3.5.5 Stopping Program Execution (Entering Debug Mode)

To enter Debug mode, the debugger issues the DebugReqOn JTAG instruction, which asserts the DebugReq input to
the CPU core. Once the CPU enters Debug mode, the DebugAck signal is asserted, which can be determined by
reading the Status. DebugAck or Result.DebugAckN register bits.
7.3.5.6 Starting Program Execution (Exiting Debug Mode)

To exit Debug mode, the debugger issues the DebugReqOff JTAG instruction, which negates the DebugReq input to
the CPU core. Once the CPU exits Debug mode, the DebugAck signal is negated, which can be determined by
reading the Status. DebugAck or Result.DebugAckN register bits.
7.3.5.7 User Single Step Mode

User Single Step mode, in which the CPU single steps through the code in Program Memory, is enabled when the
debugger issues the DebugStepUser JTAG instruction. From Debug mode, the OCI executes one user instruction
by pulsing DebugStep active for one clock (or until the first program fetch has completed). The core responds by
fetching and executing one instruction, then returning to Debug mode. DebugAck is negated during the step.
7.3.5.8 OCI Single Step Mode

OCI Single Step mode, also known as Programming mode, is used to execute instructions from the debugger,
typically for the purposes of programming the device. This mode is enabled when the debugger issues the
DebugStepOCI JTAG instruction. Each instruction is fed into the CPU by writing it into the result register.
When device programming is being done over the OCI, the DebugPswrOn JTAG instruction may be issued to re-
direct External Data Writes to Program Memory. The DebugPswrOff JTAG instruction may be issued to disable this
re-direction. On this device, which presents a unified Program/Data memory, this re-direction is not necessary, as the
Program RAM can be written via the external data bus.
7.3.5.9 Setting Software Breakpoints

Software breakpoints may be set by replacing the instruction with a TRAP instruction (opcode 0xA5). Upon execution
of the TRAP instruction, the core switches to Debug mode and asserts DebugAck. Through the JTAG port, the
debugger system periodically polls Status.DebugAck (by issuing the DebugNOP JTAG instruction) and begins
breakpoint processing when it becomes asserted. For breakpoints in read-only memories, Debug triggers may be
used to set hardware breakpoints.
7.3.5.10 Simple and Complex Debug Triggers

The OCI provides a set of hardware breakpoint or trigger registers that monitor bus activity and perform various
actions when specified bus events occur. Complex triggers allow a range of addresses to be matched for a trigger
rather than a single address, as is the case for a simple trigger.
7.3.5.11 Reading and Writing Memory/SFR Registers

To read from or write to an internal resource, such as a memory or SFR registers, the OCI Single Step mode is used.
In this mode, the external debugger can feed in an instruction sequence to perform the requested read/write
operation. Read values are placed into the accumulator, which may then be read out of the result register using the
DebugNOP JTAG instruction.
7.3.5.12 Trace Buffer

The IS2083BM 8051 MCU implements a trace buffer to trace the messages from the OCI to the off-chip debugger.
7.3.5.13 Instruction Trace

The trace buffer memory stores the branches executed by the core. At every change of flow, the most recent PC from
the old code sequence and the first PC from the new sequence are stored together as a trace record (frame).
Change of flow events include branches, calls, returns, interrupts, and resets.

IS2083
7.4 General Purpose I/O Pins

The IS2083BM provides up to 19 GPIOs that can be configured by using the Config Tool. The MFB (PWR) pin must
be configured as the power On/Off key, and the remaining pins can be configured for any one of the default functions
as provided in the following table.
Table 7-4. GPIO Assigned Pins Function(1)
Pin Name Function Assigned (in Embedded Mode)

P0_0 External codec reset
P0_1 Forward (FWD) button
P0_2 Play or pause (PLAY/PAUSE) button
P0_3 Reverse (REV) button
P0_5 Volume decrease (VOL_DN) button
P0_6 Available for user configuration
P1_2 I2C SCL (muxed with 2-wire CPU debug data)
P1_3 I2C (muxed with 2-wire CPU debug clock)
P1_6 PWM
P2_7 Volume increase (VOL_UP) button
P3_2 Line-In detect
P3_4 SYS_CFG (muxed with UART_RTS)(2)
P8_5 UART_TXD(3)(4)
P8_6 UART_RXD(3)(4)
1. This table reflects the default IO assignment as per the Embedded mode. The GPIOs are user configurable by
Config Tool.
2. GPIO P3_4 is used to enter Test mode during reset. If the user wants to use this pin to control external
peripherals, care must be taken to ensure this pin is not pulled LOW and accidentally enters Test mode.
3. Microchip recommends to reserve UART port (P8_5 and P8_6) for Flash download in Test mode during
production.
4. Currently, GPIOs ports P8_5 and P8_6 APIs (button detect driver) are not implemented.
7.5 I2S Mode Application

The IS2083BM SoC provides one I2S digital audio I/O interface to connect with an external codec or DSP. It provides
8, 16, 44.1, 48, 88.2 and 96 kHz sampling rates for 16- and 24-bit data formats. The I2S settings can be configured
by the Config Tool. The I2S pins are as follows:
• SCLK1: Serial/Bit clock (IS2083BM input/output)
• RFS1: Receive frame sync (IS2083BM input/output)
• MCLK: Master clock (IS2083BM output)

IS2083
• DR1: Receive data (IS2083BM input)

• DT1: Transmit data (IS2083BM output)
The MCLK is the master clock output provided to an external I2S device to use as its system clock. This signal is
optional and is not required if the external I2S device provides its own system clock. This signal is not used with the
internal audio codec.
The following figures illustrate the I2S signal connection between the IS2083BM and an external DSP. The Config
Tool can be used to configure the IS2083BM as a master or slave.
Note: In this context, the terms “master” and “slave” refer to the I2S clocks and frame syncs, not to the audio data
itself.
Figure 7-8. IS2083BM in I2S Master Mode
External DSP/ IS2083BM

Codec
BCLK SCLK1
DACLRC RFS1
MCLK MCLK
ADCDAT DR1
DACDAT DT1
Figure 7-9. IS2083BM in I2S Slave Mode
External DSP/ IS2083BM

Codec
BCLK SCLK1
DACLRC RFS1
ADCDAT DR1
DACDAT DT1
7.6 Host MCU Interface

The IS2083BM multi-speaker firmware supports following modes of operation:
• Embedded mode
– In this mode, an external microcontroller (MCU) is not required. The multi-speaker (MSPK) firmware is
integrated on the IS2083BM to perform application specific controls.
• Host mode:
– Requires an external MCU for application specific system control. The host MCU can control IS2083BM
through UART command set.
The following figure illustrates the UART interface between the IS2083BM and an external MCU.

IS2083
Figure 7-10. Host MCU Interface Over UART
MCU IS2083BM
MCU_WAKE UP P0_0
UART_RX UART_TXD
UART_TX UART_RXD
MFB MFB
GPIO RST_N
Note: For more details, refer to the IS2083 Bluetooth® Audio Application Design Guide Application Note.
All registers and flip-flops are synchronously Reset by an active-high internal Reset signal. External hardware Reset,
or Watchdog Timer Reset can activate the Reset state. A high on RST_N pin or Watchdog Reset request for two
clock cycles, while the oscillator is running, resets the device. The falling edge of clock is used for synchronization of
the Reset signal. It ensures that all flip-flops are triggered by system clock and gated clocks are properly Reset.
Although a device POR (from the on-chip CLDO) does not explicitly drive the reset tree, but rather causes the
assertion of the RST_N pin as follows:
1. POR causes the RST_N pad to drive '0' out.
2. Since the RST_N input buffer is always enabled, during a POR, the ‘0’ propagates to the RST_N input buffer.
3. The RSTGEN modules see the RST_N pin asserted.

IS2083
Electrical Specifications
8. Electrical Specifications
This section provides an overview of the IS2083BM device’s electrical characteristics.
Table 8-1. Absolute Maximum Ratings
Parameter Min. Typ. Max. Unit

Ambient temperature under bias (TAMBIENT) –40 — +85 ºC
Storage temperature (TSTORAGE) –65 — +150 ºC
Digital core supply voltage (VDD_CORE) 0 — 1.35 V
RF supply voltage (VCC_RF) 0 — 1.35 V
SAR ADC supply voltage (SAR_VDD) 0 — 2.1 V
Codec supply voltage (VDDA/VDDAO) 0 — 3.3 V
I/O supply voltage (VDD_IO) 0 — 3.6 V
Buck1 and Buck2 supply voltage (BK1_VDD and 0 — 4.3 V
BK2_VDD)
Supply voltage (LDO31_VIN) 0 — 4.3 V
Battery input voltage (VBAT_IN) 0 — 4.3 V
Adapter input voltage (VADAP_IN) 0 — 7.0 V
Junction operating temperature (TJUNCTION) –40 — +125 ºC
Stresses listed on the preceding table cause permanent damage to the device. This is a stress rating only.
CAUTION
The functional operation of the device at those or any other conditions and those indicated in the operation
listings of this specification are not implied. Exposure to maximum rating conditions for extended periods
affects device reliability.
The following tables provide the recommended operating conditions and the electrical specifications of the IS2083BM
SoC.
Table 8-2. Recommended Operating Condition

Digital core supply voltage (VDD_CORE) 1.14 1.2 1.26 V
RF supply voltage (VCC_RF) 1.22 1.28 1.34 V
SAR ADC supply voltage (SAR_VDD) 1.62 1.8 1.98 V
Codec supply voltage (VDDA) 1.62 1.8 1.98 V
I/O supply voltage (VDD_IO) 3.0 3.3 3.6 V
Buck1 supply voltage (BK1_VDD) 3.0 3.8 4.25 V
Buck2 supply voltage (BK2_VDD) 3.0 3.8 4.25 V
Supply voltage (LDO31_VIN) 3.0 3.8 4.25 V
Input voltage for battery (VBAT_IN) 3.2 3.8 4.2 V
Input voltage for adapter (VADAP_IN(1)) 4.5 5 5.5 V
Operation temperature (TOPERATION) -40 +25 +85 ºC

IS2083
1. ADAP_IN is recommended only for charging the battery in the battery-powered applications.
Table 8-3. Buck1 (RF/Core/ULPC) Switching Regulator(1)

Input voltage 3.0 3.8 4.25 V
Output voltage (Iload = 70 mA and VIN = 4V) 1.4 1.5 1.75 V
Output voltage accuracy — ±5 — %
Output voltage adjustable step — 50 — mV/Step
Output adjustment range –0.1 — +0.25 V
Average load current (Iload) 120 — — mA
Conversion efficiency (VBAT_IN = 3.8V and Iload = 50 mA) — 88 (2) — %
Quiescent current (PFM) — — 40 μA
Output current (peak) 200 — — mA
Shutdown current — — <1 μA
1. These parameters are characterized, but not tested on the production device.
2. Test condition: Temperature +25ºC and wired inductor 10 μH.
Table 8-4. Buck2 (Audio Codec) Switching Regulator(1)

Output voltage (Iload = 70 mA, VIN = 4V 1.7 1.8 2.05 V
Output voltage accuracy — ±5 — %
Output voltage adjustable step — 50 — mV/Step
Output adjustment range –0.1 — +0.25 V
Average load current (Iload) 120 — — mA
Conversion efficiency — 88(2) — %
(VBAT_IN = 3.8V, Iload= 50 mA)
Quiescent current (PFM) — — 40 µA

Output current (peak) 200 — — mA
Shutdown current — — <1 µA
1. These parameters are characterized, but not tested on the production device.
2. Test condition: Temperature +25ºC and wired inductor 10 μH.
Table 8-5. LDO Regulator(1)

Output voltage LDO31_VO — 3.3 — V
Output accuracy (VIN= 3.7V, Iload= 100 mA and +27ºC) — ±5 — %
Average output current — — 100 mA

IS2083
Drop-out voltage (Iload = maximum output current) — — 300 mA
Quiescent current (excluding load and Iload < 1 mA) — 45 — µA
Shutdown current — — <1 µA
1. These parameters are characterized, but not tested on production device.

2. Test condition: Temperature +25ºC. The above measurements are done at +25ºC.
Table 8-6. Battery Charger (1)

Adapter input voltage (VADAP_IN) 4.6(2) 5.0 5.5 V
Supply current (only charger) — 3 4.5 mA
Maximum battery fast charge Headroom(3) > 0.7V — 350 — mA
current (VADAP_IN = 5V)
Headroom = 0.3V to 0.7V — 175(4) — mA
(VADAP_IN = 4.5V)
Trickle charge voltage threshold — 3 — V
Battery charge termination current (% of fast charge — 10 — %
current)

2. It needs more time to get battery fully charged when ADAP_IN = 4.5V.
3. Headroom = VADAP_IN – VBAT_IN.
4. When VADAP_IN – VBAT_IN > 2V, the maximum fast charge current is 175 mA for thermal protection.
Table 8-7. SAR ADC Operating Conditions
Parameter Condition Min. Typ. Max. Unit

Shutdown current (IOFF) PDI_ADC = 1 — — 1 μA
Resolution — — 10 — bits
Effective Number of Bits (ENOB) — 7 8 — bits
SAR core clock (FCLOCK) — — 0.5 1 MHz
Conversion time per channel 10 FCLOCK cycles 10 20 — μs
(TCONV)
Offset error (EOFFSET) — -5 — +5 %
Gain error (EGAIN) — — — +1 %
ADC SAR core power-up (tPU) PDI_ADC transitions — — 500 ns
from 1 to 0

IS2083
Parameter Condition Min. Typ. Max. Unit
Input voltage range (VIN) Channel 8 (SK2 Pin) 0.25 — 1.4 V
Channel 9 (SK1 Pin) 0.25 — 1.4 V
Channel 10 (OTP) 0.25 — 1.4 V
Channel 11 (ADAP_IN 2.25 — 12.6 V
Pin)
Channel 12 (BAT_IN 1.0 — 5.6 V
Pin)
Table 8-8. LED Driver(1)

Open-drain voltage — — 3.6 V
Programmable current range 0 — 5.25 mA
Intensity control — 16 — step
Current step — 0.35 — mA
Power-down open-drain current — — 1 μA
Shutdown current — — 1 μA

Table 8-9. Audio Codec Digital-to-Analog Converter
Parameters Min. Typ. Max. Unit

DC Specifications
Shutdown mode current — — 2 μA
Over-sampling rate — 128 — fs
Sample width resolution 16 — 20 Bits
Output sample rate 8 — 48 kHz
Digital gain –54 — 4.85 dB
Digital gain resolution 2 6 0 dB
Analog gain –28 — 3 dB
Analog gain resolution — 1 — dB
Turn ON/OFF click and pop Single-ended — — 2 mV
level
Capless — — 1 mV
Gain pop — 1 1 mV
Allowed load Resistive 16 — — Ω
Capacitive — — 500 pF
AC Specifications(1)
SNR – Capless mode AVDD = 1.8V 93 — — dB
SNR – Cap mode AVDD = 1.8V 95 — — dB

IS2083
Parameters Min. Typ. Max. Unit
Output voltage full-scale swing 495 (1.4) 742.5 (2.1) — mV rms
(Vpp)
Total harmonic distortion AVDD = 1.8V — –80 — dB
Inter-channel isolation –90 –80 — dB
Dynamic range Capless and Single- — 95 — dB
ended
Playback Mode Power
Stereo mode current (16Ω or Capless — 2 — mA
unload)
Single-ended — 1.85 —
Mono mode current (16Ω or Capless — 1.55 — mA
unload)
Single-ended — 1.40 —
Maximum output power (AVDD Capless — 14 — mW
= 1.8V)
Single-ended — 14 — mW
1. fin = 1 kHz, bandwidth = 20 Hz to 20 kHz, A-weighted, THD+N < 0.01%, 0 dBFS signal, load = 100 kΩ.
Table 8-10. Audio Codec Analog-to-Digital Converter
Parameter (Condition) Min. Typ. Max. Unit

DC Specifications
Shutdown mode — 1 2 µA
Sample width resolution — — 16 Bits
Input sample rate 8 — 48 kHz
Digital gain –54 — 4.85 dB
Digital gain resolution 2 6 — dB
Microphone boost gain — 20 — dB
Analog gain step — 1 — dB
Input full-scale at maximum gain (Differential) — 4 — mV rms
Input full-scale at minimum gain (Differential) — 800 — mV rms
3 dB bandwidth — 20 — kHz
Microphone mode input impedance (Resistance) — 6 10 kΩ
Microphone mode input impedance (Capacitance) — — 20 pF
AC Specifications(1)
SNR (AVDD = 1.8V) 88 — — dB
Total harmonic distortion (AVDD = 1.8V) — –70 — dB
Dynamic range (AVDD = 1.8V) — –88 — dB
THD+N (microphone input) at 30 mVrms input — 0.02 — %
Record Mode Power

IS2083
Parameter (Condition) Min. Typ. Max. Unit
Stereo Record mode current — 1.75 — mA
Mono Record mode current — 0.95 — mA
1. fin = 1 kHz, bandwidth= 20 Hz to 20 kHz, A-weighted, THD+N <1%, 150 mVPP input.
Table 8-11. Transmitter Section Class1 (MPA Configuration) for BDR and EDR(1, 2)
Parameter(3, 4) Bluetooth Specification Min. Typ. Max. Unit

Transmit power BDR 0 to 20 10.5 11 11.5 dBm
Transmit power EDR 2M 0 to 20 9 9.5 10 dBm
Transmit power EDR 3M 0 to 20 9 9.5 10 dBm

2. Test condition: VCC_RF = 1.28V, temperature +25ºC.
3. The RF transmit power is the average power measured for the mid-channel (Channel 39).
4. The RF transmit power is calibrated during production using the MP tool software and MT8852 Bluetooth test
equipment.
Table 8-12. Transmitter Section Class2 (LPA Configuration) for BDR and EDR(1, 2)
Parameter(3, 4) Bluetooth Specification Min. Typ. Max. Unit

Transmit power BDR –6 to 4 1.5 2 2.5 dBm
Transmit power EDR 2M –6 to 4 0 0.5 1 dBm
Transmit power EDR 3M –6 to 4 0 0.5 1 dBm

3. The RF transmit power is the average power measured for the mid-channel (Channel 39).
4. The RF transmit power is calibrated during production using the MP tool software and MT8852 Bluetooth test
equipment.
Table 8-13. Receiver Section for BDR, EDR, Bluetooth Low Energy(1, 2)
Parameter Packet Type Bluetooth Min. Typ. Max. Unit

Specification
Sensitivity at 0.1% GFSK ≤–70 — –88 — dBm
BER
Sensitivity at π/4 DQPSK ≤–70 — –90 — dBm
0.01% BER
8 DPSK ≤–70 — –84 — dBm
Sensitivity at 0.1% Bluetooth Low ≤–70 — –92 — dBm
BER Energy


IS2083
Table 8-14. IS2083BM System Current Consumption(1)
Modes Condition Role Packet Type Current (Typ.) Unit

A2DP mode Internal codec, iOS Master Slave 2DH5/3DH5 12.0576 mA
Internal codec, Android™ Master 3DH5 12.3218 mA
Slave
Sniff mode(2) Internal codec, Bluetooth Slave DM1 547.232 µA
Low Energy disabled
Master 2DH1/3DH1 555.7494 µA
Internal codec, Bluetooth Slave DM1 832.109 µA
Low Energy enabled
Master 2DH1/3DH1 863.8432 µA
SCO/eSCO Mute at both far end and Slave 2EV3 14.1004 mA
connection near end
Master 2EV3 13.9436 mA
Inquiry scan Bluetooth Low Energy ─ ─ 1.354 mA
disabled
Bluetooth Low Energy ─ ─ 1.704 mA
enabled
Standby System off Slave ─ 2.8162 µA
mode
Master ─ 2.855 µA
RF modes(3) Continuous TX mode Modulation OFF, PL0 59 mA
Modulation 30 mA
ON, PL0
Modulation 35.5 mA
OFF, PL2
Modulation 22 mA
ON, PL2
Continuous RX mode Packet count disable 49 mA
Packet count enable 38.5 mA
1. Measurement conditions are:

– VBAT_IN = 3.8V; current measured across BAT_IN
– Standalone BM83 DVT3 module used for measurements; no LEDs, no speaker load.
– iPhone6 (iOS v12.2) and OnePlus6 (Android Oxygen version 9.0.3) used for measurements.
– Current measurements average over a period of 120 secs.
– Distance between DUT (BM83) and Bluetooth source (smartphone) is 30 cms.
– All measurements are taken inside a shield room.
2. Internal Codec mode enabled, UART disabled, Auto-Unsniff mode is disabled.
3. RF TX power is set to 10 dBm.
8.1 Timing Specifications

The following figures illustrate the timing diagram of the IS2083BM/BM83 in I2S and PCM modes.

IS2083
Figure 8-1. Timing Diagram for I2S Modes (Master/Slave)
1/fs
SCLK1
RFS1
Left channel Right channel
DR1/DT1 Bn-1 Bn-2 B1 B0 Bn-1 Bn-2 B1 Bn
Word length
Figure 8-2. Timing Diagram for PCM Modes (Master/Slave)
1/fs
SCLK1
RFS1
Left channel Right channel
DR1/DT1 Bn-1 Bn-2 B1 Bn Bn-1 Bn-2 B1 Bn
Word length
The following figure illustrates the timing diagram of the audio interface.
Figure 8-3. Audio Interface Timing Diagram
tSCLKCH tSCLKCL
SCLK1 tSCLKCY
RFS1
tRFSH tRFSSU
DR1
tDH
The following table provides the timing specifications of the audio interface.
Table 8-15. Audio Interface Timing Specifications (1)
Parameter Symbol Min. Typ. Max. Unit

SCLK1 duty ratio dSCLK — 50 — %

IS2083
Parameter Symbol Min. Typ. Max. Unit
SCLK1 cycle time tSCLKCY 50 — — ns
SCLK1 pulse width high tSCLKCH 20 — — ns
SCLK1 pulse width low tSCLKCL 20 — — ns
RFS1 setup time to SCLK1 rising edge tRFSSU 10 — — ns
RFS1 hold time from SCLK1 rising edge tRFSH 10 — — ns
DR1 hold time from SCLK1 rising edge tDH 10 — — ns
1. Test Conditions: Slave mode, fs = 48 kHz, 24-bit data, and SCLK1 period = 256 fs.

IS2083
Package Information
9. Package Information
Note: For the most recent package drawings, see the Microchip Packaging Specification located at http://
www.microchip.com/packaging.
Figure 9-1. 82-Ball Very Thin Fine Pitch Ball Grid Array (3MX) - 5.5x5.5 mm Body [VFBGA]
D A
NOTE 1 B
1 2 3 4 5 6 7 8 9 10
A
B
C
D
(DATUM B)
E
F
E
(DATUM A) G
H
J
2X
K
0.10 C
2X
0.10 C
TOP VIEW
(A2) A1
0.10 C
C
SEATING A
PLANE 82X
(A3) 0.08 C
SIDE VIEW
D1
1 2 3 4 5 6 7 8 9 10
K
J
H
G
F
E e E1
e D
2
C
B
A
NOTE 1
e
BOTTOM VIEW

IS2083
Package Information
Figure 9-2. 82-Ball Very Thin Fine Pitch Ball Grid Array (3MX) - 5.5x5.5 mm Body [VFBGA]
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 82
Pitch e 0.50 BSC
Overall Height A - - 0.90
Standoff A1 0.11 - 0.21
Mold Thickness A2 0.54 REF
Substrate Thickness A3 0.125 REF
Overall Length D 5.50 BSC
Overall Terminal Spacing D1 4.50 BSC
Overall Width E 5.50 BSC
Overall Terminal Spacing E1 4.50 BSC
Terminal Diameter b 0.20 0.25 0.30
Notes :
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.

IS2083
Package Information
Figure 9-3. IS2083BM Recommended Land Pattern

1 2 3 4 5 6 7 8 9 10
C E
D
E
C2
F
H G
ØX
E
SILK SCREEN
C1
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.50 BSC
Overall Contact Pad Spacing C1 4.50
Overall Contact Pad Spacing C2 4.50
Contact Pad Width (X82) X 0.20
Contact Pad to Contact Pad G 0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process

IS2083
Package Information
Figure 9-4. IS2083BM Package Marking Information
XXX: Chip serial number version and e1 Pb-free JEDEC designator for SAC305
YY: Year code (last 2 digits of calendar year)

WW: Week code (week of January 1 is week "01")
NNN: Alphanumeric traceability code
Note:
(1) SAC305 is the pre-solder version. Customer needs to take care solder paste before screen printing.

IS2083
Ordering Information
10. Ordering Information

Table 10-1. Ordering Information
Device Description Package Details Part Number
IS2083BM Bluetooth Audio Dual mode Flash SoC, 2 5.5 mm X 5.5 mm X 0.9 IS2083BM-232
microphones, 1 stereo digital mm, 82 LD VFBGA
microphone, analog and I2S output
Bluetooth Audio Dual mode, Flash SoC, 5.5 mm X 5.5 mm X 0.9 IS2083BM-2L2
2 microphones, 1 stereo digital mm, 82 LD VFBGA
microphone, LDAC support and I2S
output

IS2083
Document Revision History
11. Document Revision History

Revision Date Section Description
B 09/2019 Document Minor edits.
6.1 Device Operation Updated Figure 6-1
6.7 Battery Charging Updated Figure 6-2
6.8 SAR ADC • Changed the section title to SAR ADC from Battery
Voltage Monitoring and combined Ambient
Temperature Detection Section.
• Updated contents.
7. Application • Reorganized sections in this chapter.

Information • Added 7.1 Power On/Off Sequence section.
• Updated 7.2 Reset section.
• Updated 7.4 General Purpose I/O Pins.
8. Electrical Added Table 8-7

Specifications
A 07/2019 Document Initial Revision

IS2083
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help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: http://www.microchip.com/support
Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today,
when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these
methods, to our knowledge, require using the Microchip products in a manner outside the operating
specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of
intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code
protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection
features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital
Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you
may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for your
convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with

IS2083
your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER

EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such
use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless
otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,
BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,
KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST,
MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer,
QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control,
HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus,
ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider,
Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP,
INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,
PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad
I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-5034-4
Quality Management System

For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality.

Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Australia - Sydney India - Bangalore Austria - Wels
2355 West Chandler Blvd. Tel: 61-2-9868-6733 Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 China - Beijing India - New Delhi Fax: 43-7242-2244-393
Tel: 480-792-7200 Tel: 86-10-8569-7000 Tel: 91-11-4160-8631 Denmark - Copenhagen
Fax: 480-792-7277 China - Chengdu India - Pune Tel: 45-4450-2828
Technical Support: Tel: 86-28-8665-5511 Tel: 91-20-4121-0141 Fax: 45-4485-2829
http://www.microchip.com/support China - Chongqing Japan - Osaka Finland - Espoo
Web Address: Tel: 86-23-8980-9588 Tel: 81-6-6152-7160 Tel: 358-9-4520-820
http://www.microchip.com China - Dongguan Japan - Tokyo France - Paris
Atlanta Tel: 86-769-8702-9880 Tel: 81-3-6880- 3770 Tel: 33-1-69-53-63-20
Duluth, GA China - Guangzhou Korea - Daegu Fax: 33-1-69-30-90-79
Tel: 678-957-9614 Tel: 86-20-8755-8029 Tel: 82-53-744-4301 Germany - Garching
Fax: 678-957-1455 China - Hangzhou Korea - Seoul Tel: 49-8931-9700
Austin, TX Tel: 86-571-8792-8115 Tel: 82-2-554-7200 Germany - Haan
Tel: 512-257-3370 China - Hong Kong SAR Malaysia - Kuala Lumpur Tel: 49-2129-3766400
Boston Tel: 852-2943-5100 Tel: 60-3-7651-7906 Germany - Heilbronn
Westborough, MA China - Nanjing Malaysia - Penang Tel: 49-7131-72400
Tel: 774-760-0087 Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Germany - Karlsruhe
Fax: 774-760-0088 China - Qingdao Philippines - Manila Tel: 49-721-625370
Chicago Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Germany - Munich
Itasca, IL China - Shanghai Singapore Tel: 49-89-627-144-0
Tel: 630-285-0071 Tel: 86-21-3326-8000 Tel: 65-6334-8870 Fax: 49-89-627-144-44
Fax: 630-285-0075 China - Shenyang Taiwan - Hsin Chu Germany - Rosenheim
Dallas Tel: 86-24-2334-2829 Tel: 886-3-577-8366 Tel: 49-8031-354-560
Addison, TX China - Shenzhen Taiwan - Kaohsiung Israel - Ra’anana
Tel: 972-818-7423 Tel: 86-755-8864-2200 Tel: 886-7-213-7830 Tel: 972-9-744-7705
Fax: 972-818-2924 China - Suzhou Taiwan - Taipei Italy - Milan
Detroit Tel: 86-186-6233-1526 Tel: 886-2-2508-8600 Tel: 39-0331-742611
Novi, MI China - Wuhan Thailand - Bangkok Fax: 39-0331-466781
Tel: 248-848-4000 Tel: 86-27-5980-5300 Tel: 66-2-694-1351 Italy - Padova
Houston, TX China - Xian Vietnam - Ho Chi Minh Tel: 39-049-7625286
Tel: 281-894-5983 Tel: 86-29-8833-7252 Tel: 84-28-5448-2100 Netherlands - Drunen
Indianapolis China - Xiamen Tel: 31-416-690399
Noblesville, IN Tel: 86-592-2388138 Fax: 31-416-690340
Tel: 317-773-8323 China - Zhuhai Norway - Trondheim
Fax: 317-773-5453 Tel: 86-756-3210040 Tel: 47-72884388
Tel: 317-536-2380 Poland - Warsaw
Los Angeles Tel: 48-22-3325737
Mission Viejo, CA Romania - Bucharest
Tel: 949-462-9523 Tel: 40-21-407-87-50
Fax: 949-462-9608 Spain - Madrid
Tel: 951-273-7800 Tel: 34-91-708-08-90
Raleigh, NC Fax: 34-91-708-08-91
Tel: 919-844-7510 Sweden - Gothenberg
New York, NY Tel: 46-31-704-60-40
Tel: 631-435-6000 Sweden - Stockholm
San Jose, CA Tel: 46-8-5090-4654
Tel: 408-735-9110 UK - Wokingham
Tel: 408-436-4270 Tel: 44-118-921-5800
Canada - Toronto Fax: 44-118-921-5820
Tel: 905-695-1980
Fax: 905-695-2078

IS2083 - Datasheet

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IS2083 Bluetooth® Stereo Audio SoC Data Sheet

Radio Frequency (RF)/Analog

© 2019 Microchip Technology Inc. Datasheet DS70005403B-page 1

– Up to +11 dBm (typical) for Basic Data Rate (BDR)

DSP Voice and Audio Processing

8051 MCU Debug Features

© 2019 Microchip Technology Inc. Datasheet DS70005403B-page 2

© 2019 Microchip Technology Inc. Datasheet DS70005403B-page 3

6. Power Management Unit.......................................................................................................................34

© 2019 Microchip Technology Inc. Datasheet DS70005403B-page 4

10. Ordering Information............................................................................................................................. 61

11. Document Revision History...................................................................................................................62

The Microchip Website.................................................................................................................................63

Product Change Notification Service............................................................................................................63

Microchip Devices Code Protection Feature................................................................................................ 63

Quality Management System....................................................................................................................... 64

Worldwide Sales and Service.......................................................................................................................65

© 2019 Microchip Technology Inc. Datasheet DS70005403B-page 5

1.1 Reference Documentation

A2DP Advanced Audio Distribution Profile

AAC Advanced Audio Codec

ADC Analog-to-Digital Converter

AEC Acoustic Echo Cancellation

AFH Adaptive Frequency Hopping

ANCS Apple Notification Center Service

API Application Programming Interfaces

AVRCP Audio/Video Remote Control Profile

BDR Basic Data Rate

BER Bit Error Rate

BLE Bluetooth Low Energy

BOM Bill of Materials

BPF Band Pass Filter

CVSD Continuous Variable Slope Delta

DAC Digital-to-Analog Converter

DFU Device Firmware Upgrade

DIS Device Information Service

DLE Data Length Extension

© 2019 Microchip Technology Inc. Datasheet DS70005403B-page 6

DPSK Differential Phase Shift Keying

DQPSK Differential Quadrature Phase Shift Keying

DSP Digital Signal Processor

EDR Enhanced Data Rate

EMC Electromagnetic Compatibility

EVB Evaluation Board

FET Field Effect Transistor

GAP General Access Profile

GATT General Attribute Profile

GFSK Gaussian Frequency Shift Keying

GPIO General Purpose Input Output

GUI Graphical User Interface

HFP Hands-free Profile

HPF High Pass Filter

HSP Headset Profile

I2C Inter-Integrated Circuit

I2S Inter-IC Sound

ICSP In-Circuit Serial Programming

IDE Integrated Development Environment

IPE Integrated Programming Environment

JTAG Joint Test Action Group