Intel 3 Series Express Chipset Family: Datasheet
Intel 3 Series Express Chipset Family: Datasheet
Intel 3 Series Express Chipset Family: Datasheet
Family
Datasheet
- For the Intel® 82Q35, 82Q33, 82G33 Graphics and Memory
Controller Hub (GMCH) and Intel® 82P35 Memory Controller
Hub (MCH)
August 2007
2 Datasheet
Contents
1 Introduction ...................................................................................................19
1.1 Terminology ........................................................................................24
1.2 Reference Documents ...........................................................................26
1.3 (G)MCH Overview.................................................................................27
1.3.1 Host Interface.........................................................................27
1.3.2 System Memory Interface.........................................................28
1.3.3 Direct Media Interface (DMI).....................................................29
1.3.4 PCI Express* Interface.............................................................29
1.3.5 Graphics Features (Intel® 82Q35, 82Q33, 82G33 GMCH Only) .......30
1.3.6 SDVO and Analog Display Features (Intel® 82Q35, 82Q33,
82G33 GMCH Only) .................................................................30
1.3.7 (G)MCH Clocking .....................................................................31
1.3.8 Thermal Sensor ......................................................................31
1.3.9 Power Management .................................................................32
1.3.10 Intel® Active Management Technology (Intel® AMT)/ Controller
Link (Intel® 82Q35 GMCH Only) ................................................32
1.3.11 Intel® Trusted Execution Technology (Intel® 82Q35 GMCH Only) .... 33
1.3.12 Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
(Intel® 82Q35 GMCH Only) .......................................................33
2 Signal Description ...........................................................................................35
2.1 Host Interface Signals ...........................................................................36
2.2 System Memory (DDR2/DDR3) Channel A Interface Signals........................40
2.3 System Memory (DDR2/DDR3) Channel B Interface Signals........................41
2.4 System Memory DDR2/DDR3 Miscellaneous Signals .................................. 42
2.5 PCI Express* Interface Signals ...............................................................43
2.6 Controller Link Interface Signals .............................................................43
2.7 Analog Display Signals (Intel® 82Q33, GMCH, 82Q33 GMCH, and 82G33
GMCH Only) ........................................................................................44
2.8 Clocks, Reset, and Miscellaneous ............................................................45
2.9 Direct Media Interface...........................................................................46
2.10 Serial DVO Interface (Intel® 82Q35, 82Q33, 82G33 GMCH Only) ................. 47
2.11 Power and Grounds ..............................................................................50
Datasheet 3
3.3 PCI Memory Address Range (TOLUD – 4GB) .............................................61
3.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ..................63
3.3.2 HSEG (FEDA_0000h–FEDB_FFFFh).............................................63
3.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................. 63
3.3.4 High BIOS Area.......................................................................63
3.4 Main Memory Address Space (4 GB to TOUUD) .........................................64
3.4.1 Memory Re-claim Background ...................................................65
3.4.2 Memory Reclaiming .................................................................65
3.5 PCI Express* Configuration Address Space...............................................65
3.6 PCI Express* Graphics Attach (PEG)........................................................66
3.7 Graphics Memory Address Ranges (Intel® 82Q35, 82Q33, and 82G33
(G)MCH Only) ......................................................................................67
3.8 System Management Mode (SMM) ..........................................................67
3.8.1 SMM Space Definition ..............................................................68
3.8.2 SMM Space Restrictions............................................................68
3.8.3 SMM Space Combinations .........................................................69
3.8.4 SMM Control Combinations .......................................................69
3.8.5 SMM Space Decode and Transaction Handling..............................69
3.8.6 Processor WB Transaction to an Enabled SMM Address Space ........69
3.8.7 SMM Access through GTT TLB (Intel® 82Q35, 82Q33, 82G33
GMCH Only) ...........................................................................70
3.9 Memory Shadowing ..............................................................................70
3.10 I/O Address Space................................................................................70
3.10.1 PCI Express* I/O Address Mapping ............................................71
3.11 (G)MCH Decode Rules and Cross-Bridge Address Mapping ..........................72
3.11.1 Legacy VGA and I/O Range Decode Rules ...................................72
4 (G)MCH Register Description ............................................................................73
4.1 Register Terminology ............................................................................74
4.2 Configuration Process and Registers ........................................................76
4.2.1 Platform Configuration Structure ...............................................76
4.3 Configuration Mechanisms .....................................................................77
4.3.1 Standard PCI Configuration Mechanism ......................................77
4.3.2 PCI Express* Enhanced Configuration Mechanism ........................77
4.4 Routing Configuration Accesses ..............................................................79
4.4.1 Internal Device Configuration Accesses.......................................80
4.4.2 Bridge Related Configuration Accesses........................................80
4.4.2.1 PCI Express* Configuration Accesses ........................... 80
4.4.2.2 DMI Configuration Accesses .......................................81
4.5 I/O Mapped Registers ...........................................................................81
4.5.1 CONFIG_ADDRESS—Configuration Address Register ..................... 81
4.5.2 CONFIG_DATA—Configuration Data Register ............................... 83
5 DRAM Controller Registers (D0:F0)....................................................................85
5.1 DRAM Controller (D0:F0).......................................................................85
5.1.1 VID—Vendor Identification........................................................87
5.1.2 DID—Device Identification ........................................................87
5.1.3 PCICMD—PCI Command ...........................................................88
5.1.4 PCISTS—PCI Status .................................................................89
5.1.5 RID—Revision Identification ......................................................90
5.1.6 CC—Class Code.......................................................................91
5.1.7 MLT—Master Latency Timer ......................................................91
5.1.8 HDR—Header Type ..................................................................92
4 Datasheet
5.1.9 SVID—Subsystem Vendor Identification......................................92
5.1.10 SID—Subsystem Identification ..................................................92
5.1.11 CAPPTR—Capabilities Pointer ....................................................93
5.1.12 PXPEPBAR—PCI Express* Egress Port Base Address .....................93
5.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base ..............94
5.1.14 GGC—GMCH Graphics Control Register (Intel® 82Q35, 82Q33,
82G33 GMCH Only) .................................................................95
5.1.15 DEVEN—Device Enable.............................................................97
5.1.16 PCIEXBAR—PCI Express* Register Range Base Address ................99
5.1.17 DMIBAR—Root Complex Register Range Base Address ................ 101
5.1.18 PAM0—Programmable Attribute Map 0...................................... 102
5.1.19 PAM1—Programmable Attribute Map 1...................................... 104
5.1.20 PAM2—Programmable Attribute Map 2...................................... 105
5.1.21 PAM3—Programmable Attribute Map 3...................................... 106
5.1.22 PAM4—Programmable Attribute Map 4...................................... 107
5.1.23 PAM5—Programmable Attribute Map 5...................................... 108
5.1.24 PAM6—Programmable Attribute Map 6...................................... 109
5.1.25 LAC—Legacy Access Control.................................................... 110
5.1.26 REMAPBASE—Remap Base Address Register.............................. 111
5.1.27 REMAPLIMIT—Remap Limit Address Register ............................. 111
5.1.28 SMRAM—System Management RAM Control .............................. 112
5.1.29 ESMRAMC—Extended System Management RAM Control ............. 113
5.1.30 TOM—Top of Memory............................................................. 114
5.1.31 TOUUD—Top of Upper Usable Dram ......................................... 115
5.1.32 GBSM—Graphics Base of Stolen Memory................................... 116
5.1.33 BGSM—Base of GTT stolen Memory.......................................... 117
5.1.34 TSEGMB—TSEG Memory Base ................................................. 117
5.1.35 TOLUD—Top of Low Usable DRAM ............................................ 118
5.1.36 ERRSTS—Error Status ............................................................ 119
5.1.37 ERRCMD—Error Command ...................................................... 121
5.1.38 SMICMD—SMI Command........................................................ 122
5.1.39 SKPD—Scratchpad Data ......................................................... 122
5.1.40 CAPID0—Capability Identifier .................................................. 123
5.2 MCHBAR ........................................................................................... 127
5.2.1 CHDECMISC—Channel Decode Miscellaneous............................. 130
5.2.2 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 ................. 131
5.2.3 C0DRB1—Channel 0 DRAM Rank Boundary Address 1 ................. 132
5.2.4 C0DRB2—Channel 0 DRAM Rank Boundary Address 2 ................. 133
5.2.5 C0DRB3—Channel 0 DRAM Rank Boundary Address 3 ................. 133
5.2.6 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute ......................... 134
5.2.7 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute ......................... 135
5.2.8 C0CYCTRKPCHG—Channel 0 CYCTRK PCHG............................... 135
5.2.9 C0CYCTRKACT—Channel 0 CYCTRK ACT ................................... 136
5.2.10 C0CYCTRKWR—Channel 0 CYCTRK WR ..................................... 137
5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ................................... 138
5.2.12 C0CYCTRKREFR—Channel 0 CYCTRK REFR ................................ 138
5.2.13 C0CKECTRL—Channel 0 CKE Control ........................................ 139
5.2.14 C0REFRCTRL—Channel 0 DRAM Refresh Control......................... 140
5.2.15 C0ODTCTRL—Channel 0 ODT Control ....................................... 142
5.2.16 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 ................. 143
5.2.17 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 ................. 143
5.2.18 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 ................. 144
5.2.19 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 ................. 144
5.2.20 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes ........................ 145
5.2.21 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes ........................ 145
Datasheet 5
5.2.22 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG............................... 146
5.2.23 C1CYCTRKACT—Channel 1 CYCTRK ACT ................................... 147
5.2.24 C1CYCTRKWR—Channel 1 CYCTRK WR ..................................... 148
5.2.25 C1CYCTRKRD—Channel 1 CYCTRK READ................................... 149
5.2.26 C1CKECTRL—Channel 1 CKE Control ........................................ 150
5.2.27 C1REFRCTRL—Channel 1 DRAM Refresh Control......................... 151
5.2.28 C1ODTCTRL—Channel 1 ODT Control ....................................... 153
5.2.29 EPC0DRB0—ME Channel 0 DRAM Rank Boundary Address 0........ 154
5.2.30 EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1 ......... 154
5.2.31 EPC0DRB2—EP Channel 0 DRAM Rank Boundary Address 2 ......... 154
5.2.32 EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3 ......... 155
5.2.33 EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute.................. 155
5.2.34 EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute.................. 156
5.2.35 EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE............................. 156
5.2.36 EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT ............................ 157
5.2.37 EPDCYCTRKWRTWR—EPD CYCTRK WRT WR .............................. 158
5.2.38 EPDCYCTRKWRTRD—EPD CYCTRK WRT READ............................ 159
5.2.39 EPDCKECONFIGREG—EPD CKE Related Configuration Register ..... 160
5.2.40 MEMEMSPACE—ME Memory Space Configuration ....................... 162
5.2.41 EPDREFCONFIG—EP DRAM Refresh Configuration....................... 163
5.2.42 TSC1—Thermal Sensor Control 1 ............................................. 165
5.2.43 TSC2—Thermal Sensor Control 2 ............................................. 166
5.2.44 TSS—Thermal Sensor Status................................................... 168
5.2.45 TSTTP—Thermal Sensor Temperature Trip Point......................... 169
5.2.46 TCO—Thermal Calibration Offset.............................................. 170
5.2.47 THERM1—Hardware Throttle Control ........................................ 171
5.2.48 TIS—Thermal Interrupt Status ................................................ 172
5.2.49 TSMICMD—Thermal SMI Command.......................................... 174
5.2.50 PMSTS—Power Management Status ......................................... 175
5.3 EPBAR .............................................................................................. 176
5.3.1 EPESD—EP Element Self Description ........................................ 176
5.3.2 EPLE1D—EP Link Entry 1 Description........................................ 177
5.3.3 EPLE1A—EP Link Entry 1 Address ............................................ 177
5.3.4 EPLE2D—EP Link Entry 2 Description........................................ 178
5.3.5 EPLE2A—EP Link Entry 2 Address ............................................ 179
6 PCI Express* Registers (D1:F0) ...................................................................... 180
6.1 PCI Express* Configuration Register Details (D1:F0) ............................... 183
6.1.1 VID1—Vendor Identification .................................................... 183
6.1.2 DID1—Device Identification .................................................... 183
6.1.3 PCICMD1—PCI Command ....................................................... 184
6.1.4 PCISTS1—PCI Status ............................................................. 186
6.1.5 RID1—Revision Identification .................................................. 187
6.1.6 CC1—Class Code ................................................................... 187
6.1.7 CL1—Cache Line Size............................................................. 188
6.1.8 HDR1—Header Type .............................................................. 188
6.1.9 PBUSN1—Primary Bus Number ................................................ 188
6.1.10 SBUSN1—Secondary Bus Number ............................................ 189
6.1.11 SUBUSN1—Subordinate Bus Number........................................ 189
6.1.12 IOBASE1—I/O Base Address ................................................... 190
6.1.13 IOLIMIT1—I/O Limit Address................................................... 190
6.1.14 SSTS1—Secondary Status ...................................................... 191
6.1.15 MBASE1—Memory Base Address.............................................. 192
6.1.16 MLIMIT1—Memory Limit Address ............................................. 193
6.1.17 PMBASE1—Prefetchable Memory Base Address .......................... 194
6 Datasheet
6.1.18 PMLIMIT1—Prefetchable Memory Limit Address.......................... 195
6.1.19 PMBASEU1—Prefetchable Memory Base Address ........................ 196
6.1.20 PMLIMITU1—Prefetchable Memory Limit Address........................ 197
6.1.21 CAPPTR1—Capabilities Pointer................................................. 198
6.1.22 INTRLINE1—Interrupt Line...................................................... 198
6.1.23 INTRPIN1—Interrupt Pin......................................................... 198
6.1.24 BCTRL1—Bridge Control ......................................................... 199
6.1.25 PM_CAPID1—Power Management Capabilities............................ 201
6.1.26 PM_CS1—Power Management Control/Status ............................ 202
6.1.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities ................ 203
6.1.28 SS—Subsystem ID and Subsystem Vendor ID ........................... 203
6.1.29 MSI_CAPID—Message Signaled Interrupts Capability ID .............. 204
6.1.30 MC—Message Control............................................................. 204
6.1.31 MA—Message Address............................................................ 205
6.1.32 MD—Message Data ................................................................ 205
6.1.33 PEG_CAPL—PCI Express*-G Capability List................................ 206
6.1.34 PEG_CAP—PCI Express*-G Capabilities..................................... 206
6.1.35 DCAP—Device Capabilities ...................................................... 207
6.1.36 DCTL—Device Control ............................................................ 208
6.1.37 DSTS—Device Status ............................................................. 209
6.1.38 LCAP—Link Capabilities .......................................................... 210
6.1.39 LCTL—Link Control ................................................................ 212
6.1.40 LSTS—Link Status ................................................................. 214
6.1.41 SLOTCAP—Slot Capabilities..................................................... 215
6.1.42 SLOTCTL—Slot Control ........................................................... 216
6.1.43 SLOTSTS—Slot Status............................................................ 219
6.1.44 RCTL—Root Control ............................................................... 220
6.1.45 RSTS—Root Status ................................................................ 221
6.1.46 PEGLC—PCI Express*-G Legacy Control .................................... 222
6.1.47 VCECH—Virtual Channel Enhanced Capability Header ................. 223
6.1.48 PVCCAP1—Port VC Capability Register 1 ................................... 223
6.1.49 PVCCAP2—Port VC Capability Register 2 ................................... 224
6.1.50 PVCCTL—Port VC Control........................................................ 224
6.1.51 VC0RCAP—VC0 Resource Capability ......................................... 225
6.1.52 VC0RCTL—VC0 Resource Control ............................................. 226
6.1.53 VC0RSTS—VC0 Resource Status .............................................. 227
6.1.54 RCLDECH—Root Complex Link Declaration Enhanced .................. 228
6.1.55 ESD—Element Self Description ................................................ 228
6.1.56 LE1D—Link Entry 1 Description ............................................... 229
6.1.57 LE1A—Link Entry 1 Address .................................................... 229
6.1.58 PEGSSTS—PCI Express*-G Sequence Status ............................. 230
7 Direct Memory Interface (DMI) Registers.......................................................... 232
7.1 Direct Memory Interface (DMI) Configuration Register Details ................... 233
7.1.1 DMIVCECH—DMI Virtual Channel Enhanced Capability ................ 233
7.1.2 DMIPVCCAP1—DMI Port VC Capability Register 1 ....................... 234
7.1.3 DMIPVCCAP2—DMI Port VC Capability Register 2 ....................... 234
7.1.4 DMIPVCCTL—DMI Port VC Control............................................ 235
7.1.5 DMIVC0RCAP—DMI VC0 Resource Capability ............................. 235
7.1.6 DMIVC0RCTL0—DMI VC0 Resource Control ............................... 236
7.1.7 DMIVC0RSTS—DMI VC0 Resource Status .................................. 237
7.1.8 DMIVC1RCAP—DMI VC1 Resource Capability ............................. 237
7.1.9 DMIVC1RCTL1—DMI VC1 Resource Control ............................... 238
7.1.10 DMIVC1RSTS—DMI VC1 Resource Status .................................. 239
7.1.11 DMILCAP—DMI Link Capabilities .............................................. 239
Datasheet 7
7.1.12 DMILCTL—DMI Link Control .................................................... 240
7.1.13 DMILSTS—DMI Link Status ..................................................... 241
8 Integrated Graphics Device Registers (D2:F0,F1) (Intel® 82Q35, 82Q33,
82G33 GMCH Only) ....................................................................................... 242
8.1 Integrated Graphics Register Details (D2:F0).......................................... 242
8.1.1 VID2—Vendor Identification .................................................... 243
8.1.2 DID—Device Identification ...................................................... 244
8.1.3 PCICMD2—PCI Command ....................................................... 244
8.1.4 PCISTS2—PCI Status ............................................................. 246
8.1.5 RID2—Revision Identification .................................................. 247
8.1.6 CC—Class Code..................................................................... 247
8.1.7 CLS—Cache Line Size............................................................. 248
8.1.8 MLT2—Master Latency Timer................................................... 248
8.1.9 HDR2—Header Type .............................................................. 249
8.1.10 GMADR—Graphics Memory Range Address ................................ 249
8.1.11 IOBAR—I/O Base Address....................................................... 250
8.1.12 SVID2—Subsystem Vendor Identification .................................. 250
8.1.13 SID2—Subsystem Identification .............................................. 251
8.1.14 ROMADR—Video BIOS ROM Base Address ................................. 251
8.1.15 CAPPOINT—Capabilities Pointer ............................................... 252
8.1.16 INTRLINE—Interrupt Line ....................................................... 252
8.1.17 INTRPIN—Interrupt Pin .......................................................... 252
8.1.18 MINGNT—Minimum Grant ....................................................... 253
8.1.19 MAXLAT—Maximum Latency ................................................... 253
8.1.20 CAPID0—Capability Identifier .................................................. 254
8.1.21 MGGC—GMCH Graphics Control Register................................... 255
8.1.22 DEVEN—Device Enable........................................................... 257
8.1.23 SSRW—Software Scratch Read Write........................................ 259
8.1.24 BSM—Base of Stolen Memory.................................................. 259
8.1.25 HSRW—Hardware Scratch Read Write ...................................... 259
8.1.26 MC—Message Control............................................................. 260
8.1.27 MA—Message Address............................................................ 261
8.1.28 MD—Message Data ................................................................ 261
8.1.29 GDRST—Graphics Debug Reset ............................................... 262
8.1.30 PMCAPID—Power Management Capabilities ID ........................... 263
8.1.31 PMCAP—Power Management Capabilities .................................. 263
8.1.32 PMCS—Power Management Control/Status ................................ 264
8.1.33 SWSMI—Software SMI ........................................................... 265
8.2 IGD Configuration Register Details (D2:F1) ............................................ 266
8.2.1 VID2—Vendor Identification .................................................... 268
8.2.2 DID2—Device Identification .................................................... 268
8.2.3 PCICMD2—PCI Command ....................................................... 269
8.2.4 PCISTS2—PCI Status ............................................................. 270
8.2.5 RID2—Revision Identification .................................................. 271
8.2.6 CC—Class Code Register ........................................................ 271
8.2.7 CLS—Cache Line Size............................................................. 272
8.2.8 MLT2—Master Latency Timer................................................... 272
8.2.9 HDR2—Header Type .............................................................. 273
8.2.10 MMADR—Memory Mapped Range Address ................................. 273
8.2.11 SVID2—Subsystem Vendor Identification .................................. 274
8.2.12 SID2—Subsystem Identification .............................................. 274
8.2.13 ROMADR—Video BIOS ROM Base Address ................................. 275
8.2.14 CAPPOINT—Capabilities Pointer ............................................... 275
8.2.15 MINGNT—Minimum Grant ....................................................... 276
8 Datasheet
8.2.16 MAXLAT—Maximum Latency ................................................... 276
8.2.17 CAPID0—Mirror of Dev0 Capability Identifier ............................. 276
8.2.18 MGGC—Mirror of Dev 0 GMCH Graphics Control Register ............. 277
8.2.19 DEVEN—Device Enable........................................................... 279
8.2.20 SSRW—Mirror of Fun 0 Software Scratch Read Write .................. 281
8.2.21 BSM—Mirror of Func0 Base of Stolen Memory............................ 281
8.2.22 HSRW—Mirror of Dev2 Func0 Hardware Scratch Read Write ........ 282
8.2.23 GDRST—Mirror of Dev2 Func0 Graphics Reset ........................... 282
8.2.24 PMCAPID—Mirror of Fun 0 Power Management Capabilities ID...... 283
8.2.25 PMCAP—Mirror of Fun 0 Power Management Capabilities ............. 284
8.2.26 PMCS—Power Management Control/Status ................................ 285
8.2.27 SWSMI—Mirror of Func0 Software SMI ..................................... 286
9 Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) ............... 288
9.1 Host Embedded Controller Interface (HECI1) Configuration Register
Details (D3:F0) .................................................................................. 288
9.1.1 ID— Identifiers ..................................................................... 289
9.1.2 CMD— Command .................................................................. 290
9.1.3 STS— Device Status .............................................................. 291
9.1.4 RID— Revision ID.................................................................. 292
9.1.5 CC— Class Code.................................................................... 292
9.1.6 CLS— Cache Line Size............................................................ 292
9.1.7 MLT— Master Latency Timer ................................................... 293
9.1.8 HTYPE— Header Type ............................................................ 293
9.1.9 HECI_MBAR— HECI MMIO Base Address ................................... 294
9.1.10 SS— Sub System Identifiers ................................................... 294
9.1.11 CAP— Capabilities Pointer....................................................... 295
9.1.12 INTR— Interrupt Information .................................................. 295
9.1.13 MGNT— Minimum Grant ......................................................... 295
9.1.14 MLAT— Maximum Latency ...................................................... 296
9.1.15 HFS— Host Firmware Status ................................................... 296
9.1.16 PID— PCI Power Management Capability ID .............................. 296
9.1.17 PC— PCI Power Management Capabilities.................................. 297
9.1.18 PMCS— PCI Power Management Control And Status ................... 298
9.1.19 MID— Message Signaled Interrupt Identifiers ............................ 299
9.1.20 MC— Message Signaled Interrupt Message Control ..................... 299
9.1.21 MA— Message Signaled Interrupt Message Address .................... 300
9.1.22 MUA— Message Signaled Interrupt Upper Address (Optional)....... 300
9.1.23 MD— Message Signaled Interrupt Message Data ........................ 301
9.1.24 HIDM—HECI Interrupt Delivery Mode ....................................... 301
9.2 HECI2 Configuration Register Details (D3:F1) (Intel® 82Q35 and
82Q33 GMCH only) ............................................................................. 302
9.2.1 ID— Identifiers ..................................................................... 303
9.2.2 CMD— Command .................................................................. 303
9.2.3 STS— Device Status .............................................................. 305
9.2.4 RID— Revision ID.................................................................. 306
9.2.5 CC— Class Code.................................................................... 306
9.2.6 CLS— Cache Line Size............................................................ 306
9.2.7 MLT— Master Latency Timer ................................................... 307
9.2.8 HTYPE— Header Type ............................................................ 307
9.2.9 HECI_MBAR— HECI MMIO Base Address ................................... 308
9.2.10 SS— Sub System Identifiers ................................................... 308
9.2.11 CAP— Capabilities Pointer....................................................... 309
9.2.12 INTR— Interrupt Information .................................................. 309
9.2.13 MGNT— Minimum Grant ......................................................... 309
Datasheet 9
9.2.14 MLAT— Maximum Latency ...................................................... 310
9.2.15 HFS— Host Firmware Status ................................................... 310
9.2.16 PID— PCI Power Management Capability ID .............................. 310
9.2.17 PC— PCI Power Management Capabilities.................................. 311
9.2.18 PMCS— PCI Power Management Control And Status ................... 312
9.2.19 MID— Message Signaled Interrupt Identifiers ............................ 313
9.2.20 MC— Message Signaled Interrupt Message Control ..................... 313
9.2.21 MA— Message Signaled Interrupt Message Address .................... 314
9.2.22 MUA— Message Signaled Interrupt Upper Address (Optional)....... 314
9.2.23 MD— Message Signaled Interrupt Message Data ........................ 315
9.2.24 HIDM—HECI Interrupt Delivery Mode ....................................... 315
9.3 IDE Function for Remote Boot and Installations PT IDER Register
Details (D3:F2) (Intel® 82Q35 and 82Q33 GMCH Only) ............................ 316
9.3.1 ID—Identification .................................................................. 317
9.3.2 CMD—Command Register ....................................................... 317
9.3.3 STS—Device Status ............................................................... 319
9.3.4 RID—Revision ID................................................................... 320
9.3.5 CC—Class Codes ................................................................... 320
9.3.6 CLS—Cache Line Size............................................................. 320
9.3.7 MLT—Master Latency Timer .................................................... 321
9.3.8 HTYPE—Header Type ............................................................. 321
9.3.9 PCMDBA—Primary Command Block IO Bar ................................ 322
9.3.10 PCTLBA—Primary Control Block Base Address............................ 322
9.3.11 SCMDBA—Secondary Command Block Base Address................... 323
9.3.12 SCTLBA—Secondary Control Block base Address ........................ 323
9.3.13 LBAR—Legacy Bus Master Base Address ................................... 324
9.3.14 SS—Sub System Identifiers .................................................... 325
9.3.15 EROM—Expansion ROM Base Address....................................... 325
9.3.16 CAP—Capabilities Pointer........................................................ 326
9.3.17 INTR—Interrupt Information ................................................... 326
9.3.18 MGNT—Minimum Grant .......................................................... 327
9.3.19 MLAT—Maximum Latency ....................................................... 327
9.3.20 PID—PCI Power Management Capability ID ............................... 327
9.3.21 PC—PCI Power Management Capabilities................................... 328
9.3.22 PMCS—PCI Power Management Control and Status .................... 328
9.3.23 MID—Message Signaled Interrupt Capability ID ......................... 330
9.3.24 MC—Message Signaled Interrupt Message Control ...................... 330
9.3.25 MA—Message Signaled Interrupt Message Address ..................... 331
9.3.26 MAU—Message Signaled Interrupt Message Upper Address .......... 331
9.3.27 MD—Message Signaled Interrupt Message Data ......................... 332
9.4 Serial Port for Remote Keyboard and Text KT Redirection Register
Details (D3:F3) (Intel® 82Q35 and 82Q33 GMCH Only) ............................ 333
9.4.1 ID—Identification .................................................................. 334
9.4.2 CMD—Command Register ....................................................... 334
9.4.3 STS—Device Status ............................................................... 336
9.4.4 RID—Revision ID................................................................... 337
9.4.5 CC—Class Codes ................................................................... 337
9.4.6 CLS—Cache Line Size............................................................. 337
9.4.7 MLT—Master Latency Timer .................................................... 338
9.4.8 HTYPE—Header Type ............................................................. 338
9.4.9 KTIBA—KT IO Block Base Address............................................ 339
9.4.10 KTMBA—KT Memory Block Base Address................................... 339
9.4.11 SS—Sub System Identifiers .................................................... 340
9.4.12 EROM—Expansion ROM Base Address....................................... 341
9.4.13 CAP—Capabilities Pointer........................................................ 341
10 Datasheet
9.4.14 INTR—Interrupt Information ................................................... 342
9.4.15 MGNT—Minimum Grant .......................................................... 342
9.4.16 MLAT—Maximum Latency ....................................................... 343
9.4.17 PID—PCI Power Management Capability ID ............................... 343
9.4.18 PC—PCI Power Management Capabilities................................... 344
9.4.19 PMCS—PCI Power Management Control and Status .................... 345
9.4.20 MID—Message Signaled Interrupt Capability ID ......................... 346
9.4.21 MC—Message Signaled Interrupt Message Control ...................... 347
9.4.22 MA—Message Signaled Interrupt Message Address ..................... 348
9.4.23 MAU—Message Signaled Interrupt Message Upper Address .......... 348
9.4.24 MD—Message Signaled Interrupt Message Data ......................... 349
10 Functional Description ................................................................................... 350
10.1 Host Interface.................................................................................... 350
10.1.1 FSB IOQ Depth ..................................................................... 350
10.1.2 FSB OOQ Depth .................................................................... 350
10.1.3 FSB GTL+ Termination ........................................................... 350
10.1.4 FSB Dynamic Bus Inversion .................................................... 350
10.1.4.1 APIC Cluster Mode Support ...................................... 351
10.2 System Memory Controller................................................................... 352
10.2.1 System Memory Organization Modes ........................................ 352
10.2.2 Single Channel Mode ............................................................. 352
10.2.3 Dual Channel Symmetric Mode ................................................ 352
10.2.4 Dual Channel Asymmetric Mode with Intel® Flex Memory Mode
Enabled ............................................................................... 353
10.2.5 System Memory Technology Supported .................................... 354
10.3 PCI Express* ..................................................................................... 355
10.3.1 PCI Express* Architecture....................................................... 355
10.3.2 Transaction Layer.................................................................. 355
10.3.3 Data Link Layer..................................................................... 355
10.3.4 Physical Layer....................................................................... 355
10.4 Intel® Serial Digital Video Output (SDVO) (Intel® 82Q35, 82Q33,
82G33 GMCH Only) ............................................................................ 356
10.4.1 Intel® SDVO Capabilities......................................................... 356
10.4.2 Intel® SDVO Modes................................................................ 357
10.4.3 PCI Express* and Internal Graphics Simultaneous Operation ....... 358
10.4.3.1 Standard PCI Express* Cards and Internal Graphics..... 358
10.4.3.2 Media Expansion Cards (Concurrent SDVO and PCI
Express*) .............................................................. 358
10.5 Integrated Graphics Controller (Intel® 82Q35, 82Q33, 82G33 GMCH Only) . 360
10.5.1 3D Graphics Pipeline .............................................................. 360
10.5.2 3D Engine ............................................................................ 361
10.5.3 Texture Engine ..................................................................... 362
10.5.4 Raster Engine ....................................................................... 362
10.6 Display Interfaces (Intel® 82Q35, 82Q33, 82G33 Only GMCH) .................. 362
10.6.1 Analog Display Port Characteristics .......................................... 363
10.6.1.1 Integrated RAMDAC ................................................ 363
10.6.1.2 Sync Signals .......................................................... 363
10.6.1.3 VESA/VGA Mode ..................................................... 363
10.6.1.4 DDC (Display Data Channel)..................................... 364
Datasheet 11
10.6.2.2 ADD2/Media Expansion Card (MEC) ........................... 364
10.6.2.3 TMDS Capabilities ................................................... 364
10.6.2.4 HDMI Capabilities ................................................... 365
10.6.2.5 LVDS Capabilities.................................................... 365
10.6.2.6 TV-IN Capabilities ................................................... 365
10.6.2.7 TV-Out Capabilities ................................................. 365
10.6.2.8 Control Bus............................................................ 366
10.6.3 Multiple Display Configurations................................................ 366
10.7 Power Management ............................................................................ 367
10.7.1 ACPI.................................................................................... 367
10.7.2 PCI Express Active State Power Management ............................ 367
10.8 Thermal Sensor.................................................................................. 368
10.8.1 PCI Device 0 Function 0 ......................................................... 368
10.8.2 MCHBAR Thermal Sensor Registers .......................................... 368
10.8.3 Programming Sequence ......................................................... 369
10.8.4 Trip Point Temperature Programming ....................................... 370
10.9 Clocking............................................................................................ 371
10.9.1 Overview ............................................................................. 371
10.9.2 Platform Clocks ..................................................................... 372
11 Electrical Characteristics ................................................................................ 374
11.1 Absolute Minimum and Maximum Ratings .............................................. 374
11.2 Current Consumption .......................................................................... 375
11.3 Signal Groups .................................................................................... 378
11.4 DC Characteristics .............................................................................. 381
11.4.1 I/O Buffer Supply Voltages ..................................................... 381
11.4.2 General DC Characteristics ..................................................... 382
11.4.3 R, G, B / CRT DAC Display DC Characteristics (Intel® 82Q35,
82Q33, 82G33 Only).............................................................. 387
12 Ballout and Package Information ..................................................................... 388
12.1 Ballout.............................................................................................. 388
14 Testability.................................................................................................... 426
14.1 XOR Test Mode Initialization ................................................................ 426
14.2 XOR Chain Definition .......................................................................... 428
14.3 XOR Chains ....................................................................................... 429
12 Datasheet
Figures
Figure 1-1. Intel® Q35/Q33 Express Chipsets System Block Diagram Example..........21
Figure 1-2. Intel® G33 Express Chipset System Block Diagram Example ..................22
Figure 1-3. Intel® P35 Express Chipset System Block Diagram Example ..................23
Figure 3-1. System Address Ranges...................................................................54
Figure 3-2. DOS Legacy Address Range..............................................................55
Figure 3-3. Main Memory Address Range ............................................................59
Figure 3-4. PCI Memory Address Range..............................................................62
Figure 4-1. Memory Map to PCI Express* Device Configuration Space.....................78
Figure 4-2. GMCH Configuration Cycle Flow Chart ................................................79
Figure 10-1. sDVO Conceptual Block Diagram ................................................... 357
Figure 10-2. Concurrent savon / PCI Express* Non-Reversed Configurations ......... 359
Figure 10-3. Concurrent SDVO / PCI Express* Reversed Configurations ................ 359
Figure 10-4. Integrated 3D Graphics Pipeline .................................................... 361
Figure 10-5. Intel® 3 Series Express Chipset Clocking Diagram ............................ 372
Figure 12-1. (G)MCH Ballout Diagram (Top View Left – Columns 43–30) ............... 389
Figure 12-2. (G)MCH Ballout Diagram (Top View Middle– Columns 29–15) ............ 390
Figure 12-3. (G)MCH Ballout Diagram (Top View Right – Columns 14–1)............... 391
Figure 13-1. (G)MCH Package Drawing............................................................. 425
Figure 14-1. XOR Test Mode Initialization Cycles ............................................... 426
Datasheet 13
Tables
Table 2-1. SDVO/PCI Express* Signal Mapping....................................................49
Table 3-1. Expansion Area Memory Segments .....................................................57
Table 3-2. Extended System BIOS Area Memory Segments ...................................57
Table 3-3. System BIOS Area Memory Segments.................................................58
Table 3-4. Pre-allocated Memory Example for 64 MB DRAM, 1 MB VGA, 1 MB
GTT stolen and 1 MB TSEG ...............................................................60
Table 3-5. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and
1-MB TSEG.....................................................................................68
Table 3-6. SMM Space .....................................................................................69
Table 5-1. DRAM Controller Register Address Map (D0:F0)....................................85
Table 5-2. MCHBAR Register Address Map ........................................................ 127
Table 5-3. DRAM Rank Attribute Register Programming ...................................... 134
Table 5-4. EPBAR Register Address Map ........................................................... 176
Table 6-1. PCI Express* Register Address Map (D1:F0) ...................................... 180
Table 7-1. DMI Register Address Map............................................................... 232
Table 8-1. Integrated Graphics Device Register Address Map (D2:F0) ................... 242
Table 8-2. Integrated Graphics Device Register Address Map (D2:F1) ................... 266
Table 9-1. HECI Function in ME Subsystem Register Address Map ........................ 288
Table 9-2. Second HECI Function in ME Subsystem Register Address Map ............. 302
Table 9-3. IDE Function for Remote Boot and Installations PT IDER Register
Address Map.................................................................................. 316
Table 9-4. Serial Port for Remote Keyboard and Text KT Redirection Register
Address Map................................................................................. 333
Table 10-1. Sample System Memory Dual Channel Symmetric Organization
Mode with Intel® Flex Memory Mode Enabled .................................... 353
Table 10-2. Sample System Memory Dual Channel Asymmetric Organization
Mode with Intel® Flex Memory Mode Disabled ................................... 353
Table 10-3 Supported DIMM Module Configurations............................................ 354
Table 10-4. Concurrent SDVO / PCI Express* Configuration Strap Controls............ 358
Table 10-5. Intel® G33 and P35 Express Chipset (G)MCH Voltage Rails ................. 367
Table 10-6. Intel® Q35 and Q33 Express Chipset GMCH Voltage Rails ................... 367
Table 11-1. Absolute Minimum and Maximum Ratings ........................................ 374
Table 11-2. Intel® Q35/Q33 Express Chipset – GMCH Current Consumption in S0 .. 376
Table 11-3. Current Consumption in S3, S4, S5 with Intel® Active Management
Technology Operation (82Q35 GMCH Only) ...................................... 377
Table 11-4. Signal Groups .............................................................................. 378
Table 11-5. I/O Buffer Supply Voltage............................................................. 381
Table 11-6. DC Characteristics ....................................................................... 382
Table 11-7. R, G, B / CRT DAC Display DC Characteristics: Functional Operating
Range (VCCA_DAC = 3.3 V ± 5%) ................................................. 387
Table 12-1. Ballout – Sorted by Ball................................................................. 392
Table 12-2. Ballout – Sorted by Signal ............................................................. 411
Table 14-1. XOR Chain 14 functionality ............................................................ 427
Table 14-2. XOR Chain Outputs....................................................................... 428
Table 14-3. XOR Chain 0................................................................................ 429
Table 14-4. XOR Chain 1................................................................................ 430
Table 14-5. XOR Chain 2................................................................................ 430
Table 14-6. XOR Chain 3................................................................................ 431
14 Datasheet
Table 14-7. XOR Chain 4................................................................................ 431
Table 14-8. XOR Chain 5................................................................................ 432
Table 14-9. XOR Chain 6................................................................................ 432
Table 14-10. XOR Chain 7 .............................................................................. 433
Table 14-11. XOR Chain 8 .............................................................................. 433
Table 14-12. XOR Chain 9 .............................................................................. 434
Table 14-13. XOR Chain 10 ............................................................................ 434
Table 14-14. XOR Chain 11 ............................................................................ 435
Table 14-15. XOR Chain 12 ............................................................................ 436
Table 14-16. XOR Chain 13 ............................................................................ 436
Table 14-17. XOR Chain 14 ............................................................................ 436
Datasheet 15
Revision History
-002 • Added Intel 82Q35 GMCH and Intel 82Q33 GMCH specifications August 2007
16 Datasheet
Intel® 3 Series Chipset (G)MCH
Features
• Processor/Host Interface (FSB) • Integrated Graphics Device (82Q35, 82Q33,
⎯ Supports Intel® Core™2 Duo desktop processor 82G33 GMCH only)
⎯ Supports Intel® Core™2 Quad desktop processor ⎯ Core frequency of 400 MHz
⎯ 800/1067/1333 MT/s (200/266/333 MHz) FSB ⎯ 1.6 GP/s pixel rate
⎯ Hyper-Threading Technology (HT Technology) ⎯ High-Quality 3D Setup and Render Engine
⎯ High-Quality Texture Engine
⎯ FSB Dynamic Bus Inversion (DBI)
⎯ 3D Graphics Rendering Enhancements
⎯ 36-bit host bus addressing
⎯ 2D Graphics
⎯ 12-deep In-Order Queue ⎯ Video Overlay
⎯ 1-deep Defer Queue ⎯ Multiple Overlay Functionality
⎯ GTL+ bus driver with integrated GTL termination
• Analog Display (82Q35, 82Q33, 82G33 GMCH
resistors
only)
⎯ Supports cache Line Size of 64 bytes
⎯ 350 MHz Integrated 24-bit RAMDAC
• System Memory Interface ⎯ Up to 2048x1536 @ 75 Hz refresh
⎯ One or two channels (each channel consisting of 64 ⎯ Hardware Color Cursor Support
data lines) ⎯ DDC2B Compliant Interface
⎯ Single or Dual Channel memory organization • Digital Display (82Q35, 82Q33, 82G33 GMCH
⎯ DDR2-800/667 frequencies only)
⎯ DDR3-1066/800 frequencies (82G33 GMCH and ⎯ SDVO ports in single mode supported
82P35 MCH only) ⎯ 225 MHz dot clock on each 12-bit interface
⎯ Unbuffered, non-ECC DIMMs only ⎯ Flat panels up to 2048x1536 @ 60 Hz or
⎯ Supports 1-Gb, 512-Mb DDR2 or DDR3 technologies digital CRT/HDTV at 1400x1050 @ 85Hz
for x8 and x16 devices ⎯ Dual independent display options with
⎯ 8 GB maximum memory digital display
• Direct Media Interface (DMI) ⎯ Multiplexed digital display channels
⎯ Chip-to-chip connection interface to Intel ICH9 (supported with ADD2 Card).
⎯ 2 GB/s point-to-point DMI to ICH9 (1 GB/s each ⎯ Supports TMDS transmitters or TV-Out
direction) encoders
⎯ 100 MHz reference clock (shared with PCI Express ⎯ ADD2/MEC card uses PCI Express graphics
graphics attach) x16 connector
⎯ 32-bit downstream addressing ⎯ Two channels multiplexed with PCI Express*
⎯ Messaging and Error Handling Graphics port
⎯ Supports Hot-Plug and Display
• PCI Express* Interface
⎯ One x16 PCI Express port • Thermal Sensor
⎯ Compatible with the PCI Express Base Specification, ⎯ Catastrophic Trip Point support
Revision 1.1 ⎯ Hot Trip Point support for SMI generation
⎯ Raw bit rate on data pins of 2.5 Gb/s resulting in a • Power Management
real bandwidth per pair of 250 MB/s ⎯ PC99 suspend to DRAM support (“STR”,
mapped to ACPI state S3)
⎯ ACPI Revision 2.0 compatible power
management
⎯ Supports processor states: C0, C1, C2
⎯ Supports System states: S0, S1, S3, and S5
⎯ Supports processor Thermal Management 2
• Package
⎯ FC-BGA. 34 mm × 34 mm. The 1226 balls
are located in a non-grid pattern
Datasheet 17
18 Datasheet
Introduction
1 Introduction
The Intel® 3 Series Chipsets are designed for use with the Intel® Core™2 Duo desktop
processor and Intel® Core™2 Quad processor based platforms. Each chipset contains
two components: GMCH (or MCH) for the host bridge and I/O Controller Hub 9 (ICH9)
for the I/O subsystem. The 82Q33 GMCH is part of the Intel® Q35 Express chipset.
The 82Q33 GMCH is part of the Intel® Q33 Express chipset. The 82G33 GMCH is part
of the Intel® G33 Express chipset. The 82P35 MCH is part of the Intel® P35 Express
chipset. The ICH9 is the ninth generation I/O Controller Hub and provides a multitude
of I/O related functions. The following figures show example system block diagrams
for the Intel® Q35, Q33, G33 and P35 Express chipsets.
This document is the datasheet for the Intel® 82Q35, 82Q33, and 82G33 Graphics and
Memory Controller Hub (GMCH) and Intel® 82P35 Memory Controller Hub (MCH).
Topics covered include; signal description, system memory map, PCI register
description, a description of the (G)MCH interfaces and major functional units,
electrical characteristics, ballout definitions, and package characteristics.
The primary difference between the Intel® 82Q35, 82Q33, 82G33 GMCH and 82P35
MCH is that the 82Q35 GMCH, 82Q33 GMCH, and 82G33 GMCH have an integrated
graphics device (IGD) plus the associated display interfaces. The 82P35 does not
contain an IGD and the associated interfaces.
Note: Unless otherwise specified, the information in this document applies to the Intel®
82Q35, 82Q33, 82G33 Graphics and Memory Controller Hub (GMCH) and Intel® 82P35
Memory Controller Hub (MCH).
Note: The term (G)MCH refers to the 82Q35 GMCH, 82Q33 GMCH, 82G33 GMCH and 82P35
MCH.
Note: Unless otherwise specified, ICH9 refers to the Intel® 82801IB ICH9, Intel® 82801IR
ICH9R, and Intel® 82801IH ICH9DH I/O Controller Hub 9 components.
Note: The term ICH9 refers to the ICH9, ICH9R, and ICH9DH components.
Datasheet 19
Introduction
DDR3-1067/800 DDR3-1067/800
Discrete Graphics PCI Express x16 PCI Express x16 PCI Express x16 PCI Express x16
Alerting Standard Yes1 Yes Yes (DDR2 only)3 Yes (DDR2 only)3
Format (ASF)
NOTE:
1. For the 82Q35 GMCH, only one manageability solution can be supported, AMT or ASF.
2. Intel® Active Management Technology requires the platform to have an Intel® AMT-
enabled chipset, network hardware and software, connection with a power source and
an active LAN port.
3. ASF is available on 82G33 GMCH and 82P35 MCH with DDR2 system memory only.
ASF on 82G33 GMCH and 82P35 MCH with DDR3 system memory is not a validated
configuration.
20 Datasheet
Introduction
Figure 1-1. Intel® Q35/Q33 Express Chipsets System Block Diagram Example
Processor
Analog
Display
VGA
System Memory
Channel A
DDR2
Display MEC GMCH
SDVO
Channel B
DDR2
Graphics OR
Display
Card PCI Express*
x16 Graphics
DMI Controller
Interface Link
USB 2.0
(Supports 12 USB ports Power Management
Dual EHCI Controller)
Clock Generators
SATA (6 ports)
®
Intel System Management
Intel® High Definition (TCO)
Audio Codec(s)
SMBus 2.0/I2C
Intel® ICH9
PCI Express* x1
Intel® Gigabit GLCI
Ethernet Phy
Flash
SPI BIOS
LCI
PCI Bus
GPIO
S S
L L
LPC I/F O ... O
T T
Other ASICs
(optional) Super I/O
TPM
(optional) Firmware Hub
Sys_Blk_Q35-Q33
Datasheet 21
Introduction
Figure 1-2. Intel® G33 Express Chipset System Block Diagram Example
Processor
Analog
Display System Memory
VGA
Channel A
DDR2/DDR3
GMCH
Display MEC
Channel B
SDVO DDR2/DDR3
Graphics OR
Display
Card PCI Express*
x16 Graphics
DMI Controller
Interface Link
USB 2.0
(Supports 12 USB ports Power Management
Dual EHCI Controller)
Clock Generators
SATA (6 ports)
®
Intel System Management
®
Intel High Definition (TCO)
Audio Codec(s)
SMBus 2.0/I2C
Intel® ICH9
PCI Express* x1
Intel® Gigabit GLCI
Ethernet Phy
Flash
SPI BIOS
LCI
PCI Bus
GPIO
S S
L L
LPC I/F O ... O
T T
Other ASICs
(optional) Super I/O
TPM
(optional) Firmware Hub
Sys_Blk_Q35-G33
22 Datasheet
Introduction
Figure 1-3. Intel® P35 Express Chipset System Block Diagram Example
Processor
System Memory
Channel B
DDR2/DDR3
DMI Controller
Interface Link
USB 2.0
(Supports 12 USB ports Power Management
Dual EHCI Controller)
Clock Generators
SATA (6 ports)
®
Intel System Management
Intel® High Definition (TCO)
Audio Codec(s)
SMBus 2.0/I2C
Intel® ICH9
PCI Express* x1
®
Intel Gigabit GLCI
Ethernet Phy
SPI BIOS
Flash
LCI
PCI Bus
GPIO
S S
L L
LPC I/F O ... O
T T
Other ASICs
(optional) Super I/O
TPM
(optional) Firmware Hub
Sys_Blk_P35
Datasheet 23
Introduction
1.1 Terminology
Term Description
ADD Card Advanced Digital Display Card. Provides digital display options for an Intel
Graphics Controller that supports ADD cards (have DVOs multiplexed with
AGP interface). Keyed like an AGP 4x card and plugs into an AGP connector.
Will not work with an Intel Graphics Controller that implements Intel® SDVO.
ADD2 Card Advanced Digital Display Card – 2nd Generation. Provides digital display
options for an Intel graphics controller that supports ADD2 cards. Plugs into
an x16 PCI Express* connector but utilizes the multiplexed SDVO interface.
Will not work with an Intel Graphics Controller that supports Intel® DVO and
ADD cards.
Chipset / Root Used in this specification to refer to one or more hardware components that
– Complex connects processor complexes to the I/O and memory subsystems. The
chipset may include a variety of integrated devices.
CLink GMCH-ICH9 Control Link
Core The internal base logic in the (G)MCH
CRT Cathode Ray Tube
DBI Dynamic Bus Inversion
DDR2 A second generation Double Data Rate SDRAM memory technology
DDR3 A third generation Double Data Rate SDRAM memory technology
DMA Translating the address in a DMA request (DVA) to a host physical address
Remapping (HPA)
DMI (G)MCH-Intel® ICH9 Direct Media Interface
Domain A collection of physical, logical or virtual resources that are allocated to work
together. Domain is used as a generic term for virtual machines, partitions,
etc.
DVI Digital Video Interface. Specification that defines the connector and interface
for digital displays.
DVMT Dynamic Video Memory Technology
FSB Front Side Bus, synonymous with Host or processor bus
Full Reset Full reset is when PWROK is de-asserted. Warm reset is when both RSTIN#
and PWROK are asserted.
GAW Guest Address Width. GAW refers to the DMA virtual addressability limit.
GMCH Graphics and Memory Controller Hub. GMCH is a component that contains
the processor interface, DRAM controller, and x16 PCI Express port (typically
the external graphics interface). It communicates with the I/O controller hub
(Intel® ICH9) over the DMI interconnect. The GMCH contains an embedded
graphics controller.
Memory Controller Hub. See MCH.
GPA Guest Physical Address is the view of physical memory from software
running in a partition. GPA is also used in this document as an example
usage for DMA virtual addresses (DVA)
24 Datasheet
Introduction
Term Description
Media Media Expansion Card. MEC provides digital display options for an Intel
Expansion Graphics Controller that supports MEC cards. Plugs into an x16 PCI Express
Card connector but uses the multiplexed SDVO interface. Adds Video In
(MEC) capabilities to platform. Will not work with an Intel Graphics Controller that
supports DVO and ADD cards. MEC Will function as an ADD2 card in an
ADD2 supported system, but Video In capabilities will not work.
MCH Memory Controller Hub. MCH is a component that contains the processor
interface, DRAM controller, and x16 PCI Express port (typically the external
graphics interface). It communicates with the I/O controller hub (Intel®
ICH9) over the DMI interconnect. The MCH does not contain an embedded
graphics controller.
MGAW Maximum Guest Address Width. MGAW refers to the maximum DMA virtual
addressability supported by a DMA-remapping hardware implementation.
HAW Host Address Width. This refers to the maximum host physical address that
can be accessed by a given processor / root-complex implementation. The
host BIOS typically reports the host system address map.
Host This term is used synonymously with processor
HPA Host Physical Address
IGD Internal Graphics Device
INTx An interrupt request signal where X stands for interrupts A, B, C and D
Intel® ICH9 Ninth generation I/O Controller Hub component that contains the primary
PCI interface, LPC interface, USB2.0, SATA, and other I/O functions. For this
GMCH, the term Intel® ICH refers to Intel® ICH9.
Intel® ME Intel® Management Engine that provides core functionality for Intel® AMT.
IOTLB I/O Translation Look aside Buffer. IOTLB refers to an address translation
cache in a DMA-remapping hardware unit that caches effective translations
from DVA (GPA) to HPA.
IOQ In Order Queue
MVMM A VMM offering that can be measured for security properties
MSI Message Signaled Interrupt. A transaction conveying interrupt information to
the receiving agent through the same path that normally carries read and
write commands.
OOQ Out of Order Queuing
PDE Cache/ PDE (non-leaf) cache refers to address translation caches in a DMA-
Non-leaf remapping hardware unit that caches page directory entries at the various
Cache page-directory levels. These are also referred to as non-leaf caches in this
document.
PCI Express* A high-speed serial interface whose configuration is software compatible with
the legacy PCI specifications.
Primary PCI The physical PCI bus that is driven directly by the Intel® ICH9 component.
Communication between Primary PCI and the (G)MCH occurs over DMI. Note
that the Primary PCI bus is not PCI Bus 0 from a configuration standpoint.
SERR System Error. An indication that an unrecoverable error has occurred on an
I/O bus.
Rank A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four
x16 SDRAM devices in parallel, ignoring ECC. These devices are usually, but
not always, mounted on a single side of a DIMM.
SCI System Control Interrupt. Used in ACPI protocol.
Datasheet 25
Introduction
Term Description
SDVO Serial Digital Video Out (SDVO). Digital display channel that serially
transmits digital display data to an external SDVO device. The SDVO device
accepts this serialized format and then translates the data into the
appropriate display format (i.e. TMDS, LVDS, and TV-Out). This interface is
not electrically compatible with the previous digital display channel - DVO.
SDVO Device Third party codec that uses SDVO as an input. May have a variety of output
formats, including DVI, LVDS, HDMI, TV-out, etc.
SMI System Management Interrupt. Used to indicate any of several system
conditions such as thermal sensor events, throttling activated, access to
System Management RAM, chassis open, or other system state related
activity.
TMDS Transition Minimized Differential Signaling. Signaling interface from Silicon
Image that is used in DVI and HDMI.
Intel® TXT Intel® Trusted Execution Technology defines platform level enhancements
that provide the building blocks for creating trusted platforms.
UMA Unified Memory Architecture used for system memory. Typically used by IGD
or ME functionality.
VCO Voltage Controlled Oscillator
VMM Virtual Machine Monitor. A software layer that controls virtualization
26 Datasheet
Introduction
The (G)MCH can use a single LGA775 socket processor. The (G)MCH supports FSB
frequencies of 200/266/333 MHz. Host-initiated I/O cycles are decoded to PCI
Express, DMI, or the (G)MCH configuration space. Host-initiated memory cycles are
decoded to PCI Express, DMI, or system memory. PCI Express device accesses to non-
cacheable system memory are not snooped on the host bus. Memory accesses
initiated from PCI Express using PCI semantics and from DMI to system SDRAM will be
snooped on the host bus.
Datasheet 27
Introduction
28 Datasheet
Introduction
Direct Media Interface (DMI) is the chip-to-chip connection between the (G)MCH and
ICH9. This high-speed interface integrates advanced priority-based servicing allowing
for concurrent traffic and true isochronous transfer capabilities. Base functionality is
completely software transparent permitting current and legacy software to operate
normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS)
transactions, the ICH9 supports two virtual channels on DMI: VC0 and VC1. These two
channels provide a fixed arbitration scheme where VC1 is always the highest priority.
VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be
specifically enabled and configured at both ends of the DMI link (i.e., the ICH9 and
(G)MCH).
• A chip-to-chip connection interface to Intel ICH9
• 2 GB/s point-to-point DMI to ICH9 (1 GB/s each direction)
• 100 MHz reference clock (shared with PCI Express Graphics Attach)
• 32-bit downstream addressing
• APIC and MSI interrupt messaging support. Will send Intel-defined “End Of
Interrupt” broadcast message when initiated by the processor.
• Message Signaled Interrupt (MSI) messages
• SMI, SCI, and SERR error indication
The (G)MCH contains one 16-lane (x16) PCI Express port intended for an external PCI
Express graphics card. The PCI Express port is compliant to the PCI Express* Base
Specification revision 1.1. The x16 port operates at a frequency of 2.5 Gb/s on each
lane while employing 8b/10b encoding, and supports a maximum theoretical
bandwidth of 40 Gb/s in each direction. The 82Q35/82Q33/82G33 GMCHs multiplex
the PCI Express interface with the Intel® SDVO ports.
• One, 16-lane PCI Express port intended for Graphics Attach, compatible to the PCI
Express* Base Specification revision 1.1.
• PCI Express frequency of 1.25 GHz resulting in 2.5 Gb/s each direction per lane.
• Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface
• Maximum theoretical realized bandwidth on the interface of 4 GB/s in each
direction simultaneously, for an aggregate of 8 GB/s when x16.
• PCI Express* Graphics Extended Configuration Space. The first 256 bytes of
configuration space alias directly to the PCI Compatibility configuration space. The
remaining portion of the fixed 4 KB block of memory-mapped space above that
(starting at 100h) is known as extended configuration space.
• PCI Express Enhanced Addressing Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.
Datasheet 29
Introduction
The GMCH provides an integrated graphics device (IGD) delivering cost competitive
3D, 2D and video capabilities. The GMCH contains an extensive set of instructions for
3D operations, 2D operations, motion compensation, overlay, and display control. The
GMCH’s video engines support video conferencing and other video applications. The
GMCH uses a UMA configuration with DVMT for graphics memory. The GMCH also has
the capability to support external graphics accelerators via the PCI Express Graphics
(PEG) port but cannot work concurrently with the integrated graphics device. High
bandwidth access to data is provided through the system memory port.
The GMCH provides interfaces to a progressive scan analog monitor and two SDVO
ports. For the GMCH, the SDVO ports are multiplexed with PCI Express x16 graphics
port signals. The GMCH supports two multiplexed SDVO ports that each drive pixel
clocks up to 225 MHz. The SDVO ports can each support a single-channel SDVO
device. If both ports are active in single-channel mode, they can have different display
timing and data.
The digital display channels are capable of driving a variety of SDVO devices (e.g.,
TMDS, TV-Out). Note that SDVO only works with the Integrated Graphics Device
(IGD). The GMCH is capable of driving an Advanced Digital Display (ADD2) card or
Media Expansion Card. The Media Expansion Card adds video-in capabilities. The
GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant
external device and connector, the GMCH has a high-speed interface to a digital
display (e.g., flat panel or digital CRT).
The GMCH is compliant with HDMI specification 1.1. When combined with a HDMI
compliant external device and connector, the external HDMI device can support
standard, enhanced, or high-definition video, plus multi-channel digital audio on a
single cable.
30 Datasheet
Introduction
Datasheet 31
Introduction
32 Datasheet
Introduction
Intel® Trusted Execution Technology (Intel® TXT) is a security initiative that involves
the processor, chipset and platform. Intel® Trusted Execution Technology requires the
following support in the chipset:
• FSB encodings for LTMW and LTMR cycles
• Measured launch of a VMM, using a TPM
• Protected path from the processor to the TPM, which is enabled by the processor
• Ranges of memory protected from DMA accesses.
®
Intel® TXT is only supported by the Intel Q35 Express chipset.
Datasheet 33
Introduction
34 Datasheet
Signal Description
2 Signal Description
This chapter provides a detailed description of (G)MCH signals. The signals are
arranged in functional groups according to their associated interface.
Signal Description
Type
PCI Express* PCI Express interface signals. These signals are compatible with PCI Express
1.1 Signaling Environment AC Specifications and are AC coupled. The buffers
are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|) * 2 =
1.2 Vmax. Single-ended maximum = 1.25 V. Single-ended minimum = 0 V.
DMI Direct Media Interface signals. These signals are compatible with PCI Express
1.1 Signaling Environment AC Specifications, but are DC coupled. The buffers
are not 3.3 V tolerant.
Differential voltage spec = (|D+ - D-|) * 2 = 1.2 Vmax.
Single-ended maximum = 1.25 V. Single-ended minimum = 0 V.
HCSL Host Clock Signal Level buffers. Current mode differential pair.
SSTL_1.8 Stub Series Termination Logic. These are 1.8 V output capable buffers. 1.8 V
tolerant.
SSTL_1.5 Stub Series Termination Logic. These are 1.5 V output capable buffers. 1.5 V
tolerant
Datasheet 35
Signal Description
Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the
termination voltage of the Host Bus (VTT).
FSB_ADSB I/O Address Strobe: The processor bus owner asserts FSB_ADSB
to indicate the first of two cycles of a request phase. The
GTL+
(G)MCH can assert this signal for snoop cycles and interrupt
messages.
FSB_BNRB I/O Block Next Request: Used to block the current request bus
owner from issuing new requests. This signal is used to
GTL+
dynamically control the processor bus pipeline depth.
FSB_BPRIB O Priority Agent Bus Request: The (G)MCH is the only Priority
Agent on the processor bus. It asserts this signal to obtain the
GTL+
ownership of the address bus. This signal has priority over
symmetric bus requests and will cause the current symmetric
owner to stop issuing new transactions unless the FSB_LOCKB
signal was asserted.
FSB_DBSYB I/O Data Bus Busy: This signal is used by the data bus owner to
hold the data bus for transfers requiring more than one cycle.
GTL+
FSB_DEFERB O Defer: This signal indicates that the (G)MCH will terminate the
transaction currently being snooped with either a deferred
GTL+
response or with a retry response.
36 Datasheet
Signal Description
FSB_DINVB_3:0 I/O Dynamic Bus Inversion: These signals are driven along with
the FSB_DB_63:0 signals. They indicate if the associated
GTL+
signals are inverted. FSB_DINVB_3:0 are asserted such that
4x
the number of data bits driven electrically low (low voltage)
within the corresponding 16 bit group never exceeds 8.
FSB_DINVB_3 FSB_DB_63:48
FSB_DINVB_2 FSB_DB_47:32
FSB_DINVB_1 FSB_DB_31:16
FSB_DINVB_0 FSB_DB_15:0
FSB_DRDYB I/O Data Ready: This signal is asserted for each cycle that data is
transferred.
GTL+
FSB_ADSTBB_1:0 I/O Host Address Strobe: The source synchronous strobes are
used to transfer FSB_AB_31:3 and FSB_REQB_4:0 at the 2x
GTL+
transfer rate.
2x
Strobe Address Bits
FSB_ADSTBB_1 FSB_AB_31:17
FSB_DB_63:0 I/O Host Data: These signals are connected to the processor data
bus. Data on FSB_DB_63:0 is transferred at a 4x rate. Note
GTL+
that the data signals may be inverted on the processor bus,
4x
depending on the FSB_DINVB_3:0 signals.
Datasheet 37
Signal Description
FSB_HITB I/O Hit: This signal indicates that a caching agent holds an
unmodified version of the requested line. Also, driven in
GTL+
conjunction with FSB_HITMB by the target to extend the
snoop window.
FSB_HITMB I/O Hit Modified: This signal indicates that a caching agent holds
a modified version of the requested line and that this agent
GTL+
assumes responsibility for providing the line. Also, driven in
conjunction with FSB_HITB to extend the snoop window.
FSB_LOCKB I Host Lock: All processor bus cycles sampled with the
assertion of FSB_LOCKB and FSB_ADSB, until the negation of
GTL+
FSB_LOCKB must be atomic (i.e., no DMI or PCI-Express
access to DRAM are allowed when FSB_LOCKB is asserted by
the processor).
FSB_REQB_4:0 I/O Host Request Command: These signals define the attributes
of the request. FSB_REQB_4:0 are transferred at 2x rate.
GTL+
Asserted by the requesting agent during both halves of
2x Request Phase. In the first half the signals define the
transaction type to a level of detail that is sufficient to begin a
snoop request. In the second half the signals carry additional
information to define the complete transaction type.
FSB_TRDYB O Host Target Ready: This signal indicates that the target of
the processor transaction is able to enter the data transfer
GTL+
phase.
38 Datasheet
Signal Description
FSB_RCOMP I/O Host RCOMP: This signal is used to calibrate the Host GTL+
I/O buffers. This signal is powered by the Host Interface
A
termination rail (VTT). Connects to FSB_XRCOMP1IN in the
package.
FSB_DVREF I/O Host Reference Voltage: Reference voltage input for the
Data signals of the Host GTL interface.
A
FSB_ACCVREF I/O Host Reference Voltage: Reference voltage input for the
Address, signals of the Host GTL interface.
A
Datasheet 39
Signal Description
40 Datasheet
Signal Description
Datasheet 41
Signal Description
42 Datasheet
Signal Description
CMOS
CMOS
CMOS
CMOS
Datasheet 43
Signal Description
CRT_IREF I/O Resistor Set: Set point resistor for the internal color palette
DAC.
A
44 Datasheet
Signal Description
DPL_REFCLKINP HCSL
1 = DDR2
Datasheet 45
Signal Description
NOTES: For the 82P35 MCH, this signal should be pulled low.
PWROK I/O Power OK: When asserted, PWROK is an indication to the
(G)MCH that core power has been stable for at least 10 us.
HVIN
0 0 Reserved
1 1 Normal
46 Datasheet
Signal Description
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
Datasheet 47
Signal Description
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
PCI Express*
COD
COD
NOTE: Table 2-1 shows the mapping of SDVO signals to the PCI Express* lanes in the various
possible configurations as determined by the strapping configuration. Note that slot-
reversed configurations do not apply to the Integrated-graphics only variants.
48 Datasheet
Signal Description
Configuration-wise Mapping
Datasheet 49
Signal Description
VSS 0V Ground
50 Datasheet
System Address Map
The (G)MCH supports PEG port upper pre-fetchable base/limit registers. This allows
the PEG unit to claim IO accesses above 36 bit, complying with the PCI Express
Specification. Addressing of greater than 8 GB is allowed on either the DMI Interface
or PCI Express interface. The (G)MCH supports a maximum of 8 GB of DRAM. No
DRAM memory will be accessible above 8 GB.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI Interface. The exception to this rule is VGA ranges, which may be
mapped to PCI-Express, DMI, or to the internal graphics device (IGD). In the absence
of more specific references, cycle descriptions referencing PCI should be interpreted as
the DMI Interface/PCI, while cycle descriptions referencing PCI Express or IGD are
related to the PCI Express bus or the internal graphics device respectively. The
(G)MCH does not remap APIC or any other memory spaces above TOLUD (Top of Low
Usable DRAM). The TOLUD register is set to the appropriate value by BIOS. The
reclaim base/reclaim limit registers remap logical accesses bound for addresses above
4 GB onto physical addresses that fall within DRAM.
Datasheet 51
System Address Map
52 Datasheet
System Address Map
• MCHBAR
⎯ GFXVTBAR – Memory-mapped window to Graphics VT remap engine registers.
(4 KB window)
⎯ DMIVC1BAR – Memory-mapped window to DMI VC1 VT remap engine
registers. (4 KB window)
⎯ VTMEBAR – Memory-mapped window to ME VT remap engine registers (4 KB
window)
⎯ VTDPVC0BAR – Memory-mapped window to PEG/DMI VC0 VT remap engine
registers. (4 KB window)
Datasheet 53
System Address Map
PCI Memory
Address
Device Device Device
Range
3 1 0
(subtractively
Bars Bars
decoded to
DMI
TOM 64 MB Aligned
Independently Programmable Reclaim Limit =
Main Memory EP-UMA
Non-Overlapping Windows Reclaim Base +X
TOUUD Base Reclaim (1 – 64 MB)
(64 MB Aligned) EP Stolen Base 1 MB Aligned
Address 0 – 63 MB
Range Unusable
64 MB Aligned
Reclaim Base
(64 MB Aligned)
Main Memory
OS Visible
Address
> 4 GB
Range
4 GB
Main Memory
Address
Range OS Visible
< 4 GB
1 MB
Legacy
Address
0 Range
Memap_Sys_Addr_Ranges
NOTE:
1. References to Internal Graphics Device address ranges are for the
82Q35/82Q33/82G33 GMCH only.
54 Datasheet
System Address Map
000F_FFFFh 1 MB
System BIOS (Upper)
64 KB
000F_0000h 960 KB
000E_FFFFh Extended System BIOS
(Lower)
000E_0000h 64 KB (16 KB x 4) 896 KB
000D_FFFFh
Expansion Area
128 KB (16 KB x 8)
000C_0000h
768 KB
000B_FFFFh
Legacy Video Area
(SMM Memory)
128 KB
000A_0000h
0009_FFFFh 640 KB
DOS Area
0000_0000h
MemMap_Legacy
Datasheet 55
System Address Map
The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to
the main memory controlled by the (G)MCH.
The legacy 128 KB VGA memory range, frame buffer, (000A_0000h – 000B_FFFFh)
can be mapped to IGD (Device 2), to PCI Express (Device 1), and/or to the DMI
Interface. The appropriate mapping depends on which devices are enabled and the
programming of the VGA steering bits. Based on the VGA steering bits, priority for
VGA mapping is constant. The (G)MCH always decodes internally mapped devices
first. Internal to the GMCH, decode precedence is always given to IGD. The (G)MCH
always positively decodes internally mapped devices, namely the IGD and PCI-
Express. Subsequent decoding of regions mapped to PCI Express or the DMI Interface
depends on the Legacy VGA configuration bits (VGA Enable and MDAP). This region is
also the default for SMM space.
When compatible SMM space is enabled, SMM-mode processor accesses to this range
are routed to physical system DRAM at 000A 0000h – 000B FFFFh. Non-SMM-mode
processor accesses to this range are considered to be to the Video Buffer Area as
described above. PCI Express and DMI originated cycles to enabled SMM space are not
allowed and are considered to be to the Video Buffer Area if IGD is not enabled as the
VGA device. PCI Express and DMI initiated cycles are attempted as Peer cycles, and
will master abort on PCI if no external VGA device claims them.
The PCI to PCI Bridge Architecture Specification Revision 1.2 requires that 16-bit VGA
decode be a feature.
56 Datasheet
System Address Map
This 128 KB ISA Expansion region (000C_0000h – 000D_FFFFh) is divided into eight
16 KB segments. Each segment can be assigned one of four Read/Write states: read-
only, write-only, read/write, or disabled. Typically, these blocks are mapped through
(G)MCH and are subtractive decoded to ISA space. Memory that is disabled is not
remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Datasheet 57
System Address Map
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM
memory area.
The (G)MCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all
memory residing on DMI should be set as non-cacheable, there will normally not be
IWB cycles targeting DMI. However, DMI becomes the default target for processor and
DMI originated accesses to disabled segments of the PAM region. If the MTRRs
covering the PAM regions are set to WB or RD it is possible to get IWB cycles targeting
DMI. This may occur for processor originated cycles and for DMI originated cycles to
disabled PAM regions.
For example, say that a particular PAM region is set for “Read Disabled” and the MTRR
associated with this region is set to WB. A DMI master generates a memory read
targeting the PAM region. A snoop is generated on the FSB and the result is an IWB.
Since the PAM region is “Read Disabled” the default target for the Memory Read
becomes DMI. The IWB associated with this cycle will cause the (G)MCH to hang.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
58 Datasheet
System Address Map
8 GB
Main Memory
.
.
.
.
.
FFFF_FFFFh 4 GB
FLASH
APIC
LT
TSEG (1MB/2MB/8MB,
optional)
Main Memory
0100_0000h
ISA Hole (optional)
00F0_0000h
Main Memory
0010_0000h
DOS Compatibility Memory
0h
Datasheet 59
System Address Map
Video accelerators originally used this hole. It is also used by validation and customer
SV teams for some of their test cards. That is why it is being supported. There is no
inherent BIOS request for the 15 MB – 16 MB window.
3.2.2 TSEG
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory,
which is at the top of Low Usable physical memory (TOLUD). SMM-mode processor
accesses to enabled TSEG access the physical DRAM at the same address. Non-
processor originated accesses are not allowed to SMM space. PCI Express, DMI, and
Internal Graphics originated cycle to enabled SMM space are handled as invalid cycle
type with reads and writes to location 0 and byte enables turned off for writes. When
the extended SMRAM space is enabled, processor accesses to the TSEG range without
SMM attribute or without WB attribute are also forwarded to memory as invalid
accesses (see table 8). Non-SMM-mode Write Back cycles that target TSEG space are
completed to DRAM for cache coherency. When SMM is enabled the maximum amount
of memory available to the system is equal to the amount of physical DRAM minus the
value in the TSEG register which is fixed at 1 MB, 2 MB, or 8 MB.
Voids of physical addresses that are not accessible as general system memory and
reside within system memory address range (< TOLUD) are created for SMM-mode,
legacy VGA graphics compatibility, and GFX GTT stolen memory. It is the
responsibility of BIOS to properly initialize these regions. The following table
details the location and attributes of the regions. Enabling/Disabling these ranges are
described in the (G)MCH Control Register Device 0 (GCC).
Table 3-4. Pre-allocated Memory Example for 64 MB DRAM, 1 MB VGA, 1 MB GTT stolen
and 1 MB TSEG
03D0_0000h – SMM Mode Only - TSEG Address Range & Pre-allocated Memory
03DF_FFFFh processor Reads
60 Datasheet
System Address Map
With PCI Express port, there are two exceptions to this rule.
• Addresses decoded to the PCI Express Memory Window defined by the MBASE1
and MLIMIT1 registers are mapped to PCI Express.
• Addresses decoded to the PCI Express prefetchable Memory Window defined by
the PMBASE1 and PMLIMIT1 registers are mapped to PCI Express.
Datasheet 61
System Address Map
There are sub-ranges within the PCI Memory address range defined as APIC
Configuration Space, FSB Interrupt Space, and High BIOS Address Range. The
exceptions listed above for internal graphics and the PCI Express ports MUST NOT
overlap with these ranges.
FFFF_FFFFh 4 GB
High BIOS
FFE0_0000h 4 GB – 2 MB
DMI Interface
(subtractive decode)
FEF0_0000h 4 GB – 17 MB
FSB Interrupts
FEE0_0000h 4 GB – 18 MB Optional HSEG
DMI Interface
FEDA_0000h to
(subtractive decode) FEDB_FFFFh
FED0_0000h 4 GB – 19 MB
Local (Processor) APIC
FEC8_0000h
I/O APIC
FEC0_0000h 4 GB – 20 MB
DMI Interface
(subtractive decode)
F000_0000h
4 GB – 256 MB
Possible address
PCI Express Configuration range/size (not
Space ensured)
E000_0000h 4 GB – 512 MB
BARs, Internal
Graphics
DMI Interface ranges, PCI
(subtractive decode) Express Port,
CHAPADR could
be here.
TOLUD
MemMap_PCI
62 Datasheet
System Address Map
This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in
the ICH9 portion of the chipset, but may also exist as stand-alone components like
PXH.
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that
may be populated in the system. Since it is difficult to relocate an interrupt controller
using plug-and-play software, fixed address decode regions have been allocated for
them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh)
are always forwarded to DMI.
The (G)MCH optionally supports additional I/O APICs behind the PCI Express
“Graphics” port. When enabled via the PCI Express Configuration register (Device 1
Offset 200h), the PCI Express port will positively decode a subset of the APIC
configuration space – specifically FEC8_0000h thru FECF_FFFFh. Memory request to
this range would then be forwarded to the PCI Express port. This mode is intended for
the entry Workstation/Server SKU of the (G)MCH, and would be disabled in typical
Desktop systems. When disabled, any access within entire APIC Configuration space
(FEC0_0000h to FECF_FFFFh) is forwarded to DMI.
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any
device on PCI Express or DMI may issue a Memory Write to 0FEEx_xxxxh. The
(G)MCH will forward this Memory Write along with the data to the FSB as an Interrupt
Message Transaction. The (G)MCH terminates the FSB transaction by providing the
response and asserting HTRDYB. This memory write cycle does not go to DRAM.
Datasheet 63
System Address Map
less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that
full 2 MB must be considered.
The new reclaim configuration registers exist to reclaim lost main memory space. The
greater than 32 bit reclaim handling will be handled similar to other (G)MCHs.
Upstream read and write accesses above 36-bit addressing will be treated as invalid
cycles by PEG and DMI.
Top of Memory
The “Top of Memory” (TOM) register reflects the total amount of populated physical
memory. This is NOT necessarily the highest main memory address (holes may exist
in main memory address map due to addresses allocated for memory-mapped I/O
above TOM). TOM is used to allocate the Intel Management Engine's stolen memory.
The Intel ME stolen size register reflects the total amount of physical memory stolen
by the Intel ME. The ME stolen memory is located at the top of physical memory. The
ME stolen memory base is calculated by subtracting the amount of memory stolen by
the Intel ME from TOM.
The Top of Upper Usable DRAM (TOUUD) register reflects the total amount of
addressable DRAM. If reclaim is disabled, TOUUD will reflect TOM minus Intel ME
stolen size. If reclaim is enabled, then it will reflect the reclaim limit. Also, the reclaim
base will be the same as TOM minus ME stolen memory size to the nearest 64 MB
alignment.
TOLUD register is restricted to 4 GB memory (A[31:20]), but the (G)MCH can support
up to 16 GB, limited by DRAM pins. For physical memory greater than 4 GB, the
TOUUD register helps identify the address range in between the 4 GB boundary and
the top of physical memory. This identifies memory that can be directly accessed
(including reclaim address calculation) which is useful for memory access indication,
early path indication, and trusted read indication. When reclaim is enabled, TOLUD
must be 64 MB aligned, but when reclaim is disabled, TOLUD can be 1 MB aligned.
C1DRB3 cannot be used directly to determine the effective size of memory as the
values programmed in the DRBs depend on the memory mode (stacked, interleaved).
The Reclaim Base/Limit registers also can not be used because reclaim can be
disabled. The C0DRB3 register is used for memory channel identification (channel 0
vs. channel 1) in the case of stacked memory.
64 Datasheet
System Address Map
The following are examples of Memory Mapped IO devices are typically located below
4 GB:
• High BIOS
• HSEG
• TSEG
• Graphics stolen
• XAPIC
• Local APIC
• FSB Interrupts
• Mbase/Mlimit
• Memory-mapped I/O space that supports only 32 B addressing
The (G)MCH provides the capability to re-claim the physical memory overlapped by
the Memory Mapped IO logical address space. The (G)MCH re-maps physical memory
from the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to an
equivalent sized logical address range located just below the Intel ME's stolen
memory.
Datasheet 65
System Address Map
Conceptually, address decoding for each range follows the same basic concept. The
top 12 bits of the respective Memory Base and Memory Limit registers correspond to
address bits A[31:20] of a memory address . For the purpose of address decoding, the
(G)MCH assumes that address bits A[19:0] of the memory base are zero and that
address bits A[19:0] of the memory limit address are FFFFFh. This forces each
memory address range to be aligned to 1MB boundary and to have a size granularity
of 1 MB.
The (G)MCH positively decodes memory accesses to PCI Express memory address
space as defined by the following equations:
Note that the (G)MCH Device 1 memory range registers described above are used to
allocate memory address space for any PCI Express devices sitting on PCI Express
that require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In
other words, the memory access enable bit must be set in the device 1 PCICMD1
register to enable the memory base/limit and pre-fetchable base/limit windows.
The upper PMUBASE1/PMULIMIT1 registers have been implemented for PCI Express
Specification compliance. The (G)MCH locates MMIO space above 4 GB using these
registers.
66 Datasheet
System Address Map
These ranges can reside above the Top-of-Low-DRAM and below High BIOS and APIC
address ranges. They MUST reside above the top of memory (TOLUD) and below 4 GB
so they do not steal any physical DRAM memory space.
GMADR is a Prefetchable range in order to apply USWC attribute (from the processor
point of view) to that range. The USWC attribute is used by the processor for write
combining.
Note: DMI Interface and PCI Express masters are not allowed to access the SMM space.
Datasheet 67
System Address Map
SMM space is defined by its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the processor
to access SMM space. DRAM SMM space is defined as the range of physical DRAM
memory locations containing the SMM code. SMM space can be accessed at one of
three transaction address ranges: Compatible, High and TSEG. The Compatible and
TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space
is the same address range. Since the High SMM space is remapped the addressed and
DRAM SMM space is a different address range. Note that the High DRAM space is the
same as the Compatible Transaction Address space. Table 3-5 describes three unique
address ranges.
Table 3-5. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and 1-MB TSEG
NOTES:
1. STOLEN memory is only for the 82Q35/82Q33/82G33 GMCH.
If any of the following conditions are violated the results of SMM accesses are
unpredictable and may cause the system to hang:
1. The Compatible SMM space must not be set-up as cacheable.
2. High or TSEG SMM transaction address space must not overlap address space
assigned to system DRAM, or to any “PCI” devices (including DMI Interface, PCI-
Express, and graphics devices). This is a BIOS responsibility.
3. Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
4. When TSEG SMM space is enabled, the TSEG space must not be reported to the
OS as available DRAM. This is a BIOS responsibility.
5. Any address translated through the GMADR TLB must not target DRAM from
A_0000–F_FFFFh.
68 Datasheet
System Address Map
Global Enable High Enable TSEG Enable Compatible High (H) TSEG (T)
G_SMRAME H_SMRAM_EN TSEG_EN (C) Range Range Range
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit
allows software to write to the SMM ranges without being in SMM mode. BIOS
software can use this bit to initialize SMM code at powerup. The D_LCK bit limits the
SMM range access to only SMM mode accesses. The D_CLS bit causes SMM (both
CSEG and TSEG) data accesses to be forwarded to the DMI Interface or PCI Express.
The SMM software can use this bit to write to video memory while running SMM code
out of DRAM.
Only the processor is allowed to access SMM space. PCI Express and DMI Interface
originated transactions are not allowed to SMM space.
Datasheet 69
System Address Map
Accesses through GTT TLB address translation to enabled SMM DRAM space are not
allowed. Writes will be routed to memory address 000C_0000h with byte enables de-
asserted and reads will be routed to memory address 000C_0000h. If a GTT TLB
translated address hits enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface originated accesses are never allowed to access SMM
space directly or through the GTT TLB address translation. If a GTT TLB translated
address hits enabled SMM DRAM space, an error is recorded.
PCI Express and DMI Interface write accesses through GMADR range will be snooped.
Assesses to GMADR linear range (defined via fence registers) are supported. PCI
Express and DMI Interface tileY and tileX writes to GMADR are not supported. If, when
translated, the resulting physical address is to enabled SMM DRAM space, the request
will be remapped to address 000C_0000h with de-asserted byte enables.
PCI Express and DMI Interface read accesses to the GMADR range are not supported
therefore will have no address translation concerns. PCI Express and DMI Interface
reads to GMADR will be remapped to address 000C_0000h. The read will complete
with UR (unsupported request) completion status.
GTT fetches are always decoded (at fetch time) to ensure not in SMM (actually,
anything above base of TSEG or 640 KB – 1 MB). Thus, they will be invalid and go to
address 000C_0000h, but that is not specific to PCI Express or DMI; it applies to
processor or internal graphics engines. Also, since the GMADR snoop would not be
directly to the SMM space, there would not be a writeback to SMM. In fact, the
writeback would also be invalid (because it uses the same translation) and go to
address 000C_0000h.
70 Datasheet
System Address Map
The processor allows 64 K+3 bytes to be addressed within the I/O space. The (G)MCH
propagates the processor I/O address without any translation on to the destination
bus and therefore provides addressability for 64K+3 byte locations. Note that the
upper 3 locations can be accessed only during I/O address wrap-around when
processor bus HAB_16 address signal is asserted. HAB_16 is asserted on the
processor bus whenever an I/O access is made to 4 bytes from address 0FFFDh,
0FFFEh, or 0FFFFh. HAB_16 is also asserted when an I/O access is made to 2 bytes
from address 0FFFFh.
A set of I/O accesses (other than ones used for configuration space access) are
consumed by the internal graphics device if it is enabled. The mechanisms for internal
graphics I/O decode and the associated control is explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded
normally to the DMI Interface bus unless they fall within the PCI Express I/O address
range as defined by the mechanisms explained below. I/O writes are NOT posted.
Memory writes to ICH9 or PCI Express are posted. The PCICMD1 register can disable
the routing of I/O cycles to the PCI Express.
The (G)MCH responds to I/O cycles initiated on PCI Express or DMI with an UR status.
Upstream I/O cycles and configuration cycles should never occur. If one does occur,
the request will route as a read to memory address 000C_0000h so a completion is
naturally generated (whether the original request was a read or write). The
transaction will complete with an UR completion status.
For Pentium® 4 processors, I/O reads that lie within 8-byte boundaries but cross 4-
byte boundaries are issued from the processor as 1 transaction. The (G)MCH breaks
this into 2 separate transactions. I/O writes that lie within 8-byte boundaries but cross
4-byte boundaries are assumed to be split into 2 transactions by the processor.
The (G)MCH can be programmed to direct non-memory (I/O) accesses to the PCI
Express bus interface when processor initiated I/O cycle addresses are within the PCI
Express I/O address range. This range is controlled via the I/O Base Address
(IOBASE) and I/O Limit Address (IOLIMIT) registers in (G)MCH Device 1 configuration
space.
Address decoding for this range is based on the following concept. The top 4 bits of
the respective I/O Base and I/O Limit registers correspond to address bits A[15:12] of
an I/O address. For the purpose of address decoding, the (G)MCH assumes that lower
12 address bits A[11:0] of the I/O base are zero and that address bits A[11:0] of the
I/O limit address are FFFh. This forces the I/O address range alignment to 4 KB
boundary and produces a size granularity of 4 KB.
The (G)MCH positively decodes I/O accesses to PCI Express I/O address space as
defined by the following equation:
The (G)MCH also forwards accesses to the Legacy VGA I/O ranges according to the
settings in the Device 1 configuration registers BCTRL (VGA Enable) and PCICMD1
Datasheet 71
System Address Map
Note that the (G)MCH Device 1 I/O address range registers defined above are used for
all I/O space allocation for any devices requiring such a window on PCI Express.
The PCICMD1 register can disable the routing of I/O cycles to PCI Express.
HIGHMEM = 4 GB to TOM
72 Datasheet
(G)MCH Register Description
Datasheet 73
(G)MCH Register Description
Item Definition
RO Read Only bit(s). Writes to these bits have no effect. This may be a status
bit or a static value.
RO/S Read Only / Sticky bit(s). Writes to these bits have no effect. These are
status bits only. Bits are not returned to their default values by "warm"
reset, but will be reset with a cold/complete reset (for PCI Express related
bits a cold reset is “Power Good Reset” as defined in the PCI Express spec).
RS/WC Read Set / Write Clear bit(s). The first time the bit is read with an enabled
byte, it returns the value 0, but a side-effect of the read is that the value
changes to 1. Any subsequent reads with enabled bytes return a 1 until a 1
is written to the bit. When the bit is read, but the byte is not enabled, the
state of the bit does not change, and the value returned is irrelevant, but will
match the state of the bit.
RW Read / Write bit(s). These bits can be read and written by software.
Hardware may only change the state of this bit by reset.
RWC Read / Write Clear bit(s). These bits can be read. Internal events may set
this bit. A software write of ‘1’ clears (sets to ‘0’) the corresponding bit(s)
and a write of ‘0’ has no effect.
RWC/L Read / Write Clear / Lockable bit(s). These bits can be read. Internal events
may set this bit. A software write of ‘1’ clears (sets to ‘0’) the corresponding
bit(s) and a write of ‘0’ has no effect. Additionally there is a Key bit (which is
marked R/W/K or R/W/L/K) that, when set, prohibits this bit field from being
writeable (bit field becomes Read Only).
RWC/S Read / Write Clear / Sticky bit(s). These bits can be read. Internal events
may set this bit. A software write of ‘1’ clears (sets to ‘0’) the corresponding
bit(s) and a write of ‘0’ has no effect. Bits are not cleared by "warm" reset,
but will be reset with a cold/complete reset (for PCI Express related bits a
cold reset is “Power Good Reset” as defined in the PCI Express spec).
RW/B Read / Write / Blind bit(s). These bits can be read and written by software.
Additionally there is a selector bit which, when set, changes what may be
read from these bits. The value written is always stored in a hidden register.
When the selector bit indicates that the written value should not be read,
some other status is read from this bit. When the selector bit indicates that
the written value should be read, the value in the hidden register is read
from this bit.
RW/B/L Read / Write / Blind / Lockable bit(s). These bits can be read and written by
software. Additionally there is a selector bit which, when set, changes what
may be read from these bits. The value written is always stored in a hidden
register. When the selector bit indicates that the written value should not be
read, some other status is read from this bit. When the selector bit indicates
that the written value should be read, the value in the hidden register is read
from this bit. Additionally there is a Key bit (which is marked R/W/K or
R/W/L/K) that, when set, prohibits this bit field from being writeable (bit
field becomes Read Only).
74 Datasheet
(G)MCH Register Description
Item Definition
RW/K Read / Write / Key bit(s). These bits can be read and written by software.
Additionally this bit, when set, prohibits some other bit field(s) from being
writeable (bit fields become Read Only).
RW/L Read / Write / Lockable bit(s). These bits can be read and written by
software. Additionally there is a Key bit (which is marked R/W/K or R/W/L/K)
that, when set, prohibits this bit field from being writeable (bit field becomes
Read Only).
RW/L/K Read / Write / Lockable / Key bit(s). These bits can be read and written by
software. Additionally this bit is a Key bit that, when set, prohibits this bit
field and/or some other specified bit fields from being writeable (bit fields
become Read Only).
RW/S Read / Write / Sticky bit(s). These bits can be read and written by software.
Bits are not cleared by "warm" reset, but will be reset with a cold/complete
reset (for PCI Express related bits a cold reset is “Power Good Reset” as
defined in the PCI Express spec).
RW/S/B Read / Write / Sticky / Blind bit(s). These bits can be read and written by
software. Additionally there is a selector bit which, when set, changes what
may be read from these bits. The value written is always stored in a hidden
register. When the selector bit indicates that the written value should not be
read, some other status is read from this bit. When the selector bit indicates
that the written value should be read, the value in the hidden register is read
from this bit. Bits are not cleared by "warm" reset, but will be reset with a
cold/complete reset (for PCI Express related bits a cold reset is “Power Good
Reset” as defined in the PCI Express spec).
RW/SC Read / Write / Self Clear bit(s). These bits can be read and written by
software. When the bit is ‘1’, hardware may clear the bit to ‘0’ based upon
internal events, possibly sooner than any subsequent software read could
retrieve a ‘1’.
RW/SC/L Read / Write / Self Clear / Lockable bit(s). These bits can be read and
written by software. When the bit is ‘1’, hardware may clear the bit to ‘0’
based upon internal events, possibly sooner than any subsequent software
read could retrieve a ‘1’. Additionally there is a bit (which is marked R/W/K
or R/W/L/K) that, when set, prohibits this bit field from being writeable (bit
field becomes Read Only).
RWO Write Once bit(s). Once written by software, bits with this attribute become
Read Only. These bits can only be cleared by a Reset. If there are multiple
R/WO fields within a DWORD, they should be written all at once (atomically)
to avoid capturing an incorrect value.
WO Write Only. These bits may be written by software, but will always return
zeros when read. They are used for write side-effects. Any data written to
these registers cannot be retrieved.
Datasheet 75
(G)MCH Register Description
The DMI physically connects the (G)MCH and the Intel ICH9; so, from a configuration
standpoint, the DMI is logically PCI bus 0. As a result, all devices internal to the
(G)MCH and the Intel ICH9 appear to be on PCI bus 0.
Note: The ICH9 internal LAN controller does not appear on bus 0 – it appears on the
external PCI bus (whose number is configurable).
The system’s primary PCI expansion bus is physically attached to the Intel ICH9 and,
from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-
to-PCI bridge and therefore has a programmable PCI Bus number. The PCI Express
Graphics Attach appears to system software to be a real PCI bus behind a PCI-to-PCI
bridge that is a device resident on PCI bus 0.
Note: A physical PCI bus 0 does not exist and that DMI and the internal devices in the
(G)MCH and Intel ICH9 logically constitute PCI Bus 0 to configuration software.
The (G)MCH contains four PCI devices within a single physical component. The
configuration registers for the four devices are mapped as devices residing on PCI bus
0.
• Device 0: Host Bridge/DRAM Controller. Logically this appears as a PCI device
residing on PCI bus #0. Device 0 contains the standard PCI header registers, PCI
Express base address register, DRAM control (including thermal/throttling
control), configuration for the DMI, and other (G)MCH specific registers.
• Device 1: Host-PCI Express Bridge. Logically this appears as a “virtual” PCI-to-
PCI bridge residing on PCI bus #0 and is compliant with PCI Express Specification
rev 1.0. Device 1 contains the standard PCI-to-PCI bridge registers and the
standard PCI Express/PCI configuration registers (including the PCI Express
memory address mapping). It also contains Isochronous and Virtual Channel
controls in the PCI Express extended configuration space.
• Device 2: Internal Graphics Control (82Q35, 82Q33 ,82G33 GMCH only).
Logically, this appears as a PCI device residing on PCI bus #0. Physically, device 2
contains the configuration registers for 3D, 2D, and display functions.
• Device 3: Manageability Engine Device. ME Control.
76 Datasheet
(G)MCH Register Description
PCI Express extends the configuration space to 4096 bytes per device/function as
compared to 256 bytes allowed by PCI Specification Revision 2.3. PCI Express
configuration space is divided into a PCI 2.3 compatible region, which consists of the
first 256B of a logical device’s configuration space and a PCI Express extended region
which consists of the remaining configuration space.
The PCI compatible region can be accessed using either the Standard PCI
Configuration Mechanism or using the PCI Express Enhanced Configuration Mechanism
described in this section. The extended configuration registers may only be accessed
using the PCI Express Enhanced Configuration Mechanism. To maintain compatibility
with PCI configuration addressing mechanisms, system software must access the
extended configuration space using 32-bit operations (32-bit aligned) only. These 32-
bit operations include byte enables allowing only appropriate bytes within the DWord
to be accessed. Locked transactions to the PCI Express memory mapped configuration
address space are not supported. All changes made using either access mechanism
are equivalent.
Datasheet 77
(G)MCH Register Description
Located By PCI
Express* Base
Address MemMap_PCIExpress
Just the same as with PCI devices, each device is selected based on decoded address
information that is provided as a part of the address portion of Configuration Request
packets. A PCI Express device will decode all address information fields (bus, device,
function and extended address numbers) to provide access to the correct register.
1. use the PCI compatible configuration mechanism to enable the PCI Express
enhanced configuration mechanism by writing 1 to bit 0 of the PCIEXBAR
register.
2. use the PCI compatible configuration mechanism to write an appropriate PCI
Express base address into the PCIEXBAR register
3. calculate the host address of the register you wish to set using (PCI Express
base + (bus number * 1 MB) + (device number * 32KB) + (function number *
4 KB) + (1 B * offset within the function) = host address)
4. use a memory write or memory read cycle to the calculated host address to
write or read that register.
78 Datasheet
(G)MCH Register Description
Datasheet 79
(G)MCH Register Description
The (G)MCH decodes the Bus Number (bits 23:16) and the Device Number fields of
the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the
configuration cycle is targeting a PCI Bus #0 device.
If the targeted PCI Bus #0 device exists in the (G)MCH and is not disabled, the
configuration cycle is claimed by the appropriate device.
Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs.
• Bus Number [7:0] is Header Byte 8 [7:0]
• Device Number [4:0] is Header Byte 9 [7:3]
• Function Number [2:0] is Header Byte 9 [2:0]
See the PCI Express specification for more information on both the PCI 2.3 compatible
and PCI Express Enhanced Configuration Mechanism and transaction rules.
The device on other side of link must be Device #0. The (G)MCH will Master Abort any
Type 0 Configuration access to a non-zero Device number. If there is to be more than
one device on that side of the link there must be a bridge implemented in the
downstream device.
When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access is within the claimed range (between the upper bound
of the bridge device’s Subordinate Bus Number register and the lower bound of the
bridge device’s Secondary Bus Number register) but doesn't match the Device #1
Secondary Bus Number, a PCI Express Type 1 Configuration TLP is generated on the
secondary side of the PCI Express link.
80 Datasheet
(G)MCH Register Description
If the Bus Number is zero, the (G)MCH will generate a Type 0 Configuration Cycle TLP
on DMI. If the Bus Number is non-zero, and falls outside the range claimed by the
Host-PCI Express bridge, the (G)MCH will generate a Type 1 Configuration Cycle TLP
on DMI.
The ICH9 routes configurations accesses in a manner similar to the (G)MCH. The ICH9
decodes the configuration TLP and generates a corresponding configuration access.
Accesses targeting a device on PCI Bus #0 may be claimed by an internal device. The
ICH7 compares the non-zero Bus Number with the Secondary Bus Number and
Subordinate Bus Number registers of its P2P bridges to determine if the configuration
access is meant for Primary PCI, or some other downstream PCI bus or PCI Express
link.
Configuration accesses that are forwarded to the ICH9, but remain unclaimed by any
device or bridge will result in a master abort.
Datasheet 81
(G)MCH Register Description
82 Datasheet
(G)MCH Register Description
Datasheet 83
(G)MCH Register Description
84 Datasheet
DRAM Controller Registers (D0:F0)
Warning: Address locations that are not listed are considered Intel Reserved registers locations.
Reads to Reserved registers may return non-zero values. Writes to reserved locations
may cause system failures.
All registers that are defined in the PCI 2.3 specification, but are not necessary or
implemented in this component are simply not included in this document. The
reserved/unimplemented space in the PCI configuration header space is not
documented as such in this summary.
Datasheet 85
DRAM Controller Registers (D0:F0)
60–67h PCIEXBAR PCI Express Register Range Base 00000000E0 RO, RW/L,
Address 000000h RW/L/K
68–6Fh DMIBAR Root Complex Register Range Base 0000000000 RO, RW/L
Address 000000h
86 Datasheet
DRAM Controller Registers (D0:F0)
This register combined with the Device Identification register uniquely identifies any
PCI device.
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
Datasheet 87
DRAM Controller Registers (D0:F0)
15:10 RO Reserved
00h
9 RO Fast Back-to-Back Enable (FB2B): This bit controls whether or not
0b the master can do fast back-to-back write. Since device 0 is strictly a
target, this bit is not implemented and is hardwired to 0.
8 RW SERR Enable (SERRE): This bit is a global enable bit for Device 0
0b SERR messaging. The (G)MCH does not have an SERR signal. The
(G)MCH communicates the SERR condition by sending an SERR
message over DMI to the ICH.
Note that this bit only controls SERR messaging for the Device 0.
Device 1 has its own SERRE bits to control error reporting for error
conditions occurring in that device. The control bits are used in a
logical OR manner to enable the SERR DMI message mechanism.
7 RO Address/Data Stepping Enable (ADSTEP): Address/data stepping
0b is not implemented in the (G)MCH, and this bit is hardwired to 0.
6 RW Parity Error Enable (PERRE): This bit controls whether or not the
0b Master Data Parity Error bit in the PCI Status register can bet set.
0= Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
5 RO VGA Palette Snoop Enable (VGASNOOP): The (G)MCH does not
0b implement this bit and it is hardwired to a 0.
4 RO Memory Write and Invalidate Enable (MWIE): The (G)MCH will
0b never issue memory write and invalidate commands. This bit is
therefore hardwired to 0.
3 RO Special Cycle Enable (SCE): The (G)MCH does not implement this bit
0b and it is hardwired to a 0. Writes to this bit position have no effect.
2 RO Bus Master Enable (BME): The (G)MCH is always enabled as a
1b master on the backbone. This bit is hardwired to a 1.
1 RO Memory Access Enable (MAE): The (G)MCH always allows access to
1b main memory. This bit is not implemented and is hardwired to 1.
0 RO I/O Access Enable (IOAE): This bit is not implemented in the
0b (G)MCH and is hardwired to a 0.
88 Datasheet
DRAM Controller Registers (D0:F0)
This status register reports the occurrence of error events on Device 0's PCI interface.
Since the (G)MCH Device 0 does not physically reside on PCI_A many of the bits are
not implemented.
14 RWC Signaled System Error (SSE): Software clears this bit by writing a 1
0b to it.
1= The (G)MCH Device 0 generated a SERR message over DMI for any
enabled Device 0 error condition. Device 0 error conditions are
enabled in the PCICMD, ERRCMD, and DMIUEMSK registers. Device
0 error flags are read/reset from the PCISTS, ERRSTS, or DMIUEST
registers.
13 RWC Received Master Abort Status (RMAS): Software clears this bit by
0b writing a 1 to it.
12 RWC Received Target Abort Status (RTAS): Software clears this bit by
0b writing a 1 to it.
10:9 RO DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to
00b these bit positions have no affect. Device 0 does not physically connect
to PCI_A. These bits are set to "00" (fast decode) so that optimum
DEVSEL timing for PCI_A is not limited by the (G)MCH.
NOTE: This bit can only be set when the Parity Error Enable bit in the
PCI Command register is set.
Datasheet 89
DRAM Controller Registers (D0:F0)
6 RO Reserved
0b
3:0 RO Reserved
0h
This register contains the revision number of the (G)MCH Device #0. These bits are
read only and writes to this register have no effect.
90 Datasheet
DRAM Controller Registers (D0:F0)
This register identifies the basic function of the device, a more specific sub-class, and
a register-specific programming interface.
23:16 RO Base Class Code (BCC): This is an 8-bit value that indicates the
06h base class code for the (G)MCH.
15:8 RO Sub-Class Code (SUBCC): This is an 8-bit value that indicates the
00h category of Bridge into which the (G)MCH falls.
Device 0 in the (G)MCH is not a PCI master. Therefore this register is not
implemented.
7:0 RO Reserved
00h
Datasheet 91
DRAM Controller Registers (D0:F0)
This register identifies the header layout of the configuration space. No physical
register exists at this location.
7:0 RO PCI Header (HDR): This field always returns 0 to indicate that the
00h (G)MCH is a single function device with standard header layout. Reads
and writes to this location have no effect.
92 Datasheet
DRAM Controller Registers (D0:F0)
63:36 RO Reserved
0000000h
35:12 RW/L PCI Express Egress Port MMIO Base Address (PXPEPBAR): This
000000h field corresponds to bits 35:12 of the base address PCI Express Egress
Port MMIO configuration space. BIOS will program this register
resulting in a base address for a 4 KB block of contiguous memory
address space. This register ensures that a naturally aligned 4 KB
space is allocated within the first 64 GB of addressable memory space.
System Software uses this base address to program the (G)MCH
MMIO register set. All the bits in this register are locked in Intel® TXT
mode.
11:1 RO Reserved
000h
0 RW/L PXPEPBAR Enable (PXPEPBAREN):
0b 0 = PXPEPBAR is disabled and does not claim any memory
1 = PXPEPBAR memory mapped accesses are claimed and decoded
appropriately
This register is locked by Intel® TXT.
Datasheet 93
DRAM Controller Registers (D0:F0)
This is the base address for the (G)MCH Memory Mapped Configuration space. There is
no physical memory within this 16 KB window that can be addressed. The 16 KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the (G)MCH MMIO Memory Mapped Configuration space is disabled
and must be enabled by writing a 1 to MCHBAREN [Dev 0, offset48h, bit 0]
All the bits in this register are locked in Intel® Execution Technology mode.
The register space contains memory control, initialization, timing, and buffer strength
registers; clocking registers; and power and thermal management registers. The
16 KB space reserved by the MCHBAR register is not accessible during Intel®
Execution Technology mode of operation or if the ME security lock is asserted
(MESMLCK.ME_SM_lock at PCI device 0, function 0, offset F4h) except for the
following offset ranges.
63:36 RO Reserved
0000000h
35:14 RW/L GMCH Memory Mapped Base Address (MCHBAR): This field
000000h corresponds to bits 35:14 of the base address (G)MCH Memory Mapped
configuration space. BIOS will program this register resulting in a base
address for a 16 KB block of contiguous memory address space. This
register ensures that a naturally aligned 16 KB space is allocated.
System Software uses this base address to program the (G)MCH
Memory Mapped register set. All the bits in this register are locked in
Intel® TXT mode.
13:1 RO Reserved
0000h
94 Datasheet
DRAM Controller Registers (D0:F0)
15:10 RO Reserved
00h
9:8 RW/L GTT Graphics Memory Size (GGMS): This field is used to select the
0h amount of main memory that is pre-allocated to support the Internal
Graphics Translation Table. The BIOS ensures that memory is pre-
allocated only when Internal graphics is enabled.
11 = Reserved
Note: This register is locked and becomes Read Only when the
D_LCK bit in the SMRAM register is set.
Datasheet 95
DRAM Controller Registers (D0:F0)
7:4 RW/L Graphics Mode Select (GMS): This field is used to select the
0011b amount of Main Memory that is pre-allocated to support the Internal
Graphics device in VGA (non-linear) and Native (linear) modes. The
BIOS ensures that memory is pre-allocated only when Internal
graphics is enabled.
BIOS Requirement: BIOS must not set this field to 000 if IVD (bit 1
of this register) is 0.
3:2 RO Reserved
00b
1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and
I/O), and the Sub-Class Code field within Device 2 function 0
Class Code register is 80h.
BIOS Requirement: BIOS must not set this bit to 0 if the GMS field
(bits 6:4 of this register) pre-allocates no memory. This bit MUST be
set to 1 if Device 2 is disabled either via a fuse or fuse override
(CAPID0[46] = 1) or via a register (DEVEN[3] = 0).
0 RO Reserved
0b
96 Datasheet
DRAM Controller Registers (D0:F0)
This register allows for enabling/disabling of PCI devices and functions that are within
the (G)MCH. All the bits in this register are Intel® TXT Lockable.
31:10 RO Reserved
00000h
Datasheet 97
DRAM Controller Registers (D0:F0)
5 RO Reserved
0b
82P35 MCH
Reserved
82P35 MCH
Reserved
2 RO Reserved
0b
98 Datasheet
DRAM Controller Registers (D0:F0)
This is the base address for the PCI Express configuration space. This window of
addresses contains the 4 KB of configuration space for each PCI Express device that
can potentially be part of the PCI Express Hierarchy associated with the (G)MCH.
There is not actual physical memory within this window of up to 256 MB that can be
addressed. The actual length is determined by a field in this register. Each PCI Express
Hierarchy requires a PCI Express BASE register. The (G)MCH supports one PCI
Express hierarchy. The region reserved by this register does not alias to any PCI 2.3
compliant memory mapped space. For example, MCHBAR reserves a 16 KB space and
PXPEPBAR reserves a 4 KB space both outside of PCIEXBAR space. They cannot be
overlayed on the space reserved by PCIEXBAR for devices 0.
On reset, this register is disabled and must be enabled by writing a 1 to the enable
field in this register. This base address shall be assigned on a boundary consistent
with the number of buses (defined by the Length field in this register), above TOLUD
and still within 64 bit addressable memory space. All other bits not decoded are read
only 0. The PCI Express Base Address cannot be less than the maximum address
written to the Top of physical memory register (TOLUD). Software must ensure that
these ranges do not overlap with known ranges located above TOLUD. Software must
ensure that the sum of Length of enhanced configuration region + TOLUD + (other
known ranges reserved above TOLUD) is not greater than the 36-bit addressable limit
of 64 GB. In general system implementation and number of PCI/PCI Express/PCI-X
buses supported in the hierarchy will dictate the length of the region.
All the Bits in this register are locked in Intel® TXT mode.
63:36 RO Reserved
0000000h
Datasheet 99
DRAM Controller Registers (D0:F0)
35:28 RW/L PCI Express Base Address (PCIEXBAR): This field corresponds to
0Eh bits 35:28 of the base address for PCI Express enhanced configuration
space. BIOS will program this register resulting in a base address for a
contiguous memory address space; size is defined by bits 2:1 of this
register.
The address used to access the PCI Express configuration space for a
specific device can be determined as follows:
27 RW/L 128 MB Base Address Mask (128ADMSK): This bit is either part of
0b the PCI Express Base Address (R/W) or part of the Address Mask (RO,
read 0b), depending on the value of bits 2:1 in this register.
25:3 RO Reserved
000000h
2:1 RW/L/K Length (LENGTH): This Field describes the length of this region.
00b
Enhanced Configuration Space Region/Buses Decoded
11 = Reserved
100 Datasheet
DRAM Controller Registers (D0:F0)
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the (G)MCH. There is no physical memory within this 4 KB window
that can be addressed. The 4 KB reserved by this register does not alias to any PCI
2.3 compliant memory mapped space. On reset, the Root Complex configuration space
is disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0]
All the Bits in this register are locked in Intel® TXT mode.
63:36 RO Reserved
0000000h
35:12 RW/L DMI Base Address (DMIBAR): This field corresponds to bits 35:12
000000h of the base address DMI configuration space. BIOS will program this
register resulting in a base address for a 4KB block of contiguous
memory address space. This register ensures that a naturally aligned
4 KB space is allocated within the first 64 GB of addressable memory
space. System Software uses this base address to program the DMI
register set.
11:1 RO Reserved
000h
0 RW/L DMIBAR Enable (DMIBAREN):
0b 0 = DMIBAR is disabled and does not claim any memory
1 = DMIBAR memory mapped accesses are claimed and decoded
appropriately
This register is locked by Intel® TXT.
Datasheet 101
DRAM Controller Registers (D0:F0)
This register controls the read, write, and shadowing attributes of the BIOS area from
0F0000h–0FFFFFh. The (G)MCH allows programmable memory attributes on 13
Legacy memory segments of various sizes in the 768 KB to 1 MB address range.
Seven Programmable Attribute Map (PAM) Registers are used to support these
features. Cacheability of these areas is controlled via the MTRR registers in the P6
processor. Two bits are used to specify memory attributes for each memory segment.
These bits apply to both host accesses and PCI initiator accesses to the PAM areas.
These attributes are:
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0,
the segment is Read Only. Each PAM Register controls two regions, typically 16 KB in
size.
Note that the (G)MCH may hang if a PCI Express Graphics Attach or DMI originated
access to Read Disabled or Write Disabled PAM segments occur (due to a possible IWB
to non-DRAM).
For these reasons the following critical restriction is placed on the programming of the
PAM regions: At the time that a DMI or PCI Express Graphics Attach accesses to the
PAM region may occur, the targeted PAM segment must be programmed to be both
readable and writeable.
102 Datasheet
DRAM Controller Registers (D0:F0)
7:6 RO Reserved
00b
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
3:0 RO Reserved
0h
Datasheet 103
DRAM Controller Registers (D0:F0)
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C0000h–0C7FFFh.
7:6 RO Reserved
00b
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
3:2 RO Reserved
00b
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
104 Datasheet
DRAM Controller Registers (D0:F0)
This register controls the read, write, and shadowing attributes of the BIOS areas from
0C8000h–0CFFFFh.
7:6 RO Reserved
00b
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
3:2 RO Reserved
00b
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
Datasheet 105
DRAM Controller Registers (D0:F0)
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D0000h–0D7FFFh.
7:6 RO Reserved
00b
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
3:2 RO Reserved
00b
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
106 Datasheet
DRAM Controller Registers (D0:F0)
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D8000h–0DFFFFh.
7:6 RO Reserved
00b
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
3:2 RO Reserved
00b
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
Datasheet 107
DRAM Controller Registers (D0:F0)
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E0000h–0E7FFFh.
7:6 RO Reserved
00b
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
3:2 RO Reserved
00b
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
108 Datasheet
DRAM Controller Registers (D0:F0)
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E8000h–0EFFFFh.
7:6 RO Reserved
00b
5:4 RW/L 0EC000h–0EFFFFh Attribute (HIENABLE): This field controls the
00b steering of read and write cycles that address the BIOS area from
0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
This register is locked by Intel® TXT.
3:2 RO Reserved
00b
1:0 RW/L 0E8000h–0EBFFFh Attribute (LOENABLE): This field controls the
00b steering of read and write cycles that address the BIOS area from
0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are
forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by
DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by
DRAM.
This register is locked by Intel® TXT.
Datasheet 109
DRAM Controller Registers (D0:F0)
This 8-bit register controls a fixed DRAM hole from 15–16 MB.
7 RW/L Hole Enable (HEN): This field enables a memory hole in DRAM space.
0b The DRAM that lies "behind" this space is not remapped.
0 = No memory hole.
6:1 RO Reserved
00000b
0 RW MDA Present (MDAP): This bit works with the VGA Enable bits in the
0b BCTRL register of Device 1 to control the routing of processor initiated
transactions targeting MDA compatible I/O and memory address ranges.
This bit should not be set if device 1's VGA Enable bit is not set.
If device 1's VGA enable bit is not set, then accesses to IO address
range x3BCh–x3BFh are forwarded to DMI.
If the VGA enable bit is set and MDA is not present, then accesses to IO
address range x3BCh–x3BFh are forwarded to PCI Express if the address
is within the corresponding IOBASE and IOLIMIT, otherwise they are
forwarded to DMI.
MDA resources are defined as the following:
The following table shows the behavior for all combinations of MDA and
VGA:
110 Datasheet
DRAM Controller Registers (D0:F0)
15:10 RO Reserved
000000b
9:0 RW/L Remap Base Address [35:26] (REMAPBASE): The value in this
3FFh register defines the lower boundary of the Remap window. The Remap
window is inclusive of this address. In the decoder A[25:0] of the
Remap Base Address are assumed to be 0s. Thus, the bottom of the
defined memory range will be aligned to a 64 MB boundary.
When the value in this register is greater than the value programmed
into the Remap Limit register, the Remap window is disabled.
15:10 RO Reserved
000000b
9:0 RW/L Remap Limit Address [35:26] (REMAPLMT): The value in this
000h register defines the upper boundary of the Remap window. The Remap
window is inclusive of this address. In the decoder A[25:0] of the
remap limit address are assumed to be Fhs. Thus the top of the defined
range will be one less than a 64 MB boundary.
When the value in this register is less than the value programmed into
the Remap Base register, the Remap window is disabled.
Datasheet 111
DRAM Controller Registers (D0:F0)
The SMRAMC register controls how accesses to Compatible and Extended SMRAM
spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit
is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.
7 RO Reserved
0b
6 RW/L SMM Space Open (D_OPEN): When D_OPEN=1 and D_LCK=0, the
0b SMM space DRAM is made visible even when SMM decode is not
active. This is intended to help BIOS initialize SMM space. Software
should ensure that D_OPEN=1 and D_CLS=1 are not set at the same
time.
4 RW/L/K SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN
0b is reset to 0 and D_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN,
TSEG_SZ and TSEG_EN become read only. D_LCK can be set to 1 via
a normal configuration space write but can only be cleared by a Full
Reset. The combination of D_LCK and D_OPEN provide convenience
with security. The BIOS can use the D_OPEN function to initialize SMM
space and then use D_LCK to "lock down" SMM space in the future so
that no application software (or BIOS itself) can violate the integrity of
SMM space, even if the program has knowledge of the D_OPEN
function.
112 Datasheet
DRAM Controller Registers (D0:F0)
7 RW/L Enable High SMRAM (H_SMRAME): This bit controls the SMM memory
0b space location (i.e., above 1 MB or below 1 MB) When G_SMRAME is 1
and H_SMRAME is set to 1, the high SMRAM memory space is enabled.
SMRAM accesses within the range 0FEDA0000h to 0FEDBFFFFh are
remapped to DRAM addresses within the range 000A0000h to
000BFFFFh. Once D_LCK has been set, this bit becomes read only.
6 RWC Invalid SMRAM Access (E_SMERR): This bit is set when processor
0b has accessed the defined memory ranges in Extended SMRAM (High
Memory and T-segment) while not in SMM space and with the D-OPEN
bit = 0. It is software's responsibility to clear this bit. The software must
write a 1 to this bit to clear it.
5 RO SMRAM Cacheable (SM_CACHE): This bit is forced to 1 by the
1b (G)MCH.
4 RO L1 Cache Enable for SMRAM (SM_L1): This bit is forced to 1 by the
1b (G)MCH.
3 RO L2 Cache Enable for SMRAM (SM_L2): This bit is forced to 1 by the
1b (G)MCH.
2:1 RW/L TSEG Size (TSEG_SZ): Selects the size of the TSEG memory block if
00b enabled. Memory from the top of DRAM space is partitioned away so that
it may only be accessed by the processor interface and only then when
the SMM bit is set in the request packet. Non-SMM accesses to this
memory region are sent to DMI when the TSEG memory block is
enabled.
00 = 1 MB TSEG. (TOLUD – GTT Graphics Memory Size – Graphics
Stolen Memory Size – 1 MB) to (TOLUD – GTT Graphics Memory
Size – Graphics Stolen Memory Size).
01 = 2 MB TSEG. (TOLUD – GTT Graphics Memory Size – Graphics
Stolen Memory Size – 2 MB) to (TOLUD – GTT Graphics Memory
Size – Graphics Stolen Memory Size).
10 = 8 MB TSEG. (TOLUD – GTT Graphics Memory Size – Graphics
Stolen Memory Size – 8 MB) to (TOLUD – GTT Graphics Memory
Size – Graphics Stolen Memory Size).
11 = Reserved.
Once D_LCK has been set, these bits becomes read only.
Datasheet 113
DRAM Controller Registers (D0:F0)
This Register contains the size of physical memory. BIOS determines the memory size
reported to the OS using this Register.
15:10 RO Reserved
00h
9:0 RW/L Top of Memory (TOM): This register reflects the total amount of
001h populated physical memory. This is NOT necessarily the highest main
memory address (holes may exist in main memory address map due
to addresses allocated for memory mapped I/O). These bits
correspond to address bits 35:26 (64 MB granularity). Bits 25:0 are
assumed to be 0. All the bits in this register are locked in Intel® TXT
mode.
114 Datasheet
DRAM Controller Registers (D0:F0)
Configuration software must set this value to TOM minus all EP stolen memory if
reclaim is disabled. If reclaim is enabled, this value must be set to (reclaim limit + 1
byte) 64 MB aligned since reclaim limit is 64 MB aligned. Address bits 19:0 are
assumed to be 000_0000h for the purposes of address comparison. The Host interface
positively decodes an address towards DRAM if the incoming address is less than the
value programmed in this register and greater than or equal to 4 GB.
All the Bits in this register are locked in Intel® TXT mode.
Datasheet 115
DRAM Controller Registers (D0:F0)
This register contains the base address of graphics data stolen DRAM memory. BIOS
determines the base of graphics data stolen memory by subtracting the graphics data
stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0, offset
B0h, bits 15:4).
Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM
register is set.
31:20 RW/L Graphics Base of Stolen Memory (GBSM): This register contains
000h bits 31:20 of the base address of stolen DRAM memory. BIOS
determines the base of graphics stolen memory by subtracting the
graphics stolen memory size (PCI Device 0, offset 52h, bits 6:4) from
TOLUD (PCI Device 0, offset B0h, bits 15:04).
Note: This register is locked and becomes Read Only when the D_LCK
bit in the SMRAM register is set.
19:0 RO Reserved
00000h
116 Datasheet
DRAM Controller Registers (D0:F0)
This register contains the base address of stolen DRAM memory for the GTT. BIOS
determines the base of GTT stolen memory by subtracting the GTT graphics stolen
memory size (PCI Device 0 offset 52 bits 9:8) from the graphics stolen memory base
(PCI Device 0, offset A4h, bits 31:20).
Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM
register is set.
31:20 RW/L Graphics Base of Stolen Memory (GBSM): This register contains
000h bits 31:20 of the base address of stolen DRAM memory. BIOS
determines the base of graphics stolen memory by subtracting the
GTT graphics stolen memory size (PCI Device 0, offset 52h, bits 9:8)
from the graphics stolen memory base (PCI Device 0, offset A4h, bits
31:20).
Note: This register is locked and becomes Read Only when the D_LCK
bit in the SMRAM register is set.
19:0 RO Reserved
00000h
31:20 RW/L TESG Memory base (TSEGMB): This register contains bits 31:20 of
000h the base address of TSEG DRAM memory. BIOS determines the base
of TSEG memory by subtracting the TSEG size (PCI Device 0, offset
9Eh, bits 2:1) from graphics GTT stolen base (PCI Device 0, offset
A8h, bits 31:20).
Once D_LCK has been set, these bits becomes read only.
19:0 RO Reserved
00000h
Datasheet 117
DRAM Controller Registers (D0:F0)
This 16 bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics Memory
and Graphics Stolen Memory are within the DRAM space defined. From the top,
(G)MCH optionally claims 1 to 64 MB of DRAM for internal graphics if enabled 1, 2 MB
of DRAM for GTT Graphics Stolen Memory (if enabled) and 1, 2, or 8 MB of DRAM for
TSEG, if enabled.
Programming Example :
C1DRB3 is set to 4 GB
BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the
system. This 20MB range at the very top of addressable memory space is lost to APIC
and Intel® TXT.
The system memory requirements are: 4GB (max addressable space) – 1 GB (PCI
space) – 35 MB (lost memory) = 3 GB – 35 MB (minimum granularity) = ECB0_0000h
Since ECB0_0000h (PCI and other system requirements) is less than 1_0000_0000h,
TOLUD should be programmed to ECBh.
118 Datasheet
DRAM Controller Registers (D0:F0)
15:4 RW/L Top of Low Usable DRAM (TOLUD): This register contains bits
001h 31:20 of an address one byte above the maximum DRAM memory
below 4 GB that is usable by the operating system. Address bits 31:20
programmed to 01h implies a minimum memory size of 1 MB.
Configuration software must set this value to the smaller of the
following 2 choices: maximum amount memory in the system minus
ME stolen memory plus one byte or the minimum address allocated
for PCI memory. Address bits 19:0 are assumed to be 0_0000h for
the purposes of address comparison. The Host interface positively
decodes an address towards DRAM if the incoming address is less than
the value programmed in this register.
Note that the Top of Low Usable DRAM is the lowest address above
both Graphics Stolen memory and TSEG. BIOS determines the base of
Graphics Stolen Memory by subtracting the Graphics Stolen Memory
Size from TOLUD and further decrements by TSEG size to determine
base of TSEG. All the Bits in this register are locked in Intel® TXT
mode.
3:0 RO Reserved
0000b
This register is used to report various error conditions via the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked
by clearing the appropriate status bit by software writing a 1 to it.
15 RO Reserved
0b
If this bit is already set, then an interrupt message will not be sent on
a new error event.
Datasheet 119
DRAM Controller Registers (D0:F0)
If this bit is already set, then an interrupt message will not be sent on
a new error event.
10 RO Reserved
0b
8 RO Reserved
0b
0 = Software has cleared this flag since the most recent throttling
event.
6:0 RO Reserved
0s
120 Datasheet
DRAM Controller Registers (D0:F0)
This register controls the (G)MCH responses to various system errors. Since the
(G)MCH does not have an SERR# signal, SERR messages are passed from the (G)MCH
to the ICH over DMI.
When a bit in this register is set, a SERR message will be generated on DMI whenever
the corresponding flag is set in the ERRSTS register. The actual generation of the
SERR message is globally enabled for Device #0 via the PCI Command register.
15:12 RO Reserved
0h
10 RO Reserved
0b
8:7 RW Reserved
00b
6:0 RO Reserved
0s
Datasheet 121
DRAM Controller Registers (D0:F0)
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively. Note that one and only one message type can be enabled.
15:12 RO Reserved
0h
10:0 RO Reserved
0s
This register holds 32 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
122 Datasheet
DRAM Controller Registers (D0:F0)
Control of bits in this register are only required for customer visible SKU
differentiation.
87:79 RO Reserved
0s
Definitions:
82P35 MCH
Reserved
Datasheet 123
DRAM Controller Registers (D0:F0)
75:73 RO Reserved
00b
1 = Enable
1 = Enable
1 = Enable
1 = Enable
67:58 RO Reserved
0s
57 RO ME Disable (MED):
0b
0 = ME feature is enabled
1 = ME feature is disabled
56:48 RO Reserved
0s
82P35 MCH
Reserved
124 Datasheet
DRAM Controller Registers (D0:F0)
82P35 MCH
Reserved
1 = Not Capable of x16 PEG port, instead PEG limited to x8 and below.
Causes PEG port to enable and train logical lanes 7:0 only. Logical
lanes 15:8 are powered down, and the Max Link Width field of the
Link Capability register reports x8 instead of x16. (in the case of
lane reversal, lanes 15:8 are active and lanes 7:0 are powered
down)
43:39 RO Reserved
00000b
Datasheet 125
DRAM Controller Registers (D0:F0)
37:34 RO Reserved
0000b
33:31 RO DDR Frequency Capability (DDRFC): This field controls which values
000b may be written to the Memory Frequency Select field 6:4 of the
Clocking Configuration registers (MCHBAR Offset C00h). Any attempt to
write an unsupported value will be ignored.
NOTE: DDR3 is only supported on the 82G33 GMCH and 82P35 MCH
components.
30:28 RO FSB Frequency Capability (FSBFC): This field controls which values
000b are allowed in the PSB Frequency Select Field 2:0 of the Clocking
Configuration Register. These values are determined by the BSEL[2:0]
frequency straps. Any unsupported strap values will render the (G)MCH
System Memory Interface inoperable.
27:24 RO CAPID Version (CAPIDV): This field has the value 0001b to identify
1h the first revision of the CAPID register definition.
23:16 RO CAPID Length (CAPIDL): This field has the value 0bh to indicate the
0bh structure length (11 bytes).
7:0 RO Capability Identifier (CAP_ID): This field has the value 1001b to
09h identify the CAP_ID assigned by the PCI SIG for vendor dependent
capability pointers.
126 Datasheet
DRAM Controller Registers (D0:F0)
5.2 MCHBAR
The MCHBAR registers are offset from the MCHBAR base address. Table 5-2 provides
an address map of the registers listed by address offset in ascending order. Detailed
register bit descriptions follow the table.
Datasheet 127
DRAM Controller Registers (D0:F0)
128 Datasheet
DRAM Controller Registers (D0:F0)
Datasheet 129
DRAM Controller Registers (D0:F0)
7 RW/L Reserved
0b
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
1 RW/L Reserved
0b
0 = Not Present
1 = Present
130 Datasheet
DRAM Controller Registers (D0:F0)
The DRAM Rank Boundary Registers define the upper boundary address of each DRAM
rank with a granularity of 64 MB. Each rank has its own single-word DRB register.
These registers are used to determine which chip select will be active for a given
address. Channel and rank map:
Ch 0, Rank 0 = 200h
Ch 0, Rank 1 = 202h
Ch 0, Rank 2 = 204h
Ch 0, Rank 3 = 206h
Ch 1, Rank 0 = 600h
Ch 1, Rank 1 = 602h
Ch 1, Rank 2 = 604h
Ch 1, Rank 3 = 606h
Programming Guide
If Channel 0 is empty, all of the C0DRBs are programmed with 00h.
Datasheet 131
DRAM Controller Registers (D0:F0)
15:10 RO Reserved
000000b
= R0
15:10 RO Reserved
000000b
= (R1 + R0)
132 Datasheet
DRAM Controller Registers (D0:F0)
15:10 RO Reserved
000000b
= (R2 + R1 + R0)
15:10 RO Reserved
000000b
= (R3 + R2 + R1 + R0)
Datasheet 133
DRAM Controller Registers (D0:F0)
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Ch 0, Rank 0, 1= 208h–209h
Ch 0, Rank 2, 3 = 20Ah–20Bh
Ch 1, Rank 0, 1= 608h–609h
Ch 1, Rank 2, 3= 60Ah–60Bh
DRA[7:0] = "00" means Cfg 0 , DRA[7:0] ="01" means Cfg 1 .... DRA[7:0] = "09" means Cfg 9
and so on.
1 Gb 2,3 128M 8 14 10 3 1 GB 8k
NOTE: DDR3 is only supported on the 82G33 GMCH and 82P35 MCH components.
15:8 R/W Channel 0 DRAM Rank-1 Attributes (C0DRA1): This field defines
00h DRAM pagesize/number-of-banks for rank1 for given channel. See
Table 5-3 for programming.
7:0 R/W Channel 0 DRAM Rank-0 Attributes (C0DRA0): This field defines
00h DRAM page size/number-of-banks for rank0 for given channel. See
Table 5-3 for programming.
134 Datasheet
DRAM Controller Registers (D0:F0)
15:11 RO Reserved
00000b
Datasheet 135
DRAM Controller Registers (D0:F0)
31:28 RO Reserved
0h
136 Datasheet
DRAM Controller Registers (D0:F0)
Datasheet 137
DRAM Controller Registers (D0:F0)
23:21 RO Reserved
000b
20:17 RW Min ACT To READ Delay (C0sd_cr_act_rd): This field indicates the
0h minimum allowed spacing (in DRAM clocks) between the ACT and
READ commands to the same rank-bank. This field corresponds to
tRCD_rd in the DDR Specification.
16:12 RW Same Rank Write To READ Delay (C0sd_cr_wrsr_rd): This field
00000b indicates the minimum allowed spacing (in DRAM clocks) between the
WRITE and READ commands to the same rank. This field corresponds
to tWTR in the DDR Specification.
11:8 RW Different Ranks Write To READ Delay (C0sd_cr_wrdr_rd): This
0000b field indicates the minimum allowed spacing (in DRAM clocks) between
the WRITE and READ commands to different ranks. This field
corresponds to tWR_RD in the DDR Specification.
7:4 RW Same Rank Read To Read Delay (C0sd_cr_rdsr_rd): This field
0000b indicates the minimum allowed spacing (in DRAM clocks) between two
READ commands to the same rank.
3:0 RW Different Ranks Read To Read Delay (C0sd_cr_rddr_rd): This
0000b field indicates the minimum allowed spacing (in DRAM clocks) between
two READ commands to different ranks. This field corresponds to
tRD_RD.
15:13 RO Reserved
000b
12:9 RW Same Rank PALL to REF Delay (C0sd_cr_pchgall_rfsh): This
0000b field indicates the minimum allowed spacing (in DRAM clocks)
between the PRE-ALL and REF commands to the same rank.
8:0 RW Same Rank REF to REF Delay (C0sd_cr_rfsh_rfsh): This field
000000000b indicates the minimum allowed spacing (in DRAM clocks) between
two REF commands to same ranks.
138 Datasheet
DRAM Controller Registers (D0:F0)
31:28 RO Reserved
0000b
15:14 RO Reserved
00b
Datasheet 139
DRAM Controller Registers (D0:F0)
0000–0001 = Reserved
0010–1001 = 2–9clocks
1010–1111 = Reserved
47:42 RO Reserved
00h
41:37 RW Direct Rcomp Quiet Window (DIRQUIET): This field indicates the
10000b amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
26 RW Reserved
0b
140 Datasheet
DRAM Controller Registers (D0:F0)
This bit has no effect when Refresh is enabled (i.e., there is no mode
where Refresh is enabled but the counter does not run). Thus, in
conjunction with bit 23 REFEN, the modes are:
REFEN:REFCNTEN Description
0 = Disabled
1 = Enabled
0 = Not Done
1 = Done
21:20 RW Reserved
00b
00 = 5
01 = 6
10 = 7
11 = 8
00 = 3
01 = 4
10 = 5
11 = 6
Datasheet 141
DRAM Controller Registers (D0:F0)
00 = 1
01 = 2
10 = 3
11 = 4
31:12 RO Reserved
00000h
11:8 RW Reserved
0000b
7:4 RW Reserved
0000b
3:0 RW Reserved
0000b
142 Datasheet
DRAM Controller Registers (D0:F0)
The operation of this register is detailed in the description for register C0DRB0.
15:10 RO Reserved
000000b
The operation of this register is detailed in the description for register C0DRB0.
15:10 RO Reserved
000000b
Datasheet 143
DRAM Controller Registers (D0:F0)
The operation of this register is detailed in the description for register C0DRB0.
15:10 RO Reserved
000000b
The operation of this register is detailed in the description for register C0DRB0.
15:10 RO Reserved
000000b
9:0 RW/L Channel 1 DRAM Rank Boundary Address 3 (C1DRBA3): See
000h C0DRB3 register. In stacked mode, this will be cumulative of Ch0
DRB3.
This register is locked by ME stolen Memory lock.
144 Datasheet
DRAM Controller Registers (D0:F0)
The operation of this register is detailed in the description for register C0DRA01.
The operation of this register is detailed in the description for register C0DRA01.
Datasheet 145
DRAM Controller Registers (D0:F0)
15:11 RO Reserved
00000b
146 Datasheet
DRAM Controller Registers (D0:F0)
31:28 RO Reserved
0h
Datasheet 147
DRAM Controller Registers (D0:F0)
148 Datasheet
DRAM Controller Registers (D0:F0)
23:21 RO Reserved
0h
Datasheet 149
DRAM Controller Registers (D0:F0)
31:28 RO Reserved
0h
150 Datasheet
DRAM Controller Registers (D0:F0)
15:14 RO Reserved
00b
1010–1111 = Reserved.
0000–0001 = Reserved.
47:42 RO Reserved
00h
0 = Disable
1 = Enable
Datasheet 151
DRAM Controller Registers (D0:F0)
This bit has no effect when Refresh is enabled (i.e., there is no mode
where Refresh is enabled but the counter does not run). Thus, in
conjunction with bit 23 REFEN, the modes are:
REFEN:REFCNTEN Description
1 = Enabled
0 = Not Done
1 = Done
00 = 3
01 = 4
10 = 5
11 = 6
00 = 5
01 = 6
10 = 7
11 = 8
00 = 3
01 = 4
10 = 5
11 = 6
152 Datasheet
DRAM Controller Registers (D0:F0)
00 = 1
01 = 2
10 = 3
11 = 4
31:12 RO Reserved
00000h
Datasheet 153
DRAM Controller Registers (D0:F0)
15:10 RO Reserved
000000b
15:10 RO Reserved
000000b
15:10 RO Reserved
000000b
154 Datasheet
DRAM Controller Registers (D0:F0)
15:10 RO Reserved
000000b
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the CxDRA registers describes the page
size of a pair of ranks. Channel and rank map:
Datasheet 155
DRAM Controller Registers (D0:F0)
156 Datasheet
DRAM Controller Registers (D0:F0)
31:21 RO Reserved
000h
20:17 RW ACT to ACT Delayed (C0sd_cr_act_act[): This field indicates the
0000b minimum allowed spacing (in DRAM clocks) between two ACT
commands to the same rank.
16:13 RW PRE to ACT Delayed (C0sd_cr_pre_act): This field indicates the
0000b minimum allowed spacing (in DRAM clocks) between the PRE and ACT
commands to the same rank-bank:12:9R/W0000bPRE-ALL to ACT
Delayed (C0sd_cr_preall_act):
This field indicates the minimum allowed spacing (in DRAM clocks)
between the PRE-ALL and ACT commands to the same rank.
12:9 RO Reserved
0h
8:0 RW REF to ACT Delayed (C0sd_cr_rfsh_act): This field indicates the
00000000 minimum allowed spacing (in DRAM clocks) between REF and ACT
0b commands to the same rank.
Datasheet 157
DRAM Controller Registers (D0:F0)
7:4 RO Reserved
0h
158 Datasheet
DRAM Controller Registers (D0:F0)
23:23 RO Reserved
0h
22:20 RW EPDunit DQS Slave DLL Enable to Read Safe (EPDSDLL2RD):
000b This field provides the setting for Read command safe from the point
of enabling the slave DLLs.
19:18 RO Reserved
0h
17:14 RW Min ACT To READ Delayed (C0sd_cr_act_rd): This field indicates
0h the minimum allowed spacing (in DRAM clocks) between the ACT and
READ commands to the same rank-bank.
8:6 RO Reserved
0h
2:0 RO Reserved
0h
Datasheet 159
DRAM Controller Registers (D0:F0)
34:32 RW EPDunit TXP count (EPDCKETXP): This field specifies the timing
000b requirement for Active power down exit or fast exit pre-charge power
down exit to any command or slow exit pre-charge power down to
Non-DLL (rd/wr/odt) command.
31:29 RW Mode Select (sd0_cr_sms): This field indicates the mode in which
111b the controller is operating in.
01 = EMRS
10 = EMRS2
11 = EMRS3
16:15 RO Reserved
0h
0 = Normal mode
160 Datasheet
DRAM Controller Registers (D0:F0)
11:10 RO Reserved
0h
Datasheet 161
DRAM Controller Registers (D0:F0)
This register provides settings to enable the ME memory space and define the size of
EP memory if enabled.
7:5 RO Reserved
000b
4:0 R/W ME-UMA(Sx) Region Size (EXRS): These bits are written by
00000b firmware to indicate the desired size of ME-UMA(Sx) memory region.
This is done prior to bring up core power and allowing BIOS to
initialize memory. Within channel 0 DDR, the physical base address
for MEUMA(Sx) will be determined by:
162 Datasheet
DRAM Controller Registers (D0:F0)
31 RO Reserved
0b
00 = Add 0 Refreshes
01 = Add 1 Refreshes
10 = Add 2 Refreshes
11 = Add 3 Refreshes
This bit has no effect when Refresh is enabled (i.e. there is no mode
where Refresh is enabled but the counter does not run). Thus, in
conjunction with bit 23 REFEN, the modes are:
REFEN:REFCNTEN Description
1 = Enabled
0 = Not Done
1 = Done
Datasheet 163
DRAM Controller Registers (D0:F0)
0000 = 0
0001 = 1
.......
1000 = 8
0000 = 0
0001 = 1
.......
1000 = 8
0000 = 0
0001 = 1
.......
1000 = 8
164 Datasheet
DRAM Controller Registers (D0:F0)
This register controls the operation of the thermal sensor. Bits 7:1 of this register are
reset to their defaults by CL_PWROK. Bit 0 is reset to its default by PLTRST#.
7 RW/L Thermal Sensor Enable (TSE): This bit enables power to the
0b thermal sensor. Lockable via TCO bit 7.
0 = Disabled
1 = Enabled
0 = hysteresis disabled
...
...
0 = Catastrophic
1 = Hot
Datasheet 165
DRAM Controller Registers (D0:F0)
Software can poll this bit until it reads a 0, and will then own the
usage of the thermal sensor.
This bit has no other effect on the hardware, and is only used as a
semaphore among various independent software threads that may
need to use the thermal sensor.
Software that reads this register but does not intend to claim
exclusive access of the thermal sensor must write a one to this bit if it
reads a 0, in order to allow other software threads to claim it.
See also THERM3 bit 7 and IUB, which are independent additional
semaphore bits.
This register controls the operation of the thermal sensor. All bits in this register are
reset to their defaults by CL_PWROK.
7:4 RO Reserved
0h
3:0 RW/L Thermometer Mode Enable and Rate (TE): If analog thermal
0h sensor mode is not enabled by setting these bits to 0000b, these bits
enable the thermometer mode functions and set the Thermometer
controller rate.
166 Datasheet
DRAM Controller Registers (D0:F0)
Note: The same legacy thermal sensor design in prior (G)MCHs has
been used in this design. However, the thermal sensor logic
runs in a memory command clock domain that is ½ the
frequency of the memory clock used in prior designs. Hence
the period counted for the thermal sensor settling time has
doubled for the same settings, compared to prior (G)MCHs.
Thus the thermal sensor programming should be updated to
maintain the same thermometer rate count as in prior
(G)MCHs.
NOTE: The settling time for DAC and Thermal Diode is between 2 and
5 us. To meet this requirement the SE value must be
programmed to be 5 us or more. Recommendation is to use:
“0010” setting for DDR 667/800 and “0011” setting for DDR
1066.
Datasheet 167
DRAM Controller Registers (D0:F0)
This read only register provides trip point and other status of the thermal sensor. All
bits in this register are reset to their defaults by CL_PWROK.
3:2 RO Reserved
00b
0 RO Direct Hot Comparator Read (DHCR): This bit reads the output of
0b the Hot comparator directly, without latching via the Thermometer
mode circuit. Used for testing.
168 Datasheet
DRAM Controller Registers (D0:F0)
This register :
• Sets the target values for the trip points in thermometer mode. See also
TST[Direct DAC Connect Test Enable].
• Reports the relative thermal sensor temperature
TR and HTPS can both vary between 0 and 255. But RELT will be
clipped between ±127 to keep it an 8 bit number.
23:16 RW Aux0 Trip point setting (A0TPS): Sets the target for the Aux0 trip
00h point.
15:8 RW/L Hot Trip Point Setting (HTPS): Sets the target value for the Hot
00h trip point.
7:0 RW/L Catastrophic Trip Point Setting (CTPS): Sets the target for the
00h Catastrophic trip point. See also TST[Direct DAC Connect Test
Enable].
Datasheet 169
DRAM Controller Registers (D0:F0)
Bit 7: reset to its default by PLTRST#. Bits 6:0 reset to their defaults by CL_PWROK.
7 RW/L/K Lock Bit for Catastrophic (LBC): This bit, when written to a 1, locks
0b the Catastrophic programming interface, including bits 7:0 of this
register and bits 15:0 of TSTTP, bits 1,7 of TSC 1, bits 3:0 of TSC 2,
bits 4:0 of TSC 3, and bits 0,7 of TST. This bit may only be set to a 0
by a hardware reset (PLTRST#). Writing a 0 to this bit has no effect.
6:0 RW/L Calibration Offset (CO): This field contains the current calibration
00h offset for the Thermal Sensor DAC inputs. The calibration offset is a
twos complement signed number which is added to the temperature
counter value to help generate the final value going to the thermal
sensor DAC.
Once this register has been overwritten by software, the values of the
TCO fuses can be read using the Therm3 register.
While this is a seven-bit field, the 7th bit is sign extended to 9 bits for
TCO operation. The range of 00h to 3Fh corresponds to 0 0000 0000 to
0 0011 1111. The range of 41h to 7Fh corresponds to 1 1100 001 (i.e.,
negative 3Fh) to 1 1111 1111 (i.e., negative 1), respectively.
170 Datasheet
DRAM Controller Registers (D0:F0)
Datasheet 171
DRAM Controller Registers (D0:F0)
This register is used to report which specific error condition resulted in the dev. 0 fn. 0
ERRSTS[Thermal Sensor event for SMI/SCI/SERR] or memory mapped IIR Thermal
Event. Software can examine the current state of the thermal zones by examining the
TSS. Software can distinguish internal or external Trip Event by examining EXTTSCS.
15:10 RO Reserved
00h
0 = No trip for this event Software must write a 1 to clear this status
bit.
6:5 RO Reserved
00b
172 Datasheet
DRAM Controller Registers (D0:F0)
0 = No trip for this event Software must write a 1 to clear this status
bit.
0 = No trip for this event Software must write a 1 to clear this status
bit.
0 = No trip for this event Software must write a 1 to clear this status
bit.
1:0 RO Reserved
00b
Datasheet 173
DRAM Controller Registers (D0:F0)
This register selects specific errors to generate a SMI DMI special cycle, as enabled by
the Device 0 SMI Error Command Register [SMI on (G)MCH Thermal Sensor Trip]. The
SMI must not be enabled at the same time as the SERR/SCI for the thermal sensor
event.
7:3 RO Reserved
00h
174 Datasheet
DRAM Controller Registers (D0:F0)
31:9 RO Reserved
000000h
8 RWC/S Warm Reset Occurred (WRO): Set by the PMunit whenever a Warm
0b Reset is received, and cleared by PWROK=0.
BIOS Requirement: BIOS can check and clear this bit whenever
executing POST code. This way BIOS knows that if the bit is set, then
the PMSTS bits [1:0] must also be set, and if not BIOS needs to
power-cycle the platform.
7:2 RO Reserved
00h
Datasheet 175
DRAM Controller Registers (D0:F0)
5.3 EPBAR
Table 5-4. EPBAR Register Address Map
This register provides information about the root complex element containing this Link
Declaration Capability.
31:24 RO Port Number (PN): This field specifies the port number associated
00h with this element with respect to the component that contains this
element. A value of 00h indicates to configuration software that this is
the default Express port.
23:16 RWO Component ID (CID): This field indicates identifies the physical
00h component that contains this Root Complex Element.
15:8 RO Number of Link Entries (NLE): This field indicates the number of
0sh link entries following the Element Self Description. This field reports 2
(one each for PEG and DMI).
7:4 RO Reserved
0h
3:0 RO Element Type (ET): This field indicates the type of the Root
1h Complex Element. Value of 1 h represents a port to system memory.
176 Datasheet
DRAM Controller Registers (D0:F0)
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
31:24 RO Target Port Number (TPN): Specifies the port number associated
01h with the element targeted by this link entry (DMI). The target port
number is with respect to the component that contains this element as
specified by the target component ID.
23:16 RWO Target Component ID (TCID): This field indicates the physical or
00h logical component that is targeted by this link entry.
BIOS Requirement: Must be initialized according to guidelines in the
PCI Express* Isochronous/Virtual Channel Support Hardware
Programming Specification (HPS).
15:2 RO Reserved
0000h
1 RO Link Type (LTYP): This field indicates that the link points to memory-
0b mapped space (for RCRB). The link address specifies the 64-bit base
address of the target RCRB.
0 RWO Link Valid (LV):
0b 0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
63:36 RO Reserved
0s
35:12 RWO Link Address (LA): This field contains the memory mapped base
0s address of the RCRB that is the target element (DMI) for this link
entry.
11:0 RO Reserved
0s
Datasheet 177
DRAM Controller Registers (D0:F0)
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
31:24 RO Target Port Number (TPN): This field specifies the port number
02h associated with the element targeted by this link entry (PEG). The
target port number is with respect to the component that contains
this element as specified by the target component ID.
23:16 RWO Target Component ID (TCID): This field indicates the physical or
00h logical component that is targeted by this link entry. A value of 0 is
reserved. Component IDs start at 1. This value is a mirror of the
value in the Component ID field of all elements in this component.
15:2 RO Reserved
0s
1 RO Link Type (LTYP): This field indicates that the link points to
1b configuration space of the integrated device which controls the x16
root port.
178 Datasheet
DRAM Controller Registers (D0:F0)
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
63:28 RO Reserved for Configuration Space Base Address (): Not required if
0s root complex has only one configuration space.
19:15 RO Device Number (DEVN): Target for this link is PCI Express x16 port
00001b (Device 1).
11:0 RO Reserved
0s
Datasheet 179
PCI Express* Registers (D1:F0)
Warning: When reading the PCI Express "conceptual" registers such as this, you may not get a
valid value unless the register value is stable.
Unless explicitly documented as Reserved and Zero, all bits marked as reserved are
part of the Reserved and Preserved type, which have historically been the typical
definition for Reserved.
Note: Most (if not all) control bits in this device cannot be modified unless the link is down.
Software is required to first Disable the link, then program the registers, and then re-
enable the link (which will cause a full-retrain with the new settings).
180 Datasheet
PCI Express* Registers (D1:F0)
Datasheet 181
PCI Express* Registers (D1:F0)
182 Datasheet
PCI Express* Registers (D1:F0)
This register combined with the Device Identification register uniquely identify any PCI
device.
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
Datasheet 183
PCI Express* Registers (D1:F0)
15:11 RO Reserved
00h
0 = Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.
184 Datasheet
PCI Express* Registers (D1:F0)
2 RW Bus Master Enable (BME): This bit controls the ability of the PEG
0b port to forward Memory and IO Read/Write Requests in the upstream
direction. This bit does not affect forwarding of Completions from the
primary interface to the secondary interface.
Datasheet 185
PCI Express* Registers (D1:F0)
14 RWC Signaled System Error (SSE): This bit is set when this Device
0b sends an SERR due to detecting an ERR_FATAL or ERR_NONFATAL
condition and the SERR Enable bit in the Command register is 1.
Both received (if enabled by BCTRL1[1]) and internally detected
error messages affect this field.
This bit can only be set when the Parity Error Enable bit in the PCI
Command register is set.
6 RO Reserved
0b
186 Datasheet
PCI Express* Registers (D1:F0)
2:0 RO Reserved
000b
This register contains the revision number of the (G)MCH device 1. These bits are read
only and writes to this register have no effect.
This register identifies the basic function of the device, a more specific sub-class, and
a register- specific programming interface.
23:16 RO Base Class Code (BCC): This field indicates the base class code for
06h this device. This code has the value 06h, indicating a Bridge device.
15:8 RO Sub-Class Code (SUBCC): This field indicates the sub-class code for
04h this device. The code is 04h indicating a PCI to PCI Bridge.
Datasheet 187
PCI Express* Registers (D1:F0)
This register identifies the header layout of the configuration space. No physical
register exists at this location.
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
bus #0.
188 Datasheet
PCI Express* Registers (D1:F0)
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge (i.e., to PCI Express-G). This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express-G. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express-G.
Datasheet 189
PCI Express* Registers (D1:F0)
This register controls the processor to PCI Express-G I/O access routing based on the
following formula:
Only the upper 4 bits are programmable. For the purpose of address decode, address
bits A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will
be aligned to a 4 KB boundary.
3:0 RO Reserved
0h
This register controls the processor to PCI Express-G I/O access routing based on the
following formula:
Only the upper 4 bits are programmable. For the purpose of address decode, address
bits A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range
will be at the top of a 4 KB aligned address block.
3:0 RO Reserved
0h
190 Datasheet
PCI Express* Registers (D1:F0)
SSTS1 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (i.e., PCI Express side) of the "virtual" PCI-PCI bridge
embedded within (G)MCH.
15 RWC Detected Parity Error (DPE): This bit is set by the Secondary Side
0b for a Type 1 Configuration Space header device whenever it receives a
Poisoned TLP, regardless of the state of the Parity Error Response
Enable bit in the Bridge Control Register.
14 RWC Received System Error (RSE): This bit is set when the Secondary
0b Side for a Type 1 configuration space header device receives an
ERR_FATAL or ERR_NONFATAL.
13 RWC Received Master Abort (RMA): This bit is set when the Secondary
0b Side for Type 1 Configuration Space Header Device (for requests
initiated by the Type 1 Header Device itself) receives a Completion
with Unsupported Request Completion Status.
12 RWC Received Target Abort (RTA): This bit is set when the Secondary
0b Side for Type 1 Configuration Space Header Device (for requests
initiated by the Type 1 Header Device itself) receives a Completion
with Completer Abort Completion Status.
8 RWC Master Data Parity Error (SMDPE): When set, this bit indicates that
0b the (G)MCH received across the link (upstream) a Read Data
Completion Poisoned TLP (EP=1). This bit can only be set when the
Parity Error Enable bit in the Bridge Control register is set.
6 RO Reserved
0b
4:0 RO Reserved
00h
Datasheet 191
PCI Express* Registers (D1:F0)
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are
read-only and return zeroes when read. This register must be initialized by the
configuration software. For the purpose of address decode, address bits A[19:0] are
assumed to be 0. Thus, the bottom of the defined memory address range will be
aligned to a 1 MB boundary.
3:0 RO Reserved
0h
192 Datasheet
PCI Express* Registers (D1:F0)
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are
read-only and return zeroes when read. This register must be initialized by the
configuration software. For the purpose of address decode, address bits A[19:0] are
assumed to be FFFFFh. Thus, the top of the defined memory address range will be at
the top of a 1MB aligned memory block. NOTE: Memory range covered by MBASE and
MLIMIT registers are used to map non-prefetchable PCI Express address ranges
(typically where control/status memory-mapped I/O data structures of the graphics
controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address
ranges (typically graphics local memory). This segregation allows application of USWC
space attribute to be performed in a true plug-and-play manner to the prefetchable
address range for improved processor - PCI Express memory access performance.
Note also that configuration software is responsible for programming all address range
registers (prefetchable, non-prefetchable) with the values that provide exclusive
address ranges i.e. prevent overlap with each other and/or with the ranges covered
with the main memory. There is no provision in the (G)MCH hardware to enforce
prevention of overlap and operations of the system in the case of overlap are not
ensured.
3:0 RO Reserved
0h
Datasheet 193
PCI Express* Registers (D1:F0)
This register in conjunction with the corresponding Upper Base Address register
controls the processor-to-PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤
PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined
memory address range will be aligned to a 1 MB boundary.
3:0 RO 64-bit Address Support: This field indicates that the upper 32 bits of
1h the prefetchable memory region base address are contained in the
Prefetchable Memory base Upper Address register at 28h.
194 Datasheet
PCI Express* Registers (D1:F0)
This register in conjunction with the corresponding Upper Limit Address register
controls the processor-to-PCI Express prefetchable memory access routing based on
the following formula:
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1MB aligned memory block. Note that
prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e. prefetchable) from the processor perspective.
3:0 RO 64-bit Address Support: This field indicates that the upper 32 bits of
1h the prefetchable memory region limit address are contained in the
Prefetchable Memory Base Limit Address register at 2Ch
Datasheet 195
PCI Express* Registers (D1:F0)
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Base Address register
controls the processor-to-PCI Express prefetchable memory access routing based on
the following formula:
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined
memory address range will be aligned to a 1 MB boundary.
196 Datasheet
PCI Express* Registers (D1:F0)
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40- bit address. The lower 8 bits of the Upper Limit Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1MB aligned memory block.
Datasheet 197
PCI Express* Registers (D1:F0)
7:0 RO First Capability (CAPPTR1): The first capability in the list is the
88h Subsystem ID and Subsystem Vendor ID Capability.
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
7:0 RO Interrupt Pin (INTPIN): As a single function device, the PCI Express
01h device specifies INTA as its interrupt pin. 01h=INTA.
198 Datasheet
PCI Express* Registers (D1:F0)
This register provides extensions to the PCICMD1 register that are specific to PCI-to-
PCI bridges. The BCTRL provides additional control for the secondary interface (i.e.,
PCI Express) as well as some bits that affect the overall behavior of the "virtual" Host-
PCI Express bridge in the (G)MCH (e.g., VGA compatible address ranges mapping).
15:12 RO Reserved
0h
6 RW Secondary Bus Reset (SRESET): Setting this bit triggers a hot reset
0b on the corresponding PCI Express Port. This will force the LTSSM to
transition to the Hot Reset state (via Recovery) from L0, L0s, or L1
states.
Datasheet 199
PCI Express* Registers (D1:F0)
200 Datasheet
PCI Express* Registers (D1:F0)
31:27 RO PME Support (PMES): This field indicates the power states in which
19h this device may indicate PME wake via PCI Express messaging. D0,
D3hot & D3cold. This device is not required to do anything to support
D3hot & D3cold, it simply must report that those states are
supported. Refer to the PCI Power Management 1.1 specification for
encoding explanation and other power management details.
18:16 RO PCI PM CAP Version (PCIPMCV): A value of 011b indicates that this
011b function complies with revision 1.2 of the PCI Power Management
Interface Specification.
7:0 RO Capability ID (CID): Value of 01h identifies this linked list item
01h (capability structure) as being for PCI Power Management registers.
Datasheet 201
PCI Express* Registers (D1:F0)
202 Datasheet
PCI Express* Registers (D1:F0)
31:16 RO Reserved
0000h
15:8 RO Pointer to Next Capability (PNC): This contains a pointer to the
80h next item in the capabilities list which is the PCI Power Management
capability.
7:0 RO Capability ID (CID): Value of 0Dh identifies this linked list item
0Dh (capability structure) as being for SSID/SSVID registers in a PCI-to-PCI
Bridge.
System BIOS can be used as the mechanism for loading the SSID/SVID values. These
values must be preserved through power management transitions and a hardware
reset.
Datasheet 203
PCI Express* Registers (D1:F0)
When a device supports MSI it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address.
7:0 RO Capability ID (CID): Value of 05h identifies this linked list item
05h (capability structure) as being for MSI registers.
15:8 RO Reserved
00h
7 RO 64-bit Address Capable (64AC): Hardwired to 0 to indicate that the
0b function does not implement the upper 32 bits of the Message Address
register and is incapable of generating a 64-bit memory address.
6:4 RW Multiple Message Enable (MME): System software programs this
000b field to indicate the actual number of messages allocated to this
device. This number will be equal to or less than the number actually
requested.
3:1 RO Multiple Message Capable (MMC): System software reads this field
000b to determine the number of messages being requested by this device.
204 Datasheet
PCI Express* Registers (D1:F0)
15:0 RW Message Data (MD): Base message data pattern assigned by system
0000h software and used to handle an MSI from the device.
Datasheet 205
PCI Express* Registers (D1:F0)
15:14 RO Reserved
00b
206 Datasheet
PCI Express* Registers (D1:F0)
15 RO Role Based Error Reporting (RBER): This bit indicates that this
1b device implements the functionality defined in the Error Reporting ECN
as required by the PCI Express 1.1 specification.
2:0 RO Max Payload Size (MPS): Hardwired to indicate 128B max supported
000b payload for Transaction Layer Packets (TLP).
Datasheet 207
PCI Express* Registers (D1:F0)
This register provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
15:8 RO Reserved
000h
208 Datasheet
PCI Express* Registers (D1:F0)
This register reflects status corresponding to controls in the Device Control register.
The error reporting bits are in reference to errors detected by this device, not errors
messages received across the link.
15:6 RO Reserved and Zero: For future R/WC/S implementations; software must
000h use 0 for writes to bits.
4 RO Reserved
0b
Datasheet 209
PCI Express* Registers (D1:F0)
31:24 RO Port Number (PN): This field indicates the PCI Express port number
02h for the given PCI Express link. Matches the value in Element Self
Description[31:24].
23:21 RO Reserved
000b
For Upstream Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
For Upstream Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
210 Datasheet
PCI Express* Registers (D1:F0)
17:15 RWO L1 Exit Latency (L1ELAT): This field indicates the length of time this
010b Port requires to complete the transition from L1 to L0. The value 010
b indicates the range of 2 us to less than 4 us.
Both bytes of this register that contain a portion of this field must be
written simultaneously in order to prevent an intermediate (and
undesired) value from ever existing.
14:12 RO L0s Exit Latency (L0SELAT): Indicates the length of time this Port
100b requires to complete the transition from L0s to L0.
9:4 RO Max Link Width (MLW): This field indicates the maximum number of
10h lanes supported for this link.
Datasheet 211
PCI Express* Registers (D1:F0)
15:9 RO Reserved
0000000b
212 Datasheet
PCI Express* Registers (D1:F0)
4 RW Link Disable (LD): Writes to this bit are immediately reflected in the
0b value read from the bit, regardless of actual Link state.
0 = Normal operation
1 = Link is disabled. Forces the LTSSM to transition to the Disabled
state (via Recovery) from L0, L0s, or L1 states. Link retraining
happens automatically on 0 to 1 transition, just like when coming
out of reset.
3 RO Read Completion Boundary (RCB): Hardwired to 0 to indicate
0b 64 byte.
1:0 RW Active State PM (ASPM): This field controls the level of active state
00b power management supported on the given link.
00 = Disabled
10 = Reserved
Datasheet 213
PCI Express* Registers (D1:F0)
1 = The device uses the same physical reference clock that the
platform provides on the connector.
11 RO Link Training (LTRN): This bit indicates that the Physical Layer
0b LTSSM is in the Configuration or Recovery state, or that 1b was
written to the Retrain Link bit but Link training has not yet begun.
Hardware clears this bit when the LTSSM exits the
Configuration/Recovery state once Link training is complete.
9:4 RO Negotiated Width (NW): Indicates negotiated link width. This field
00h is valid only when the link is in the L0, L0s, or L1 states (after link
width negotiation is successfully completed).
00h = Reserved
01h = X1
02h = Reserved
04h = Reserved
08h = Reserved
10h = X16
214 Datasheet
PCI Express* Registers (D1:F0)
31:19 RWO Physical Slot Number (PSN): Indicates the physical slot number
0000h attached to this Port.
16:15 RWO Slot Power Limit Scale (SPLS): This field specifies the scale used
00b for the Slot Power Limit Value.
00 = 1.0x
01 = 0.1x
10 = 0.01x
11 = 0.001x
14:7 RWO Slot Power Limit Value (SPLV): In combination with the Slot Power
00h Limit Scale value, specifies the upper limit on power supplied by slot.
Power limit (in Watts) is calculated by multiplying the value in this
field by the value in the Slot Power Limit Scale field.
Datasheet 215
PCI Express* Registers (D1:F0)
PCI Express Slot related registers allow for the support of Hot Plug.
15:13 RO Reserved
000b
216 Datasheet
PCI Express* Registers (D1:F0)
Depending on the form factor, the power is turned on/off either to the
slot or within the adapter. Note that in some cases the power
controller may autonomously remove slot power or not respond to a
power-up request based on a detected fault condition, independent of
the Power Controller Control setting.
0 = Power On
1 = Power Off
00 = Reserved
01 = On
10 = Blink
11 = Off
Datasheet 217
PCI Express* Registers (D1:F0)
0 = Disable (default)
0 = Disable (default)
218 Datasheet
PCI Express* Registers (D1:F0)
PCI Express Slot related registers allow for the support of Hot Plug.
0 = Slot Empty
5 RO Reserved
0b
3 RWC Detect Changed (PDC): This bit is set when the value reported in
0b Presence Detect State is changed.
Datasheet 219
PCI Express* Registers (D1:F0)
This register allows control of PCI Express Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
15:4 RO Reserved
000h
2 RW System Error on Fatal Error Enable (SEFEE): This bit controls the
0b Root Complex's response to fatal errors.
220 Datasheet
PCI Express* Registers (D1:F0)
This register provides information about PCI Express Root Complex specific
parameters.
31:18 RO Reserved
0000h
15:0 RO PME Requestor ID (PMERID): This field indicates the PCI requestor
0000h ID of the last PME requestor.
Datasheet 221
PCI Express* Registers (D1:F0)
This register controls functionality that is needed by Legacy (non-PCI Express aware)
operating systems during run time.
31:3 RO Reserved
00000000h
222 Datasheet
PCI Express* Registers (D1:F0)
This register indicates PCI Express device Virtual Channel capabilities. Extended
capability structures for PCI Express devices are located in PCI Express extended
configuration space and have different field definitions than standard PCI capability
structures.
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
31:7 RO Reserved
0000000h
6:4 RO Low Priority Extended VC Count (LPEVCC): This field indicates the
000b number of (extended) Virtual Channels in addition to the default VC
belonging to the low-priority VC (LPVC) group that has the lowest
priority with respect to other VC resources in a strict-priority VC
Arbitration.
The value of 0 in this field implies strict VC arbitration.
3 RO Reserved
0b
2:0 RO Extended VC Count (EVCC): This field indicates the number of
000b (extended) Virtual Channels in addition to the default VC supported by
the device.
Datasheet 223
PCI Express* Registers (D1:F0)
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
15:4 RO Reserved
000h
0 RO Reserved
0b
224 Datasheet
PCI Express* Registers (D1:F0)
31:16 RO Reserved
0000h
1 = Any transaction without the No Snoop bit set within the TLP
header will be rejected as an Unsupported Request.
14:0 RO Reserved
0000h
Datasheet 225
PCI Express* Registers (D1:F0)
This register controls the resources associated with PCI Express Virtual Channel 0.
31 RO VC0 Enable (VC0E): For VC0, this is hardwired to 1 and read only as
1b VC0 can never be disabled.
30:27 RO Reserved
0h
26:24 RO VC0 ID (VC0ID): Assigns a VC ID to the VC resource. For VC0, this
000b is hardwired to 0 and read only.
23:8 RO Reserved
0000h
7:1 RW TC/VC0 Map (TCVC0M): This field indicates the TCs (Traffic
7Fh Classes) that are mapped to the VC resource. Bit locations within this
field correspond to TC values. For example, when bit 7 is set in this
field, TC7 is mapped to this VC resource. When more than one bit in
this field is set, it indicates that multiple TCs are mapped to the VC
resource. In order to remove one or more TCs from the TC/VC Map of
an enabled VC, software must ensure that no new or outstanding
transactions with the TC labels are targeted at the given Link.
0 RO TC0/VC0 Map (TC0VC0M): Traffic Class 0 is always routed to VC0.
1b
226 Datasheet
PCI Express* Registers (D1:F0)
15:2 RO Reserved
0000h
1 RO VC0 Negotiation Pending (VC0NP):
1b 0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization
or disabling).
This bit indicates the status of the process of Flow Control initialization.
It is set by default on Reset, as well as whenever the corresponding
Virtual Channel is Disabled or the Link is in the DL_Down state. It is
cleared when the link successfully exits the FC_INIT2 state.
Before using a Virtual Channel, software must check whether the VC
Negotiation Pending fields for that Virtual Channel are cleared in both
Components on a Link.
0 RO Reserved
0b
Datasheet 227
PCI Express* Registers (D1:F0)
This capability declares links from this element (PEG) to other elements of the root
complex component to which it belongs. See PCI Express specification for
link/topology declaration requirements.
31:20 RO Pointer to Next Capability (PNC): This is the last capability in the
000h PCI Express extended capabilities list
19:16 RO Link Declaration Capability Version (LDCV): Hardwired to 1 to
1h indicate compliances with the 1.1 version of the PCI Express
specification.
15:0 RO Extended Capability ID (ECID): Value of 0005h identifies this linked
0005h list item (capability structure) as being for PCI Express Link Declaration
Capability.
This register provides information about the root complex element containing this Link
Declaration Capability.
31:24 RO Port Number (PN): This field specifies the port number associated
02h with this element with respect to the component that contains this
element. This port number value is utilized by the Express port of the
component to provide arbitration to this Root Complex Element.
23:16 RWO Component ID (CID): This field identifies the physical component
00h that contains this Root Complex Element.
15:8 RO Number of Link Entries (NLE): This field indicates the number of
01h link entries following the Element Self Description. This field reports 1
(to Express port only as we don't report any peer-to-peer capabilities
in our topology).
7:4 RO Reserved
0h
3:0 RO Element Type (ET): This field indicates the type of the Root Complex
0h Element. Value of 0h represents a root port.
228 Datasheet
PCI Express* Registers (D1:F0)
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
31:24 RO Target Port Number (TPN): This field specifies the port number
00h associated with the element targeted by this link entry (Express Port).
The target port number is with respect to the component that contains
this element as specified by the target component ID.
23:16 RWO Target Component ID (TCID): This field identifies the physical or
00h logical component that is targeted by this link entry.
15:2 RO Reserved
0000h
1 RO Link Type (LTYP): This field indicates that the link points to memory-
0b mapped space (for RCRB). The link address specifies the 64-bit base
address of the target RCRB.
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
63:32 RO Reserved
00000000h
31:12 RWO Link Address (LA): This field contains the memory-mapped base
00000h address of the RCRB that is the target element (Express Port) for this
link entry.
11:0 RO Reserved
000h
Datasheet 229
PCI Express* Registers (D1:F0)
This register provides PCI Express status reporting that is required by the PCI Express
specification.
63:60 RO Reserved
0h
59:48 RO Next Transmit Sequence Number (NTSN): This field indicates the
000h value of the NXT_TRANS_SEQ counter. This counter represents the
transmit Sequence number to be applied to the next TLP to be
transmitted onto the Link for the first time.
47:44 RO Reserved
0h
43:32 RO Next Packet Sequence Number (NPSN): This field indicates the
000h packet sequence number to be applied to the next TLP to be
transmitted or re-transmitted onto the Link.
31:28 RO Reserved
0h
15:12 RO Reserved
0h
230 Datasheet
PCI Express* Registers (D1:F0)
Datasheet 231
Direct Memory Interface (DMI) Registers
232 Datasheet
Direct Memory Interface (DMI) Registers
31:20 RO Pointer to Next Capability (PNC): This field contains the offset to
040h the next PCI Express capability structure in the linked list of
capabilities (Link Declaration Capability).
Datasheet 233
Direct Memory Interface (DMI) Registers
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
31:7 RO Reserved
0000000h
6:4 RO Low Priority Extended VC Count (LPEVCC): This field indicates the
000b number of (extended) Virtual Channels in addition to the default VC
belonging to the low-priority VC (LPVC) group that has the lowest
priority with respect to other VC resources in a strict-priority VC
Arbitration.
3 RO Reserved
0b
2:0 RWO Extended VC Count (EVCC): This field indicates the number of
001b (extended) Virtual Channels in addition to the default VC supported by
the device.
31:0 RO Reserved
00000000h
234 Datasheet
Direct Memory Interface (DMI) Registers
15:4 RO Reserved
000h
0 RO Reserved
0b
31:16 RO Reserved
00000h
1 = Any transaction without the No Snoop bit set within the TLP
header will be rejected as an Unsupported Request.
14:8 RO Reserved
00h
7:0 RO Port Arbitration Capability (PAC): Having only bit 0 set indicates
01h that the only supported arbitration scheme for this VC is non-
configurable hardware-fixed.
Datasheet 235
Direct Memory Interface (DMI) Registers
This register controls the resources associated with PCI Express Virtual Channel 0.
30:27 RO Reserved
0h
23:20 RO Reserved
0h
19:17 RW Port Arbitration Select (PAS): This field configures the VC resource
000b to provide a particular Port Arbitration service. Valid value for this field
is a number corresponding to one of the asserted bits in the Port
Arbitration Capability field of the VC resource. Because only bit 0 of
that field is asserted.
16:8 RO Reserved
000h
For example, when bit 7 is set in this field, TC7 is mapped to this VC
resource. When more than one bit in this field is set, it indicates that
multiple TCs are mapped to the VC resource. In order to remove one
or more TCs from the TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions with the TC labels are
targeted at the given Link.
236 Datasheet
Direct Memory Interface (DMI) Registers
15:2 RO Reserved.
0000h
31:16 RO Reserved
00000h
15 RO Reject Snoop Transactions (REJSNPT):
1b 0 = Transactions with or without the No Snoop bit set within the TLP
header are allowed on this VC.
1 = Any transaction without the No Snoop bit set within the TLP
header will be rejected as an Unsupported Request.
14:8 RO Reserved
00h
7:0 RO Port Arbitration Capability (PAC): Having only bit 0 set indicates
01h that the only supported arbitration scheme for this VC is non-
configurable hardware-fixed.
Datasheet 237
Direct Memory Interface (DMI) Registers
This register controls the resources associated with PCI Express Virtual Channel 1.
30:27 RO Reserved
0h
23:20 RO Reserved
0h
19:17 RW Port Arbitration Select (PAS): This field configures the VC resource
000b to provide a particular Port Arbitration service. Valid value for this field
is a number corresponding to one of the asserted bits in the Port
Arbitration Capability field of the VC resource.
16:8 RO Reserved
000h
For example, when bit 7 is set in this field, TC7 is mapped to this VC
resource. When more than one bit in this field is set, it indicates that
multiple TCs are mapped to the VC resource. In order to remove one
or more TCs from the TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions with the TC labels are
targeted at the given Link.
238 Datasheet
Direct Memory Interface (DMI) Registers
15:2 RO Reserved
0000h
0 RO Reserved
0b
31:18 RO Reserved
0000h
17:15 RWO L1 Exit Latency (L1SELAT): This field indicates the length of time
010b this Port requires to complete the transition from L1 to L0.
010b = 2 us to less than 4 us.
14:12 RWO L0s Exit Latency (L0SELAT): This field indicates the length of time
010b this Port requires to complete the transition from L0s to L0.
010 = 128 ns to less than 256 ns
11:10 RO Active State Link PM Support (ASLPMS): L0s & L1 entry
11b supported.
9:4 RO Max Link Width (MLW): This field indicates the maximum number
04h of lanes supported for this link.
3:0 RO Max Link Speed (MLS): Hardwired to indicate 2.5 Gb/s.
1h
Datasheet 239
Direct Memory Interface (DMI) Registers
15:8 RO Reserved
00h
7 RW Extended Synch (EXTSYNC):
0b 0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when exiting
the L0s state and when in the Recovery state.
6:3 RO Reserved
0h
2 RW Far-End Digital Loopback (FEDLB):
0b
1:0 RW Active State Power Management Support (ASPMS): This field
00b controls the level of active state power management supported on the
given link.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s and L1 Entry Supported
240 Datasheet
Direct Memory Interface (DMI) Registers
15:10 RO Reserved and Zero for future R/WC/S implementations. Software must
00h use 0 for writes to these bits.
Datasheet 241
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
Function 0 can be VGA compatible or not, this is selected through bit 1 of GGC register
(Device 0, offset 52h).
Note: The following sections describe Device 2 PCI configuration registers only.
242 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register combined with the Device Identification register uniquely identifies any
PCI device.
Datasheet 243
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
15:11 RO Reserved
00h
244 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
2 RW Bus Master Enable (BME): This bit controls the IGD's response to
0b bus master accesses.
1 RW Memory Access Enable (MAE): This bit controls the IGD's response
0b to memory space accesses.
0 = Disable.
1 = Enable.
0 RW I/O Access Enable (IOAE): This bit controls the IGD's response to
0b I/O space accesses.
0 = Disable.
1 = Enable.
Datasheet 245
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant
master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL#
timing that has been set by the IGD.
15 RO Detected Parity Error (DPE): Since the IGD does not detect parity,
0b this bit is always hardwired to 0.
10:9 RO DEVSEL Timing (DEVT): N/A. These bits are hardwired to "00".
00b
8 RO Master Data Parity Error Detected (DPD): Since Parity Error
0b Response is hardwired to disabled (and the IGD does not do any
parity detection), this bit is hardwired to 0.
7 RO Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast
1b back-to-back when the transactions are not to the same agent.
2:0 RO Reserved
000b
246 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register contains the revision number for Device #2 Functions 0 and 1.
This register contains the device programming interface information related to the
Sub-Class Code and Base Class Code definition for the IGD. This register also contains
the Base Class Code and the function sub-class in relation to the Base Class Code.
23:16 RO Base Class Code (BCC): This is an 8-bit value that indicates the
03h base class code for the GMCH. This code has the value 03h, indicating
a Display Controller.
Datasheet 247
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
7:0 RO Cache Line Size (CLS): This field is hardwired to 0s. The IGD as a
00h PCI compliant master does not use the Memory Write and Invalidate
command and, in general, does not perform operations based on
cache line size.
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
248 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
31:29 RW Memory Base Address (MBA): Set by the OS, these bits correspond
000b to address signals 31:29.
28 RW/L 512MB Address Mask (512ADMSK): This Bit is either part of the
0b Memory Base Address (R/W) or part of the Address Mask (RO),
depending on the value of MSAC[1:0]. See MSAC (D2:F0, offset 62h)
for details.
27 RW/L 256 MB Address Mask (256ADMSK): This bit is either part of the
0b Memory Base Address (R/W) or part of the Address Mask (RO),
depending on the value of MSAC[1:0]. See MSAC (D2:F0, offset 62h)
for details.
26:4 RO Address Mask (ADM): Hardwired to 0s to indicate at least 128 MB
000000h address range.
3 RO Prefetchable Memory (PREFMEM): Hardwired to 1 to enable
1b prefetching.
2:1 RO Memory Type (MEMTYP): Hardwired to 0 to indicate 32-bit address.
00b
0 RO Memory/IO Space (MIOS): Hardwired to 0 to indicate memory
0b space.
Datasheet 249
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register provides the Base offset of the I/O registers within Device 2. Bits 15:3
are programmable allowing the I/O Base to be located anywhere in 16 bit I/O Address
Space. Bits 2:1 are fixed and return zero; bit 0 is hardwired to a one indicating that 8
bytes of I/O space are decoded. Access to the 8Bs of I/O space is allowed in PM state
D0 when IO Enable (PCICMD bit 0) set. Access is disallowed in PM states D1–D3 or if
I/O Enable is clear or if Device 2 is turned off or if Internal graphics is disabled thru
the fuse or fuse override mechanisms.
Note that access to this IO BAR is independent of VGA functionality within Device 2.
Also note that this mechanism is available only through function 0 of Device 2 and is
not duplicated in function 1.
If accesses to this IO bar is allowed then the GMCH claims all 8, 16 or 32 bit I/O
cycles from the processor that falls within the 8B claimed.
31:16 RO Reserved
0000h
15:3 RW IO Base Address (IOBASE): Set by the OS, these bits correspond
0000h to address signals 15:3.
15:0 RWO Subsystem Vendor ID (SUBVID): This value is used to identify the
0000h vendor of the subsystem. This register should be programmed by BIOS
during boot-up. Once written, this register becomes Read Only. This
register can only be cleared by a Reset.
250 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s.
Datasheet 251
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
7:0 RO Capabilities Pointer Value (CPV): This field contains an offset into
90h the function's PCI Configuration Space for the first item in the New
Capabilities Linked List, the MSI Capabilities ID registers at address
90h or the Power Management capability at D0h.
01h = INTA#.
252 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
7:0 RO Minimum Grant Value (MGV): The IGD does not burst as a PCI
00h compliant master.
Datasheet 253
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register control of bits in this register are only required for customer visible SKU
differentiation.
135:28 RO Reserved
0s
27:24 RO CAPID Version (CAPIDV): This field has the value 0001b to
1h identify the first revision of the CAPID register definition.
23:16 RO CAPID Length (CAPIDL): This field has the value 0bh to indicate
0bh the structure length (11 bytes).
7:0 RO Capability Identifier (CAP_ID): This field has the value 1001b to
09h identify the CAP_ID assigned by the PCI SIG for vendor dependent
capability pointers.
254 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
15:10 RO Reserved
00h
9:8 RO GTT Graphics Memory Size (GGMS): This field is used to select the
0h amount of Main Memory that is pre-allocated to support the Internal
Graphics Translation Table. The BIOS ensures that memory is pre-
allocated only when Internal graphics is enabled.
11 = Reserved
Note: This register is locked and becomes Read Only when the
D_LCK bit in the SMRAM register is set.
Datasheet 255
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
7:4 RO Graphics Mode Select (GMS): This field is used to select the
0011b amount of Main Memory that is pre-allocated to support the Internal
Graphics device in VGA (non-linear) and Native (linear) modes. The
BIOS ensures that memory is pre-allocated only when Internal
graphics is enabled.
Note: This register is locked and becomes Read Only when the
D_LCK bit in the
BIOS Requirement: BIOS must not set this field to 000 if IVD (bit 1
of this register) is 0.
3:0 RO Reserved
0000b
256 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register allows for enabling/disabling of PCI devices and functions that are within
the GMCH. The table below the bit definitions describes the behavior of all
combinations of transactions to devices controlled by this register. All the bits in this
register are Intel® TXT Lockable.
31:15 RO Reserved
00000h
13:10 RO Reserved
0b
9 RO EP Function 3 (D3F3EN):
1b
0 = Bus 0, Device 3, Function 3 is disabled and hidden
8 RO EP Function 2 (D3F2EN):
1b
0 = Bus 0, Device 3, Function 2 is disabled and hidden
7 RO EP Function 1 (D3F1EN):
1b
0 = Bus 0, Device 3, Function 1 is disabled and hidden
Datasheet 257
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
6 RO EP Function 0 (D3F0EN):
1b
0 = Bus 0, Device 3, Function 0 is disabled and hidden
5 RO Reserved
0b
2 RO Reserved
0b
258 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
31:0 RW Reserved
00000000h
31:20 RO Base of Stolen Memory (BSM): This register contains bits 31:20 of
078h the base address of stolen DRAM memory. The host interface
determines the base of Graphics Stolen memory by subtracting the
graphics stolen memory size from TOLUD. See Device 0 TOLUD for
more explanation.
19:0 RO Reserved
00000h
15:0 RW Reserved
0000h
Datasheet 259
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
System software can modify bits in this register, but the device is prohibited from
doing so. If the device writes the same message multiple times, only one of those
messages is ensured to be serviced. If all of them must be serviced, the device must
not generate the same message again until the driver services the earlier one.
15:8 RO Reserved
00h
7 RO 64 Bit Capable (64BCAP): Hardwired to 0 to indicate that the
0b function does not implement the upper 32 bits of the Message address
register and is incapable of generating a 64-bit memory address.
This may need to change in future implementations when addressable
system memory exceeds the 32b / 4 GB limit.
6:4 RW Multiple Message Enable (MME): System software programs this
000b field to indicate the actual number of messages allocated to this
device. This number will be equal to or less than the number actually
requested.
The encoding is the same as for the MMC field (Bits 3:1).
3:1 RO Multiple Message Capable (MMC): System Software reads this field
000b to determine the number of messages being requested by this device.
000 = 1
All of the following are reserved in this implementation
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = Reserved
111 = Reserved
0 RW MSI Enable (MSIEN): This bit controls the ability of this device to
0b generate MSIs.
260 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
Datasheet 261
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
7:4 RO Reserved
0h
3:2 RW Graphics Reset Domain (GRDOM):
00b 00 = Full Graphics Reset will be performed (both render and display
clock domain resets asserted
01 = Reserved (Invalid Programming)
10 = Reserved (Invalid Programming)
11 = Reserved (Invalid Programming)
1 RO Reserved
0b
0 RW Graphics Reset Enable (GR): Setting this bit asserts graphics-only
0b reset. The clock domains to be reset are determined by GRDOM.
Hardware resets this bit when the reset is complete. Setting this bit
without waiting for it to clear, is undefined behavior. Once this bit is
set to a 1, all GFX core MMIO registers are returned to power on
default state. All Ring buffer pointers are reset, command stream
fetches are dropped and ongoing render pipeline processing is halted,
state machines and State Variables returned to power on default state.
If the Display is reset, all display engines are halted (garbage on
screen). VGA memory is not available, Store DWords and interrupts
are not assured to be completed. Device 2 I/O registers are not
available.
When issuing the graphics reset, disable the cursor, display, and
overlay engines using the MMIO registers. Wait 1 us. Issue the
graphics reset by setting this bit to 1.
Device 2 Configuration registers continue to be available while graphics
reset is asserted.
This bit is hardware auto-clear.
262 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register is a Mirror of Function 0 with the same read/write attributes. The
hardware implements a single physical register common to both functions 0 and 1.
15:11 RO PME Support (PMES): This field indicates the power states in which
00h the IGD may assert PME#. Hardwired to 0 to indicate that the IGD
does not assert the PME# signal.
10 RO D2 Support (D2): The D2 power management state is not supported.
0b This bit is hardwired to 0.
9 RO D1 Support (D1): Hardwired to 0 to indicate that the D1 power
0b management state is not supported.
8:6 RO Reserved
000b
5 RO Device Specific Initialization (DSI): Hardwired to 1 to indicate that
1b special initialization of the IGD is required before generic class device
driver is to use it.
4 RO Reserved
0b
3 RO PME Clock (PMECLK): Hardwired to 0 to indicate IGD does not
0b support PME# generation.
2:0 RO Version (VER): Hardwired to 010b to indicate that there are 4 bytes
010b of power management registers implemented and that this device
complies with revision 1.1 of the PCI Power Management Interface
Specification.
Datasheet 263
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
15 RO PME Status (PMESTS): This bit is 0 to indicate that IGD does not
0b support PME# generation from D3 (cold).
14:13 RO Data Scale (DSCALE): The IGD does not support data register. This
00b bit always returns 00 when read, write operations have no effect.
12:9 RO Data Select (DSEL): The IGD does not support data register. This bit
0h always returns 0h when read, write operations have no effect.
7:2 RO Reserved
00h
1:0 RW Power State (PWRSTAT): This field indicates the current power state
00b of the IGD and can be used to set the IGD into a new power state. If
software attempts to write an unsupported state to this field, write
operation must complete normally on the bus, but the data is
discarded and no state change occurs. On a transition from D3 to D0
the graphics controller is optionally reset to initial values.
00 = D0 (Default)
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
264 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
As long as there is the potential that DVO port legacy drivers exist which expect this
register at this address, D2, F0 address E0h–E1h must be reserved for this register.
7:1 RW Software Flag (SWF): Used to indicate caller and SMI function
00h desired, as well as return result.
0 RW GMCH Software SMI Event (GSSMIE): When Set this bit will
0b trigger an SMI. Software must write a "0" to clear this bit.
Datasheet 265
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
266 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
Datasheet 267
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register, combined with the Device Identification register, uniquely identifies any
PCI device.
This register is unique in Function 1 (the Function 0 DID is separate). This difference
in Device ID is necessary for allowing distinct Plug and Play enumeration of function 1
when both function 0 and function 1 have the same class code.
268 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
15:10 RO Reserved
0s
9 RO Fast Back-to-Back (FB2B): Not Implemented. Hardwired to 0.
0b
8 RO SERR Enable (SERRE): Not Implemented. Hardwired to 0.
0b
7 RO Address/Data Stepping Enable (ADSTEP): Not Implemented.
0b Hardwired to 0.
1 RW Memory Access Enable (MAE): This bit controls the IGD's response
0b to memory space accesses.
0 = Disable.
1 = Enable.
0 RW I/O Access Enable (IOAE): This bit controls the IGD's response to
0b I/O space accesses.
0 = Disable.
1 = Enable.
Datasheet 269
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant
master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL#
timing that has been set by the IGD.
15 RO Detected Parity Error (DPE): Since the IGD does not detect parity,
0b this bit is always hardwired to 0.
10:9 RO DEVSEL Timing (DEVT): N/A. These bits are hardwired to "00".
00b
2:0 RO Reserved
000b
270 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register contains the revision number for Device 2 Functions 0 and 1.
This register contains the device programming interface information related to the
Sub-Class Code and Base Class Code definition for the IGD. This register also contains
the Base Class Code and the function sub-class in relation to the Base Class Code.
23:16 RO Base Class Code (BCC): This is an 8-bit value that indicates the
03h base class code for the GMCH. This code has the value 03h, indicating
a Display Controller.
Datasheet 271
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
7:0 RO Cache Line Size (CLS): This field is hardwired to 0s. The IGD as a
00h PCI compliant master does not use the Memory Write and Invalidate
command and, in general, does not perform operations based on
cache line size.
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
272 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register requests allocation for the IGD registers and instruction ports. The
allocation is for 512 KB and the base address is defined by bits 31:19.
31:19 RW Memory Base Address (MBA): Set by the OS, these bits correspond
0000h to address signals 31:19.
Datasheet 273
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
274 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s.
7:0 RO Capabilities Pointer Value (CPV): This field contains an offset into
D0h the function's PCI Configuration Space for the first item in the New
Capabilities Linked List, the MSI Capabilities ID registers at the Power
Management capability at D0h.
Datasheet 275
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
7:0 RO Minimum Grant Value (MGV): The IGD does not burst as a PCI
00h compliant master.
This register control of bits in this register are only required for customer visible SKU
differentiation.
7:0 RO Capability Identifier (CAP_ID): This field has the value 1001b to
09h identify the CAP_ID assigned by the PCI SIG for vendor dependent
capability pointers.
276 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
15:10 RO Reserved
00h
9:8 RO GTT Graphics Memory Size (GGMS): This field is used to select the
0h amount of main memory that is pre-allocated to support the Internal
Graphics Translation Table. The BIOS ensures that memory is pre-
allocated only when Internal graphics is enabled.
11 = reserved
Note: This register is locked and becomes Read Only when the D_LCK
bit in the SMRAM register is set.
Datasheet 277
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
7:4 RO Graphics Mode Select (GMS) This field is used to select the amount
0011b of Main Memory that is pre-allocated to support the Internal Graphics
device in VGA (non-linear) and Native (linear) modes. The BIOS
ensures that memory is pre-allocated only when Internal graphics is
enabled.
Note: This register is locked and becomes Read Only when the
D_LCK bit in the
BIOS Requirement: BIOS must not set this field to 000 if IVD (bit 1
of this register) is 0.
3:2 RO Reserved
00b
1 RO IGD VGA Disable (IVD):
0b 0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the
Sub-Class Code within Device 2 Class Code register is 00.
1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and
I/O), and the Sub- Class Code field within Device 2, function 0
Class Code register is 80h.
BIOS Requirement: BIOS must not set this bit to 0 if the GMS field
(bits 6:4 of this register) pre-allocates no memory.
This bit MUST be set to 1 if Device 2 is disabled either via a fuse or
fuse override (CAPID0[38] = 1) or via a register (DEVEN[3] = 0).
0 RO Reserved
0b
278 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register allows for enabling/disabling of PCI devices and functions that are within
the GMCH. The table below the bit definitions describes the behavior of all
combinations of transactions to devices controlled by this register. All the bits in this
register are Intel® TXT Lockable.
31:15 RO Reserved
00000h
13:10 RO Reserved
0s
9 RO EP Function 3 (D3F3EN):
1b
0 = Bus0:Device3:Function3 is disabled and hidden
8 RO EP Function 2 (D3F2EN):
1b
0 = Bus0:Device3:Function2 is disabled and hidden
7 RO EP Function 1 (D3F1EN):
1b
0 = Bus0:Device3:Function1 is disabled and hidden
6 RO EP Function 0 (D3F0EN):
1b
0 = Bus0:Device3:Function0 is disabled and hidden
5 RO Reserved
0b
Datasheet 279
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
2 RO Reserved
280 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
31:0 RO Reserved
00000000h
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD.
From the top of low used DRAM, GMCH claims 1 to 64 MBs of DRAM for internal
graphics if enabled.
The base of stolen memory will always be below 4 GB. This is required to prevent
aliasing between stolen range and the reclaim region.
31:20 RO Base of Stolen Memory (BSM): This register contains bits 31:20 of
078h the base address of stolen DRAM memory. The host interface
determines the base of Graphics Stolen memory by subtracting the
graphics stolen memory size from TOLUD. See Device 0 TOLUD for
more explanation.
19:0 RO Reserved
00000h
Datasheet 281
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
15:0 RO Reserved
0000h
7:4 RO Reserved
0h
1 RO Reserved
0b
282 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
Once this bit is set to a 1, all GFX core MMIO registers are returned to
power on default state. All Ring buffer pointers are reset, command
stream fetches are dropped and ongoing render pipeline processing is
halted, state machines and State Variables returned to power on
default state. If the Display is reset, all display engines are halted
(garbage on screen). VGA memory is not available; Store DWords and
interrupts are not ensured to be completed. Device #2 IO registers
are not available.
This register is a mirror of function 0 with the same R/W attributes. The hardware
implements a single physical register common to both functions 0 and 1.
7:0 RO Capability Identifier (CAP_ID): SIG defines this ID is 01h for power
01h management.
Datasheet 283
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
This register is a Mirror of Function 0 with the same read/write attributes. The
hardware implements a single physical register common to both functions 0 and 1.
15:11 RO PME Support (PMES): This field indicates the power states in which
00h the IGD may assert PME#. Hardwired to 0 to indicate that the IGD
does not assert the PME# signal.
10 RO D2 Support (D2): The D2 power management state is not
0b supported. This bit is hardwired to 0.
8:6 RO Reserved
000b
5 RO Device Specific Initialization (DSI): Hardwired to 1 to indicate
1b that special initialization of the IGD is required before generic class
device driver is to use it.
4 RO Reserved
0b
3 RO PME Clock (PMECLK): Hardwired to 0 to indicate IGD does not
0b support PME# generation.
2:0 RO Version (VER): Hardwired to 010b to indicate that there are 4 bytes
010b of power management registers implemented and that this device
complies with revision 1.1 of the PCI Power Management Interface
Specification.
284 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
15 RO PME Status (PMESTS): This bit is 0 to indicate that IGD does not
0b support PME# generation from D3 (cold).
14:13 RO Data Scale (DSCALE): The IGD does not support data register. This
00b bit always returns 0 when read, write operations have no effect.
12:9 RO Data Select (DATASEL): The IGD does not support data register.
0h This bit always returns 0 when read, write operations have no effect.
7:2 RO Reserved
00h
1:0 RW Power State (PWRSTAT): This field indicates the current power
00b state of the IGD and can be used to set the IGD into a new power
state. If software attempts to write an unsupported state to this field,
write operation must complete normally on the bus, but the data is
discarded and no state change occurs. On a transition from D3 to D0
the graphics controller is optionally reset to initial values.
00 = D0 (Default)
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
Datasheet 285
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
As long as there is the potential that DVO port legacy drivers exist which expect this
register at this address, D2:F0 address E0h–E1h must be reserved for this register.
7:1 RO Software Flag (SWF): This field is used to indicate caller and SMI
00h function desired, as well as return result.
0 RO GMCH Software SMI Event (GSSMIE): When Set, this bit will
0b trigger an SMI. Software must write a 0 to clear this bit.
286 Datasheet
Integrated Graphics Device Registers (D2:F0,F1)
(Intel® 82Q35, 82Q33, 82G33 GMCH Only)
Datasheet 287
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
288 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:0 RO Vendor ID (VID): 16-bit field which indicates Intel is the vendor,
8086h assigned by the PCI SIG.
Datasheet 289
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:11 RO Reserved
00000b
10 RW Interrupt Disable (ID): Disables this device from generating PCI line
0b based interrupts. This bit does not have any effect on MSI operation.
2 RW Bus Master Enable (BME): This bit controls the HECI host
0b controller's ability to act as a system memory master for data
transfers. When this bit is cleared, HECI bus master activity stops and
any active DMA engines return to an idle condition.
1 = Enable
Note that this bit does not block HECI accesses to ME-UMA (i.e., writes
or reads to the host and ME circular buffers through the read window
and write window registers still cause ME backbone transactions to ME-
UMA).
1 RW Memory Space Enable (MSE): This bit controls access to the HECI
0b host controller’s memory mapped register space.
0 = Disable
1= Enable
290 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
6 RO Reserved
0b
1 = Asserted
2:0 RO Reserved
000b
Datasheet 291
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
23:16 RO Base Class Code (BCC): Indicates the base class code of the HECI
07h host controller device.
15:8 RO Sub Class Code (SCC): Indicates the sub class code of the HECI host
80h controller device.
292 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
6:0 RO Header Layout (HL): Indicates that the HECI host controller uses a
0000000b target device layout.
Datasheet 293
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
63:4 RW Base Address (BA): Base address of register memory space. Bits
00000000 63:4 correspond to address bits 63:4.
0000000h
2:1 RO Type (TP): Indicates that this range can be mapped anywhere in 64-
10b bit address space.
31:16 RWO Subsystem ID (SSID): Indicates the sub-system identifier. This field
0000h should be programmed by BIOS during boot-up. Once written, this
register becomes Read Only. This field can only be cleared by PLTRST#.
294 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
7:0 RO Capability Pointer (CP): Indicates the first capability pointer offset. It
50h points to the PCI power management capability offset.
15:8 RO Interrupt Pin (IPIN): This indicates the interrupt pin the HECI host
01h controller uses. The value of 01h selects INTA# interrupt pin.
Datasheet 295
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:8 RO Next Capability (NEXT): Indicates the location of the next capability
8Ch item in the list. This is the Message Signaled Interrupts capability.
296 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:11 RO PME_Support (PSUP): Indicates the states that can generate PME#.
11001b
HECI can assert PME# from any D-state except D1 or D2 which are not
supported by HECI.
10 RO D2_Support (D2S): The D2 state is not supported for the HECI host
0b controller.
9 RO D1_Support (D1S): The D1 state is not supported for the HECI host
0b controller.
4 RO Reserved
0b
2:0 RO Version (VS): Indicates support for Revision 1.2 of the PCI Power
011b Management Specification.
Datasheet 297
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
14:9 RO Reserved.
000000b
0 = Disable
1 = Enable
7:4 RO Reserved
0000b
3 RO No_Soft_Reset (NSR): This bit indicates that when the HECI host
1b controller is transitioning from D3hot to D0 due to power state
command, it does not perform and internal reset. Configuration context
is preserved.
2 RO Reserved
0b
1:0 RW Power State (PS): This field is used both to determine the current
00b power state of the HECI host controller and to set a new power state.
The values are:
00 = D0 state
11 = D3HOT state
The D1 and D2 states are not supported for this HECI host controller.
When in the D3HOT state, the configuration space is available, but the
register memory spaces are not. Additionally, interrupts are blocked.
298 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:8 RO Next Pointer (NEXT): Indicates the next item in the list. This can be
00h other capability pointers (such as PCI-X or PCI-Express) or it can be the
last item in the list.
15:8 RO Reserved
00h
0 = Not capable
1 = Capable
Datasheet 299
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
31:2 RW Address (ADDR): This field provides the lower 32 bits of the system
00000000h specified message address, always DWord aligned.
MSI is not translated in Vtd; therefore, to avoid sending bad MSI with
address, bit [31:20] will be masked internally to generate 12'hFEE
regardless of content in register. Register attribute remains as RW.
1:0 RO Reserved
00b
31:0 RW Upper Address (UADDR): This field provides the upper 32 bits of
00000000h the system specified message address. This register is optional and
only implemented if MC.C64=1.
300 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This register is used to select interrupt delivery mechanism for HECI to Host processor
interrupts.
7:2 RO Reserved
0h
1:0 RW HECI Interrupt Delivery Mode (HIDM): These bits control what type
00b of interrupt the HECI will send when ME FW writes to set the M_IG bit
in AUX space. They are interpreted as follows:
01 = Generate SCI
10 = Generate SMI
Datasheet 301
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
54–55h PMCS PCI Power Management Control And 0008h RO, RW,
Status RWC
302 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:0 RO Vendor ID (VID): 16-bit field which indicates Intel is the vendor,
8086h assigned by the PCI SIG.
15:11 RO Reserved
00000b
10 RW Interrupt Disable (ID): Disables this device from generating PCI line
0b based interrupts. This bit does not have any effect on MSI operation.
0 = Enable
1 = Disable
Datasheet 303
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
2 RW Bus Master Enable (BME): This bit controls the HECI host controller's
0b ability to act as a system memory master for data transfers. When this
bit is cleared, HECI bus master activity stops and any active DMA
engines return to an idle condition.
1 = Enable.
Note that this bit does not block HECI accesses to ME-UMA (i.e., writes
or reads to the host and ME circular buffers through the read window
and write window registers still cause ME backbone transactions to ME-
UMA).
1 RW Memory Space Enable (MSE): This bit controls access to the HECI
0b host controller’s memory mapped register space.
0 = Disable
1 = Enable
304 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
6 RO Reserved
0b
1 = Asserted
2:0 RO Reserved
000b
Datasheet 305
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
23:16 RO Base Class Code (BCC): Indicates the base class code of the HECI
07h host controller device.
15:8 RO Sub Class Code (SCC): Indicates the sub class code of the HECI host
80h controller device.
306 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
6:0 RO Header Layout (HL): Indicates that the HECI host controller uses a
0000000b target device layout.
Datasheet 307
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This register allocates space for the HECI memory mapped registers defined in Section
1.5.6.
2:1 RO Type (TP): Indicates that this range can be mapped anywhere in 32-
10b bit address space
31:16 RWO Subsystem ID (SSID): This field indicates the sub-system identifier.
0000h This field should be programmed by BIOS during boot-up. Once
written, this register becomes Read Only. This field can only be cleared
by PLTRST#.
15:0 RWO Subsystem Vendor ID (SSVID): This field indicates the sub-system
0000h vendor identifier. This field should be programmed by BIOS during
boot-up. Once written, this register becomes Read Only. This field can
only be cleared by PLTRST#.
308 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
7:0 RO Capability Pointer (CP): This field indicates the first capability pointer
50h offset. It points to the PCI power management capability offset.
15:8 RO Interrupt Pin (IPIN): This field indicates the interrupt pin the HECI
04h host controller uses. The value of 01h selects INTA# interrupt pin.
Datasheet 309
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
31:0 RO Firmware Status Host Access (FS_HA): This field indicates current
00000000h status of the firmware for the HECI controller. This field is the host's
read only access to the FS field in the ME Firmware Status AUX
register.
15:8 RO Next Capability (NEXT): This field indicates the location of the next
8Ch capability item in the list. This is the Message Signaled Interrupts
capability.
7:0 RO Cap ID (CID): This field indicates that this pointer is a PCI power
01h management.
310 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:11 RO PME_Support (PSUP): This field indicates the states that can
11001b generate PME#.
HECI can assert PME# from any D-state except D1 or D2 which are not
supported by HECI.
10 RO D2_Support (D2S): The D2 state is not supported for the HECI host
0b controller.
9 RO D1_Support (D1S): The D1 state is not supported for the HECI host
0b controller.
8:6 RO Aux_Current (AUXC): This field reports the maximum Suspend well
000b current required when in the D3COLD state. Value of TBD is reported.
4 RO Reserved
0b
2:0 RO Version (VS): Indicates support for Revision 1.2 of the PCI Power
011b Management Specification.
Datasheet 311
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15 RWC PME Status (PMES): The PME Status bit in HECI space can be set to 1
0b by ME FW performing a write into AUX register to set PMES.
14:9 RO Reserved.
000000b
7:4 RO Reserved
0000b
3 RO No_Soft_Reset (NSR): This bit indicates that when the HECI host
1b controller is transitioning from D3hot to D0 due to power state
command, it does not perform an internal reset. Configuration context
is preserved: Reserved.
2 RO Reserved
0b
1:0 RW Power State (PS): This field is used both to determine the current
00b power state of the HECI host controller and to set a new power state.
00 = D0 state
11 = D3HOT state
The D1 and D2 states are not supported for this HECI host controller.
When in the D3HOT state, the configuration space is available, but the
register memory spaces are not. Additionally, interrupts are blocked.
312 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:8 RO Next Pointer (NEXT): This field indicates the next item in the list.
00h This can be other capability pointers (such as PCI-X or PCI-Express) or
it can be the last item in the list.
15:8 RO Reserved
00h
1 = Enable. MSI is enabled and traditional interrupt pins are not used
to generate interrupts.
Datasheet 313
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
31:2 RW Address (ADDR): This field provides the lower 32 bits of the system
00000000h specified message address, always DWord aligned.
1:0 RO Reserved
00b
314 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This register is used to select interrupt delivery mechanism for HECI to Host processor
interrupts.
7:2 RO Reserved
0h
1:0 RW HECI Interrupt Delivery Mode (HIDM): These bits control what
00b type of interrupt the HECI will send when ME FW writes to set the
M_IG bit in AUX space. They are interpreted as follows:
01 = Generate SCI
10 = Generate SMI
Datasheet 315
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
CC–CFh PMCS PCI Power Management Control and 00000000h RO, RW,
Status RO/V
316 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
9.3.1 ID—Identification
B/D/F/Type: 0/3/2/PCI
Address Offset: 00–03h
Default Value: 29C68086h
Access: RO
Size: 32 bits
This register combined with the Device Identification register uniquely identifies any
PCI device.
15:0 RO Vendor ID (VID): 16-bit field which indicates the company vendor as
8086h Intel.
This register provides basic control over the device's ability to respond to and perform
Host system related accesses.
Datasheet 317
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:11 RO Reserved
00h
2 RW Bus Master Enable (BME): This bit controls the PT function's ability to
0b act as a master for data transfers. This bit does not impact the
generation of completions for split transaction commands.
0 = Disable
1 = Enable
0 = Disable
1 = Enable
318 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This register is used by the function to reflect its PCI status to the host for the
functionality that it implements.
10:9 RO DEVSEL# Timing Status (DEVT): Controls the device select time for
0b the PT function's PCI interface.
6 RO Reserved
0b
3 RO Interrupt Status (IS): This bit reflects the state of the interrupt in
0b the function. Setting of the Interrupt Disable bit to 1 has no affect on
this bit. Only when this bit is a 1 and ID bit is 0 is the INTc interrupt
asserted to the Host
2:0 RO Reserved
000b
Datasheet 319
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
9.3.4 RID—Revision ID
B/D/F/Type: 0/3/2/PCI
Address Offset: 08h
Default Value: 00h
Access: RO
Size: 8 bits
This register identifies the basic functionality of the device (i.e., IDE mass storage).
This register defines the system cache line size in DWORD increments. This register is
mandatory for master that use the Memory-Write and Invalidate command.
7:0 RO Cache Line Size (CLS): All writes to system memory are memory
00h writes.
320 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This register defines the minimum number of PCI clocks the bus master can retain
ownership of the bus whenever it initiates new transactions.
7:0 RO Master Latency Timer (MLT): Not implemented since the function is
00h in (G)MCH.
7:0 RO Reserved
00h
Datasheet 321
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This 8-byte I/O space is used in Native Mode for the Primary Controller's Command
Block (i.e., BAR0).
31:16 RO Reserved
0000h
15:3 RW Base Address (BAR): This field provides the base address of the
0000h BAR0 I/O space (8 consecutive I/O locations)
2:1 RO Reserved
00b
This 4-byte I/O space is used in Native Mode for the Primary Controller's Control Block
(i.e., BAR1).
31:16 RO Reserved
0000h
15:2 RW Base Address (BAR): This field provides the base address of the
0000h BAR1 I/O space (4 consecutive I/O locations)
1 RO Reserved
0b
322 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This 8-byte I/O space is used in Native Mode for the secondary Controller's Command
Block. Secondary Channel is not implemented and reads return 7F7F7F7Fh and all
writes are ignored.
31:16 RO Reserved
0000h
15:3 RW Base Address (BAR): This field provides the base address of the I/O
0000h space (8 consecutive I/O locations)
2:1 RO Reserved
00b
This 4-byte I/O space is used in Native Mode for Secondary Controller's Control block.
Secondary Channel is not implemented and reads return 7F7F7F7Fh and all writes are
ignored.
31:16 RO Reserved
0000h
15:2 RW Base Address (BAR): This field provides the base address of the I/O
0000h space (4 consecutive I/O locations)
1 RO Reserved
0b
Datasheet 323
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This Bar is used to allocate I/O space for the SFF-8038i mode of operation (a.k.a. Bus
Master IDE).
31:16 RO Reserved
0000h
15:4 RW Base Address (BA): This field provides the base address of the I/O
000h space (16 consecutive I/O locations).
3:1 RO Reserved
000b
324 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
These registers are used to uniquely identify the add-in card or the subsystem that
the device resides within.
10:1 RO Reserved
000h
Datasheet 325
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This optional register is used to point to a linked list of new capabilities implemented
by the device.
7:0 RO Capability Pointer (CP): This field indicates that the first capability
C8h pointer offset is offset C8h ( the power management capability)
7:0 RW Interrupt Line (ILINE): The value written in this register indicates
00h which input of the system interrupt controller, the device's interrupt pin
is connected. This value is used by the OS and the device driver, and
has no affect on the hardware.
326 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
7:0 RO Reserved
00h
7:0 RO Reserved
00h
15:8 RO Next Capability (NEXT): The value of D0h points to the MSI
D0h capability.
7:0 RO Cap ID (CID): Indicates that this pointer is a PCI power management.
01h
Datasheet 327
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
8:6 RO Aux Current (AUXC): PME# from D3 (cold) state is not supported,
000b therefore this field is 000b.
4 RO Reserved
0b
2:0 RO Version (VS): Indicates support for revision 1.2 of the PCI power
011b management specification.
This register implements the PCI PM Control and Status Register to allow PM state
transitions and Wake up.
Note the NSR bit of this register. All registers (PCI configuration and Device Specific)
marked with D3->D0 transition reset will only do so if this bit reads a 0. If this bit is a
1, the D3->D0 transition will not reset the registers.
328 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
31:16 RO Reserved
0h
14:9 RO Reserved
00h
7:4 RO Reserved
0000b
1:0 RW Power State (PS): This field is used both to determine the current
00b power state of the PT function and to set a new power state. The
values are:
00 = D0 state
11 = D3HOT state
Datasheet 329
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:8 RO Next Pointer (NEXT): Value indicates this is the last item in the
00h capabilities list.
15:8 RO Reserved
00h
6:4 RW Multiple Message Enable (MME): These bits are R/W for software
000b compatibility, but only one message is ever sent by the PT function
330 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This register specifies the DWord aligned address programmed by system software for
sending MSI.
1:0 RO Reserved
00b
This register provides the upper 32 bits of the message address for the 64bit address
capable device.
31:4 RO Reserved
0000000h
Datasheet 331
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:0 RW Data (DATA): This content is driven onto the lower word of the data
0000h bus of the MSI memory write transaction
332 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
Datasheet 333
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
9.4.1 ID—Identification
B/D/F/Type: 0/3/3/PCI
Address Offset: 00-03h
Default Value: 29C78086h
Access: RO
Size: 32 bits
This register combined with the Device Identification register uniquely identifies any
PCI device.
15:0 RO Vendor ID (VID): 16-bit field which indicates the company vendor as
8086h Intel
This register provides basic control over the device's ability to respond to and perform
Host system related accesses.
15:11 RO Reserved
00h
334 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
0 = Disable
1 = Enable
0 = Disable
1 = Enable
0 = Disable
1 = Enable
Datasheet 335
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This register is used by the function to reflect its PCI status to the host for the
functionality that it implements.
10:9 RO DEVSEL# Timing Status (DEVT): Controls the device select time for
00b the PT function's PCI interface.
6 RO Reserved
0b
3 RO Interrupt Status (IS): This bit reflects the state of the interrupt in
0b the function. Setting of the Interrupt Disable bit to 1 has no affect on
this bit. Only when this bit is a 1 and ID bit is 0 is the INTB interrupt
asserted to the Host.
2:0 RO Reserved
000b
336 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
9.4.4 RID—Revision ID
B/D/F/Type: 0/3/3/PCI
Address Offset: 08h
Default Value: 00h
Access: RO
Size: 8 bits
This register identifies the basic functionality of the device i.e. Serial Com Port.
This register defines the system cache line size in DWORD increments. This register is
mandatory for master that uses the Memory-Write and Invalidate command.
7:0 RO Cache Line Size (CLS): All writes to system memory are Memory
00h Writes.
Datasheet 337
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This register defines the minimum number of PCI clocks the bus master can retain
ownership of the bus whenever it initiates new transactions.
7:0 RO Master Latency Timer (MLT): Not implemented since the function is in
00h (G)MCH.
7:0 RO Reserved
00h
338 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This register provides the base address for the 8-byte I/O space for KT.
Note: Reset: Host system Reset or D3->D0 transition.
31:16 RO Reserved
0000h
15:3 RW Base Address (BAR): This field provides the base address of the I/O
0000h space (8 consecutive I/O locations)
2:1 RO Reserved
00b
31:12 RW Base Address (BAR): This field provides the base address of the
00000h memory-mapped IO BAR
11:4 RO Reserved
00h
2:1 RO Type (TP): Indicates that this range can be mapped anywhere in 32-
00b bit address space.
Datasheet 339
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This registers are used to uniquely identify the add-in card or the subsystem that the
device resides within.
340 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
10:1 RO Reserved
000h
This optional register is used to point to a linked list of new capabilities implemented
by the device.
7:0 RO Capability Pointer (CP): This field indicates that the first capability
C8h pointer offset is offset c8h ( the power management capability)
Datasheet 341
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
7:0 RW Interrupt Line (ILINE): The value written in this field indicates which
00h input of the system interrupt controller, the device's interrupt pin is
connected to. This value is used by the OS and the device driver, and
has no affect on the hardware.
7:0 RO Reserved
00h
342 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
7:0 RO Reserved
00h
15:8 RO Next Capability (NEXT): The value of D0h points to the MSI
D0h capability
7:0 RO Cap ID (CID): This field indicates that this pointer is a PCI power
01h management
Datasheet 343
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
8:6 RO Aux Current (AUXC): PME# from D3 (cold) state is not supported;
000b therefore, this field is 000b.
4 RO Reserved
0b
2:0 RO Version (VS): Indicates support for revision 1.2 of the PCI power
011b management specification.
344 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This register implements the PCI PM Control and Status Register to allow PM state
transitions and Wake up.
Note: Note the NSR bit of this register. All registers (PCI configuration and Device Specific)
marked with D3->D0 transition reset will only do so if this bit reads a 0. If this bit is a
1, the D3->D0 transition will not reset the registers.
31:16 RO Reserved
0h
14:9 RO Reserved
00h
7:4 RO Reserved
0h
Datasheet 345
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
1:0 RW Power State (PS): This field is used both to determine the current
00b power state of the PT function and to set a new power state.
00 = D0 state
11 = D3HOT state
15:8 RO Next Pointer (NEXT): Value indicates this is the last item in the list.
00h
346 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:8 RO Reserved
00h
6:4 RW Multiple Message Enable (MME): These bits are R/W for software
000b compatibility, but only one message is ever sent by the PT function.
Datasheet 347
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
This register specifies the DWord aligned address programmed by system software for
sending MSI.
31:2 RW Address (ADDR): This field provides the lower 32 bits of the system
00000000h specified message address, always DWord aligned.
1:0 RO Reserved
00b
This register provides the upper 32 bits of the message address for the 64bit address
capable device.
31:4 RO Reserved
0000000h
3:0 RW Address (ADDR): This field provides the upper 4 bits of the system
0000b specified message address.
348 Datasheet
Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3)
15:0 RW Data (DATA): This MSI data is driven onto the lower word of the data
0000h bus of the MSI memory write transaction.
Datasheet 349
Functional Description
10 Functional Description
The (G)MCH supports only one outstanding deferred transaction on the FSB.
FSB_DINVB_0 FSB_DB_15:0
FSB_DINVB_1 FSB_DB_31:16
FSB_DINVB_2 FSB_DB_47:32
FSB_DINVB_3 FSB_DB_63:48
350 Datasheet
Functional Description
When the processor or the (G)MCH drives data, each 16-bit segment is analyzed. If
more than 8 of the 16 signals would normally be driven low on the bus, the
corresponding HDINV# signal will be asserted, and the data will be inverted prior to
being driven on the bus. Whenever the processor or the (G)MCH receives data, it
monitors FSB_DINVB_3:0 to determine if the corresponding data segment should be
inverted.
Datasheet 351
Functional Description
Note: References in this section to DDR3 are for the 82G33 GMCH and 82P35 only.
The system memory controller supports three memory organization modes, Single
Channel, Dual Channel Symmetric, and Dual Channel Asymmetric.
In this mode, all memory cycles are directed to a single channel. Single channel mode
is used when either Channel A or Channel B DIMMs are populated in any order, but
not both.
This mode provides maximum performance on real applications. Addresses are ping-
ponged between the channels after each cache line (64 byte boundary). If there are
two requests, and the second request is to an address on the opposite channel from
the first, that request can be sent before data from the first request has returned. If
two consecutive cache lines are requested, both may be retrieved simultaneously,
since they are ensured to be on opposite channels.
Dual channel symmetric mode is used when both Channel A and Channel B DIMMs are
populated in any order with the total amount of memory in each channel being the
same, but the DRAM device technology and width may vary from one channel to the
other.
Table 10-1 is a sample dual channel symmetric memory configuration showing the
rank organization.
352 Datasheet
Functional Description
Table 10-1. Sample System Memory Dual Channel Symmetric Organization Mode with
Intel® Flex Memory Mode Enabled
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start in channel 0 and stay there until the end of the highest rank in
channel 0, and then addresses continue from the bottom of channel 1 to the top.
Normal applications are unlikely to make requests that alternate between addresses
that are on opposite channels with this memory organization; so, in most cases,
bandwidth will be limited to that of a single channel.
Dual channel asymmetric mode is used when both Channel A and Channel B DIMMs
are populated in any order with the total amount of memory in each channel being
different.
Table 10-2 is a sample dual channel asymmetric memory configuration showing the
rank organization:
Table 10-2. Sample System Memory Dual Channel Asymmetric Organization Mode with
Intel® Flex Memory Mode Disabled
Datasheet 353
Functional Description
The (G)MCH supports the following DDR2 and DDR3 Data Transfer Rates, DIMM
Modules, and DRAM Device Technologies:
• DDR2 Data Transfer Rates: 667 (PC2-5300) and 800 (PC2-6400)
• DDR3 Data Transfer Rates: 800 (PC3-6400) and 1066 (PC3-8500)
• DDR2 DIMM Modules:
⎯ Raw Card C - Single Sided x16 un-buffered non-ECC
⎯ Raw Card D - Single Sided x8 un-buffered non-ECC
⎯ Raw Card E - Double Sided x8 un-buffered non-ECC
• DDR3 DIMM Modules:
⎯ Raw Card A - Single Sided x8 un-buffered non-ECC
⎯ Raw Card B - Double Sided x8 un-buffered non-ECC
⎯ Raw Card C - Single Sided x16 un-buffered non-ECC
⎯ Raw Card F - Double Sided x16 un-buffered non-ECC
• DDR2 and DDR3 DRAM Device Technology: 512 MB and 1 GB
354 Datasheet
Functional Description
This (G)MCH is part of a PCI Express root complex. This means it connects a host
processor/memory subsystem to a PCI Express hierarchy. The control registers for
this functionality are located in device 1 configuration space and two Root Complex
Register Blocks (RCRBs). The DMI RCRB contains registers for control of the ICH9
attach ports.
The PCI Express architecture is specified in layers. Compatibility with the PCI
addressing model (a load-store architecture with a flat address space) is maintained to
ensure that all existing applications and drivers operate unchanged. The PCI Express
configuration uses standard mechanisms as defined in the PCI Plug-and-Play
specification. The initial speed of 1.25 GHz (250 MHz internally) results in
2.5 GB/s/direction which provides a 250 MB/s communications channel in each
direction (500 MB/s total) that is close to twice the data rate of classic PCI per lane.
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer’s primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also
manages flow control of TLPs.
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and
error correction.
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and
impedance matching circuitry.
Datasheet 355
Functional Description
Essentially, an SDVO port will transmit display data in a high speed, serial format
across differential AC coupled signals. An SDVO port consists of a sideband differential
clock pair and a number of differential data pairs.
SDVO ports can support a variety of display types including LVDS, DVI, Analog CRT,
TV-Out and external CE type devices. The GMCH uses an external SDVO device to
translate from SDVO protocol and timings to the desired display format and timings.
The Internal Graphics Controller can have one or two SDVO ports multiplexed on the
x16 PCI Express interface. When an external x16 PCI Express graphics accelerator is
not in use, an ADD2 card may be plugged into the x16 connector or if a x16 slot is not
present, the SDVO(s) may be located ‘down’ on the motherboard to access the
multiplexed SDVO ports and provide a variety of digital display options.
The ADD2/Media Expansion card is designed to fit in a x16 PCI Express connector. The
ADD2/Media Expansion card can support one or two devices. If a single channel SDVO
device is used, it should be attached to the channel B SDVO pins. The ADD2 card can
support two separate SDVO devices when the interface is in Dual Independent or Dual
Simultaneous Standard modes. The Media Expansion card adds Video in capabilities.
The SDVO port defines a two-wire point-to-point communication path between the
SDVO device and GMCH. The SDVO control clock and data provide similar functionality
to I2C. However unlike I2C, this interface is intended to be point-to-point (from the
GMCH to the SDVO device) and requires the SDVO device to act as a switch and direct
traffic from the SDVO control bus to the appropriate receiver. Additionally, this control
bus will be able to run at faster speeds (up to 1 MHz) than a traditional I2C interface
would.
356 Datasheet
Functional Description
Analog RGB
Monitor
Control Clock
Control Data
TV Clock In
Stall
Interrupt
SDVO Port C
Graphics RedC / AlphaB External Device(s)
Device(s) or TV
GreenC
BlueC
PCI
Express*
Logic ClockB
SDVO Port B
RedB
GreenB
BlueB
GMCH
SDVO_BlkDia
Datasheet 357
Functional Description
For the GMCH, the only supported PCI Express width when SDVO is present is x1.
Notes:
1. The Configuration #s refer to the following figures (no intentional relation to validation
configurations).
2. Configurations 4, 5, and 6 (required addition of SDVO/PCI Express* Concurrent Strap).
358 Datasheet
Functional Description
GMCH GMCH
PEG PEG 1 3 5
Signals Pins
0 0 0 0 0
0 PCIe Lane 0
x1 x4
PCIe sDVO PCIe
x8
x16 sDVO MEC Card
PCIe (ADD2)
Card Card
sDVO Lane 7
Video Out
sDVO
sDVO Lane 0
15 15 15 15 15
SDVO-Conc-PCIe_Non-Reversed_Config
GMCH GMCH
PEG PEG 2 4 6
Signals Pins
15 0 15 15 15
sDVO Lane 0
sDVO
PCI Express x16 Connector
sDVO Lane 7
x16 x8
Reversed
PCIe sDVO
Card (ADD2) MEC Card
Card
x4 PCIe Lane N
x1 sDVO Video In
PCIe (ADD2) PCIe
Card Card
0 PCIe Lane 0
0 15 0 0 0
SDVO-Conc-PCIe_Reversed_Config
Datasheet 359
Functional Description
The GMCH contains a variety of planes, such as display, overlay, cursor and VGA. A
plane consists of rectangular shaped image that has characteristics such as source,
size, position, method, and format. These planes get attached to source surfaces that
are rectangular memory surfaces with a similar set of characteristics. They are also
associated with a particular destination pipe.
A pipe consists of a set of combined planes and a timing generator. The GMCH has
two independent display pipes, allowing for support of two independent display
streams. A port is the destination for the result of the pipe. The GMCH contains three
display ports; 1 analog (DAC) and two digital (SDVO ports B and C). The ports will be
explained in more detail later in this chapter.
The entire IGD is fed with data from its memory controller. The GMCH’s graphics
performance is directly related to the amount of bandwidth available. If the engines
are not receiving data fast enough from the memory controller (e.g., single-channel
DDR3 1066), the rest of the IGD will also be affected.
The rest of this chapter will focus on explaining the IGD components, their limitations,
and dependencies.
The GMCH graphics is the next step in the evolution of integrated graphics. In addition
to running the graphics engine at 400 MHz, the GMCH graphics has two pixel pipelines
that provide a 1.3 GB/s fill rate that enables an excellent consumer gaming
experience.
The 3D graphics pipeline for the GMCH has a deep pipelined architecture in which each
stage can simultaneously operate on different primitives or on different portions of the
same primitive. The 3D graphics pipeline is divided into four major stages: geometry
processing, setup (vertex processing), texture application, and rasterization.
The GMCH graphics is optimized for use with current and future Intel® processors for
advance software based transform and lighting techniques (geometry processing) as
defined by the Microsoft DirectX* API. The other three stages of 3D processing are
handled on the integrated graphics device. The setup stage is responsible for vertex
processing; converting vertices to pixels. The texture application stage applies
textures to pixels. The rasterization engine takes textured pixels and applies lighting
and other environmental affects to produce the final pixel value. From the
rasterization stage, the final pixel value is written to the frame buffer in memory so it
can be displayed.
360 Datasheet
Functional Description
Processor
Geometry:
Transform and Lighting, Vertex Shader
GMCH
Setup Engine:
Vertices in, Pixels out
Texture Engine:
Pixels in, Textured Pixels out
Raster Engine:
Textured Pixels in, Final Pixels out
3D-Gfx_Pipeline
10.5.2 3D Engine
The 3D engine on the GMCH has been designed with a deep pipelined architecture,
where performance is maximized by allowing each stage of the pipeline to
simultaneously operate on different primitives or portions of the same primitive. The
GMCH supports Perspective-Correct Texture Mapping, Multitextures, Bump-Mapping,
Cubic Environment Maps, Bilinear, Trilinear and Anisotropic MIP mapped filtering,
Gouraud shading, Alpha-blending, Vertex, and Per Pixel Fog and Z/W Buffering.
The 3D pipeline subsystem performs the 3D rendering acceleration. The main blocks
of the pipeline are the setup engine, scan converter, texture pipeline, and raster
pipeline. A typical programming sequence would be to send instructions to set the
state of the pipeline followed by rending instructions containing 3D primitive vertex
data.
Datasheet 361
Functional Description
The GMCH has one dedicated display port, the analog port. SDVO ports B and C are
multiplexed with the PCI Express Graphics (PEG) interface and are not available if an
external PEG device is in use. When a system uses a PEG connector, SDVO ports B
and C can be used via an ADD2 (Advanced Digital Display 2) or MEC (Media Expansion
Card).
• The (G)MCH’s analog port uses an integrated 350 MHz RAMDAC that can directly
drive a standard progressive scan analog monitor up to a resolution of 2048x1536
pixels with 32-bit color at 75 Hz.
• The GMCH’s SDVO ports are each capable of driving a 225MP pixel rate. Each port
is capable of driving a digital display up to 1920x1200 @ 60Hz.
The GMCH is compliant with DVI Specification 1.0. When combined with a DVI
compliant external device and connector, the GMCH has a high speed interface to a
digital display (e.g., flat panel or digital CRT).
The GMCH is compliant with HDMI. When combined with a HDMI compliant external
device and connector, the external HDMI device can supports standard, enhanced, or
high-definition video, plus multi-channel digital audio on a single cable.
362 Datasheet
Functional Description
The analog display port provides a RGB signal output along with a HSYNC and VSYNC
signal. There is an associated DDC signal pair that is implemented using GPIO pins
dedicated to the analog port. The intended target device is for a CRT based monitor
with a VGA connector. Display devices such as LCD panels with analog inputs may
work satisfactory but no functionality added to the signals to enhance that capability.
Sync on Green No
Voltage 2.5 V
Stereo Sync No
Datasheet 363
Functional Description
The GMCH implements a hardware GMBus controller that can be used to control these
signals allowing for transactions speeds up to 400 kHz.
The GMCH has several options for driving digital displays. The GMCH contains two
SDVO ports that are multiplexed on the PEG interface. When an external PEG graphics
accelerator is not present, the GMCH can use the multiplexed SDVO ports to provide
extra digital display options. These additional digital display capabilities may be
provided through an ADD2/Media Expansion Card, which is designed to plug in to a
PCI Express connector.
The shared SDVO ports each support a pixel clock up to 200 MHz and can support a
variety of transmission devices.
SDVOCTRLDATA is an open-drain signal that will act as a strap during reset to tell the
GMCH whether the interface is a PCI Express interface or an SDVO interface. When
implementing SDVO, either via ADD2 cards or with a down device, a pull-up is placed
on this line to signal to the GMCH to run in SDVO mode and for proper GMBus
operation.
364 Datasheet
Functional Description
The TV-out interface on GMCH allows an external TV encoder device to drive a pixel
clock signal on SDVO_TVClk[+/-] that the GMCH uses as a reference frequency. The
frequency of this clock is dependent on the output resolution required.
The overscan compensation scaling and the flicker filter is done in the external TV
encoder chip. Care must be taken to allow for support of TV sets with high
performance de-interlacers and progressive scan displays connected to by way of a
non-interlaced signal. Timing will be generated with pixel granularity to allow more
overscan ratios to be supported.
Analog content protection will be provided through the external encoder using
Macrovision 7.01. DVD software must verify the presence of a Macrovision TV encoder
before playback continues. Simple attempts to disable the Macrovision operation must
be detected.
Datasheet 365
Functional Description
10.6.2.7.3 Connectors
Target TV connectors support includes the CVBS, S-Video, Component, HDMI and
SCART connectors. The external TV encoder in use will determine the method of
support.
366 Datasheet
Functional Description
10.7.1 ACPI
The GMCH supports ACPI 2.0 system power states S0, S1, S3, and S5; and processor
C0, C1, and C2 states. During S3, the GMCH VCC core, PCI Express, and processor
VTT voltage rails are powered down – also known as S3-Cold.
Table 10-5. Intel® G33 and P35 Express Chipset (G)MCH Voltage Rails
S5 0V 0V 0V 0V 0V
Table 10-6. Intel® Q35 and Q33 Express Chipset GMCH Voltage Rails
S3 Moff 0V 0V 0V 0V 0V
Wake-on-ME
S5 Moff 0V 0V 0V 0V 0V
The GMCH supports ACPI device power states D0, D1, D2, and D3 for the integrated
graphics device.
The GMCH supports ACPI device power states D0 and D3 for the PCI Express interface
Datasheet 367
Functional Description
368 Datasheet
Functional Description
The following sequence must be followed in BIOS to properly set up the Hot Trip Point
and ICH SMI# signal assertion:
1. In Thermal Sensor Control 1 Register (TSC1), set thermal sensor enable bit (TSE)
and the hysteresis value (DHA) by writing 99h to MCHBAR CD8h
2. Program the Hot Trip Point Register (TSTTP[HTPS]) by writing the appropriate
value to MCHBAR CDCh bits [15:8]
3. Program the Catastrophic Trip Point Setting Register (TSTTP[CTPS]) by writing
2Ch to MCHBAR CDCh bits [7:0]
4. In Thermal Sensor Control 2 Register (TSC2), program the Thermometer Mode
Enable and Rate (TE) by writing 04h to MCHBAR CD9h bits [3:0]
5. In the Hardware Protection Register (THERM1), program the Halt on Catastrophic
bit (HOC) by writing 08h to MCHBAR CE4h bits [7:0]
6. Lock the Hardware Protection by writing a 1 to the Lock bit (HTL) at MCHBAR
CE4h bit [0]
7. In Thermal SMI Command Register (TSMICMD), set the SMI# on Hot bit by
writing a 02h to MCHBAR CF1h
8. Program the SMI Command register (SMICMD[TSTSMI]) by writing a 1 to bit 11 to
PCI CCh
9. Program the TCO Register (TCO[TSLB]) to lock down the other register settings by
writing a 1 to bit 7 of MCHBAR CE2h
10. Clear this bit of the TIS register to allow subsequent interrupts of this type to get
registered.
11. Clear the global thermal sensor event bit in the Error Status Register, bit 11.
12.
13. In thermal sensor status register (TSS), the Hot trip indicator (HTI) bit is set if
this condition is still valid by the time the software gets to read the register.
Datasheet 369
Functional Description
The Catastrophic and Hot trip points are programmed in the TSTTP Register. Bits 7:0
are for the Catastrophic Trip Point (CTPS), and bits 15:8 are for the Hot Trip Point
(HTPS).
Note: The Catastrophic Trip Point is recommended to fixed at 118 C. The Hot Trip Point is
recommended to be between 95 C and 105 C. Programming the Hot Trip Point above
this range is not recommended.
To program both trip point settings, the following polynomial equation should be used.
In this case the “value” is a decimal number between 0 and 128. For the Catastrophic
Trip Point, a decimal value of 41 (29h) should be used to hit 118 C.
The CTPS should then be programmed with 29h. The Hot Trip Point is also
programmed in the same manner.
370 Datasheet
Functional Description
10.9 Clocking
10.9.1 Overview
The (G)MCH has a total of 5 PLLs providing many times that many internal clocks. The
PLLs are:
• Host PLL – Generates the main core clocks in the host clock domain. Can also be
used to generate memory and internal graphics core clocks. Uses the Host clock
(H_CLKIN) as a reference.
• Memory IO PLL - Optionally generates low jitter clocks for memory IO interface, as
opposed to from Host PLL. Uses the Host FSB differential clock
(HPL_CLKINP/HPL_CLKINN) as a reference. Low jitter clock source from Memory
I/O PLL is required for DDR667 and higher frequencies.
• PCI Express PLL – Generates all PCI Express related clocks, including the Direct
Media Interface that connects to the ICH. This PLL uses the 100 MHz clock
(G_CLKIN) as a reference.
• Display PLL A – Generates the internal clocks for Display A. Uses D_REFCLKIN as a
reference.
• Display PLL B – Generates the internal clocks for Display B. Also uses D_REFCLKIN
as a reference.
• CK505 is the Clocking chip required for the Intel® 3 Series Express Chipset
platform
Datasheet 371
Functional Description
Slot 0
Slot 2
Slot 3
Slot 1
X 16 PCI Express
PCI 33 MHz
P1 PCI Down Device
PCI 33 MHz
P2 TPM LPC
PCI 33 MHz OSC
P3
24 MHz
Intel High
Definition Audio 32.768 kHz
372 Datasheet
Functional Description
Datasheet 373
Electrical Characteristics
11 Electrical Characteristics
This chapter contains the DC specifications for the (G)MCH.
Note: References to SDVO, IGD, DAC Display Interface are for the 82Q35, 82Q33, and
82G33 GMCH only.
Although the (G)MCH contains protective circuitry to resist damage from static electric
discharge, precautions should always be taken to avoid high static voltages or electric
fields.
(G)MCH Core
VCC 1.25 V Core Supply Voltage with respect to VSS -0.3 1.375 V
VTT_FSB System Bus Input Voltage with respect to VSS -0.3 1.32 V
VCCA_HPLL 1.25 V Host PLL Analog Supply Voltage with respect to -0.3 1.375 V
VSS
VCC_DDR 1.8 V DDR2 / 1.5 V DDR3 System Memory Supply -0.3 4.0 V
Voltage with respect to VSS
374 Datasheet
Electrical Characteristics
VCC_CKDDR 1.8 V DDR2 / 1.5 V DDR3 Clock System Memory -0.3 4.0 V
Supply Voltage with respect to VSS
VCCA_MPLL 1.25 V System Memory PLL Analog Supply Voltage -0.3 1.375 V
with respect to VSS
VCC_EXP 1.25 V PCI Express* and DMI Supply Voltage with -0.3 1.375 V
respect to VSS
VCCA_EXP 3.3 V PCI Express* Analog Supply Voltage with -0.3 3.63 V
respect to VSS
VCCAPLL_EXP 1.25 V PCI Express* PLL Analog Supply Voltage with -0.3 1.375 V
respect to VSS
VCCA_DAC 3.3 V Display DAC Analog Supply Voltage with respect to -0.3 3.63 V
VSS
VCCD_CRT 1.5 V Display DAC Digital Supply Voltage with -0.3 1.98 V
respect to VSS
VCCDQ_CRT 1.5 V Display DAC Quiet Digital Supply Voltage with -0.3 1.98 V
respect to VSS
VCCA_DPLLA 1.25 V Display PLL A Analog Supply Voltage with -0.3 1.375 V
respect to VSS
VCCA_DPLLB 1.25 V Display PLL B Analog Supply Voltage with -0.3 1.375 V
respect to VSS
CMOS Interface
VCC3_3 3.3 V CMOS Supply Voltage with respect to VSS -0.3 3.63 V
NOTE:
1. Possible damage to the MCH may occur if the MCH temperature exceeds 150 °C. Intel does
not guarantee functionality for parts that have exceeded temperatures above 150 °C due to
specification violation.
Datasheet 375
Electrical Characteristics
NOTES:
1. Measurements are for current coming through chipset’s supply pins.
2. Rail includes DLLs (and FSB sense amps on VCC).
3. Sustained Measurements are combined because one voltage regulator on the platform supplies
both rails on the MCH.
376 Datasheet
Electrical Characteristics
Table 11-3 shows the maximum power consumption for the MCH in the ACPI S3, S4,
and S5 states with Intel® Active Management Technology support. Platforms that
utilize Intel Active Management Technology will keep DRAM memory powered in S4
and S5. Current consumption used by the MCH will vary between the “Idle” case and
the “Max” case, depending on activity on the Intel® Management Engine. For the
majority of the time, the Intel Management Engine will be in the “Idle” state. In
addition, Max values are measured with fast silicon at 96° C Tcase temperature, at the
Max voltage listed in the following table. The Max values are measured with a
synthetic tool that forces maximum allowable bandwidth on the DRAM interface. It is
unknown if commercial SW management applications will be able to generate this
level of power consumption.
Table 11-3. Current Consumption in S3, S4, S5 with Intel® Active Management
Technology Operation (82Q35 GMCH Only)
IMCH_CL 1.25 V Supply Current for VCC_CL, VCCA_MPLL, 625 1501 mA 1,2
MCH with Intel AMT VCCA_HPLL
NOTES:
1. Estimate is only for max current coming through chipset’s supply pins, and is the ICC for the MCH only.
2. Icc max values are determined on a per-interface basis. Max currents cannot occur
simultaneously on all interfaces.
Datasheet 377
Electrical Characteristics
PCI Express* / PCI Express interface signals. These signals are compatible with PCI
Intel® sDVO Express 1.1 Signaling Environment AC Specifications and are AC coupled.
The buffers are not 3.3 V tolerant. Differential voltage spec =
(|D+ – D-|) * 2 = 1.2 Vmax. Single-ended maximum = 1.25 V. Single-
ended minimum = 0 V.
DMI Direct Media Interface signals. These signals are compatible with PCI
Express 1.0 Signaling Environment AC Specifications, but are DC coupled.
The buffers are not 3.3 V tolerant. Differential voltage spec = (|D+ - D-|)
* 2 = 1.2Vmax. Single-ended maximum = 1.25 V. Single-ended minimum
= 0 V.
GTL+ Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for
complete details.
HCSL Host Clock Signal Level buffers. Current mode differential pair. Differential
typical swing = (|D+ – D-|) * 2 = 1.4 V. Single ended input tolerant from
-0.35 V to 1.2 V. Typical crossing voltage 0.35 V.
SSTL-1.8 Stub Series Termination Logic. These are 1.8 V output capable buffers.
1.8 V tolerant.
SSTL-1.5 Stub Series Termination Logic. These are 1.5 V output capable buffers.
1.5 V tolerant.
378 Datasheet
Electrical Characteristics
Datasheet 379
Electrical Characteristics
Clocks
NOTES:
1. See Section 2.10 for Intel® sDVO & PCI Express* Pin Mapping
2. Current Mode Reference pin. DC specification not required.
380 Datasheet
Electrical Characteristics
11.4 DC Characteristics
The I/O buffer supply voltage is measured at the MCH package pins. The tolerances
shown in the following table are inclusive of all noise from DC up to 20 MHz. In the
lab, the voltage rails should be measured with a bandwidth limited oscilloscope with a
roll off of 3 dB/decade above 20 MHz under all operating conditions.
The following table indicates which supplies are connected directly to a voltage
regulator or to a filtered voltage rail. For voltages that are connected to a filter, they
should me measured at the input of the filter.
VCCA_EXP SDVO, PCI Express* Analog Supply Voltage 3.135 3.3 3.465 V 2
NOTES:
1. The VCCD_CRT and VCCDQ_CRT can also operate at a nominal 1.8 V +/- 5% input voltage. Only
the 1.5 V nominal voltage setting will be validated internally.
Datasheet 381
Electrical Characteristics
2. These rails are filtered from other voltage rails on the platform and should be measured at the
input of the filter. See the Platform Design Guide for proper implementation of the filter circuits.
3. VCCA_DAC voltage tolerance should only be measured when the DAC is turned ON and at a
stable resolution setting. Any noise on the DAC during power on or display resolution changes do
not impact the circuit.
4. MCH supports both Vtt=1.2V nominal and Vtt=1.1V nominal depending on the identified
processor.
Platform Reference Voltages at the top of the following table are specified at DC only.
Vref measurements should be made with respect to the supply voltage. Customers
should refer to the Platform Design Guide for proper decoupling of the Vref voltage
dividers on the platform.
Reference Voltages
Host Interface
VIH_H Host GTL+ Input High Voltage (0.666 x VTT_FSB VTT_FSB + 0.1 V
VTT_FSB) + 0.1
382 Datasheet
Electrical Characteristics
1.25V PCI Express* Interface 1.1 (includes PCI Express* and Intel® sDVO)
Datasheet 383
Electrical Characteristics
Input Clocks
SDVO_CTRLDATA, SDVO_CTRLCLK
CRT_DDC_DATA, CRT_DDC_CLK
CL_DATA, CL_CLK
384 Datasheet
Electrical Characteristics
CL_RST#
ICH_SYNCB
EXP_SLR, EXP_EN
Datasheet 385
Electrical Characteristics
CRT_HSYNC, CRT_VSYNC
NOTES:
1. Determined with 2x MCH Buffer Strength Settings into a 50 Ω to 0.5xVCC_DDR test load.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in
Transmitter compliance eye diagram of PCI Express* specification and measured over any 250
consecutive TX Uls.
3. Specified at the measurement point over any 250 consecutive Uls. The test load shown in
Receiver compliance eye diagram of PCI Express* spec should be used as the RX device when
taking measurements.
4. Applies to pin to VCC or VSS leakage current for the DDR_A_DQ_63:0 and DDR_B_DQ_63:0
signals.
5. Applies to pin to pin leakage current between DDR_A_DQS_7:0, DDR_A_DQSB_7:0,
DDR_B_DQS_7:0, and DDR_B_DQSB_7:0 signals.
6. Crossing voltage defined as instantaneous voltage when rising edge of BCLK0 equals falling edge
of BCLK1.
7. VHavg is the statistical average of the VH measured by the oscilloscope.
8. The crossing point must meet the absolute and relative crossing point specifications
simultaneously.
Refer to the appropriate processor Electrical, Mechanical, and Thermal Specifications for further
information.
386 Datasheet
Electrical Characteristics
1, 2, 4 (white
Max Luminance (full-scale) 0.665 0.700 0.770 V video level
voltage)
1, 3, 4 (black
Min Luminance — 0.000 — V video level
voltage)
Monotonicity ensured —
NOTES:
1. Measured at each R, G, B termination according to the VESA Test Procedure – Evaluation of
Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2. Max steady-state amplitude
3. Min steady-state amplitude
4. Defined for a double 75 Ω termination.
5. Set by external reference resistor value.
6. INL and DNL measured and calculated according to VESA Video Signal Standards.
7. Max full-scale voltage difference among R, G, B outputs (percentage of steady-state full-scale
voltage).
Datasheet 387
Ballout and Package Information
12.1 Ballout
Figure 12-1, Figure 12-2, and Figure 12-3 show the (G)MCH ballout diagram as
viewed from the top side of the package. The figures are divided into a left-side view
and right-side view of the package.
Note: Notes for Figure 12-1, Figure 12-2, and Figure 12-3, and Table 12-1 and Table 12-2.
1. Balls that are listed as RSVD are reserved.
2. Some balls marked as reserved (RSVD) are used in XOR testing. See Chapter 14
for details.
3. Balls that are listed as NC are No Connects.
4. Analog Display Signals (CRT_RED, CRT_REDB, CRT_GREEN, CRT_GREENB,
CRT_BLUE, CRT_BLUEB, CRT_IREF, CRT_HSYNC, CRT_VSYNC, CRT_DDC_CLK,
CRT_DDC_DATA) and the SDVO_CTRLCLK and SDVO_CTRLDATA signals are not
used on the 82P35 MCH. Contact your Intel field representative for proper
termination of the corresponding balls.
5. For the 82Q35, 82Q33, 82G33 GMCH, the PCI Express and SDVO signals are
multiplexed. However, only the PCI Express signal name is included in the
following ballout figures and table. See Section 2.10 for the PCI Express to SDVO
signal name mapping.
388 Datasheet
Ballout and Package Information
Figure 12-1. (G)MCH Ballout Diagram (Top View Left – Columns 43–30)
43 42 41 40 39 38 37 36 35 34 33 32 31 30
Datasheet 389
Ballout and Package Information
Figure 12-2. (G)MCH Ballout Diagram (Top View Middle– Columns 29–15)
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
DDR3_D
VCC_DD DDR_A_ VCC_DD
VSS VCC_DDR VSS RAMRST
R MA_12 R
BC B BC
DDR_B_ODT_ DDR_A_ DDR_A_ VCC_DD DDR_A_ VCC_DD DDR_B_ VCC_DD DDR_B_
DDR3_A_MA0 VCC_DDR VCC_DDR DDR_B_WEB VCC_DDR DDR_A_MA_3
BB 0 MA_5 MA_7 R CKE_2 R BS_0 R MA_1 BB
DDR_B_CSB_ DDR_B_ODT_ DDR_B_CSB_ DDR_B_CSB_ DDR_A_ DDR_A_ DDR_A_ DDR_A_ DDR_B_ DDR_B_
DDR_A_MA_2
BA 1 2 2 0 MA_6 MA_9 MA_14 CKE_3 MA_10 MA_2 BA
DDR_B_ODT_ DDR_B_MA_1 DDR_B_RAS DDR_A_ DDR_A_ DDR_A_ DDR_B_ DDR_B_
DDR_A_MA_1 DDR_A_MA_4
AY 3 3 B MA_11 BS_2 CKE_0 BS_1 MA_3 AY
DDR_B_ODT_ DDR_B_CKB_ DDR_B_CAS DDR_B_DQ_2 DDR_A_ VCC_DD DDR_A_ DDR_B_ DDR_B_
VCC_DDR
AW 1 4 B 9 MA_8 R CKE_1 DQ_23 MA_0 AW
DDR_B_DQ_2 DDR_A_ VCC_DD DDR_B_
DDR_B_CK_4 VSS VCC_DDR VSS VSS VSS
AV 4 DQ_31 R DQ_22 AV
DDR_B_CKB_ DDR_B_DQS DDR_B_DQ_2 DDR_A_ DDR_A_ DDR_B_ DDR_B_
DDR_B_CK_1 VSS VSS
AU 3 B_3 8 DQ_26 DQSB_3 DQ_18 DQ_16 AU
DDR_B_CKB_ DDR_B_DQ_2 DDR_B_DQS_ DDR_B_DQ_2 DDR_A_ DDR_A_ DDR_A_ DDR_B_
VSS VSS
AT 1 6 3 5 DQ_27 DQS_3 DQ_24 DQ_19 AT
DDR_B_DQ_3 DDR_A_ DDR_B_
DDR_B_CK_3 VSS VSS VSS VSS VSS VSS
AR 0 DQ_25 DQSB_2 AR
DDR_B_DQ_2 DDR_A_ DDR_A_ DDR_B_
DDR_A_CK_3 DDR_A_CK_1 VSS DDR_B_DM_3 RSVD VSS
AP 7 DQ_30 DQ_28 DQS_2 AP
DDR3_D
DDR_A_CKB_ DDR_B_DQ_3 DDR_A_ DDR_A_
VSS VSS VSS RSVD VSS RAM_PW
1 1 DM_3 DQ_29
AN ROK AN
DDR_A_CKB_ CL_PWR
VSS DDR_A_CK_4 VSS VSS RSVD VSS RSTINB PWROK
AM 4 OK AM
AL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL AL
AK VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL AK
AJ VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL AJ
AH AH
AG VCC_CL VCC_CL VCC_CL VCC_CL VCC VCC VCC VCC VCC VCC VCC VCC VCC AG
AF VCC_CL VCC_CL VCC VCC VCC VSS VCC VSS VCC VSS VCC VCC VCC AF
AE VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC AE
AD VCC_CL VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VCC AD
AC VCC_CL VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC AC
AB VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC AB
AA VCC_CL VCC VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC AA
Y VCC_CL VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VCC Y
W VCC VCC VCC VSS VCC VSS VCC VSS VCC VCC VCC W
V VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC V
U VSS VSS VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC U
T T
R RSVD VTT_FSB VTT_FSB VTT_FSB VTT_FSB VSS RSVD VCC VCC VCC R
P VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VSS VCC VSS VSS VCC P
N VTT_FSB VSS VTT_FSB VTT_FSB VTT_FSB VSS NC RSVD RSVD RSVD N
M VTT_FSB VSS FSB_DB_47 VTT_FSB VTT_FSB VSS VSS RSVD VSS VSS M
L VSS FSB_DB_42 FSB_DB_45 VTT_FSB VTT_FSB VSS VSS RSVD RSVD RSVD L
ALLZTES PEG_RX
FSB_DB_38 FSB_DB_43 VSS VTT_FSB VTT_FSB VSS VSS RSVD
K T P_1 K
PEG_RX
FSB_DB_40 VSS FSB_DB_46 VTT_FSB VTT_FSB VSS BSEL1 BSEL2 EXP_EN
J N_1 J
FSB_DSTBNB
VSS FSB_DB_44 VTT_FSB VTT_FSB VSS VSS RSVD VSS VSS
H _2 H
SDVO_C
FSB_DINVB_ FSB_DSTBPB RFU_G1
VTT_FSB VTT_FSB VTT_FSB VSS BSEL0 MTYPE TRLDAT
2 _2 5
G A G
XORTES
FSB_DB_41 VSS VTT_FSB VTT_FSB VTT_FSB VSS VSS RSVD VSS
F T F
EXP_SL SDVO_C CRT_VS
VTT_FSB VTT_FSB VTT_FSB VSS VTT_FSB VSS TCEN
E R TRLCLK YNC E
FSB_SCOMP CRT_BL CRT_GR
VTT_FSB VTT_FSB VTT_FSB FSB_DVREF FSB_RCOMP VSS VSS VSS VSS
D B UEB EENB D
VCCA_D VCCD_C CRT_GR CRT_RE VCCA_D CRT_HS
VTT_FSB VTT_FSB VSS FSB_SCOMP VCCA_HPLL
C PLLB RT EEN DB AC YNC C
FSB_ACCVR VCCDQ_ CRT_BL CRT_RE VCCA_D VCCAPL
VTT_FSB VTT_FSB VTT_FSB VSS FSB_SWING VSS VSS VSS VCC3_3
B EF CRT UE D AC L_EXP B
VCCA_D CRT_IRE VCCA_E
VTT_FSB VSS VCCA_MPLL VSS
A PLLA F XP A
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
390 Datasheet
Ballout and Package Information
Figure 12-3. (G)MCH Ballout Diagram (Top View Right – Columns 14–1)
14 13 12 11 10 9 8 7 6 5 4 3 2 1
DDR_B_CKE_ DDR_A_DQ_2
VCC_DDR VSS VSS VSS NC TEST1
BC 1 2 BC
DDR_B_MA_1 DDR_B_CKE_ DDR_A_DQ_1 DDR_A_DQ_1 DDR_A_DQ_2 DDR_A_DQ_1
DDR_B_MA_5 DDR_B_MA_8 VCC_DDR VSS DDR_A_DM_2 NC NC
BB 4 3 9 6 1 1 BB
DDR_B_MA_1 DDR_B_CKE_ DDR_A_DQ_1 DDR_A_DQSB DDR_A_DQ_2 DDR_A_DQ_1
DDR_B_MA_4 DDR_B_MA_7 RSVD VSS
BA 2 2 8 _2 0 0 BA
DDR_B_MA_1 DDR_A_DQ_2 DDR_A_DQS_ DDR_A_DQ_1 DDR_A_DQ_1 DDR_A_DQ_1
DDR_B_MA_9 DDR_B_BS_2 VSS
AY 1 3 2 7 5 4 AY
DDR_B_CKE_ DDR_A_DQS_ DDR_A_DQSB
DDR_B_DM_2 DDR_B_MA_6 DDR_B_DM_1 DDR_B_DQ_3 DDR_B_DQ_2 DDR_A_DM_1
AW 0 1 _1 AW
DDR_B_DQ_1 DDR_B_DQ_1 DDR_B_DQS_
VSS VSS VSS DDR_A_DQ_8 DDR_A_DQ_9 VSS
AV 7 4 0 AV
DDR_B_DQ_2 DDR_B_DQ_1 DDR_B_DQ_1 DDR_B_DQSB DDR_A_DQ_1 DDR_A_DQ_1
DDR_B_DQ_9 DDR_B_DQ_7 VSS VSS
AU 0 5 3 _0 2 3 AU
AT VSS VSS DDR_B_DQ_8 AT
DDR_B_DQ_1 DDR_B_DQS_ DDR_B_DQ_1
VSS DDR_B_DM_0 VSS DDR_A_DQ_6 DDR_A_DQ_7 DDR_A_DQ_3 DDR_A_DQ_2
AR 1 1 2 AR
DDR_B_DQ_1 DDR_B_DQSB DDR_A_DQSB DDR_A_DQS_
VSS
AP 0 _1 _0 0 AP
AN VSS VSS VSS DDR_B_DQ_6 DDR_B_DQ_1 DDR_B_DQ_0 DDR_B_DQ_5 DDR_B_DQ_4 VSS DDR_A_DQ_1 DDR_A_DM_0 AN
DDR_B_DQ_2 DDR_RCOMP DDR_RCOMP
VSS VSS VSS DDR_VREF CL_VREF VSS DDR_A_DQ_5 DDR_A_DQ_0
AM 1 VOH VOL AM
DDR_RCOMP DDR_RCOMP
VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL DDR_A_DQ_4
AL XPD XPU AL
AK VCC_CL VCC_CL VCC_CL VCC_CL AK
AJ VCC_CL VCC_CL VCC VCC VCC VCC VCC VCC VCC VCC VCC_CL VCC_CL VCC_CL AJ
AH VCC VCC VCC AH
AG VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC AG
AF VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VCC VCC VCC AF
AE VSS VSS VSS AE
AD VCC CL_CLK CL_DATA VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP AD
AC VCC VCC EXP_COMPI EXP_COMPO VSS DMI_TXN_2 DMI_TXP_2 VSS VCC VSS VCC_EXP VCC_EXP VCC_EXP AC
AB DMI_RXP_3 VSS VSS AB
AA VCC VCC CL_RSTB RSVD RSVD RSVD VSS DMI_RXP_2 DMI_RXN_2 VSS DMI_RXN_3 VCC DMI_TXN_3 AA
Y VCC VCC RSVD VCC VSS DMI_RXN_1 DMI_RXP_1 VSS VCC VSS DMI_TXN_1 DMI_TXP_3 VSS Y
W DMI_TXP_1 VSS DMI_RXP_0 W
V VCC VCC VCC VSS VCC VCC VSS DMI_TXP_0 DMI_TXN_0 VSS PEG_TXP_15 VSS DMI_RXN_0 V
U VCC VCC RSVD RSVD VCC VCC VSS VSS VCC VSS PEG_TXN_15 VCC PEG_TXP_14 U
T PEG_RXP_14 PEG_TXN_14 VSS T
R VCC RSVD RSVD VSS PEG_RXN_13 PEG_RXP_13 VSS PEG_RXN_15 PEG_RXP_15 VSS PEG_RXN_14 VSS PEG_TXP_13 R
P VCC PEG_TXP_12 VSS PEG_TXN_13 P
N VSS VCC VCC VSS VCC VCC VSS VCC VSS PEG_TXN_12 VCC PEG_TXP_11 N
CRT_DDC_CL
VSS VSS PEG_RXN_10 PEG_RXP_10 VSS PEG_RXN_12 PEG_RXP_12 PEG_RXP_11 PEG_TXN_11 VSS
M K M
CRT_DDC_DA
VCC VSS PEG_RXP_9 PEG_RXN_9 VSS VCC VSS PEG_RXN_11 VSS PEG_TXP_10
L TA L
K VSS VSS PEG_TXN_9 VSS PEG_TXN_10 K
J ICH_SYNCB PEG_RXP_3 PEG_RXP_4 VSS VSS VCC VSS PEG_TXP_9 VCC VCC J
H VSS PEG_RXN_3 PEG_RXN_4 H
G VSS VSS VSS VSS VSS PEG_RXP_8 PEG_RXN_8 PEG_TXN_8 VCC VSS G
F PEG_RXP_0 PEG_RXP_2 VCC VCC PEG_RXP_5 PEG_RXN_6 PEG_TXP_8 VSS PEG_TXP_7 F
E PEG_RXN_0 PEG_RXN_2 VSS VSS PEG_RXN_5 PEG_RXP_6 VSS PEG_TXN_7 VSS E
DPL_REFCLKI
PEG_TXN_0 PEG_TXP_0 PEG_TXN_2 PEG_TXP_4 PEG_TXN_4 VCC VSS PEG_RXN_7
D NN D
DPL_REFCLKI
VCC VSS PEG_TXP_2 VCC VSS VSS VSS PEG_RXP_7 VSS
C NP C
B VSS EXP_CLKINN EXP_CLKINP PEG_TXP_1 VSS PEG_TXP_3 PEG_TXN_3 PEG_TXN_5 PEG_TXP_5 PEG_TXN_6 PEG_TXP_6 NC B
A RSVD VSS PEG_TXN_1 VSS VSS VSS A
14 13 12 11 10 9 8 7 6 5 4 3 2 1
Datasheet 391
Ballout and Package Information
392 Datasheet
Ballout and Package Information
Datasheet 393
Ballout and Package Information
394 Datasheet
Ballout and Package Information
Datasheet 395
Ballout and Package Information
396 Datasheet
Ballout and Package Information
Datasheet 397
Ballout and Package Information
398 Datasheet
Ballout and Package Information
Datasheet 399
Ballout and Package Information
400 Datasheet
Ballout and Package Information
Datasheet 401
Ballout and Package Information
402 Datasheet
Ballout and Package Information
Datasheet 403
Ballout and Package Information
404 Datasheet
Ballout and Package Information
Datasheet 405
Ballout and Package Information
406 Datasheet
Ballout and Package Information
Datasheet 407
Ballout and Package Information
408 Datasheet
Ballout and Package Information
Datasheet 409
Ballout and Package Information
410 Datasheet
Ballout and Package Information
Datasheet 411
Ballout and Package Information
412 Datasheet
Ballout and Package Information
Datasheet 413
Ballout and Package Information
414 Datasheet
Ballout and Package Information
Datasheet 415
Ballout and Package Information
416 Datasheet
Ballout and Package Information
Datasheet 417
Ballout and Package Information
418 Datasheet
Ballout and Package Information
Datasheet 419
Ballout and Package Information
420 Datasheet
Ballout and Package Information
Datasheet 421
Ballout and Package Information
422 Datasheet
Ballout and Package Information
Datasheet 423
Package Specifications
13 Package Specifications
The (G)MCH is available in a 34 mm [1.34 in] x 34 mm [1.34 in] Flip Chip Ball Grid
Array (FC-BGA) package with 1226 solder balls. The (G)MCH package uses a “balls
anywhere” concept. Minimum ball pitch is 0.8 mm [0.031 in], but ball ordering does
not follow a 0.8 mm grid. Figure 13-1 shows the package dimensions.
424 Datasheet
Package Specifications
Datasheet 425
Testability
14 Testability
In the (G)MCH, testability for Automated Test Equipment (ATE) board level testing has
been implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with
one input pin connected to it which allows for pad to ball to trace connection testing.
The XOR testing methodology is to boot the part using straps to enter XOR mode (A
description of the boot process follows). Once in XOR mode, all of the pins of an XOR
chain are driven to logic 1. This action will force the output of that XOR chain to either
a 1 if the number of the pins making up the chain is even or a 0 if the number of the
pins making up the chain is odd.
Once a valid output is detected on the XOR chain output, a walking 0 pattern is moved
from one end of the chain to the other. Every time the walking 0 is applied to a pin on
the chain, the output will toggle. If the output does not toggle, there is a disconnect
somewhere between die, package, and board and the system can be considered a
failure.
CL_PWROK
PWROK
CL_RST#
RSTIN#
STRAP PINS
HCLKP/GCLKP
HCLKN/GCLKN
XOR inputs
XOR output X
XOR
426 Datasheet
Testability
The above figure shows the wave forms to be able to boot the part into XOR mode.
The straps that need to be controlled during this boot process are BSEL[2:0],
SDVO_CTRLDATA, EXP_EM, EXP_SLR, and XORTEST.
On Broadwater platforms, all strap values must be driven before PWROK asserts.
BSEL0 must be a 1. BSEL[2:1] need to be defined values, but logic value in any order
will do. XORTEST must be driven to 0.
Because of the different functionalities of the SDVO/PCI Express interface, not all of
the pins will be used in all implementations. Due to the need to minimize test points
and unnecessary routing, the XOR Chain 14 is dynamic depending on the values of
SDVO_CTRLDATA, EXP_SLR, and EXP_EN. See Table 14-1 for what parts of XOR Chain
14 become valid XOR inputs depending on the use of SDVO_CTRLDATA, EXP_SLR, and
EXP_EN.
EXP_RXP[15:0]
EXP_RXN[15:0]
0 1 0
EXP_TXP[15:0]
EXP_TXN[15:0]
EXP_RXP[15:0]
EXP_RXN[15:0]
0 1 1
EXP_TXP[15:0]
EXP_TXN[15:0]
EXP_RXP[15:8]
EXP_RXN[15:8]
1 0 0
EXP_TXP[15:8]
EXP_TXN[15:8]
EXP_RXP[7:0]
EXP_RXN[7:0]
1 0 1
EXP_TXP[7:0]
EXP_TXN[7:0]
EXP_RXP[15:0]
EXP_RXN[15:0]
1 1 0
EXP_TXP[15:0]
EXP_TXN[15:0]
EXP_RXP[15:0]
EXP_RXN[15:0]
1 1 1
EXP_TXP[15:0]
EXP_TXN[15:0]
Datasheet 427
Testability
428 Datasheet
Testability
Datasheet 429
Testability
29 V36 FSB_AB_22
30 R38 FSB_AB_23
Table 14-4. XOR Chain 1
31 U34 FSB_ADSTBB_1
Pin Ball
Count # Signal Name 32 R37 FSB_AB_19
33 AA37 FSB_AB_35
1 L37 FSB_AB_6
34 U37 FSB_AB_17
2 N35 FSB_AB_15
35 N39 FSB_AB_18
3 L36 FSB_AB_7
36 V38 FSB_AB_31
4 L39 FSB_AB_4
37 R39 FSB_AB_21
5 M38 FSB_AB_11
38 Y36 FSB_AB_32
6 L38 FSB_REQB_2
39 V35 FSB_AB_28
7 J37 FSB_REQB_4
40 P42 FSB_AB_20
8 N34 FSB_AB_10
9 L35 FSB_REQB_1
430 Datasheet
Testability
12 AU31 DDR_A_CKB_0
13 AN27 DDR_A_CKB_1
Table 14-6. XOR Chain 3
14 AP27 DDR_A_CK_1
Pin Ball
Count # Signal Name 15 BA21 DDR_A_MA_9
29 BB6 DDR_A_DM_2
30 AW1 DDR_A_DQSB_1
Table 14-7. XOR Chain 4
31 AW3 DDR_A_DM_1
Pin Ball
Count # Signal Name 32 AP3 DDR_A_DQSB_0
33 AN2 DDR_A_DM_0
1 BB35 DDR_A_ODT_0
2 AY35 DDR_A_CSB_1
3 AY37 DDR3_A_CSB1
4 BA38 DDR_A_ODT_1
5 BB31 DDR_A_MA_10
6 BA34 DDR_A_CSB_0
7 BB29 DDR3_A_MA0
Datasheet 431
Testability
10 AG42 DDR_A_DQS_6
1 AC41 DDR_A_DQSB_7
11 AH43 DDR_A_DQ_49
2 AC40 DDR_A_DM_7
12 AE40 DDR_A_DQ_51
3 AG41 DDR_A_DQSB_6
13 AJ41 DDR_A_DQ_53
4 AG40 DDR_A_DM_6
14 AF42 DDR_A_DQ_55
5 AL40 DDR_A_DQSB_5
15 AF41 DDR_A_DQ_54
6 AM43 DDR_A_DM_5
16 AJ42 DDR_A_DQ_52
7 AR40 DDR_A_DQSB_4
17 AJ40 DDR_A_DQ_48
8 AU43 DDR_A_DM_4
18 AF39 DDR_A_DQ_50
9 AY38 DDR_A_MA_13
19 AL41 DDR_A_DQS_5
10 AW35 DDR_A_CASB
20 AL39 DDR_A_DQ_47
11 AY31 DDR_A_BS_1
21 AN40 DDR_A_DQ_44
12 BA31 DDR_A_BS_0
22 AM39 DDR_A_DQ_41
13 BB34 DDR3_A_WEB
23 AL42 DDR_A_DQ_46
14 AY33 DDR_A_RASB
24 AN41 DDR_A_DQ_40
15 BA33 DDR_A_WEB
25 AK42 DDR_A_DQ_42
16 AY20 DDR_A_BS_2
26 AN42 DDR_A_DQ_45
17 AY21 DDR_A_MA_11
27 AK41 DDR_A_DQ_43
18 BA19 DDR_A_MA_14
28 AR41 DDR_A_DQS_4
19 BC20 DDR_A_MA_12
29 AV40 DDR_A_DQ_36
30 AV42 DDR_A_DQ_32
Table 14-9. XOR Chain 6
31 AP41 DDR_A_DQ_39
Pin Ball 32 AN39 DDR_A_DQ_35
Count # Signal Name
33 AU40 DDR_A_DQ_33
1 AC42 DDR_A_DQS_7
34 AV41 DDR_A_DQ_37
2 AB41 DDR_A_DQ_58
35 AP42 DDR_A_DQ_34
3 AE42 DDR_A_DQ_60
36 AR42 DDR_A_DQ_38
4 AD43 DDR_A_DQ_57
37 AT20 DDR_A_DQS_3
5 AB42 DDR_A_DQ_63
38 AR18 DDR_A_DQ_25
6 AA40 DDR_A_DQ_59
39 AU21 DDR_A_DQ_26
7 AC39 DDR_A_DQ_62
40 AV20 DDR_A_DQ_31
8 AE41 DDR_A_DQ_61
41 AP20 DDR_A_DQ_30
432 Datasheet
Testability
55 AW2 DDR_A_DQS_1
56 AY3 DDR_A_DQ_15
Table 14-11. XOR Chain 8
57 BA4 DDR_A_DQ_10
Pin Ball
58 BB3 DDR_A_DQ_11 Count # Signal Name
15 BA17 DDR_B_MA_10
Datasheet 433
Testability
22 AW12 DDR_B_MA_6
23 AY15 DDR_B_MA_3
Table 14-13. XOR Chain 10
24 AU26 DDR_B_DQSB_3
Pin Ball
25 AP23 DDR_B_DM_3 Count # Signal Name
7 AD36 DDR_B_DQ_56
9 AD34 DDR_B_DQ_60
Pin Ball
Count # Signal Name 10 AG35 DDR_B_DQS_6
434 Datasheet
Testability
40 AT23 DDR_B_DQ_25
41 AV24 DDR_B_DQ_24
Table 14-14. XOR Chain 11
42 AR24 DDR_B_DQ_30
Pin Ball
43 AW23 DDR_B_DQ_29 Count # Signal Name
Datasheet 435
Testability
3 R7 PEG_RXN_15
5 T2 PEG_TXN_14
Pin Ball
Count # Signal Name
6 U2 PEG_TXP_14
1 G17 SDVO_CTRLDATA 7 R4 PEG_RXN_14
2 E17 SDVO_CTRLCLK 8 T4 PEG_RXP_14
3 L13 CRT_DDC_DATA 9 P1 PEG_TXN_13
4 M13 CRT_DDC_CLK 10 R2 PEG_TXP_13
11 R10 PEG_RXN_13
Table 14-16. XOR Chain 13 12 R9 PEG_RXP_13
31 G5 PEG_RXN_8
32 G6 PEG_RXP_8
33 E2 PEG_TXN_7
436 Datasheet
Testability
34 F2 PEG_TXP_7 50 B9 PEG_TXP_3
37 B4 PEG_TXN_6 53 D9 PEG_TXN_2
49 B7 PEG_TXN_3
Datasheet 437
Intel:
LE82Q35 S LJA7