aE GCOMN, Inc. Technical NOG 3.6 pi pm plem piam pi Getting Gain out of Power GaAsFETs Meme Mees Lee Mee bee Steve C. CrippsMaticom.. inc. Technical Notes 3.6 Getting Gain Out of Power GaAsFETS Steve C. Cripps 1. Introduction Despite being well into its third decade of commercial availability, the GaAsFET still has an unenviable reputation as an unfriendly device which is very difficult to match. This is particularly so for medium and high power devices, which seem reluctant to yield their minimum -never mind typical- data sheet gain and power performance parameters. The facts are that GaAsFETs, especially high power GaAsFETs, are difficult to match, but manufacturers’ data is usually correct. If your design is giving lower gain, you are probably doing something wrong, and the purpose of this note is to highlight some of the “traps” that await the ‘unwary when venturing into higher power amplifier design for the first time. 2. Background ‘The input, or gate, of a GaAsFET can be quite accurately modelled over a very wide frequency range as a series R-C network (Fig.1). Most manufacturers, and designers, try to reference their measurements to the chip itself, so that the bondwire inductance can be considered to be part of the external matching network. The basic action of the GaAsFET is transconductive, a current being generated in the drain circuit which is directly proportional to the voltage across the gate-source Vin ar junction which is a reverse biased Schottky barrier diode, At small signal levels, the RF impedance of the gate diode is mainly a capacitance, since the reverse biased junction resistance is so high. The series gate resistance is physically attributed to the resistance of the undepleted GaAs in the channel between the source and gate contacts, the gate metal, and the contact resistance. These resistive elements are purely parasitie; in an ideal device they would be absent, and much of the development activities of device technologists are directed at reducing them. Unfortunately, this means that as the cutoff frequency increases, the chances of having. anything substantially resistive to match into will decrease. The situation does not improve as the device periphery is increased to make a higher power device; the gate resistance scales downwards to fractions of an Ohm, and the capacitance grows to ‘uncomfortably high values for microwave work. In fairness to the device technologists,it should be noted here that the term “matching” means different things to different people. In this note, the primary function of the matching network is to obtain the maximum -or at least useable- gain from the device. ‘The engineer's need to present a 50 Ohm interface with the outside world is of secondary importance, and can, if necessary, be achieved using other techniques (eg. balanced stages or isolators). There is a strange irony in GaAsFET matching, in that the matching target is comprised entirely of undesirable parasitic elements that would be absent in an ideal device. One of the prime causes of lost gain in a power GaAsFET amplifier circuit is inadvertent addition to the series gate resistance. This is the major theme for this whole note, and merits quantitative examination before proceeding any further. Fig 2 shows a simplified schematic diagram of a GaAsFET input and matching network. For the purposes of analysis, the matching circuit,nt Fig. 2. GaAsFET Input Match &. consists of an ideal transformer which transforms the source impedance down to an optimum resistive value, with a series inductance to resonate out the gate capacitance. The drain enrrent is assumed to be directly proportional to the voltage across the gate junction, Vj. This voltage can therefore be taken as a relative measure of voltage gain for the whole devico. Clearly, maximum voltage swing across the gate capacitor will coincide with maximum current through the circuit, which in turn corresponds to maximum power dissipation in the resistor R,. This condition is, of course, the conjugate match condition: (V2)"CNR,R,) If now an extra resistor Rp) is inserted in sories with R,, and the transformer re-adjusted to the optimum value, the junction voltage will become (eB) NTR R RD) so that the change in available power gain of the device will be (WyMpP = RyRy) For example, a medium power (1 Watt) device such as a JS8855-AS has Ry = 0.7 Ohm, so that a series resistance in the gate circuit of 0.7 Ohm causes a reduction in available gain of 3 dB, This formula will be used in the following sections to quantify some common causes of “phantom” resistors appearing in the gate matching circuit. 2, Small Signal to Medium Power - the Traps 2.1 S-parameters Fig. 3 shows simplified circuit models for the gate input of a small signal device (JS8819-AS) and a medium power (1W) device (JS8855-AS). Also listed is the measured magnitude and phase of the $y parameter for each device at 14 GHz. By themselves, these numbers hint right away at some of the hidden problems and subsequent frustrations of the unwary designer. Clearly, if the Rg ofa JS8855-AS is 0.7 Ohm, it is entirely reasonable that its S11 magnitude should be close to unity. But which came first, the Si measurement, or the Ry value? If Rg were 1 Re | Co | gm | S14GHz) | “Mismatch” gain (600) [FET a | pF | ms | MAG ANG | =(11-181112)XaB) sssi-as | 6 | 0.35] 44 | 0.845 -118 54 IS8855-AS | 0.7 | 25 | 300 | 0.973 -171 127 (1.0) } (2.5) | (800) | (0.961 -170) any Fig. 3. GaAsFET Input ParametersAttenuation(dB) 10 fe 0.25 Rp tb 0.05 Ohm, not 0.7, the device would have an Sy; of 0.961 instead of 0.973 and the gain predicted from the 5 parameters would be 1.6 dB lower at 14GHz. Can we measure S-parameters that accurately? ‘The answer is possibly, but as the device periphery increases further, the input impedance becomes 50 far from 50 Ohms that measuring it with a network analyser is something similar to measuring the thickness of 1 mil aluminum foil by precision ‘machining 0,999 inches off a 1 inch block. Generally speaking, manufacturers of power GaAsFETs use alternative methods to infer some of the circuit model parameters, and the s parameters are then computed from the model. Gain predictions based on measured s-parameters -no matter how dilligently corrected, de-embedded, or whatever- are increasingly unreliable for larger devices. ‘TRAP #1: DON’T DEPEND ON MEASURED S PARAMETERS 2.2 Circuit and fixture losses Fig. 4 shows a familiar circuit, a matched 50 Ohm Pi attenuator. The resistor values in the table are for R(Q) Ry) Gain Loss (4B) 60 350 98 16 3300 5.0 03 17,000 15 Fig. 4. Effect of Input Attenuators on Gain (JS8855-AS) less familiar values of attenuation; 14B, .254B, and .05 dB. Alongside each of these imaginary attenuators is the reduction in gain of a JS8855-AS if the test fixture input losses were represented by the attenuation value. The numbers are quite shocking, and can be seen to arise because of the low value of gate resistance. Note especially that the gain losses are multiplied up many times from the matched attenuation value. This can be a gross source of error in many standard ANA de- embedding. Almost any measurable series resistance at the gate will have a catastrophic effect on the gain of the device; hundredths of a dB will count. ‘This has several important implications. Firstly, in simulating matching networks, losses have to be included, and if they are it will be discovered that, not only must the device be matched with an absolute minimum length of transmission line at the gate, the resistive losses of even a short length will be significant. Typically, linear simulation programs cannot model losses with sufficient accuracy, and the exact nuances of individual matching networks have to be discovered by experiment, What works fine on the computer can be @ frustrating failure in practice. Omg Fig. 5. GaAsFET With Source InductanceSubstrate Fig. 6. Typical FET Mounting Configuration ‘TRAP #2: CIRCUIT LOSSES- ANYTHING AT ALL 1S PROBABLY TOO MUCH 2.3 Source inductance ‘The evils of common lead inductance have been well covered over the years; the use of source vias on larger GaAsFETs is a clear and visible warning of potential trouble for the unwary. Fig.5 shows a simplified equivalent circuit of a GaAsFET with a common lead source inductance. Some circuit analysis gives the following relations: Vin = Ryt GC gMlin + j0La(GmVj + Tin) Vj= Tin(aC,) substituting for V;, the input impedance of the cireuit is given by: Vinllin = Rg + Uj@Cg + jobs + Bm*Le/C; ‘These equations show that one effect of the source induetance is to generate a “phantom” resistance in the gate circuit of magnitude gm*Le/Cgs. This resistance adds directly to the gate resistance, lowers the Q of the gate capacitor, and lowers the cutoff frequency of the device. Equation (1) can again be used to quantify the amount of gain reduction for different values of Ly. For a JS8855, 4 m=300 mS, Cpy=2.6 pF so the following table can be compiled: Source Ly Rpa() Gain Reduction 7) (Biy=0.70) B 0.01 135 42 0.005, 0.58 24 0.002 0.23 08 0.001 0.12 04 Once again, the results are shocking; we probably don't even have a good feel for what a .001 nH (1 pH) inductor looks like, but it sounds pretty small. Note also that these numbers refer to a JS8855, only a moderate sized 1 Watt device; the loss of gain increases as the square of the transconductance, ‘This analysis is, of course, very idealized; in practice non-unilateral effects and the output matching network would modify the absolute gain numbers considerably, but this does not alter the overall conclusion. The fact that such a tiny amount of source inductance can have a detrimental effect on gain means that the physical configuration starts to become very critical. Fig 6 shows a typical, and very convenient FET mounting arrangement, widely used. The device chip is die attached to a “rib” which raises its level to the substrate height for convenience -and shortness- of wirebonding. The rib can also be made from a good thermally conductiveFig. 7. Ground Current Disconinuity problem material, possibly different from the circuit carrier. Unfortunately, convenient and familiar though this arrangement may be, it can be a disaster for larger FETs at higher frequencies. The device is not ‘connected to the cireuit ground; the groundplane discontinuity is a common lead inductance and can cause serious gain degradation. ‘TRAP #3: FET MOUNTING RIBS AND BARS CAN BE CATASTROPHICALLY INDUCTIVE 2.4 Configurational parasities Perhaps the most common trap of all, one that even ‘those who have survived #s 1-3 fall into, is a more subtle common lead inductance problem, once again something not predicted by a circuit simulator. Fig. 7 shows a top view of the circuit in Fig.6. The designer has a computer which has optimized a nice simple matching network; a series inductance which is mainly the gate bonding wires, followed by a pair of low impedance open circuit shunt stubs acting as a substantial shunt capacitance. Unfortunately, the computer does not take account of the fact that the ground currents flowing under the stub are physically distant from the compact FET chip, and there will be some inductance in the ground return paths; once again the FET souree is not connected directly to the circuit ground, in this case because the circuit ground itself is not well defined. This, “configurational” inductance can easily be large enough to cause as much trouble as a mounting rib, In practice, the physical configuration of the die and the circuit elements are so critical that some departures from standard assembly techniques and materials may be required. As a very general guideline, the first shunt capacitive matching element should be made physically compatible with the die in terms of height and length. This usually means using a material with higher dielectric constant than alumina. ‘TRAP #4: CONFIGURATIONAL PARASITICS CAN BE AS IMPORTANT AS CIRCUIT ELEMENTS. 2.5 Thermal effects It is commonly believed that GaAs is such a poor thermal conductor that in any given situation most, of the temperature differential occurs in the few mils of GaAs between the active region and the heatsink to which the die is attached. Although this may be true up to a point, it is a very poor basis for proper heatsink design. It is an unfortunate fact that as power FETs inerease in electrical size, they do not, in general, increase their physical area at the same rate. This thermal contradiction is sometimes alleviated by use of thinner chips and/or plated heatsinks, but it is generally true to say that the function of the chip mount has to double up ag a heat spreader, as well as a simple heat conductor, for larger size chips. For example, the popular raised rib in Fig.5 falls down again, due to its restrictedFET Chip (~3mil) Fig. 8. Internally Matched 8 watt GaAsFETarea for heatspreading to take place. Another commonly held belief is that the thermal resistance of a die attach is a simple function of the thermal conductivity and thickness of the die attach material -if the layer is thin enough, the contribution of the die attach to the overall ‘temperature rise is negligible. This view is widely touted by epoxy vendors and hybrid assembly supervisors who find epoxy die attach requires less skill and can be more easily automated. The fallacy lies in the integrity of the contact or “wetting” of the metal surfaces by the die attach material; in general this is much lower for an epoxy die attach than a eutectic process. A detailed discussion of all aspects of thermal design for power GaAsFETs is beyond the scope of this note. In particular, it is not our mission to condemn, epoxy die attach or ceramic heatsinks; much technological progress has been made in these materials recently. ‘The important point is that hot, FETs have lower gain, and this can be easily blamed on electrical performance. A simple test can be performed to measure the effectiveness of your heat sink; if your amplifier is giving more than 1 dB higher gain at 6v supply than at 9v, you have a thermal problem [1]. TRAP #5: HOT FETS HAVE LOW GAIN 8. If They Can Do It... One of the best and most accesible design examples of how best to bypass the above set of “traps” and make something which works is Toshiba's own line of internally matched GaAsFETs. Fig. 8 shows diagramatically the key features of a TIM5964-8 device. Both the input and output are matched using a double section lowpass network. On the gate side, the series resonating inductance at the gate is, realized almost entirely by the bonding wires, which rrun between the gate pad and a chip eapacitor. This, chip capacitor is the key to obtaining maximum gain from the device. ‘The side view (Fig. 8(b)) shows that. the capacitor is a similar height to the GaAs chip. Both input and output matching capacitors are essentially mounted at the same groundplane level as the chip. (For ease of assembly, the chip is, in fact, raised on a small ridge, but this is only about .001 inches above the main “rib” of the package). The second section of matching, in each case, is done on a more conventional alumina substrate. The important feature is that the step in groundplane height required to accommodate the alumina substrates is not placed directly in the first, matching current loop, so that common lead effects are greatly reduced. ‘The gate matching capacitor has to be a similar height and width to match the dimensions of tho FET chip, in order to minimize configurational parasitics. This does not leave much flexibility in realizing a specific capacitor value which can run higher than 10 pF for larger chips, even at 14GHz, Careful selection of dielectric material has to be made; too low of a @ factor can be as devastating as the traps listed in section 2. Fortunately, good microwave characterization data is available from some capacitor vendors for the design of custom parts (2]. In general, ceramic rather than MIS. capacitors are used in these applications; MIS capacitors have a series substrate resistance which ‘ean be comparable, or even higher than, the FET gate resistance. ‘A thermal note; the carrier is machined from a copper tungsten composite material. These materials have been developed for applications requiring good thermal conductivity coupled with a low expansion coefficient which can be matched to ceramic materials such as alumina. They are highly recommended in these applications (3 4. Conclusions High power GaAsFETs have some extreme parameters, notably high transconductance and low input resistance, which create traps for the designer who is more accustomed to lower power devices. ‘Most of these traps do not show up using standard linear simulation programs. If these traps are avoided, or at least recognized, data sheet performance can be obtained from these devices. Dr. Steve C. Cripps is a consulting engineer at ‘Matcom. References 1. “Lechnique Simplifies Thermal Screening of Microwave Hybrids, S.C. Cripps, Microwaves & RF, Feb. 1990, pp 103-107 2. Dielectric Labs, Route 20 Kast, Cazenovia, NY 13035 3. C.M.W., 70, South Gray St., P.O. Box 2266, Indianapolis, IN 46206MATCOM Technical Notes 1. Small-Signal Analysis 1.1 A Practical Guide to GaAs FET Gain and Stability Criteria Steve C. Cripps 1.2 The Frequency Dependence of Stability Factor for Common-Source GaAs MESFETs George D. Vendelin 2. Non-Linear Effects 2.1 Intermodulation and Harmonic Distortion in GaAs FET Amplifiers Steve C. Cripps 3. Large-Signal Analysis 98.1 Large-Signal Analysis of Medium Power GaAs MESFET: JS8850A-AS at 15 GHz George D. Vendelin 3.2 Power GaAs FET Matching Network Design Steve C. Cripps 8.3 Load Terminations for Maximum Output power using the Toshiba JS8850 Series of GaAs FETs George D. Vendelin 8.4 Large-Signal SPICE Models for JS8850A-AS George D. Vendelin 3.5 An Introduction to High Efficiency GaAsFET Amplifier Modes Steve C. Cripps 3.6 Getting Gain out of Power GaAsFETs Steve C. CrippsMatcom Sales Offices ARIZONA, NEW MEXICO Ken Shade Blackhart Associates 6120 N. Desert Foothill Dr. ‘Pueson, AZ 85743 ‘Tel (602) 579-0399 FAX(602) 579-0998 COLORADO, UTAH Jim Spear Blackhart Associates 348 Vista Dr. Silt, CO 81652 ‘Tel (803) 876-5605 FAX (803) 876-5443 SOUTHERN CALIFORNIA Bill Waskowitz HyTech Associates 717-B Lakefield Rd. Westlake Village, CA 91361 Tel (818) 991-7491 FAX (805) 379-2128 GEORGIA, ALABAMA, TENNESSEE, NORTH CAROLINA, SOUTH CAROLINA Jerry Archbold Spartech Associates, Ine. 704 Holcomb Bridge Rd. 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