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    GaAs FET Power Amplifier Design (Matcom TN3r2)

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    GaAs FET Power Amplifier Design, Cripps, Small Signal Gain, Max Output Power, Load Pull Characteristics, Output Termination, Load Lines, Large Signal FET Model, Ropt, Cds, JS8851-AS

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    GaAs FET Power Amplifier Design (Matcom TN3r2)

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    fahkingmoron
    287 views11 pages
    GaAs FET Power Amplifier Design, Cripps, Small Signal Gain, Max Output Power, Load Pull Characteristics, Output Termination, Load Lines, Large Signal FET Model, Ropt, Cds, JS8851-AS

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    GaAs FET Power Amplifier Design [Matcom TN3r2]

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    GaAs FET Power Amplifier Design, Cripps, Small Signal Gain, Max Output Power, Load Pull Characteristics, Output Termination, Load Lines, Large Signal FET Model, Ropt, Cds, JS8851-AS

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    287 views11 pages

    GaAs FET Power Amplifier Design (Matcom TN3r2)

    Uploaded by

    fahkingmoron
    GaAs FET Power Amplifier Design, Cripps, Small Signal Gain, Max Output Power, Load Pull Characteristics, Output Termination, Load Lines, Large Signal FET Model, Ropt, Cds, JS8851-AS

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    Smaicom. i GaAsFET Power Amplifier Design Se ee Steve C. Cripps Matcom. inc. Technical Notes 3.2 GaAsFET Power Amplifier Design Steve C. Cripps Introduction This note describes a technique for designing GaAsFET power amplifiers, which was originally presented at the MTT Symposium in 1983 [1]. The original intent of the paper was to show how, with some modifications to take care of higher frequency effects, power GaAsFETs can be matched for optimum power using techniques well established for many years at audio and RF frequencies. Even in 1983, much had already been published on lengthy and expensive characterisation and modeling procedures for microwave power GaAs FETs that ‘were way outside the time and budget constraints of most designers. There was a need for something simple; maybe approximate, but a practical design method for designers who didn’t have that much time. On the face of it, the situation today (early 1991) would appear to be different. Microwave CAD software is now widely available, and even older microwave circuit stalwarts have largely given in to the speed and efficacy of digital simulation. Unfortunately, derivation of a model which accurately simulates the non-linear behaviour of a real microwave GaAsFET device has turned out to be a stumbling block for software vendors. Much effort is still underway to resolve this problem, and probably in the course of time an acceptable answer will be found [2]. Two particularly troublesome features of currently available non-linear models are their “propriety”, and/or the requirement for a vast number of measured data points to model a specific device. So this note presents a technique which remains what it was always intended to be; simple, low cost, approximate, for those who need something quick and easy. Some Practical Observations ‘An hour or s0 spent tuning a power device gives a lot of insight into the power matching problem, and is recommended for anyone starting off on a microwave power amplifier design. Most GaAsFET devices, from small signal up to multiwatt types, can be summarised as showing the following general characteristics: 1. Tuning the output for maximum small signal gain results in significantly lower power than the device specification (typically 1-3 4B less, depending on the deviee). 2, Tuning for maximum power results in lower gain, but the decrease in gain is less than the inerease in power. 3. Tuning for maximum saturated power is quite easy, and gives a well defined optimum point. ‘The 1 dB compression power shows a very similar increase to the saturated power under these tuning conditions. 4. Output power performance is virtually independent of input tuning. Fig. 1 shows these characteristics in graphical form, ‘The two curves correspond, approximately, to the same device under the same bias conditions, but with the two different tuning conditions. Observation (3) above is worth some further discussion, since in some ways it is the key to the whole of the present approach to power matching, Referring to Fig. 1 again, three points (A, B, C) have been identified on each curve. Each of these points represents a criterion for output power. Point B is the familiar 14B compression point; point C is the equally familiar but less-well defined saturation 32 30 _ 8 E y g NY 3 ws é / 26 4 Small-Signal Tuning / — Optimum Power Tuning a iy ©,C! =Sat. Powers L| BB = 1 dB Gain Comp, Powers AA) = Max. Linear Powers I I 1 19 at 23 25 27 29 3t Pin (dBm) Fig. 1. P;,,- Poy: characteristics of a typical 1W GaAs FET power level; point A is called the maximum linear ower, corresponding to the maximum power level at which the device has no measurable compression. Note that the increase in power between the experimental curves in going from gain tuning to power tuning is approximately the same, regardless of the power criterion (A, B, or ©) which is used. In other words, to determine the conditions for optimum power performance, we only need. to consider the linear case (A). ‘This is rather surprising. The assumption that matching a transistor for optimum power inevitably involves harmonic as well as fundamental terminations has a reasonable theoretical foundation, but the data shows otherwise. Observation (4) is also well worth re-emphasising. ‘Theorists frequently assert that the gate capacitance variation is an important contributor in non-linear simulations, but anyone who has shipped a power amplifier will tell you otherwise; output power performance seems to be virtually independent of gate tuning. ‘Those who have been brought up on bipolar transistor amplifiers will probably find much of this to their liking. Bipolar devices are not nearly so well behaved as GaAs FETs in these specific areas and GaAs FET devices should probably be more widely considered for lower frequency applications as their prices continue to come down. Load-Pull Characteristics The observation that output power is a function of output termination impedance prompts further work on the test bench to determine the charaeteristies of this functional dependence. The results can be conveniently plotted on the Smith Chart, and take the form of “contours” of constant power. A typical set of experimentally generated curves is shown in Fig. 2. ‘These contour plots are valuable to the designer, since they give an immediate design target for a matching network. Unfortunately, a different set of contours is required for each frequency in the band of interest. Here the problem starts; generating these kinds of characteristics is very time ‘consuming. Many attempts have been made to automate the process, and commercially available ‘equipment is available to do so, but this means more time and expense. Looking at the contours of Fig.2, the obvious observation is that unlike the familiar gain and noise contours, they are not circular; an inevitable result of non-linear behaviour, it is usually assumed. So what if we take an ideally linear device up to its maximum current and voltage swing for different values of impedance termination and plot the powers on the Smith Chart, do we then see cireles again? The answer, as we shall see presently, is no; for once a linear phenomena does not map onto the Smith Chart as a complete circle, and the important characteristics of experimentally measured load-pull Power contours can be predicted using straightforward linear circuit concepts. Loadtines Fig. 3 shows the idealized FET model which is used in this analysis. The device is assumed to be a current source, with a maximum current of Ise, controlled by the voltage applied to the gate. With RC coupling providing the necessary isolation between the R.P. load and D.C. bias circuitry, the device drain voltage can swing between zero and twice the drain supply voltage (2V;,). The inherent clamping effect of the gate to source diode limits the gate voltage swing to a maximum of approximately zero, when the device draws its saturated drain current; the drain current therefore swings between zero (i.e. pinchoff) and Ij,, for maximum linear power output. Of course, in a real device, the transfer characteristic will not be completely linear across this whole range, but it should be noted that an actual measurement of distortion products even at the 1B compression point would show them to be lower than 20 dBe, and probably 30 dBc at the linear power point. This observation, which is closely Fig. 3. Large-signal FET model Fig. 2. Typical load-pull curves related to the “hardness” of a typical GaAs FET compression characteristic, tends to confirm the hypothesis that gain compression, even at microwave frequencies, is caused primarily by the sudden onset of clipping on the voltage and current swings rather than a gradual increase in the combined non-linearities of the elements in the small signal device model (3). Fig. 4 shows the three simple cases of resistive loads for the FET model described. Only when the device has an optimum load resistor Roy given by: Root = 2+ Vacdlass can the full current and voltage swings be sustained, as shown in Fig. 4(B). If the load resistor is increased to some higher value Tarain lass Taeain Verain. Vas ates atvorc = t 2 Varin ody Tarain = Tae + Fo'eos(wt) (Ig = gm-Vi,) Varin = Vie Z-Tycosct) 0< Haran < Tan 9< Varain <2 Vac q Vac Varain N Z As Zp>Rope, \ : B: Zy=Rope 0 Vac Vee Fig. 4. Large-signal FET model- resistive loads C: Zp Rope Verain ———> 1: Waveforms, oadlines than the optimum, voltage “clipping” will occur (Fig. 4(A)). If the resistor is lower than the optimum value, the maximum current swing of the device will generate a smaller voltage swing which does not, fally utilize the available voltage (Fig. 4(C)). Both of the conditions (A) and (C) in Fig. 4 result in lower linear power than the optimum condition (B). ‘This reduction in output power is easy to quantify; the non-clipped RF power output in each case is: Pope = Vaan “Tass/2 (Ry, = Raggy) (@) P=Popt-Rop/R, (Ry, > Rpt) ®) P= Poe Ry/ Rope (Ry, < Rope) © For example, if Ryyy = 20 2, the two load resistor values which will give 14B lower power than the optimum are: Ry = 20- (10 °)0 and 20 - (10-1) ‘These are two points on the 14B load-pull contour for this device. The complete closed loop of the contour consists of these two resistances combined with some reactance. Fig. 5 shows the loadline representation for the case of Ry, Rog, a8 shown in Fig. 5(b). In this case, the maximum current swing is not utilized due to the high value of R,; a susceptance can therefore be shunted across the load resistor to conduet more current up to the maximum value. The power will be constant over the range of reactance and this traces, out the other half of the load pull contour at this power level. The maximum value of the shunt susceptance is given by: Mag? By?) Bray = Gop? G2) Load - Pull Contours ‘The results of the above discussion are shown in Fig. 6. The theoretical load-pull contour is actually much simpler to draw on a Smith Chart than the description may imply. All that has to be done is 1) Establish Rye 5 that we have not yet considered the effects of internal and external device parasitic reactances These do not have any influence on the results obtained so far, however in order to compare the theoretical results with actual measurements, the drain capacitance and typical bondwire inductance needs to be included as part of the impedance presented to the active device terminals. (In the case of a packaged device, the appropriate elements of the package equivalent circuit would have to be included). The whole issue is really only one of choosing a reference plane; the important point is that in this device model the drain capacitance is, treated as an “external” element despite its being physically part of the device. Fig 7(b) shows the shift in the contours for a typical device when drain capacitance and bondwire inductance are incorporated on the device side of the impedance reference plane. These contours now start to have a similar appearance to actual measured data. A less staightforward issue is the value of drain capacitance to use. A reasonable approximation is to use the small signal value obtained by fitting a model to the measured S-parameters (and often quoted in the device data sheet). The purists argue that this is not accurate because the drain capacitance will vary with drain voltage. The answer to this was, and still is, that this is not proposed as an “accurate” technique, but one which works in a wide range of practical situations. Furthermore, it must be recognised that the reactive and resistive circuit matching elements are unequivocally linear in nature; we will never be able to track the variation of the drain capacitance with an external matching element, so the solution is always going to end up as a compromise, no matter how carefully the variation is modelled! Experience has shown that the best average value to take for the large-signal drain capacitance may be in the order of 20% larger than the small signal value, but this is often within the uncertainty range of typical physical realisation of a microwave cireuit. A Design Example An example will now be given of a design for a power-matched JS8851-AS for the 2-6 GHz frequency band. The data sheet shows this device operating typically at 100mA and 10V Vj, for optimum power performance within its thermal ratings. So the value ‘f Rog i8 10/.1 = 100 © for this bias condition. Also, the small signal model gives a value for C,, of 0.26 pF. The design problem is summarised in Fig. 8. ‘Treating the drain capacitance as an external element (whose value is fixed), the matching network has to transform the 50.0 termination up to Bondwire Inductance Matching Network Fig. 8. Power matching design problem the optimum 100 @ and absorb the drain capacitance. Formulated in this manner, the problem is a classical matching synthesis problem, and is best tackled that way. Matching circuit synthesis is a subject outside the scope of this note, and we here merely quote one possible solution, using lumped elements, in Fig. 9. The load-pull contours have been drawn on the Smith chart so that the level of power match across the band can be tracked. It ean be seen that the network is doing quite a good job, just staying inside the 1 dB contour. The FET and output matching network can now be considered as a fixed block while the input match is designed. Once again, a full treatment of power Fig. 9. 2-6 GHz Power match: JS8851-AS 10V/100mA Rope = 1000 165nH__1.60pF 500 1.35nH 15°, 3GHz 0.7pF 7 GaAsFET input matching networks is outside our resent scope, and one of many possible solutions is shown in Fig. 10. It is assumed that for this bandwidth a balanced approach will be taken, so the term “matching network” is something of a misnomer; the function of the input reactive network is to match the high frequeney end of the band for maximum gain and selectively mismatch the lower frequencies to maintain a flat response. The final result, with power and gain response, is shown in Fig. 11. Does it work? Surprisingly, yes, it does. We know that there are some questionable assumptions in the foregoing treatment of a very complex subject. Those who wish to shoot us down should know that we are well aware of such matters as: a) FETs don't always have 50% efficiency b) Drain current does not hard limit at Ig, ©) Drain voltage cannot drop to zero d) Drain resistance is finite and voltage dependent ©) Large signal drain capacitance is different from small signal and is voltage dependent ) Saturated power amplifiers must be non- linear otherwise they wouldn't be saturated All of these effects, and many others, can and do play a significant part in the possible behaviour of a microwave power device. They can all be included if you have the time and the resources to invest in the necessary computational tools. But it is a fundamental fact that in the simulation of any non-linear problem, the inputs required, in the form of starting conditions and data points, increase massively as the number and range of non-linear elements increases. 1.65nH L6pF Fig. 10. Ke. 2-6 GHz power- matched ‘JS8851-AS asa In Some Wider Applications ‘The usefulness of this technique is not be confined to power amplifier design. The power performance of any amplifier over its specified frequency band is an important parameter to know for amplifier cascade and subsystem analysis, but the majority of designers still have to take a “what-it-does-is-what- you-get” approach to the power performance of their designs. Clearly, using the equations which are summarized in the appendix, it would be a simple task to incorporate power simulation into a linear analysis package, in much the same way that most of the available packages currently compute noise figure. Unfortunately, the response to date from the software community has been unenthusiastic, due to the perceived “approximate” or “inaccurate” nature of the underlying assumptions. So much emphasis is placed on the ultimate accuracy of microwave CAD models these days; a point that is often overlooked is that designers are really as much interested in trends rather than Fig. 11. Amplifier gain and power response from 2 to 6 GHz 16 $+] Gain a) 12 Frequency (GHz) absolute accuracy. The knowledge that a particular output matching network will present a severe Power mismatch at one end of the frequency band can be enough to cause the designer to rethink the topology or even the whole project, and an approximate technique such as the one described can predict such a trend as well as a full-blown non- linear simulation which needs orders of magnitude more time and CAD resources to perform. Another application for this technique is in the design of interstage networks for power MMICs, where the problem of the large mismatch between drain and gate of larger FETs is compounded by the need to maintain a power match at the driver drain to maintain good gain compression performance. The use of feedback, also, does not preclude the use of the technique; the driving point impedance at the drain can still be evaluated by some slightly innovative use of a good general purpose nodal analysis program, and the power performance can then be determined as previously described. ‘The same comments apply (with a little more innovation in configuring the analysis program) to distributed amplifiers. The relatively recent discovery that some of the FETs in a typical distributed amplifier design can absorb, rather than generate, RF power, can be predicted without need to perform large scale non- linear simulations. Conclusions ‘This note has described a technique for matching GaAs power FETs that is approximate and easy to implement. It is proposed that the technique could be used more widely as a method of predicting the power versus frequency performance of any type of amplifier design. Steve C. Cripps is a consulting engineer at Matcom. References 1. 8.C. Cripps, “A Theory for the Prediction of GaAs Load-Pull Power Contours”, IEEE MTT-S Int'l Microwave Symposium Digest, 1983, pp 221-223 2. G. D. Vendelin, “Evaluating Nonlinear Models for Microwave GaAs FETs”, IEEE Spectrum, Sept. 1990, pp 48-50 8. Matcom Technical Note 2.1, “Harmonic and Intermodulation in GaAs FET Amplifiers’ Appendix: Equation Summary For FET biased at Vg, Ing! Case 1: Optimum Power Match Rie = Yoollpe Power = Pray Prax = max“ 2* Rope = Tae/\2) = Vinax?2! Bont VagN2) Case 2: 1%! @,-R, 5%) Device is current limited Power = ?- Ry, = RyRopd) > Pinas. For 0<1X,1Rypp Oy =G,45B,) Device is voltage limited Power =2- Gy, =(G1/Gyp0)- Prag For 0<1By,|

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