ASIC DESIGN FLOW

ASIC DESIGN FLOW

Figure.Flowchart of ASIC DESIGN FLOW

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1. ASIC FRONT END FLOW:

1.1.Chip specification:

The goal is to specify the functional requirements for the

design and define the external interfaces to the related designs.

Figure 1.1.1. Chip specification Flow chart

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1.2.Partitioning of Chip (MICRO-ARCHITECTURE):

1.2.1.Good partitioning in the design provides several

advantages including:
❏ Easy handling of design requires sensible
hierarchy .
❏ Better synthesis results.
❏ Faster synthesis compile runtimes.
❏ Ability to use simpler synthesis strategies to
meet timing.
❏ Reusability.

1.2.2.Locate related combinational logic in a single

module and single process if possible

❏ The synthesis tool has more flexibility in optimising

a design when related combinational logic is located in
the same module. This is because synthesis tools cannot
move logic across hierarchical boundaries during compile
operation.

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Figure 1.2.3. Design partioning

1.3.Design Entry/Functional Verification

❏ Functional Verification is defined as the process

of verifying that an RTL (Synthesizable Verilog,
VHDL, SystemVerilog) design meets its
specification from a functional perspective. RTL
Verification is usually divided into two discrete
areas.Functional verification, and physical
verification.

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Figure 1.3.1. RTL_block /Functional Verification flow chart

1.4 RTL Block synthesis

❏ In electronics, logic synthesis is a process

by which an abstract specification of desired
circuit behavior, typically at register transfer
level (RTL), is turned into a design
implementation in terms of logic gates,
typically by a computer program called a
synthesis tool.
The stages of Synthesis can be briefly divided into

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following types :

1.4.1 Translation

❏ The RTL code is converted to generic level netlist.

1.4.2 Mapping

❏ The generated netlist from the RTL code is later

mapped on to the respective (.lib).

1.4.3 Optimization

❏ The optimization of the Design will happen and the

netlist is generated from that.

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Figure 1.4.1 Synthesis block level diagram

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Figure 1.4.2 Gate level verification diagram

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1.5 DESIGN FOR TESTABILITY(TEST INSERTION)

❏ Design for testing or design for testability

(DFT) consists of IC design techniques that add
testability features to a hardware product design.
The added features make it easier to develop and
apply manufacturing tests to the designed hardware.
The purpose of manufacturing tests is to validate
that the product hardware contains no manufacturing
defects that could adversely affect the product's
correct functioning.

Figure 1.5.1.Design for Testability

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2.ASIC BACK END FLOW

2.1 Data Preparation

❏ In Physical Design mainly Six inputs are
present
❏ Logical libraries --> format is .lib ---
>given by Vendors
❏ physical libraries -->format is .lef ---
>given by vendors
❏ Technology file -->format is .tf --->given
by fabrication peoples
❏ TLU+ file -->format is .TLUP-->given by
fabrication people
❏ Netlist --->format is .v -->given by
Synthesis People
❏ Synthesis Design Constraints -->format is
.SDC -->given by Synthesis People

2.1.1 .v (Netlist)

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❏ Netlist: Format is .V
❏ It contains Logical connectivity Of all Cell(Std
cells,Macros).
❏ It contain List of nets.
❏ In the design for Knowing connectivity by
using Fly lines.
2.1.2 .sdc (synopsys Design Constraints)

❏ These Constraints are timing Constraints .These

Constraints used for to meet timing
requirements.Constraints are

❏ CLOCK DEFINITIONS:Create Clock Period.

❏ Generated Clock Definitions
❏ Input Delay
❏ Output Delay
❏ I/O delay
❏ Max delay
❏ Min Delay
❏ --------------->Exceptions<-------------------------
❏ Multi cycle path
❏ False path
❏ Half cycle path

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❏ Disable timing arcs

❏ Case Analysis
❏ Multi cycle path, False path are Exceptions.

2.1.3 Technology file

❏ Technology file: format is .tf:

❏ It contains Name,Number conventions of
layer and via
❏ It contains Physical,electrical characteristics
of layer and via
❏ In Physical characteristics Min
width,area,height are present.
❏ In Electrical characteristics Current Density
is present.
❏ Units and Precisions of layer and via .
❏ Colors and pattern of layer and via .
❏ Physical Design rules of layer and via
❏ In Physical Design rules Wire to Wire
Spacing,Min Width between Layer and via are
present.
2.1.4 Logical Libraries (.lib)

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❏ Logical libraries :format is .lib

❏ Timing information of Standard cells, Soft
macros ,Hard macros.
❏ functionality information of Standard
cells, Soft macros.
❏ And design rules like max transition
,max capacitance, max fanout.
❏ In timing information Cell delays ,
Setup,Hold time are present.
❏ Cell delay is Function of input transition
and output load.
❏ Cell delay is calculated based on lookup
tables.
❏ Cell delays are calculated by using
linear delay models,Non linear delay
models,CCS models.
functionality is used for Optimization
Purpose.
❏ And also Contain Power information.
❏ It contains Leakage power for Default
cell,Leakage Power Density for cell,Default
Input voltage , Output voltage.
❏ PVT contains ------->Cell leakage Power

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❏ -------->Internal Power
❏ --------->Rise Transition
❏
❏ And it contains A view(sub directory) i.e.
LM(Logical Model view) view.
❏ It contains logical libraries.

2.1.5 Physical Libraries (.lef)

❏ Physical libraries: format is .lef

❏ physical information of std
cells,macros,pads.
❏ Pin information.
❏ Define unit tile placement.
❏ Minimum Width of Resolution.
❏ Hight of the placement Rows .
❏ Preferred routing Directions.
❏ Pitch of the routing tracks.
❏ Antena Rules.
❏ Routing Blockages
❏ In physical information height,area,width
are present and also it contains two views
❏ Cell View:

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❏ In this all layout information is present,it

is used at the time of tapeout
❏ FRAM view:
Fram view is abstract view, it is used at the
Place & Route.

2.1.6 TLU plus (.TLUP)

❏ TLU+ files: format is .TLUP:

❏ R,C parasitics of metal per unit length.
❏ These (R,C parasitics) are used for
calculating Net Delays.
❏ If TLU+ files are not given then these are
getting from .ITF file.
❏ For Loading TLU+ files we have to load three
other files .
❏ Those are Max Tlu+,Min TLU+,MAP file.
❏ MAP file maps the .ITF file and .tf file of the
layer and via names.

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Figure 2.1.7.Physical Design flow in ASIC

flow

2.2 SANITY CHECKS

2.2.1 Netlist checks

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❏ No Assign Statements.
❏ No Floating input Nets.
❏ No Multi-Driven Nets.
❏ No Black-Box or Empty Modules.
❏ Output pins connected to power or
ground.
2.2.2 SDC checks

❏ Missing Clocks.
❏ Flops not getting Clocks.
❏ Flops driven by Multiple clocks.
❏ Unconstrained Endpoints.
❏ Missing I/O delays.

2.2.3 Library Check

❏ Check if there is any model is missing for

the cells
❏ Library consistency check

2.2.4 Netlist (V/S) SDC Check

❏ Make sure your design is meeting “Setup”

with Zero wire-delay.

2.2.5 Netlist (v/s) Floorplan Check

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❏ All the I/O ports should have Location.

2.3 Floorplan

❏ The first step in the physical design flow is

floorplanning. Floorplanning is the process of
identifying structures that should be placed
close together, and allocating space for them in
such a manner as to meet the sometimes
conflicting goals of available space (cost of the
chip), required performance, and the desire to
have everything close to everything else.
❏ Based on the area of the design and the
hierarchy, a suitable floorplan is decided upon.
Floorplanning takes into account the macros
used in the design, memory, other IP cores and
their placement needs, the routing possibilities,
and also the area of the entire design.
Floorplanning also determines the IO structure
and aspect ratio of the design. A bad floor plan
will lead to wastage of die area and routing
congestion.
❏ In many design methodologies, area and
speed are the subjects of trade-offs. This is due

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to limited routing resources, as the more

resources used, the slower the operation.
Optimizing for minimum area allows the
design both to use fewer resources, and for
greater proximity of the sections of the design.
This leads to shorter interconnect distances,
fewer routing resources used, faster end-to-end
signal paths, and even faster and more
consistent place and route times. Done
correctly, there are no negatives to
floorplanning.
❏ As a general rule, data-path sections
benefit most from floorplanning, whereas
random logic, state machines, and other non-
structured logic can safely be left to the placer
section of the place and route software.
❏ Data paths are typically the areas of the
design where multiple bits are processed in
parallel with each bit being modified the same
way with maybe some influence from adjacent
bits. Example structures that make up data
paths are Adders, Subtractors, Counters,
Registers, and Muxes.

2.3.1 Floorplan Checks

❏ No macros overlap.

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❏ Macros on Placement grid.

❏ No I/O ports short.
❏ I/O ports should be present on routing
Track.
❏ All the Macros and I/O ports should have
fixed attribute.
❏ No blocked pins.
❏ Enough channel between macros.
❏ At Least one stripe of VDD and one stripe
of VSS should be present in the macro channel.
❏ No power/ground nets short and opens.
❏ Quick Placement.
❏ Create floor-plan placement.
❏ Analyze the Placement quality
➢ Congestion.
➢ Timing.
➢ Utilization.

2.3.2 Chip utilization factor

Chip utilization=AREA of [Area of Std cells + Macro + (Pad,Pad Filler,Corner pad)]

Area of Chip

2.3.3 Aspect Ratio

Aspect Ratio = W = Horizontal Routing Resources

H Vertical Routing Resources

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Figure 2.3.4 Floor-plan View

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Figure 2.3.5 Macro-Placement view

2.4 PowerPlan

❏ Power planning is a step which typically

is done with floorplanning in which power grid
network is created to distribute power to each
part of the design equally.
❏ Power planning can be done manually as
well as automatically through the tool.
❏ Deal with Power Distribution Network
❏ Three levels of Power Distribution
❏ Rings
Carries VDD and VSS around the chip
❏ Stripes

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Carries VDD and VSS from Rings across the

chip
❏ Rails
Connect VDD and VSS to the standard cell
VDD and VSS.

❏ For core logic, there is a core ring

enclosing the core with one or more sets of
power and ground rings. A horizontal metal
layer is used to define the top and bottom sides,
or any other horizontal segment, while the
vertical metal layer is utilized for left, right, and
any other vertical segment. These vertical and
horizontal segments are connected through an
appropriate via cut. The next consideration is to
construct the standard cell power and ground
that is Floorplanning internal to the core logic.
These internal core power and ground busses
consist of one or two sets of wires or strips that
repeat at regular intervals across the core logic,
or specified region, within the design. Each of
these power and ground strips run vertically,
horizontally, or in both directions.
❏ Figure 2.4.1 illustrates these types of
power and ground connections.
❏ If these strips run both vertically and

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horizontally at regular intervals, then the style

is known as power mesh. The total number of
strips and interval distance is solely dependent
on the ASIC core power consumption.

Figure 2.4.1 Power Structure / Power

Planning

2.5 Placement
❏ Before the start of placement
optimization all Wire Load Models
(WLM) are removed. Placement uses RC

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values from Virtual Route (VR) to

calculate timing. VR is the shortest
Manhattan distance between two pins. VR
RCs are more accurate than WLM RCs.
❏ Placement is performed in four
optimization phases:
➢ Pre-placement optimization
➢ In placement optimization
➢ Post Placement Optimization (PPO)
before clock tree synthesis (CTS)
➢ PPO after CTS.

❏ Pre-placement Optimization optimizes the

netlist before placement, HFNs (High Fanout
Nets) are collapsed. It can also downsize the
cells.

❏ In-placement optimization re-optimizes

the logic based on VR. This can perform cell
sizing, cell moving, cell bypassing, net splitting,
gate duplication, buffer insertion, area recovery.
❏ Optimization performs iteration of setup
fixing, incremental timing and congestion
driven placement.
❏ Post placement optimization before CTS
performs netlist optimization with ideal clocks.
It can fix setup, hold, max trans/cap violations.
It can do placement optimization based on
global routing. It re does HFN synthesis.
❏ Post placement optimization after CTS

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optimizes timing with propagated clock. It tries

to preserve clock skew.

Figure 2.5.1 Placement of std cells

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Figure 2.5.2 Placement of std cells with power rails

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2.6 CTS (Clock Tree Synthesis)

❏ The goal of clock tree synthesis (CTS) is to

minimize skew and insertion delay. Clock is not
propagated before CTS as shown in the picture.
After CTS hold slack should improve. Clock tree
begins at .sdc defined clock source and ends at stop
pins of flop. There are two types of stop pins known
as ignore pins and sync pins. 'Don't touch' circuits
and pins in front end (logic synthesis) are treated as
'ignore' circuits or pins at back end (physical
synthesis). 'Ignore' pins are ignored for timing
analysis. If clock is divided then separate skew
analysis is necessary.
➢ Global skew achieves zero skew between two
synchronous pins without considering logic
relationship.
➢ Local skew achieves zero skew between two
synchronous pins while considering logic relationship.
➢ If clock is skewed intentionally to improve setup slack
then it is known as useful skew.
❏ Rigidity is the term coined in Astro to indicate
the relaxation of constraints. Higher the rigidity
tighter is the constraints.

2.6.1 Clock After CTS

❏ In clock tree optimization (CTO) clock can be

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shielded so that noise is not coupled to other signals.

But shielding increases area by 12 to 15%. Since the
clock signal is global in nature the same metal layer
used for power routing is used for clock also. CTO is
achieved by buffer sizing, gate sizing, buffer
relocation, level adjustment and HFN synthesis. We
try to improve setup slack in pre-placement, in
placement and post placement optimization before
CTS stages while neglecting hold slack. In post
placement optimization after CTS hold slack is
improved. As a result of CTS lot of buffers are
added.

Figure 2.6.2 Clock Before CTS

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Figure 2.6.3 Clock After CTS

Figure 2.6.4 CTS Algorithm H-Tree

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Figure 2.6.5 CTS Algorithm FishBone

2.7.Routing

❏ There are two types of routing in the physical

design process, global routing and detailed routing.
Global routing allocates routing resources that are
used for connections. It also does track assignment
for a particular net.
❏ Detailed routing does the actual connections.
Different constraints that are to be taken care during
the routing are DRC, wire length, timing etc.

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Figure 2.7.1. Detail Routed Database

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Figure 2.7.2. Detail Routed Database with macros

2.8.Physical verification

❏ Physical verification checks the correctness of the

generated layout design. This includes verifying that
the layout.
➢ Complies with all technology requirements –
Design Rule Checking (DRC).
➢ Is consistent with the original netlist – Layout vs.
Schematic (LVS).
➢ Has no antenna effects – Antenna Rule Checking.
➢ This also includes density verification at the full
chip level Cleaning density is a very critical step
in the lower technology nodes.
➢ Complies with all electrical requirements –

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Electrical Rule Checking (ERC).

3.0.References

❏ http://users.encs.concordia.ca/~tahar/coen6551
/notes/asic-notes.pdf
❏ https://en.wikipedia.org/wiki/Physical_design_
(electronics)#cite_note-5
❏ http://vlsibyjim.blogspot.com/2015/03/power-
planning.html

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