EE ESE Mains Paper-1 2018 PDF

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ESE - 2018
MAINS EXAMINATION
Questions with Detailed Solutions

ELECTRICAL ENGINEERING

PAPER - I

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solutions. Discrepancies, if any, may please be brought to our notice. ACE Engineering Academy
do not owe any responsibility for any damage or loss to any person on account of error or omission
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PAPER REVIEW

Paper was overall moderate, material science, measurements and mathematics had some
questions from our test series. Networks questions are direct and easy. EMTL questions
are direct previous years. Some one, who followed ACE test series, feels the paper really
easy. Section-B is relatively tougher than section-A and the paper is lengthy.

SUBJECT WISE REVIEW

SUBJECT(S) LEVEL Marks

Engineering Mathematics Easy 72

Electric Circuits and Fields Easy 84

Basic Electronics Engineering Hard 84

Moderate 72
Electrical and Electronic Measurements
Moderate 84
Electrical Materials
Hard 84
Computer Fundamentals

Subject Experts,
ACE Engineering Academy
:2: ESE‐2018 Mains (Paper‐1)

SECTION – A

 5  2 0
01. (a) Let A =  2 6 2 and B = A3 – 2A2 – 5A + 6I,
 0 2 7

Where I is the identity matrix, then calculate the determinant of B. (12M)

 5  2 0
Sol: Given, A =  2 6 2
 0 2 7

Characteristic equation of A is |A – I| = 0

5    2 0 

  2 6 2   0
 0 2 7   

By expanding

3 – 182 + 99 – 162 = 0

 ( – 3)(2 – 15 + 54) = 0

 ( – 3)( – 9)( – 6) = 0

Eigen values of A are 3, 9, 6.

For B = A3 – 2A2 – 5A + 6I eigen values corresponding to

3  27 – 18 – 15 + 6 = 0

9  729 – 162 – 45 + 6 = 528

6  216 – 72 – 30 + 6 = 120

We know that determinant of A matrix is equal to product of eigen values

|B | = 0 × 528 × 120

=0

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:3: Electrical Engineering
01. (b)
q q q q q

x=0 x=1 x=2 x=4 x=8 x=16 ….x in m

An infinite number of charges each equal to q Coulombs’ are placed in a free space along
the line at x = 1, x = 2, x = 4, x = 8, x = 16 and so on. Find the expression for potential and
electric field intensity at point x = 0, due to these systems of charges. Assume that values of
x are in metres. (12M)
Sol:
y

1 2 4 8 16
(0,0) q q q x

Resultant potential at the origin is



q 1
VT 
4 0
r
i 1
as this

 
q  1 1 1 
 1  2  4  8 ......
4 0
  G .P
 

q  a  1
=   , r , a =1
4 0 1  r  2
q 1
VT  .
4 0 1  1
2
q
 VT  Volt
20

q 1 q  1 1 1  (– â )
ET 
4 0
r
i 1
2

4 0 1  4  16  64  ... x
i

 
q  1  (– â )  Q  4 (– â )
   x x
4 0  1  40 3
1
 4 

 E T  Q (– â x ) V/m
3 0

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:4: ESE‐2018 Mains (Paper‐1)
01. (c) A Silicon diode that has an ohmic resistance of 0.5 Ω with reverse saturation current
I0 = 10–12 A and  = 2.0, consumes 50 × 10–12 W extra power compared to ideal diode.
Diode operating temperature is 350K.
(i) Determine the fraction of the applied voltage that falls across the ohmic resistance.
(ii) Solve part (i), when diode current is 1A.
(iii) Compare results of part (i) & (ii) and draw conclusion. (8+2+2=12M)

Sol: Given that Ohmic resistance = 0.5 Ω


350
VT  = 30.1724 mV
11,600

VD
ID

Power Consumption = IDVD + I 2D .R

  2
I 0 e VD / VT .VD  I 0 e VD / VT R  50  10 12

I0.VD e VD / VT .I 02 e 2 VD / VT .R  50  10 12

 
10 12 VD e VD / VT  10 12 e 2 VD / VT R  50  10 12

V e
D
VD / 230.1710 13 3

 10 12 e VD / 30.1710  0.5  50

VD e16.57 VD  0.5  10 12 e 33.14 VD  50



x

When VD = 0.30  x = 43.25


VD = 0.305  x = 47.77
VD = 0.307  x = 49.70
VD = 0.3073  x = 50
 VD = 0.3073 V

Then ID = I0 e VD / VT 
= 10–12 [e0.3073/2×30.172 × 10–3]
= 162.78 pico amperes

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:5: Electrical Engineering
(i) Voltage across ohmic resistance

(ii) When ID = 1 A

Voltage across Diode is , VD = VT n 12 


1
 10 
 1 
= 2 × 30.1724 × 10–3 n 12 
 10 
= 2 × 30.1724 × 10–3 n 1012 
= 1.6673 V
VR = IDR = 0.5 V

(iii) In Part (i)  ID = 162.78 × 10–12 A, VD = 0.3073 V

Part (ii)  ID = 1 A, VD = 1.6673 V

In part (i) power consumes  50 × 10–12 W

In part (ii) power consumes

= ID VD + I 2D R

= 1 × 1.6673 + 0.5

= 2.1673 W

As diode current becomes 1 A, VD = 1.6673 and power consumes 2.1673 W

 For change in current of 162.78 PA to 1 A the voltage across diode changes from 0.3073 to

1.6673 V

For a large change in current there is a small change in voltage. So diode is a logarithmic device

(non linear device).

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:6: ESE‐2018 Mains (Paper‐1)
01. (d)
10 volts

1 2 1

d/2
d

A parallel plate capacitor consisting of two dielectric materials is shown in figure. The
middle dielectric slab is placed symmetrically with respect to the plates. If the potential
difference between one of the plates and nearest surface of dielectric interface is 4 volts,
1
determine . Assume parallel plate capacitor has an electrode area of A m2. (12M)
2

Sol: 10V 6V 4V 0V

C1 C2 C1

1 2 1

d/4 d/2 d/4


d

In this all the three dielectrics are connected in series. So, the charge is same through the
dielectrics, i.e., Q1 = Q2
A
Generally capacitance, C =
d
  A 4   A
C1 = 0 1 = 0 1
d /4 d
 A 2 0  2 A
Similarly, C2 = 0 2 =
d /2 d
C1V1 = C2V2
4 0 1 A 2  A
4  0 2 2
d d
1 1

2 4

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:7: Electrical Engineering
01. (e)
20V

D
G IDSS = 5 mA
Vp = 4V

Write the equation related to the drain current (ID) and Gate to source voltage VGS
explaining all the parameters for
(i) Depletion type MOSFET
(ii) Enhancement type MOSFET
(iii) Determine VDS for the circuit shown in the figure. (4+4+4=12M)

Sol: (i) Depletion type MOSFET


Case (i) Cutoff region:
ID = 0 ….. (1)
In this case VGS = VGS(OFF) = VP …….. 1(a)
Case (ii) Saturation region:
2
 V 
I D  I DSS 1  GS  …….. (2) (Neglecting channel length modulation effect i.e  = 0)
 VP 

Where ID is the total drain current in the device


IDSS is the drain to source current with the gate shorted to the source.
VGS is the reverse biased gate to source voltage, generally VGS is negative for an N-channel
MOSFET in Depletion Mode.
VP is the pinch-off voltage: The maximum reverse biased gate to source voltage at which
the channel becomes pinched-off or becomes very low and the current through the channel
becomes almost zero is called pinch-off voltage.
NOTE: IDSS is the device parameter, defined by manufacturer and is given by,

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:8: ESE‐2018 Mains (Paper‐1)
1 2
IDSS =  n C ox Vth ….......... (3)
2
Where "  n C ox " is know as process transconductance parameter in which n is the

mobility of electron Cox oxide capacitance and Vth is the threshold voltage.
(ii) Enhancement MOSFET:
Case (i) Cutoff Region:
ID = 0 ……. (1) in this case, VGS  VP;
Case (ii) Saturation region:
1 W
I D   n C ox VGS  Vth 2 ……. (2)
2 L
Where,
n = mobility of electron

Cox = Oxide capacitance = ox (where ox permitivity & silicon oxide tox is oxide
t ox

thickness)
(NOTE: ‘n Cox’ is known as process trans conductance parameter)
 W 
W = channel width Generally is known as aspect ratio of the MOSFET
 L 
L = channel length
VGS = applied gate to-source voltage. Generally VGS is positive in Enhancement mode of
an N-channel MOSFET.
Vth = Threshold voltage 20V

RD ID
(iii) Given IDSS = 5 mA, Vp = – 4V D
G +
Step (1) From the circuit,
VGS = OV VDS
+
Step (2): consider shockly equation, VGS
– –
2 S
 V   0 
I D  I DSS 1  GS   5mA 1   4mA
 VP    4V 
Step (3): KVL for output section,

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:9: Electrical Engineering
20V – IDRD –VDS = 0
 VDS = 20V –IDRD
Let RD = 3k
 VDS  20V  5mA  3k  5V

02. (a) Show that in the interval (0, 1)


8  n
cos πx = 
 n 1 4n 2  1
.sin 2nx (20M)

Sol: f(x) = cosπx


Half range sine series of f(x) in the interval (–1, 1)

f(x) = b
n 1
n sin nx ………...(1)

1
Where bn = 2  f x sin nx dx
0

1
bn = 2  cos x. sin nx..dx
0

1
bn =  sin nx  x   sin nx  x dx
0

  cosn  1x    cosn  1x 


1 1

bn =    
 n  1  0  n  1  0

  1n  1   1
n
1 
bn =     
 n  1 n  1   n  1 n  1 

=
 1n 
2 n  1  2n 
 where n = 1, 2, 3 ……….
  n 2  1   n 2  1

  
2n
= 2  1n  1

n 1 
4n
= 2 if n = even
n 1
=0 if n = odd

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: 10 : ESE‐2018 Mains (Paper‐1)
42m 
 ……….(2) where m = 1, 2, 3……
 4m 2  1  
Sub (2) in (1) then

8m
f x    sin 2mx 
m 1 
4m 2  1  
8  n
f x    sin 2nx  (m is dummy variable)

 n 1 4n 2  1 

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: 11 : Electrical Engineering
02. (b)
X
2

V1
10
1A 5
V1
Y

Determine the value of Load Resistance RL to be connected across terminals X-Y to receive
maximum power. Also, obtain the value of this maximum power. (20M)
Sol:
X
2
P
V1
10
1A 5
V1
Y
Thevenin’s voltage across the terminals X and Y = Vth = VXY
V1 V
At Node ‘P’, 1  1
10 5
 0.1V1 = 1
 V1 = 10
V 
VXY = 2  1   V1
 10 
 10 
= 2   10 = 12 V
 10 
Norton’s Current across the terminals X and Y = ISC = IXY
 V1 
1  
X  5 

2
P V1
V1 IXY
5
10
1A
V1 5

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: 12 : ESE‐2018 Mains (Paper‐1)
V1  V1 
I XY   1   …………… (1)
10  5 

 V 
 V1  21  1  = 0 …………… (2)
 5
2V1
V1  2 
5
7V1
2
5
10
 V1 
7
V1  V1 
I XY   1  
10  5

10  10 1 
=  1   
10  7  7 5

1  2
=  1  
7  7
1 6
= 1 = A
7 7
Thevenin’s equivalent resistance
VSC V 12
Rth = = RXY = XY  = 14 Ω
I SC I XY 6 / 7
Thevenin’s equivalent circuit across terminals XY:

14
X

12V  RL

The value of load resistance connected across terminals for max power transfer
RXY = Rth = RL = 14 
V XY2 12 2 144
Maximum power deliver to the load RL =  = = 2.571 W
4 R XY 4  14 56

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: 13 : Electrical Engineering
02. (c) +VCC

R1 RC C2
V0
C1
(, r0) Given r0 >> 10RC
Vi
I1 Z0 RE >> re

R2 RE CE (Bypass Capacitor)
Zi

Obtain the expression for voltage gain to given circuit.


(i) With bypass capacitor.
(ii) Without bypass capacitor.
(iii) Calculate voltage gain in part (i) & part (ii), if R1 = 90 kΩ, R2 = 10 kΩ, RE = 0.8 kΩ,
β = 200, r0 = 50 kΩ, RC = 2.2 kΩ and VCC = +15 V.
Compare both voltage gains and write conclusion in short. (5+5+10=20M)

Sol: (i) Given r0>> 10Rc C

RE >> re B
Vi
with bypass capacitor:
Rc
Case (i): R1 R2
E
Consider the AC model of the given circuit:

1. All DC sources = 0
Fig. 2C1
2. Xc = 0

Case (ii): small signal model of the amplifier shown in fig.2C1

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B C
+
ib ic i0
Vi R1 R2 hfe ib
hie RC
r0 V0


E E

Fig. 2C2

NOTE: hfe =  , hie = re

∵ r0 >> 10Rc the above ckt can be simplified as:

ib +
ic i0
Vi R1 R2 hie RC Vc
hfe ib

Fig. 2C3

V0
Voltage Gain, A V  :
Vi

Step (1): From the circuit shown in fig:2C2 , r0 || Rc ≃Rc ……. (1) { r0 >> 10 Rc] (as shown in fig. 2C3)

Step (2): From the circuit shown in fig 2C3, V0 = I0 Rc = –hfe ibRc = –ibRc ……. (2)
Step (3): From the input section of the circuit shown in fig 2C3,
Vi  i b h ie  i bre …….. (3)

V  i b R c  R c  R c  1 
 Av  0     g m R c …… (4)   gm 
Vi i bre re re  re 
 h fe R c h fe
 …… (5)  gm 
h ie h ie

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: 15 : Electrical Engineering
(ii) Without bypass capacitor.
1. let the DC source  0
Consider the ckt given, without CE : AC model  
2. X c  0 

VCC
V0
R1 RC
C1
 RC
Vi C2 V0

R2 R1 R2 RE
RE Vi

Fig.2C4
Fig.2C5

Vi B C io
Vi
+ +
ib hie hfeib ic

Vi R1 R2 E E RC V0

RE (1+hfe)ib
– –

Fig.2C6 small –signal model

Step (1): V0 = I0Rc = – hfe ibRc …….. (1)


Step (2): KVL for input loop:
Vi –ibhie –(1+hfe) ibRE = 0 ……… (2)
Vi = ib [ hie + (1+hfe) RE]………… (3)
V0  h fei b R c
Step (3): Voltage gain, A v   …… (4)
Vi i b h ie  1  h fe R E 

 R c  h fe  
 …… (5) h  r 
 re  1  R E  ie e 

 R c  R E  re given 
 AV  …… (6)  
1  R E  1   R E   re 

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: 16 : ESE‐2018 Mains (Paper‐1)
 Rc
NOTE: If  is large, A V  ….. (7)
RE

(iii) Given R1 = 90k, R2 = 10k, RE = 0.8k,  = 200, r0 = 50 k, Rc = 2.2 k and Vcc = 15V
Part (i): CE amplifier with bypass capacitor:
 h fe R c || r0   h fe 
AV   g m R c || r0  ……. (1)   gm 
h ie  h ie 
Case (i): Consider the DC model of the given circuit:
1. All AC source = 0
2. Xc = 
Step (1):
R 2 Vcc  10k (15V)
Vth    1.5V  VB …… (1)   isl arg e
R 1  R 2 90k  10k
15V
Step (2) : KVL for B-E loop of B.J.T:
R1 RC
Vth –VBE–IERE = 0…… (2)
Vth
VTh  VBE 1.5V  0.7V
 IE    1mA …… (3) + VBE
RE 0.8k –
R2 RE IE
1 IE 1mA
gm    = 0.03846 mho…….. (4)
re VT 26mV
Case (ii): Consider the small signal model

B C
+ +
ib ic

R1 R2 hie
Vi r0 RC V0
hfeib

– –
E E

Step (i):
V0  h fei b ro || R c  ….. (1)
Vi = ib hie …… (2)

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Step (ii):
V  h fei b (ro || R c )
AV  0  ….. (3)
Vi ib
 h fe ro || R c 
 …… (4)
h ie
= –gm (r0 ||Rc)…… (5)
= –0.03846 ℧ [50k||2.2k]……. (6)
VCC
Av = – 81.045977….. (7)
R1 RC
C1
Vi C2 V0
Part(ii) CE Amplifier without CE: I1
Case (i) : same as part(i) R2
RE
IE = 1mA…… (1)
VT 26mV
 re    26 ……. (2)
IE 1mA

Approximate Approach:
Case (ii) given ro50k & Rc = 2.2.k
 r0  R c (i.e r0 >> 10Rc), the simplified small -signal model can be shown as follows

B c
+ hie ic +
ib hfeib
I0
E E

Vi RC V0
R1 R2
RE (1+hfe)ib
– –

Step(1): V0= I0RC = –hfeibRc .......... (1)


Step(2) : KVL for input loop
Vi – ibhie– ib (1+hfe) RE = 0 ............(2)
Vi = ib [hie + (1+hfe) RE] ..............(3)
Step(3):
V  h fei b R c
AV  0  ..............(4)
Vi i b h ie  (1  h fe )R E 
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 R c
 ..............(5)
re  1   R E
 200  2.2k
 ..............(6)
200  26  201  0.8k
440
 ..............(7)
166
AV = –2.65 ..............(8)

Comparison:
Case (i): AV = –81.045977 [with by pass capacitor]
Case (ii): AV= –2.65 [without by pass capacitor]
NOTE: In a CE amplifier, if the bypass capacitor is open, the voltage gain, AV decreases,
because the unbypassed RE causes negative feed back.

This problem can be solved more accurately with the following approach:
Accurate Approach:
Case (ii): Small –signal model

B C
+ +
ib hie hfeib + ic I0
ro Vc
Vi R1 R2 E – E RC V0

R i RE (ic+ib) R 0
– –

 R 
 1  h fe   c 
r0 
Step (1): R i  h ie   R ……. (1)
  R  R  E
c E
1    
  r0  
 R 
 1    c 
r0 
  re   R ……. (2)
  R  R  E
1   C E
 
  r0  

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R C 2.2k
   0.044  1    ,
r0 50k

 
 
R i   re   1    R ….. (3)
  R  R  E
1   C E
 
  r0  
RC  RE
 r0  10(R C  R E ),  1 ….. (4)
r0

R i   re  1  R E ……. (5)

 Vi  i b R i  i b re  1   R E  …… (6)

h fe r0  h ie
Step (2): R 0  r0  …… (7)
h ie
1
RE
r0  re
 r0  ……. (8)
r
1 e
RE

r0
 r0  ……. (9) [r0 >>re]
re
1
RE

 
  
 r0 1   ……. (10)
 1  re 
 RE 

 
 200 
 r0 1  ….. (11)
5 .2 
 1 
 0 .8 
 200 
 r0 1  ….. (12)
 6.5 
 R 0  31.77r0 …… (13)

Step (3) : V0  iCR C || R C  iCR C || 31.77 r0 ……. (14)

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 i C R C …… (15) [ ∵31.77r0>> RC]

= – hfe ib RC……. (16)


V  h fei b R c  R C
Step (4): A V  0   …… (17)
Vi i b (re  1   R E re  1  R E
200  2.2k
 …….. (18)
200  26.2  201  0.8k
 440
 AV   2.65 …….. (19)
166

z 2  4z  8
03. (a) Evaluate  1 2
2
dz where C is the contour |z + 1 – i| = 2 in anti-clockwise
 z   z  2 z  5 
C

 2
sense. (20M)

Z 2  4Z  8
Sol: C  1 2 2 , |Z + 1 i| = 2
 Z   Z  2Z  5
 2
Case (1):
1 1
For Z1 = ,  1  1  i1 = 1.8 < 2
2 2
1
 Z1 = lies inside the contour
2
f ( Z) 2i
 (Z  a )
C
n
 Lt f n 1 ( Z)
(n  1)! Za

1
 For Z =
2
Z 2  4Z  8
f(Z) =
Z 2  2Z  5
Z 2  4Z  8
Z 2  2Z  5 = 2i Lt f 21 ( Z )
  1
2
(2  1)! Z  12
Z  
C

 2
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= 2i Lt1 f ( Z )
Z
2

= 2i  Lt1
Z 2
 2Z  5(2Z  4)  ( Z 2  4Z  8)(2Z  2)
Z
2
Z 2  2Z  5) 2

 2Z 2  6Z  4
= 2i  Lt1
Z  ( Z  2 Z  5)
2 2
2

1 1
 2  6  4
= 2i  4 2
2
 1 1 
  2   5 
4 2 
 0.5 
= 2i    = 0.08i
 39.0625 
Case (2):
Z2 + 2Z + 5 = (Z + 1+ 2i)(Z + 1  2i)
Z2 = 1 2i  |1 2i + 1i| = 3 > 2
 Z2 =  12i lies outside the contour
Z3 = 1 + 2i,  |1 + 2i + 1  i| = 1 < 2
 Lies inside the contour.
For Z3 = 1 + 2i
Z 2  4Z  8
= 2i Lt  2
 ( Z  1  2i )
Z ( 1 2 i )
 1
 Z   Z  1  2i Z  1  2i 
 2

(1  2i ) 2  4(1  2i )  8
= 2i  2
 1
  1  2i    1  2i  1  2i 
 2
 
1  4  4i  8i  4  8 
= 2i   
   4  9  6i 4i  
  4

 
 1  4i  24  7i
= 2i   
  7i  24  24  7i

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  4  103i 
= 2i   
 625 

= 0.04i  1.035

For, Z2 = –1 2i,  The contour integral is zero

Z 2  4Z  8
  1 2
2 = Z1 + Z2 + Z3
 Z   Z  2 Z  5
 2

= 0.08i + 0  0.04i 1.035

= 0.04i 1.035

Model Questions asked in ACE ESE mains 2018 Test Series Mock-1, Q5(c).

03. (b) 2 j 1 j 2

+
vs L1=0.03H j3 2
I1 I2

1
For the network shown, S = 24 2 sin 100 t , coefficient of coupling k = between two
3
coupled coils.
(i) Write loop equations in vector-matrix for currents I1 & I2.
(ii) Obtain the impedance seen by the source S and the power factor of the source. (20M)

Sol: j1 j2


2

+
vs L1=0.03H j3 2
I1 I2

The supply voltage VS = 24 2 sin 100 t ,

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VS(rms) = 240 v,  = 100 rad/sec
Coefficient of coupling k = 1/3
L1 = 0.03 H
XL1 = jL1 = j(100)(0.03) = j3 

Mutual inductance, M  K L1 L2

 XM = K X L1 X L 2

1
=  j3 j3 = j1 
3
Apply KVL to 1st loop
VS + 2I1 + (j3 j1)I1 + (j1)I2 = 0

VS = (2 + 2j)I1 + (j1)I2 ………. (1)

KVL to 2nd loop

(2 + j3  j2)I2 + (j1)I1 = 0

(j1)I1 + (2+j1)I2 = 0 ………… (2)

(i) Writing the loop equations I1 and I2 in matrix form

240 o  2  2 j j1   I1 
 
 0   j1 2  j1 I 2 

(ii) From the equation (2)

(j1)I1 + (2+j1)I2 = 0

 ( j1)
 I2  I1
(2  j1)

Sub in (1) equation

VS = (2+2j)I1 + (j1)I2

 ( j1)
= 2  2 j I1  ( j1)  I1
(2  j1)

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 1 
VS  I1  2  2 j  
 2 j 

VS (2  2 j )(2  j )  1 4  6 j  2  1
 =
I1 2 j 2 j
3 6j
= = 336.86 
2 j
Impedance seen by the source VS = 336.86Ω
Power factor of the source = cos36.86 = 0.8 leading

03. (c)
Cf

I 2i I 20
I1i I10 Ie
+ +
Ii V
Vi AV  0 V0
Zi Ri Vi R0
– –

(i) Explain Miller effect capacitance in brief


(ii) For the given circuit, prove that
(A) Miller effect input capacitance
C Mi  1  A v C f (4+16=20M)

(B) Miller effect output capacitance


 1 
CM o  1  C f
 Av 

Sol: (i) Miller effect capacitance:

Vi A V0

Consider a capacitor 'C' is placed between input and output sections of an amplifier having a gain
of 'A' as shown above. Then its value is multiplied by a factor of (1–A) to obtain the equivalent

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capacitance at the input side as shown in fig. The multiplication of a capacitor, C by a factor
(1–A) is referred to as Miller effect or Miller multiplication

Vi A V0

C Mi = C (1–A)

NOTE: The Miller effect capacitance cause significant effect on the high frequency response of
BJT and FET amplifiers.
Consider the small signal model of a CE amplifier at High Frequencies

B1
C
Req Cc
vi ce ImVbe
ro B1

B1


Req
B1

vi ce cc 1  I m R 1L  I m Vbe1 R 1L  R L // r0

The upper 3 dB frequency of the amplifier shown in fig , is given by


1
fH 

 ce  cc 1  g m R1L
2rbe  

Conclusion: Due to the miller effect capacitor Ce 1  g m R 'L , the upper 3-db frequency in CE 
amplifier is highly reduced.

(ii) Step(1): KVL from input to output


1
Vi  I2i  V0  0
scf

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1
 I 2i .  vi  V0
scf

 V 
 Vi 1  0 
 Vi 

= Vi [1–AV]

Vi 1  A V 
 I 2i 
 1 
 
sc
 f

Vi 1 1
  
I 2i jc f 1  A V  jC M i

 CM i  Miller effect input capaci tan ce  Cf [1  A v ]

Step: (2): KVL from output to input

1
V0  I2  Vi  0
0
scf

1
 I 20  V0  Vi
scf

 V 
 V0 1  i 
 Vo 

 1 
 V0 1  
 Av 

V 1 1
 0  
I20  1  jc M o
jcf 1  
 A V

 1 
 CM 0  Miller effect output capaci tan ce  Cf 1  
 A v

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04. (a) Let the probability density function of a random variable X be given as:
5
f ( x )  e 5 x u ( x )   e 2 x u ( x )
3
Where  is a constant and u(x) is the unit step function. Calculate:
(i) The value of 
(ii) Mean of X
(iii) Variance of X (3+7+10 M)

Sol: Given,
5
Probability density function, f ( x )  e 5 x u ( x )  e 2 x u ( x )
3

 f x dx  1


0 
5 5 x
.e dx  0 3.e dx  1
2x

 2x
2
e   0

5
 
1
3  5
e 5 x   
0 =1

2

 20 2  1 5
e e  e
3
 
 e 50  1 

1  0  1 0  1  1
2 3
 1
 1
2 3
 2 4
(i)  
2 3 3
5 5 x 4
 f(x) = e 4x   e 2 x 4 x 
3 3
0 
4 5
(ii) Mean of X, =  x  e 2 x dx   x  e 5 x dx

3 0
3
0 
4 5
E(x) =  x  e 2 x dx   x  e 5 x dx

3 0
3

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0 
4  e2x e2x  5  e 5 x e 5 x 
  x.  1   x.  1 
3 2

4   3   5 25  0

4  1  5  1 
  0    0  0   0  0    0  
3  4  3  25 

1 1
E(x) =   = –0.2666
3 15

Variance, V(x) = E(x2) – [E(x)]2


2
 E(x ) = x
2
 f x dx


0 
4 5
  x  e 2 x dx   x 2  e 5 x dx
2


3 0
3

0 
4  e 2x e 2x e 2x  5  2 e 5 x e 5 x e 5 x 
 x 2 .  2 x    2    x .  2 x   2 
3 2 4 8   3   5 25  125 0

4  2  5  2 
  0  0    0  0  0  0  0  0   0  0  

3  8  3  125 

4 1 5  2 
     
3  4  3  125 

1 2
 
3 75

= 0.36

 Variance = 0.36 – (–0.2666)2

= 0.2889

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04. (b)
Rs = 1 I I2
1
+  0.1
y  
4
Vs V1 1 = RL
50 1  V2

Yin

For the two port network shown, the y-parameter matrix is given.
(i) Obtain the input admittance Yin as shown in the figure.
V2
(ii) Obtain voltage gain (20M)
Vs

Sol:
R2=1 I1
I2
+ 4  0.1
Vs  V1 y   1 = RL
50 1  V2

Yin

The Y parameters of two port network given by


I1 = Y11V1 + Y12V2
I2 = Y21V1 + Y22V2
The Y parameters
4  0.1
Y   
50 1 

 I1 = 4V1  0.1V2 ………… (1)


 I2 = 50V1 + V2 ………… (2)
The load voltage across RL,
 V2 = (I2)(1) = I2 ………… (3)
Applying KVL to the input side
VS + (1)(I1) + V1 = 0
 VS = V1 + I1 ………… (4)
Substitute (3) in equation (1) and (2)

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I1 = 4V1 + 0.1I2 ………… (5)

I2 = 50V1  I2

 I2 = 25V1 ………… (6)

Substitute (6) in equation (5)

I1 = 4V1 + 2.5V1 = 6.5V1

I1
 = 6.5 mho = Yin
V1

Input admittance Yin = 6.5 mho

(ii) From equation (4)

VS = V1 + I1

As I1 = 6.5 V1

 VS = 7.5 V1

From equation (6) I2 = 25 V1

I2
VS = 7.5 
25
75
VS = I2
250
From (3) equation V2 = I2
V2  I2
 
VS 75
I2
250
 250
=
75
V2
= 3.33
VS

V2
Voltage gain = = 3.33
VS

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04. (c) (i) State whether the given statement is true or false for practical oscillators with reasons.
“Loop’ gain is generally made slightly larger than unity”.
(ii) In a general form of oscillator circuit given in figure.

1

+
2
Vi ( AV1 R0 )
+
– +
3 Z3

I=0 Z2
V0

Z1

Given impedance Z1, Z2 and Z3 are purely reactive.


Prove that if Z1 and Z2 are capacitors then Z3 must be an inductor and vice versa.
(5+15 M)

Sol: (i) "The given statement is TRUE for practical oscillators"


Consider the basic structure of a sinusoidal oscillator i.e. an amplifier with positive feed back as
shown in fig.
Amplifier
Xs  A X0

Feed Back
N/w 

A
The overall gain of the amplifier with positive feedback, Af is given by A f  ...... (1)
1  A
Criterion for oscillations: At a specific frequency, fo, if the loop gain, A is equal to unity (i.e.
A=1), from eq(1), Af will be infinite. That is at that frequency, fo, the circuit will have a finite
output for zero input signal. Such a circuit is called as an oscillator. This condition, loop gain
A= 1 is called as Barkhausen criterion.
But the Barkhausen Criterion i.e A=1 guarantees sustained oscillations in a
mathematical sense only. The gain, A of any physical system is a function of the device

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parameters and it is well known that the device parameters are temperature sensitive. Therefore
the gain, A cannot be maintained as constant for a long time.
Case(i): Assume that with careful design, A is maintained at unity in oscillator, so that
sustained oscillations are obtained as shown:

X0

Case(ii): Assume that the sudden change in temperature reduces the gain of the system and leads
to A, loop gain to fall below unity i.e A<1, which will cause under damped oscillations and
over period of time oscillations may be vanished as shown.

X0

Under the circumstances we need a mechanism for forcing A to remain equal to unity at the
desired amplitude of output. This task is accomplished by providing a nonlinear circuit for gain
control.
Basically the function of the gain - control mechanism is as follows: First, to
ensure that oscillations will start, the circuit is designed such that, the loop gain A is kept at
slightly greater then unity this is corresponds to designing the circuit, so that the poles are in the
right half of the 'S" plane. Thus, when the oscillations are initiated, the amplitude of oscillations
will increases. When the amplitude reaches to the desired level, the non-linear network comes
into action and causes the loop gain to be reduced to exactly unity. That is the poles will be
pulled back to the j axis. This action will cause the circuit to sustain oscillations at this desired
amplitude.
Z1 V0
(ii) Step: (1) from the ckt, Vf 
Z1  Z3
V Z1
 f 
Vo Z1  Z3

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Step (2): ZL= (Z1+ Z3)//Z2

+ R0 +
V R A Z V0
– V –

ZL AVi
Step (3): V0 = Where A is open loop gain of OP-AMP
ZL  R 0

V ZL
 0  AV  A
Vi ZL  R 0

Step (4): According to Barkhausen criterion, AV= 1

 Z L   Z1 
 A V  A    =1
 Z L  R 0   Z1  Z 3 

 z1  Z 3 Z 2 
 Z Z Z 
 1 2 3

 Z1  Z 3 2   Z1 
 A  R0   1
Z1  Z 2  Z 3  Z1  Z 3 
 
 
 
 

 Z1  Z3 Z2 
 Z1  Z2  Z3 
 
A   Z1  Z3 Z2  R 0 Z1  Z2  Z3    Z1 
1
 Z1  Z2  Z3  Z  Z 
   1 3
 
 

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AZ1 Z 2
 =1
Z1  Z3 Z2  R 0 Z1  Z2  Z3 

Step: (5) Let Z1= jx1, Z2= jx2 & Z3=jx3


 Ax1x 2
 1
jx1  x 3  jx 2  jR 0 x1  x 2  x 3 
 Ax1x 2
  1 ......... (1)
 x1  x 3 x 2  jR o x1  x 2  x 3 

Case(i): General equation for frequency of oscillation in LC oscillators:

NOTE: Since gain of amplifier is a real value and log gain, A is also a real value, the
imaginary part in equation () is should be zero.
i.e X1+ X2+ X3= 0 -------- (2)

Case (ii): condition for sustained oscillations:


consider the real part in equation (1)
Ax1x 2
 1
x1  x 3 x 2
Ax1x 2
 1
 x 2 x 2
 x2
A 
x1

NOTE:

(1) If Z1 and Z2 are capacitors, to satisfy equation (2) & to maintain a phase shift of 180 in the

feedback net work, Z3 should be an inductor.

(2) If Z1 and Z2 are inductors, again to satisfy equation (2) and to establish 180 phase shift in

the feed back Z3 should be a capacitor.

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SECTION - B

05. (a) Mention the type of Bravais space lattice, relationship of crystal axial lengths (x,y,z) and
relationship of interaxial angles (,  , ) in the following order of the crystal system.
(i) Triclinic
(ii) Monoclinic
(iii) Orthorhombic and
(iv) Trigonal (12M)
Sol:

Crystal structure Lattice Parameters

abc
1. Triclinic
      90
abc
2. Monoclinic
 =  = 90,   90
abc
3. Orthorhombic
 =  =  = 90
a=b=c
4. Rhombohedral (trigonal)
 =  = 90,   90

1 3
2 4

Triclinic
Simple
orthorhombic

Same Questions asked in ACE ESE mains 2018 Test Series Mock-1, Q8(a)(i)

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05. (b) A standard cell of 1.0185 V used with a simple potentiometer balances at 50 cm Calculate.
(i) The emf of cell which balances at 72 cm
(ii) The percentage error in voltmeter which balances at 64.5 cm when reading 1.33 V
(iii) Percentage error in an ammeter that reads 0.43 A and balance is obtained at 43.2 cm
with Pd across a 2 resistor in the ammeter circuit. (12M)

Sol: EMF of standard coil = 1.0185V


1.0185
Voltage drop per cm length of potentiometer wire, v   0.02037 V / cm
50
(i) The emf of a coil which balances at 72 cm,
= V/cm length
= 0.02037  72 = 1.46664 V
(ii) The P.D which balances at 64.5 cm is
= 0.02037 V/cm 64.5 cm
= 1.313865 V
Voltmeter reading = 1.33V
1.33  1.313865
% error   10
1.313865
= 1.228% ≃1.23% high

(iii) The P.D which balances at 43.2 cm


= 0.02037 V/cm  43.2 cm
= 0.879984 V
Current through 2 resistor
0.879984
I  0.4399A
2
0.43  0.4399
% error =  100
0.4399
= –2.26 % Low

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05.(c) (i) Write down algorithm in Pseudocode for sorting an array in descending order. Specify
the name of the algorithm you have used. (6M)
(ii) Write a program segment in any higher level language for Linear search problem.
(Specify which language you are using) (6M)

Sol: (i) void sort (array [ ], n) //size of array is n


{
for i=1 to n, step by 1
{
for j= 0 to n–i –1
{
if (Array [j] < Array [j+1])
{
temp = Array [j];
Array[j] = Array[j+1];
Array [j+1] = temp;
}
}
}
The algorithm used is: Bubble sort
Array is having index: 0 to n–1
Array size: n

(ii) Linear search:


Programming language used is C-language
int linear_search (Array [ ], item, n)
{
/* item is the element which is to be searched, n is number of elements in the array, array
has indexed 0 to n–1 */
int i;

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for (i = 0; i < n; i++)
{
if (Array [i] = = item)
{
return i; /* for successful search return index of elements*/
}
}
return –1; /* for unsuccessful search return –1 */
}

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05. (d) A non-inductive shunt is used to increase the range of a 10 A moving iron ammeter to 100
A. the impedance of the instrument including the leads is (0.06+j4.71 10-3) . If the
combination is correct on a dc circuit, find the error on ac circuit. (12M)

Sol: Impedance of instrument (Zm) = Rm + jXm = (0.06 + j4.71 × 10–3)Ω


DC Measurement:
New range 100 Rm
m= = = 10 100A Im=10A
Old range 10

 m = 10
Rm 0.06 0.06
Rsh = =   Ish Rsh
m  1 10  1 9 =90A

AC measurement:
ImZm = Ish × Rsh Zm
100A Im

(100 – Ish) × 0.062  4.7110 3 2 = Ish ×


0.06
9

0.06 Ish Rsh


(100 – Ish) × 60.1845 × 10–3 = Ish ×
9

6.01845
 I sh  = 90.0275 A
 0.06 
  60.1845  10 3 
 9 

 Im = 100 – Ish = 100 – 90.0275

Im = 9.9725 A

Im  IT
%Error =  100
IT


9.9725  10  100
10
%Error = – 0.275%

Model Questions asked in ACE ESE mains 2018 Test Series Mock-1, Q7(b)

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05.(e) (i) Explain the electrochemical breakdown in insulators and discuss any two factors that
accelerates the breakdown. (8M)
(ii) A magnetic material having almost a square hysteresis loop has a coercivity of 50 A/m
and a remanence of 0.5 T. If this material is used in a toroidal inductor of mean
diameter 1.6 cm, with a cross-sectional area of 0.2510-4 m2, calculate the power loss at
a frequency of 50 Hz when the material is driven around one complete hysteresis cycle.
(4M)

Sol: Electro-chemical deterioration is due to the presence and mobility of ions in the insulation,

which are responsible for leakage current and energy loss in the material. In most of the cases the

final breakdown resulting from electro-chemical deterioration is thermal breakdown.

Almost all insulating materials have free ions, which are responsible for leakage current in the

presence of electric field. Such ions after reaching the electrodes reduce their charge and may

also attack the electrode metal evolving some gas, or some other substance may be deposited on

to the electrodes. Such type of activities of the ions are chemically or electrically harmful and

many times lead to rapid failure of insulation. The rate of electro-chemical deterioration is

determined by the magnitude of leakage current and other factors like concentration of ions in

the insulations, temperature, and whether the material is polar one or not. To avoid electro-

chemical deterioration:

(i) The impurities should be avoided in the insulating materials

(ii) It should not be operated at elevated temperature

(iii) Care should be taken to avoid contamination in polar materials, which otherwise, will result

in high leakage currents.

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(ii) 0.5 T

50 A/m

Hysteresis losses = 100 × 1 = 100 J/m3


Volume = (πd) × cross sectional area
= π × 1.6 × 10–2 × 0.25 × 10–14
= 1.256 × 10–6 m3
Hysteresis losses = 100 × 1.256 × 10–6
For one cycle = 125.6 × 10–6 Joule
For 50 cycles = 50  125.6 × 10–6 = 62.8 10–4 joules

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06. (a) (i) Explain electrical resistivity of metals in terms of thermal and residual components. Also
draw the schematic variation of them with respect to temperature. (8M)
(ii) Write the relation between magnetic susceptibility and temperature according to Curie
Law, Curie-Weiss Law and Neel Law. Sketch the variation of reciprocal of
susceptibility with temperature as per the above laws. (6M)
(iii) What are the ferrites? Mention 3 disadvantages. State the reason, why ferrites are
suitable for high frequency operation. (6M)

Sol: (i) The thermal component T; which arises from the lattice vibrations, and the residual resistivity
r, caused by impurities and structural imperfections. The latter is independent of temperature.
The total resistivity is given by
 = T + r …………(1) (Matthiessen’s rule)
Temperature: The electrical resistance of most metals increases with increase in temperature.
At temperatures above the so called Debye temperature, the thermal component of resistivity of
conductors is approximately linear.
  0 [1+  (T – TRT)+ …..]
Where 0 is room temperature (TRT) resistivity
 is about 0.004 per C

Resistivity
total

T(thermal)

d(defect)

i(impurity)

Temperature (K)

Alloying: A solid solution has a less regular structure than a pure metal. Consequently, the
electrical conductivity of a solid solution alloy drops off rapidly with increased alloy content.
alloy = copper + Si -ohm-cm
Where S = Atomic percentage of added impurity

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i = Increases in resistivity for one atomic percent addition of impurity.


Cu–3 at% Ni
Cu–2 at% Ni
Cu–1 at% Ni
Cu

r
T

Cold Work: Mechanical distortion of the crystal structure decreases the conductivity of a
metal because the localized strains interfere with electron movement. Thus, hard drawn
copper wire has a lower conductivity than annealed copper. Subsequent annealing restores the
electrical conductivity by establishing greater regularity in the crystal lattice.
Age Hardening: Age hardening increases the resistivity of an alloy.
(ii) The relation between magnetic susceptibility and temperature

(a) Curie Law:


1/m
C
m 
T
Ex: oxygen

T
(b) Curie-Weiss Law:
1/
C
m 
T
Ex: Fe, Co, Ni
TC T

(c) Neel’s Law:


1/
C
 =
T  N
Ex: Cr, Mno
N T

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(iii) Ferrite Composition: Ferrites are the important class of magnetic materials containing iron
oxide and metal oxides in different ratio depending upon their type. On the basis of their crystal
structure, ferrites are of three types namely spinel ferrite, garnet and hexagonal ferrite.
There are 3 types of Ferrites:
(a) Spinel Ferrite: A spinel ferrite is a ferromagnetic material, containing mostly iron oxide
which is derived from magnetic (Fe2+O, Fe 22 O 3 ) represented by the formula M2+ Fe 22 O 4 . M is
a divalent metal iron like cobalt (Co), nickel (Ni), copper (Cu), manganese (Mg), zinc (Zn),
cadmium (Cd) etc. Trivalent Fe3+ ions can be replaced by trivalent metal ions like Al3+ , Cr3+,
Ga3+ etc. In all cases the ionic radii of the substituting ion should be between 0.5 to 1.0 A.
(b) Garnet Ferrite: The second type of ferrite is a garnet having cubic structure with general
formula R 32 Fe 35 O12 where R is a rate earth ion (like dysprosium (Dy3+), gadolium (Gd3+),
samarium (Sm3+) etc or yttrium (Y3+). Fe3+ can be replaced by trivalent metal ions like Al, Cr,
etc.
(c) Magneto-plumbite Ferrite: Magneto-plumbite is having a hexagonal structure and are

represented by the formula MFe12O19 where M is a divalent metal ion with large ionic radius like

Ba2+, Sr2+, Pb2+.

Disadvantages:

1. More porocity

2. High brittle.

3. More cost of production.

The ferries are used for high frequency applications

(1) High initial permeability

(2) High Remanance.

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06. (b) (i) Prove that the most probable value is the mean value (6M)
(ii) What is an RS-232 interface? How many signals it can handle? How many wires are
sufficient for operation? (6M)
(iii) What is creeping in energy meters? State the reasons for the same and how it is
avoided. (8M)

Sol: (i) Most probable value is mean value:


1. Mean is calculated based upon all the observations in the data.
2. It is amenable to algebraic treatment. The mean of the composite series interms of the means
and the sizes of the component series is given by
n

n i x
x i 1
n

n
i 1
i

3. Of all the averages arithmetic mean is affected least by fluctuations of sampling. So that
arithmetic mean is a stable average.
4. Sum of deviations of the given values from their mean is always zero.
 n 
i.e.,   f i x i  x   0 
 i 1 
5. The expected value (mean) is a weighted average of all the possible values of the random
variable.
n 
x  E x  =  x. p(x )   x. f x dx

0

 p( x )  1
x 0

 f x dx  1



Thus we see that arithmetic mean satisfies all the properties laid down by prof. Yule for an ideal
average.
(ii) RS-232 interface is standard for the interchange of serial binary data between a DTE (data
terminal equipment) such as a computer terminal and a dce (data communication equipment).

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The original standard uses 25 wires to connect the two devices.
However, in reality only three of these wires are sufficient.

(iii)In some meters, a slow but continuous rotation is obtained even when there is no current flowing
through the current coil and only pressure coil is energized. This is called creeping.
Causes:
 Main reason is Over voltages and over static friction compensation
 Excessive lubrications, vibrations, stray magnetic field of Instrument.
Creep error compensation :
(i) To eliminate the creeping error, two diametrically opposite holes are drilled in the disc ; the disc
will come to rest with one of the holes under the edge of a pole of the shunt magnet.
(ii) A small piece of iron is attached to the edge of the disc. The force of attraction exerted by the
brake magnet on the iron piece is sufficient to prevent creeping of disc.
Same Questions asked in ACE ESE mains 2018 Test Series Test-3, Q3(a), Test-9, Q7(a)

06. (c) (i) Can we use Semiconductor Memory for secondary storage ? Justify your answer. (5M)
(ii) What exactly is the role of Control Unit in CPU ? How is it different from that of a
Arithmetic Logic Unit? (6M)
(iii) How exactly is an array stored in main memory? Illustrate with the help of storage of a
matrix. What will be the exact address of element A (3, 7) of an 8  9 array A assuming
that location of the first element is d. (9M)

Sol: (i) Yes semiconductor memory can be used as secondary storage.


Now a days most of the Hard disks (Removable) are designed with semiconductor memories
with flash technology and pendrive is also used for secondary storage (pendrive uses flash
technology).
Flash memory is widely used in advanced cell phones and digital computers.
Merit: semiconductor secondary storage memory is faster than other secondary storage
memories.
Demerit: These are more costlier than other secondary storage.
Note: Example for other secondary memories are magnetic hard disk and CD & DVD.
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(ii)

 Control unit is the hardware inside a CPU for coordinating & controlling the activities of various

sub sections within the CPU and other devices connected to the system bus.

 When an instruction is fetched from code memory, its opcode part will be decoded by decoder

which produces timing information and control information. The timing information is about

further clock cycles required for completing operation & control information is about type of

operation to be performed.

The outputs of the decoder will be given to control unit. Then the role of the control unit begins

where it generates required control signals to internal sections and external units of CPU. And,

inturn operation specified in the opcode will be performed, ALU operation is different from

control unit.

 The ALU (Arithmetic Logic Unit) performs various Arithmetic (like addition, subtraction etc).

and logical (like AND, OR etc) operations.

 Control unit generates control signals to ALU to decide the type of operation.

Instructions opcode

Control signals to
internal sections
Decoders

Control Unit
ALU
Control signals to ALU

Control signals to
external sections

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(iii) Array:

An array is stored in memory on consecutive memory locations

If array is 2-D array: then array storage has 2 types of schemes: Row major order, and column

major order.

1-D array storage:

Array [5]

Suppose each element takes 2 memory locations and base address is 200.
Memory

200 0
202 1
204 2 5 elements
206 3
208 4

2-D array:
Array [2] [3]
Number of rows = 2
Number of columns = 3
A 00 A 01 A 02 
A A A 
 10 11 22 

Row Major order:


Elements are stored row-wise.
Base address=200, element size = 2

200 202 204 206 208 210


A00 A01 A02 A10 A11 A22
0 1 2 3 4 5
relative positions of elements

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Column major order:

Elements are stored column-wise

200 202 204 206 208 210


A00 A10 A01 A11 A02 A22
0 1 2 3 4 5

For the given details:

Array size = 89 = mn

Number of rows (m) = 8

Number of columns (n) = 9

Assuming element size = w

Starting address of array given = d

Starting index = 0

For row major order:

Address (A [i, j] ) = Base + w * [i * n + j]

Address (A[3,7]) = d+w* [3 * 9 + 7] = d+34w

For column Major order:

Address (A[i,j])= Base+ w* [j * m + i]

Address (A[3, 7]) = d + w * [7 * 7 + 3]

= d+52w

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07. (a) (i) Supporting with suitable figures, define initial permeability and maximum

permeability. Mention the approximate range of values for iron. Mention one

importance each of initial and maximum permeabilities. (8M)

(ii) Specific gravity of a ceramic is 3.2 g/cm3. Calculate the percentage apparent porosity

and percentage true porosity with the following data:

Ceramic when weighed dry = 360 g

Ceramic when weighed after soaking in water = 385 g

Ceramic weighed while suspended in water = 224 g (6M)

(iii) What is photo-conductivity? Discuss the factors that are to be considered for the

selection of photo-conduction material. (6M)

Sol: (i) The initial permeability is the limiting value of the core materials permeability at the origin of
the magnetization. B
1 B
i  lim
0 H  0 H

Initial permeability I = tan1

m
i
H

Maximum permeability (max): The maximum permeability is the value at the core material
permeability at high magnetization.
max = tanmax
 The initial permeability of iron is (i) = 1150
 The maximum permeability of iron is (max) = 61,000
 Initial permeability describe the relative permeability of a material of low values of B. The
maximum value for permeability is frequently a factor of between 2 and 5 or more above its
initial value.

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(ii) Given data,
Specific gravity of ceramic = 3.2 g/cm3 = 
Ceramic when weighted dry = 360g = Wd
Ceramic when weighed after soaking in water = 385g = WW
Ceramic weighed while suspended in water 224g = WS

(1) Percentage apparent porosity =


soaked water  Dry water   100
soaked water  suspended water 
385  360
=  100
385  224
= 15.52%
  Apparent specific Gravity 
(2) Percentage of true porosity = 1     100
  True specific Gravity 

 B
= 1    100
 
Wd 360
B  = 2.24
WW  WS 385  224

 2.24 
% of true porosity = 1    100 = 30%
 3.2 
(iii) Photoconductivity
 Illumination of an insulating crystal by photons of energy equal to or greater than the band gap
Eg usually excites electrons from the valence band to the conduction band. It makes available the
free electrons in the conduction band and the free holes in the valence band, both of which
contribute to the electric current under the influence of an external electric field. This
phenomenon is called photoconductivity and is used in light meters (in cameras) and solid state
infrared detectors
photons

Wire
W
H
Ohmic
Contact L

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Consider semiconducting slab placed in dark. Since a very small current flows in dark, the dark
conductivity is
d = nee + peh  0
Where n and p are free electron and hole concentrations, e and h are the electron and hole
mobilities, and e is the electron charge. When the electromagnetic radiation of an appropriate
frequency is allowed to fall on the semiconductor slab, the electrical conductivity increases, the
change in the conductivity (assuming n = p) is given by
 =  – d = n e(e + h)
 ne e   h 

d d

If “” is the carrier lifetime and f is the rate of their generation (i.e. number of electron-hole pairs
produced per second by the absorbed photons), then the average photo induced concentration is
given by
n = f 
Where n = 1020m-3 for germanium
In a practical device, the sensitivity is expressed as a gain G.
If ‘t’ is the transit time of the carriers between the electrodes then

G
t
Thus, photoconductivity is large when the lifetime is large. A pure material is generally found to
have low  (10-6s) due to the greater probability of electron hole recombination and hence is
relatively insensitive. However a careful doping can suppress recombination and hence increase
 and sensitivity.

intrinsic Extrinsic

h Ec

hole
h Electron
h
Ev

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In CdS careful doping of iodine increases  to 10-3 sec.

Iodine substituting for sulphur acts as donor.

Cd2+ vacancies act as efficient hole traps. During photoexcitation, holes are readily trapped and

electron have much less chance of recombination and hence average lifetime is increased

CdS and CdTe single crystals are widely used as photoconductors because of their high

sensitivity and response to visible light wavelengths.

Model Questions asked in ACE ESE mains 2018 Test Series Test-8, Q4(a)(i).

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07. (b)
30010–12F

20 k
1.2k
D

R
0.05 F
C

For the bridge circuit shown determine the values of R and C. Derive the formula used.
(20M)
Sol: Given bridge can be redrawn as

C
20 k
R
D
1.2 k

0.05 F

30010–12 F

 Given bridge is Schering bridge.


C1
R3
R1

D
R4

C2
C4

E, f
Under bridge balanced condition
Z1 Z4 = Z2 Z3
 j  R4  R3
 R 1    
 C1  1  jC 4 R 4  jC 2
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 j 
 R 1   jC 2 R 4   R 3 1  jC 4 R 4 
 C1 

C2R 4
j R 1 R 4 C 2   R 3  jC 4 R 4 R 3
C1

Equating real parts,

C 2 R / 4 R 1  C 4 R 3 R 4

C4 R 3
R1 
C2

 From the given data, we can write

R1 = R, C1 = C, R3 = 20 k, C2 = 0.05 F

R4 = 1.2 k, C4 = 300 10-12 F

By substituting in the above equations.

0.05  10 6  1.2  103


We get, C 
20  103

C = 3 nF

300  10 12  20  103


R = 12 10-6103104
0.05  10 6

R = 120

Model Questions asked in ACE ESE mains 2018 Test Series Test-3, Q6(a)

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07. (c) (i) How is Division exactly done by ALU? (7M)
(ii) Prove with illustration that NAND is a “Universal Gate”. (6M)
(iii) How will you implement a two-way switch using minimum number of logic gates?
(7M)
Sol: (i) Integer Division
Division is implemented using computer specific methods. Division can be implemented on
computer systems by repeatedly subtracting the divisor from the dividend and counting the
number of times that the divisor can be subtracted from the dividend before the dividend
becomes smaller than the divisor. For example, 15 can be divided by 5 by subtracting 5
repeatedly from 15, getting 10, 5 and 0 as intermediate result. The quotient, 3, is the number of
subtractions that had to be performed before the intermediate result became less than the
dividend. Below shown an exemplary division steps for 15  5.
0b0101
ob11 0b1111
00
1111
11
0011
00
11
11
0b00

An Example of Division steps for 15  5


Restoring Algorithm
The following algorithm, called the restoring algorithm for a division, can be used. Assume that

X register has k-bit dividend and Y has the k-bit divisor. Assume a sign bit S has the sign.

1. Start: Load 0 into accumulator k-bit A and dividend X is loaded into the k-bit quotient register
MQ.
2. Step A: Shift 2k-bit registers pair A- MQ left.
3. Step B: Subtract the divisor Y from A.
4. Step C: If sign of A (msb) = 1, then reset MQ0 (lsb) = 0 else set = 1

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5. Step D: If MQ0=0 add Y (restore the effect of earlier subtraction).
6. Steps A to D repeat again till the total number of cyclic operations = k.
7. At the end, A has the remainder and MQ has the quotient.

First Second
Number of operations
Step S-flag* Register Register Action Taken
(instructions)
for A for MQ
3 for clearing C,
Start 0 0b 0000 0b 0000 Clear S, A, MQ
A and M
Load dividend X (lower k bits)
0 0b 0001 0b 1110 between MQk–1 and MQ0 and 2 for loading A and MQ
dividend higher bits in A
Step 0A 0 0011 1100 Shift left S-A-M 2

Step 0B 0 0000 1100 Subtract Y from S-A, result in S-A 1

Step 0C 0 0000 1101 MQ0 = 1 as S = 0 1

Step 0D 0 0000 1101 Skip restore by adding as S = 0 1 (test S)

Step 1A 0 0001 1010 Shift left S-A-M 2

Step 1B 1 1110 1010 Subtract Y from S-A, result in S-A 1

Step 1C 1 1110 1010 MQ0 = 0 as S = 1 1

Step 1D 0 0001 1010 Add Y into S-A to restore as S= 1 1

Step 2A 0 0011 0100 Shift left S-A-M 2

Step 2B 0 0000 0100 Subtract Y from S-A, result in S-A 1

Step 2C 0 0000 0101 MQ0 = 1 as S = 0 1

Step 2D 0 0000 0101 Skip restore as S = 0 1(test S)

Step 3A 0 0000 1010 Shift left S-A-M 2

Step 3B 1 1101 1010 Subtract Y from S-A, result in S-A 1

Step 3C 1 1101 1010 MQ0 = 0 as S = 1 1

Step 3D 0 0000 1010 Add Y into S–A to restore as S = 1 1

Answer 0 Remainder = 0 Quotient Decimal 10 Total 25

* after the left shift from msb of A.

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(ii) If it is possible to implement any logic function using only the basic gates, then the gate is called

universal.

To implement any logic function the basic function required is OR, AND and NOT gates. If it is

possible to implement there three basic gates using only the gates then it is possible implement

any logic function.

(1) Realization of AND gate using NAND gate:

A AB
AB =AB
B

(2) Realization of OR gate using NAND gate:

A
A
A. B  =A+B
B B

(3) Realization of NOT gate using NAND gate:

A A. A  A

 NAND gate is universal gate

0 0
(iii)
A B
1 1

V Y

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To switch on bulb A = 0 and B = 0 (or) A = 1 and B = 1.

To switch it OFF the bulb A = 0 and B = 1 (or) A = 1 and B = 0

A B ( Y  A B  AB )
= AB
0 0 1
0 1 0
1 0 0
1 1 1

Using AND-OR:

A
B
A
B

Using NOR-NOR:

AB
A
A๏B

B AB

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08.(a) (i) Explain the Top-Bottom and Bottom-Up approach to produce the nanostructure.
Name the methods used in each case to produce nanomaterial. (8M)
(ii) The current measured in a superconducting ring by 0.01% accuracy meter after one
year shows no decay of current. If there are 1028 electrons/m3, calculate the
conductivity. How may times larger is this conductivity than that of copper of
resistivity 1.724 × 10–8 Ωm. (8M)
(iii) Addition of 0.25 atomic percent nickel and 0.4 atomic percent silver into copper at 298
K increases the resistivity by 0.012 µΩcm and 0.016 m respectively. If the
resistivity of copper is 0.015 m at 298 K, determine the conductivity of the
resulting alloy. (4M)
Sol:
(i) Top down Approach:
 Top down approach refers to slicing or successive cutting of a bulk material to get nano sized particle.

 Attrition or Milling is a typical top down method in making nano particles

 The nanomaterials are derived form a bulk substrate and obtained by progressive removal of material, until
the desired nanomaterial is obtained.

 This approach leads to the bulk production of nano material. Regardless of the defects produced by top
down approach, they will continue to play an important role in the synthesis of nano structures.

Ex: (1) photo lithography

(2) Scanning lithography

(3) E- beam lithography

Photo Lithography:

This technique follows the principle of transferring an image from a mask to a receiving substrate.

A typical lithographic process consists of three successive steps:

 Coating a substrate (Si wafer or glass) with a sensitive polymer layer (called resist)

 Exposing the resist to light, electrons or ion beams

 Developing the resist image with a suitable chemical(developer), which reveals a positive or negative image

on the substrate depending on the type of resist used.( i.e. positive tone or negative tone resist).

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(2) PHOTOLIEOGRAPHY IN
(1) PHOTO LITHOGRAPHY BIOPATTERNING
Light source
Light source

PHOTORESIST
SURFACE
1.Expose
Photorosist
Through a
PHOTORESIST
mask
Si 1. Expose
Photoresist surface
2.Deposit through a mask
2. Develop metal
Photorosist
3. Dissolve
Unexposed 2.Deposit protein
3. Chemical photorosist solution
etc
hi
METAL
4. Dissolve MICROPATTERV PROTEIN PATTERN
Unexposed
Photorosist

Problems associated with top down approach:


 The biggest problem with top down approach is the imperfection of surface structure and significant
crystallographic damage to the processed patterns. Due to these imperfections design and fabrication of
devices is difficult.
 The top down approach introduces internal stress, in addition to surface defects and contaminations

Bottom up Approach:
 Bottom up approach refers to the build up of a material from the bottom; atom by atom, molecule by
molecule or cluster by cluster.
 The colloidal dispersion is a good example of bottom up approach in the synthesis of nano particles.
 This method is not a new concept. All the living beings in nature observe growth by this approach only and
also it has been in industrial use for over a century.
Ex: The production of salt and nitrate in chemical industry.
 Bottom up approach gives a better chance to obtain nano structures with less defects, more homogeneous
chemical composition.
 Bottom up methods can be divided into gas-phase and liquid-phase methods.

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Gas-phase methods:
Plasma arcing and chemical vapour deposition

Liquid phase methods:


Sol-gel synthesis, molecular self-assembly

Chemical vapour deposition:

Pressure gauge
Substrate

Gas out

Gas in heat

The material to be deposited is first heated to its gas form and then allowed to deposit as a solid on a

surface.

 The method is normally performed under vacuum.

 The deposition can be direct or through a chemical reaction so that the material deposited is different from

the one volatilized.

 This process is routinely used to make nanopowders of oxides and carbides of metals if carbon or oxygen

are present with the metal.

 The method can also be used to generate nanopowders of pure metals, although not so easily.

 Chemical vapour deposition is often used to deposit a material on a flat surface.

 When a surface is exposed to a chemical vapour, the first layer of atoms or molecules that deposit on the

surface can act as a template on which material can grow.

Model Questions asked in ACE ESE mains 2018 Test Series Test-7, Q4(c).

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(ii) Given data,
n = 1028 elec/m3
e = 1.6 × 10–19
 = 1.724 × 10–8 Ωm
Let us assume that the super conducting ring relaxation time (t) = 3.15 × 1011 sec
ne 2 t
Electrical conductivity () =
m

=
 
2
10 28  1.6  10 19  3.15  1011
9.1 10 31
= 0.883 × 1032 n-m–1
1 1
Electrical conductivity of copper () = 
 1.724  10 8
= 0.58 × 108 n-m–1
The electrical conductivity of super conducting ring is 1.5278 × 1024 larger than copper.

(iii) Given data,

Host material = cu

cu = 0.015 Ω km

Impurity materials are Ni & Ag

Atomic percent of Ni added to cu is (SNi) = 0.25

Atomic percent of Ag added to cu is (Scu) = 0.4

Increase in resistivity of Ni (Ni) = 0.012 Ω m

Increase in resistivity of Ag (Ag) = 0.016 Ω

alloy = cu + SNi Ni + SAg Ag

= 0.015 + 0.25(0.012) + 0.4(0.016)

= 0.0244 Ωm

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08. (b) The power consumed by a single phase 11 kV load taking 100 A at 0.5 power factor lagging
is measured on a dynamometer wattmeter used in conjunction with potential transformer
(PT) and current transformer (CT). Determine the reading of the wattmeter considering
the following data:
Nominal ratio of PT and CT are 100: 1 and 20: 1
Ratio error of PT and CT are +0.8% and –0.2%
Phase angle errors of PT and CT are +42 minutes and +90 minutes.
Phase angle of the pressure coil due to its inductance is 30 minutes. (20M)

Sol: Phase angle of pressure coil circuit () = 30

Phase angle of load = cos–1(0.5) = 60

Where

V = voltage across the load = 11 kV

I = load current = 100A

 = Phase angle between current and voltage = 60

 = phase angle bandwidth

Currents in the current and pressure coils of watt meter

Vs = voltage across secondary of the potential transformer.

Is = secondary current of current transformer.

Ip = current in the wattmeter pressure coil.

 = angle by which Is lags Vs on account of inductance of pressure coil = 30 = 1/2

o
3
 = Phase angle of potential transformer = 45=
4

o
1
 = phase angle of current transformer = 90 = 1
2

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Phase angle between pressure coil current IP and current Is of wattmeter current coil

=–––

3 1 3
 60   
2 2 4

= 57.25

cos 
Correction factor  k 
cos . cos 

cos 60
=
cos0.5  cos57.25

= 0.924

kn  R
Percentage ratio error =  100
R

k n 100
Actual ratio R 
100  percentage ratio error 
20  100
Actual ratio of C.T =
100  0.2
= 20.04
100  100
Actual ratio of P.T =
100  0.8
= 99.2

Power of lead

= k  actual ratio of P.T  actual ratio of C.T  wattmeter  wattmeter reading

(2) power of lead = 11kV 0.5 100

= 0.924  20.4 99.2wattmeter reading

(3) Wattmeter reading

= 294.18 Watts

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08.(c) (i) Is the use of Virtual Memory advisable for Real Time Systems? Justify briefly your
answer (7M)
(ii) Compare briefly and precisely the LINUX OS with Windows-NT OS. (5M)
(iii) For File Management how does a DBMS help? (8M)

Sol:
(i) Generally speaking, RTOS and VM are mutually exclusive. The RT in RTOS stands for “Real
Time”, meaning that the OS has a quick (and deterministic) task swap time and IRQ latency.
You can’t really have that when some of your memory is located in Flash/SSD/HD and might
have to be swapped into main memory.
(ii)
Topics Linux Windows
Price The Linux kernel, and the Microsoft Windows usually costs
GNU utilities and libraries between $99.00 and $199.00 USD
which accompany it in most for each licensed copy. However,
distributions, are entirely free Windows 10 is being offered as a
and open source. You can free upgrade to current owners of
download and install Windows 7 or Windows 8.1.
GNU/Linux distributions
without purchase. Some
companies offer paid support
for their Linux distributions,
but the underlying software is
still free to download and
install.

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Ease of GNU/Linux operating systems Windows is one of the easiest
use have a steeper learning curve desktop operating systems to use.
for the average user. They One of its primary design
frequently require a deeper characteristics is user friendliness
understanding of the and simplicity of basic system tasks.
underlying system to perform Its ease lack
day-to-day functions. of difficulty is considered a positive
Additionally, by users who want their system to
troubleshooting technical just work. However, more proficient
issues can be a more users may be frustrated by
intimidating and complicated oversimplification of system tasks at
process than on Windows. the expense of fine-grained control
However, some distributions over the system itself.
such as Ubuntu and Linux
Mint are designed specifically
to ease the transition from
Windows to a Linux
environment.
Reliability Linux is notoriously reliable Although Microsoft Windows has
and secure. It has a strong made great improvements in
focus on process management, reliability in recent years, it's
system security, and uptime. considered less reliable than
Linux. Many of the sacrifices it
makes in the name of user-
friendliness can lead to security
vulnerabilities and system
instability.

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Software There thousands of programs Windows commands the highest
available for Linux, and many number of desktop users, and
are available as easy-to-install therefore the largest selection of
software packages — all for commercial software. It also has the
free. Also, many Windows largest selection of video games by
programs can be run on Linux a wide margin.
using compatibility layers such
as WINE. Linux supports a
wider array of free software
than Windows.
Hardware Fifteen years ago, Linux Windows has a massive user base, so
struggled to support new it would be madness for
hardware. Manufacturers often a consumer hardware manufacturer
considered Linux support a not to support Windows. As a
secondary concern (if they Windows user, you can rest assured
considered supporting it at all). that your operating system is
Furthermore, device drivers compatible with any hardware you
for might buy.
Linux were created only by
enthusiasts who devoted their
own time and resources to
making Linux compatible with
new hardware. Since then, the
Linux user base has grown
exponentially. Today, the
majority of hardware
manufacturers give Linux support
the same priority as Microsoft
Windows.

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Security Linux is a highly secure Microsoft has made great security
operating system. Although improvements over the years. But as
attack vectors are still the operating
discovered, its source code is system with the largest user base,
open and available for any user especially among novice
to review, which makes it computer users, it is the primary
easier to identify and repair target for malicious coders. As a
vulnerabilities. result, of all major operating
systems, Microsoft Windows is the
most likely to be the victim of
viruses and malware.
Support There is a massive amount of Microsoft Windows offers
online support available for integrated and online help systems,
Linux, including here on and there are thousands of
Computer Hope. informative books
about Windows available for every
skill level.

(ii) A Database Management System (DBMS) is a combination of computer software, hardware,


and information designed to electronically manipulate data via computer processing. Two
types of database management systems are DBMS’s and FMS’s. In simple terms, a File
Management System (FMS) is a Database Management System that allows access to single
files or tables at a time. FMS’s accommodate flat files that have no relation to other files. The
FMS was the predecessor for the Database Management System (DBMS), which allows
access to multiple files or tables at a time. Below are some of the problems in FMS which
was resolved in DBMS.

1) Data Redundancy and Inconsistency:-


The Redundancy leads to higher storage and access cost. In addition it may leads to data
inconsistency i.e., The various copies of same data may no longer agree.

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2) Difficulty in accessing data:-
File System requires to have an application program for each request i.e., more responsive data
retrival systems are required for general views.

3) Data Isolation:-
Because data are scattered in various files and may be in different formats. Writing new
application program s to retrieve the appropriate data is difficult.

4) Integrity problems:-
The data values stored in the database must satisfy certain types of consistency constraints.
Eg: The balance amount of customer may never fall below a prescribed amount [say Rs 500]

5) Atomicity problems:-
In many applications if a failure occurs the data be restored to the consistent state the existed
prior to the failure i.e it must happen in its entirety (or) not at all. It is difficult to ensure
atomicity in a file processing system.

6) Concurrent access anamolies:-


For the overall performance of the system and faster response many systems allow multiple users
to update the data simultaneously in such an environment, iteration of concurrent updates may
result in inconsistence in data.

CONCLUSION:-
These difficulties and many others prompted the development of database system over the file
management system.

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