Intro to UARTs

April 2010
Why use a UART?

• UARTs are everywhere!

• Simple way to send data from one system to
another system
• Add additional functionality to an application

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Why use a UART from Exar?

• Largest and broadest UART portfolio

• Highest performance UARTs
• UARTs with the most enhanced features
• Excellent technical support
• Exar also has serial transceivers!

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What is a UART?
• Universal Asynchronous Receiver/Transmitter
• Traditional Definition: Converts parallel (8-bit) data to
serial data and vice versa

TX
CS# RX
IOR# RTS#
CPU/ IOW# CTS#
MCU A2:A0 DTR#
D7:D0 DSR#
IRQ# CD#
RI#

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What is a UART?

TX
RX
USB RTS#
CPU/ PCI
CTS#
PCIe
MCU I2C/SPI DTR#
8-bit/VLIO DSR#
CD#
RI#

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 UART Block Diagram

XTAL1 BRG Transmitter TX

XTAL2

Receiver RX
INT Interrupt
RTS#
16550 CTS#
CPU Modem DTR#
UART
Interface I/O DSR#
Registers
Signals CD#
RI#

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16550 UART Registers
Address Register Name Read/Write Register Function Comment
A2-A0
000 DLL – Divisor LSB Write-Only Divisor (LSB) for BRG LCR bit-7 = 1

001 DLM – Divisor MSB Read-Only Divisor (MSB) for BRG LCR bit-7 = 1

000 THR – Transmit Holding Register Write-Only Loading data into TX FIFO LCR bit-7 = 0

000 RHR – Receive Holding Register Read-Only Unloading data from RX FIFO LCR bit-7 = 0

001 IER – Interrupt Enable Register Read/Write Enable interrupts

010 FCR – FIFO Control Register Write-Only FIFO enable and reset

010 ISR – Interrupt Status Register Read-Only Status of highest priority interrupt

011 LCR – Line Control Register Read/Write Word length, stop bits, parity select,
send break, select divisor registers
100 MCR – Modem Control Register Read/Write RTS# and DTR# output control
Interrupt output enable
Internal Loopback enable
101 LSR – Line Status Register Read-Only RX Errors/Status
TX Status
110 MSR – Modem Status Register Read-Only Modem Input Status

111 SPR – Scratch Pad Register Read/Write General Purpose Register

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16550 UART Registers
Address Register R/W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
A2-A0 Name

000 DLL R/W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

001 DLM R/W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

000 THR W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

000 RHR R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

001 IER R/W 0 0 0 0 MSR LSR TX RX

(THR) (RHR)
010 FCR W RX Trig RX Trig 0 0 DMA TX FIFO RX FIFO FIFO
Level Level Mode Reset Reset Enable

010 ISR R FIFOs FIFOs 0 0 INT INT INT INT

Enabled Enabled Source Source Source Source
011 LCR R/W Divisor Set TX Set Even Parity Stop Word Word
Enable Break Parity Parity Enable Bits Length Length
100 MCR R/W 0 0 0 Internal INT / (OP1#) RTS# DTR#
Loopback OP2# Control Control
101 LSR R RX FIFO THR/TSR THR RX Break RX RX RX RX Data
Error Empty Empty Framing Parity Overrun Ready
110 MSR R CD# RI# DSR# CTS# Delta Delta Delta Delta
CD# RI# DSR# CTS#
111 SPR R/W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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Baud Rate Generator (BRG)

• Used to generate the baud rates for both the

transmitter and receiver
• Not required for any other function including
reads and writes
• Crystal or External Clock
• 16-bit divisor programmed in DLM/DLL
registers

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Baud Rate Generator (BRG)
Clock Frequency
Baud Rate =
(Sampling Rate) X (Divisor)
• Standard clock frequencies are multiples of 1.8432 MHz
• 3.6864 MHz, 7.3728 MHz, 14.7456 MHz, 18.432 MHz, 22.1184 MHz
• Standard baud rates are multiples of 9600 bps
• 19200 bps, 38400 bps, 57600 bps, 115200 bps, 230400 bps, 460800
bps, 921600 bps
• Sampling rate is 16
• Divisor values are written into the DLM and DLL registers
• Divisor values are 1 to (216 – 1) in increments of 1

14.7456 MHz
Baud Rate = = 921600 bps
(16) X (1)

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 Transmitter
• Parallel-to-serial conversion
• Non-FIFO Mode
• Transmit Holding Register (THR) and Transmit Shift
Register (TSR)
• FIFO Mode
• Transmit (TX) FIFO and Transmit Shift Register
(TSR)
• 16X timing for bit shifting
• Character Framing
• Parity Insertion
• TX FIFO interrupt and status

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 Transmitter – Non-FIFO mode
• Write Data to Transmit Holding Register (THR)
• Data in THR is transferred to Transmit Shift
Register (TSR) when TSR is empty
• TSR shifts the data out on the TX output pin

THR
Data Byte
D7:D0 D7 D6 D5 D4 D3 D2 D1 D0 TSR TX

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 Transmitter – FIFO Mode
• Write Data to Transmit Holding Register (THR)
• Transmit data is queued in TX FIFO
• Data in TX FIFO is transferred to Transmit Shift
Register (TSR) when TSR is empty
• TSR shifts data out on TX output pin
Data Byte
D7:D0 THR

TX FIFO

D7 D6 D5 D4 D3 D2 D1 D0 TSR TX

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 TX Character Framing

• Start Bit
• Data Bits of 5, 6, 7 or 8
• Parity Bit
• Stop Bit of 1, 1.5 or 2
• Example:
• Start, 8 data, parity, with 1 stop bit

TX Idle T P D7 D6 D5 D4 D3 D2 D1 D0 S Idle = “Mark” or “1”

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Receiver
• Serial-to-Parallel Conversion
• Non-FIFO Mode
• Receive Holding Register (RHR) and Receive Shift Register (RSR)
• FIFO Mode
• RX FIFO and RSR
• 16X timing clock for mid bit sampling
• Start bit detection and verification
• RX FIFO is 11 bits wide
• 8 data bits
• 3 error bits or error tags

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Receiver – Non-FIFO Mode
• Incoming data is received in the Receive Shift Register (RSR)
• Received data is transferred to the RHR
• Error tags associated with data in RHR can be read via LSR
• Read RHR to read the data out

Data Byte
D7:D0

Error
RHR
Tags

B F P D7 D6 D5 D4 D3 D2 D1 D0 RSR RX

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Receiver – FIFO Mode
• Incoming data is received in the Receive Shift Register (RSR)
• Received data is queued in the RX FIFO
• Error tags associated with data in RHR can be read via LSR
• Read RHR to read the data out

Data Byte
D7:D0
RHR

Error
Tags RX
FIFO

B F P D7 D6 D5 D4 D3 D2 D1 D0 RSR RXD

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RX Character Validation
• Start bit detection and validation
• HIGH to LOW transition indicates a start bit
• Start bit validated if RX input is still LOW during
mid bit sampling
• Data, parity and stop bits are sampled at mid bit
• A valid stop bit is HIGH when the stop bit is
sampled

Idle T P D7 D6 D5 D4 D3 D2 D1 D0 S Idle = “Mark” or “1” RX

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RX Error Reporting
• Line Status errors
• Error tags are associated with each byte
• Framing error if stop bit is not detected
• Parity error if parity bit is incorrect
• Break detected if RX input is LOW for duration of one
character time and stop bit is not detected
• Overrun error if character is received in RSR when
RX FIFO is full
• Non-FIFO mode
• RHR has a data byte and data received in RSR
• RSR data overwrites RHR data
• FIFO mode
• RX FIFO is full and data is received in RSR
• Data in RX FIFO is not overwritten by data in RSR

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Modem I/Os
• Legacy Modem Signals

Signal Name Description Input/Output

RTS# Request-to-Send Output
CTS# Clear-to-Send Input
DTR# Data-Terminal-Ready Output
DSR# Data-Set-Ready Input
CD# Carrier-Detect Input
RI# Ring-Indicator Input

• Used for hardware flow control or as general purpose

inputs or outputs
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Internal Loopback Mode
VCC
TX
Transmit Shift Register
(THR/FIFO)

MCR bit-4=1

Internal Data Bus Lines and Control Signals

Receive Shift Register
(RHR/FIFO) RX
VCC

RTS#
RTS#

Modem / General Purpose Control Logic

CTS# CTS#
VCC
DTR#
DTR#

DSR#
DSR#
OP1#
RI#
RI#
OP2#
CD#
CD#
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Interrupts
Priority ISR ISR ISR ISR Source of Interrupt
Level bit-3 bit-2 bit-1 bit-0
1 0 1 1 0 LSR (RX Data Error)
2 1 1 0 0 RXRDY (RX Data Time-out)
3 0 1 0 0 RXRDY (RX Data Ready)
4 0 0 1 0 TXRDY (TX Empty)
5 0 0 0 0 MSR (Modem Status)
- 0 0 0 1 None

• Interrupt Source Register (ISR)

• If there are multiple interrupts, ISR reports only the highest pending
interrupt
• Lower priority interrupts will be reported when higher priority
interrupts are cleared

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