AN1048/D RC Snubber Networks For Thyristor Power Control and Transient Suppression

By George Templeton Thyristor Applications Engineer

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APPLICATION NOTE

INTRODUCTION
Edited and Updated

RC networks are used to control voltage transients that could falsely turn-on a thyristor. These networks are called snubbers. The simple snubber consists of a series resistor and capacitor placed around the thyristor. These components along with the load inductance form a series CRL circuit. Snubber theory follows from the solution of the circuits differential equation. Many RC combinations are capable of providing acceptable performance. However, improperly used snubbers can cause unreliable circuit operation and damage to the semiconductor device. Both turn-on and turn-off protection may be necessary for reliability. Sometimes the thyristor must function with a range of load values. The type of thyristors used, circuit configuration, and load characteristics are influential. Snubber design involves compromises. They include cost, voltage rate, peak voltage, and turn-on stress. Practical solutions depend on device and circuit physics. STATIC dV dt
WHAT IS STATIC dV ? dt dV Static is a measure of the ability of a thyristor to dt

dV dt

DEVICE PHYSICS

Static dV turn-on is a consequence of the Miller effect and regeneration (Figure 1). A change in voltage across the junction capacitance induces a current through it. This current is proportional to the rate of voltage change dV . It triggers the device on when it becomes large enough to raise the sum of the NPN and PNP transistor alphas to unity.
A A
IB P

dt

dt

IA PNP V
P

PE NB dv dt CJ G t NE PB C

I1
IC N

CJ P CJ N

IJ

IC

IJ
IB N IK

I2 G

NPN

K TWO TRANSISTOR MODEL OF SCR

dV CJ dt IA + 1 * (aN ) ap) CJ CEFF + 1*(aN)ap)

K INTEGRATED STRUCTURE

retain a blocking state under the influence of a voltage transient.

Figure 6.1.

dV dt

Model

Semiconductor Components Industries, LLC, 2008

June, 2008 Rev. 3

Publication Order Number: AN1048/D

AN1048/D
CONDITIONS INFLUENCING dV dt s

170 150 130 STATIC dV (V/ s) dt 110 90 70 50 30 10 25 40 55 70 85 100 115 130 145 MAC 228A10 VPK = 800 V

Transients occurring at line crossing or when there is no initial voltage across the thyristor are worst case. The collector junction capacitance is greatest then because the depletion layer widens at higher voltage. Small transients are incapable of charging the selfcapacitance of the gate layer to its forward biased threshold voltage (Figure 2). Capacitance voltage divider action between the collector and gate-cathode junctions and builtin resistors that shunt current away from the cathode emitter are responsible for this effect.
180 160 140 STATIC dV (V/ s) dt 120 100 80 60 40 20 0 100 200 300 400 500 600 PEAK MAIN TERMINAL VOLTAGE (VOLTS) 700 800 MAC 228A10 TRIAC TJ = 110C

TJ, JUNCTION TEMPERATURE (C)

Figure 6.3. Exponential

dV versus Temperature dt
s

dV dt

FAILURE MODE

Occasional unwanted turn-on by a transient may be acceptable in a heater circuit but isnt in a fire prevention sprinkler system or for the control of a large motor. Turn-on is destructive when the follow-on current amplitude or rate is excessive. If the thyristor shorts the power line or a charged capacitor, it will be damaged. Static dV turn-on is non-destructive when series impedance limits the surge. The thyristor turns off after a halfcycle of conduction. High dV aids current spreading in the thyristor, improving its ability to withstand dI. Breakdown turn-on does not have this benefit and should be prevented.
140 120 100 MAC 228A10 800 V 110C

dt

Figure 6.2. Exponential

dV versus Peak Voltage dt

s

dt

dt

tion below the maximum voltage and temperature rating. Avalanche multiplication will increase leakage current and reduce dV capability if a transient is within roughly 50 volts of the actual device breakover voltage. A higher rated voltage device guarantees increased dV at lower voltage. This is a consequence of the exponential rating method where a 400 V device rated at 50 V/s has a
dt dt dt

Static dV does not depend strongly on voltage for operadt

STATIC dV (V/ s) dt

80 60 40 RINTERNAL = 600

higher dV to 200 V than a 200 V device with an identical rating. However, the same diffusion recipe usually applies for all voltages. So actual capabilities of the product are not much different. Heat increases current gain and leakage, lowering

20 0 10 100 1000 GATEMT1 RESISTANCE (OHMS) 10,000

dV , dt
s

the gate trigger voltage and noise immunity

(Figure 3).

dV Figure 6.4. Exponential dt s versus Gate to MT1 Resistance

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IMPROVING dV dt s Static dV can be improved by adding an external resistor dt

10 MEG GATECATHODE RESISTANCE (OHMS)

MCR22006 TA = 65C 10 V K A G

from the gate to MT1 (Figure 4). The resistor provides a

dt

path for leakage and dV induced currents that originate in the drive circuit or the thyristor itself. Non-sensitive devices (Figure 5) have internal shorting resistors dispersed throughout the chips cathode area. This design feature improves noise immunity and high temperature blocking stability at the expense of increased trigger and holding current. External resistors are optional for nonsensitive SCRs and TRIACs. They should be comparable in size to the internal shorting resistance of the device (20 to 100 ohms) to provide maximum improvement. The internal resistance of the thyristor should be measured with an ohmmeter that does not forward bias a diode junction.

1 MEG

100 K

10K 0.001

0.01

0.1

10

100

STATIC dV (Vms) dt

dV Figure 6.6. Exponential dt versus s Gate-Cathode Resistance

2200 2000 1800 STATIC dV (V/ s) dt 1600 1400 1200 1000 800 600 MAC 158 VPK = 600 V

A gate-cathode capacitor (Figure 7) provides a shunt path for transient currents in the same manner as the resistor. It also filters noise currents from the drive circuit and enhances the built-in gate-cathode capacitance voltage divider effect. The gate drive circuit needs to be able to charge the capacitor without excessive delay, but it does not need to supply continuous current as it would for a resistor that increases dV the same amount. However, the capacitor does not enhance static thermal stability.
130 120

dt

50

60

dV Figure 6.5. Exponential dt s versus Junction Temperature

STATIC dV (V/ s) dt

70 80 90 100 110 TJ, JUNCTION TEMPERATURE (C)

120

130

110

MAC 228A10 800 V 110C

100 90 80 70

Sensitive gate TRIACs run 100 to 1000 ohms. With an external resistor, their dV capability remains inferior to dt non-sensitive devices because lateral resistance within the gate layer reduces its benefit. Sensitive gate SCRs (IGT t 200 A) have no built-in resistor. They should be used with an external resistor. The recommended value of the resistor is 1000 ohms. Higher values reduce maximum operating temperature and dV

60 0.001

0.01 0.1 GATE TO MT1 CAPACITANCE (F)

dV Figure 6.7. Exponential dt versus Gate s to MT1 Capacitance

The maximum dV

dt

dt

(Figure 6). The capability of these parts varies by more than 100 to 1 depending on gate-cathode termination.

Actual improvement stops before this because of spreading resistance in the thyristor. An external capacitor of about 0.1 F allows the maximum enhancement at a higher value of RGK.

improvement occurs with a short.

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AN1048/D
One should keep the thyristor cool for the highest dV

dt .
s

for sinusoidal currents is given by the slope of the secant line between the 50% and 0% levels as:
f I TM dI + 61000 Ams dt c

Also devices should be tested in the application circuit at the highest possible temperature using thyristors with the lowest measured trigger current. TRIAC COMMUTATING dV dt
WHAT IS COMMUTATING dV ? dt The commutating dV rating applies when a TRIAC has dt

where f = line frequency and ITM = maximum on-state current in the TRIAC. Turn-off depends on both the Miller effect displacement current generated by dV across the collector capacitance and the currents resulting from internal charge storage within the volume of the device (Figure 10). If the reverse recovery current resulting from both these components is high, the lateral IR drop within the TRIAC base layer will forward bias the emitter and turn the TRIAC on. Commutating dV capability is lower when turning off from the positive direction of current conduction because of device geometry. The gate is on the top of the die and obstructs current flow. Recombination takes place throughout the conduction period and along the back side of the current wave as it declines to zero. Turn-off capability depends on its shape. If the current amplitude is small and its zero crossing dI
dt dt

been conducting and attempts to turn-off with an inductive load. The current and voltage are out of phase (Figure 8). The TRIAC attempts to turn-off as the current drops below the holding value. Now the line voltage is high and in the opposite polarity to the direction of conduction. Successful turn-off requires the voltage across the TRIAC to rise to the instantaneous line voltage at a rate slow enough to prevent retriggering of the device.
VOLTAGE/CURRENT R VLINE L i G 1 VMT21

2 VMT21

dt

PHASE ANGLE

dI dt

low, there is little volume charge storage and turn-off becomes limited by dV . At moderate current amplitudes,
TIME

is

dt

TIME i VLINE

the volume charge begins to influence turn-off, requiring a larger snubber. When the current is large or has rapid zero crossing, dV

dV dt

dt

Figure 6.8. TRIAC Inductive Load Turn-Off

dV dt

delay time to voltage reapplication determine whether turnoff will be successful or not (Figures 11, 12).
c
G MT1 TOP N N N
Previously Conducting Side

has little influence. Commutating dI and

dt

dV DEVICE PHYSICS dt c
P

A TRIAC functions like two SCRs connected in inverseparallel. So, a transient of either polarity turns it on. There is charge within the crystals volume because of prior conduction (Figure 9). The charge at the boundaries of the collector junction depletion layer responsible for

N + N N N -

dV is also present. TRIACs have lower dV than dt s dt c dV because of this additional charge. dt
s

The volume charge storage within the TRIAC depends on the peak current before turn-off and its rate of zero crossing dI . In the classic circuit, the load impedance
c

dt

REVERSE RECOVERY CURRENT PATH

MT2 LATERAL VOLTAGE DROP

STORED CHARGE FROM POSITIVE CONDUCTION

and line frequency determine dI . The rate of crossing

c

dt

Figure 6.9. TRIAC Structure and Current Flow at Commutation

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AN1048/D
CONDITIONS INFLUENCING dV dt c Commutating dV depends on charge storage and recovdt

VOLTAGE/CURRENT

di dt

dV dt

ery dynamics in addition to the variables influencing static

c TIME

0 VMT21 VOLUME STORAGE CHARGE IRRM CHARGE DUE TO dV/dt

and the size of recovery currents, making turn-off more difficult. Loads that slow the rate of current zero-crossing aid turn-off. Those with harmonic content hinder turn-off.
Circuit Examples

dV. High temperatures increase minority carrier life-time dt

Figure 6.10. TRIAC Current and Voltage at Commutation

Figure 13 shows a TRIAC controlling an inductive load in a bridge. The inductive load has a time constant longer than the line period. This causes the load current to remain constant and the TRIAC current to switch rapidly as the line voltage reverses. This application is notorious for causing TRIAC turn-off difficulty because of high dI .
c
RS C i

dt

E V MAIN TERMINAL VOLTAGE (V) LS

dI dt c
t

DC MOTOR R L + L u 8.3 ms R

60 Hz E

Figure 6.13. Phase Controlling a Motor in a Bridge

VT 0 td TIME

Figure 6.11. Snubber Delay Time

0.5 NORMALIZED DELAY TIME (td* = W0 td) 0.2 0.2 0.1 0.1 0.05 0.02 RL = 0 M=1 IRRM = 0 0.005 0.01 0.02 0.05 0.01 VT E 0.001 0.002 0.005 0.1 0.2 0.3 0.5 1

High currents lead to high junction temperatures and rates of current crossing. Motors can have 5 to 6 times the normal current amplitude at start-up. This increases both junction temperature and the rate of current crossing, leading to turn-off problems. The line frequency causes high rates of current crossing in 400 Hz applications. Resonant transformer circuits are doubly periodic and have current harmonics at both the primary and secondary resonance. Non-sinusoidal currents can lead to turn-off difficulty even if the current amplitude is low before zero-crossing.

dV dt

0.05 0.03 0.02

dV dt

FAILURE MODE

DAMPING FACTOR

Figure 6.12. Delay Time To Normalized Voltage

turn-on or total turn-off failure is possible. This can be destructive if the TRIAC conducts asymmetrically causing a dc current component and magnetic saturation. The winding resistance limits the current. Failure results because of excessive surge current and junction temperature.

failure causes a loss of phase control. Temporary

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AN1048/D
IMPROVING dV dt c

Is +

Hs ML where : 0.4 p N

The same steps that improve dV

dt

when stored charge dominates turn-off. Steps that reduce the stored charge or soften the commutation are necessary then. Larger TRIACs have better turn-off capability than smaller ones with a given load. The current density is lower in the larger device allowing recombination to claim a greater proportion of the internal charge. Also junction temperatures are lower. TRIACs with high gate trigger currents have greater turn-off ability because of lower spreading resistance in the gate layer, reduced Miller effect, or shorter lifetime. The rate of current crossing can be adjusted by adding a commutation softening inductor in series with the load. Small high permeability square loop inductors saturate causing no significant disturbance to the load current. The inductor resets as the current crosses zero introducing a large inductance into the snubber circuit at that time. This slows the current crossing and delays the reapplication of blocking voltage aiding turn-off. The commutation inductor is a circuit element that introduces time delay, as opposed to inductance, into the circuit. It will have little influence on observed dV at the device. The following example illustrates the improvement resulting from the addition of an inductor constructed by winding 33 turns of number 18 wire on a tape wound core (52000-1A). This core is very small having an outside diameter of 3/4 inch and a thickness of 1/8 inch. The delay time can be calculated from:
(N A B 10 *8) ts + where: E dt

aid dV

dt

except

Hs = MMF to saturate = 0.5 Oersted ML = mean magnetic path length = 4.99 cm.
Is + (.5) (4.99) + 60 mA. .4 p 33

SNUBBER PHYSICS
UNDAMPED NATURAL RESONANCE w0 + I Radianssecond LC

Resonance determines dV and boosts the peak capacitor voltage when the snubber resistor is small. C and L are related to one another by 02. dV scales linearly with 0 when the damping factor is held constant. A ten to one reduction in dV requires a 100 to 1 increase in either component.
dt DAMPING FACTOR +R 2 dt dt

C L

The damping factor is proportional to the ratio of the circuit loss and its surge impedance. It determines the trade off between dV and peak voltage. Damping factors between 0.01 and 1.0 are recommended.
The Snubber Resistor Damping and dV dt dt

When t 0.5, the snubber resistor is small, and dV

dt

depends mostly on resonance. There is little improvement in dV for damping factors less than 0.3, but peak voltage and snubber discharge current increase. The voltage wave has a 1-COS () shape with overshoot and ringing. Maxidt dt

ts = time delay to saturation in seconds. B = saturating flux density in Gauss A = effective core cross sectional area in cm2 N = number of turns. For the described inductor:
t s + (33 turns) (0.076 cm 2 ) (28000 Gauss) (1 10 8 ) (175 V) + 4.0 ms.

mum dV occurs at a time later than t = 0. There is a time delay before the voltage rise, and the peak voltage almost doubles. When u 0.5, the voltage wave is nearly exponential in shape. The maximum instantaneous dV occurs at t = 0. There is little time delay and moderate voltage overshoot. When u 1.0, the snubber resistor is large and dV depends mostly on its value. There is some overshoot even through the circuit is overdamped. High load inductance requires large snubber resistors and small snubber capacitors. Low inductances imply small resistors and large capacitors.
dt dt

The saturation current of the inductor does not need to be much larger than the TRIAC trigger current. Turn-off failure will result before recovery currents become greater than this value. This criterion allows sizing the inductor with the following equation:

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AN1048/D
Damping and Transient Voltages

Figure 14 shows a series inductor and filter capacitor connected across the ac main line. The peak to peak voltage of a transient disturbance increases by nearly four times. Also the duration of the disturbance spreads because of ringing, increasing the chance of malfunction or damage to the voltage sensitive circuit. Closing a switch causes this behavior. The problem can be reduced by adding a damping resistor in series with the capacitor.

Table 1 shows suggested minimum resistor values estimated (Appendix A) by testing a 20 piece sample from the four different TRIAC die sizes.
Table 1. Minimum Non-inductive Snubber Resistor for Four Quadrant Triggering.
Peak VC Volts 200 300 400 600 800 Rs Ohms 3.3 6.8 11 39 51 dI dt A/s 170 250 308 400 400

TRIAC Type Non-Sensitive Gate (IGT u 10 mA) 8 to 40 A(RMS)

100 H 340 V 0 10 s

0.05 0.1 F V VOLTAGE SENSITIVE CIRCUIT

+700 V (VOLTS)

Reducing dI dt

TRIAC dI can be improved by avoiding quadrant 4

0

-700 0 10 TIME (s) 20

triggering. Most optocoupler circuits operate the TRIAC in quadrants 1 and 3. Integrated circuit drivers use quadrants 2 and 3. Zero crossing trigger devices are helpful because they prohibit triggering when the voltage is high. Driving the gate with a high amplitude fast rise pulse increases dI capability. The gate ratings section defines the maximum allowed current. Inductance in series with the snubber capacitor reduces
dI. It should not be more than five percent of the load dt inductance to prevent degradation of the snubbers dV dt dt

dt

Figure 6.14. Undamped LC Filter Magnifies and Lengthens a Transient dI dt Non-Inductive Resistor

The snubber resistor limits the capacitor discharge current and reduces dI stress. High dI destroys the thyristor even though the pulse duration is very short. The rate of current rise is directly proportional to circuit voltage and inversely proportional to series inductance. The snubber is often the major offender because of its low inductance and close proximity to the thyristor. With no transient suppressor, breakdown of the thyristor sets the maximum voltage on the capacitor. It is possible to exceed the highest rated voltage in the device series because high voltage devices are often used to supply low voltage specifications. The minimum value of the snubber resistor depends on the type of thyristor, triggering quadrants, gate current amplitude, voltage, repetitive or non-repetitive operation, and required life expectancy. There is no simple way to predict the rate of current rise because it depends on turn-on speed of the thyristor, circuit layout, type and size of snubber capacitor, and inductance in the snubber resistor. The equations in Appendix D describe the circuit. However, the values required for the model are not easily obtained except by testing. Therefore, reliability should be verified in the actual application circuit.
dt dt

suppression capability. Wirewound snubber resistors sometimes serve this purpose. Alternatively, a separate inductor can be added in series with the snubber capacitor. It can be small because it does not need to carry the load current. For example, 18 turns of AWG No. 20 wire on a T50-3 (1/2 inch) powdered iron core creates a non-saturating 6.0 H inductor. A 10 ohm, 0.33 F snubber charged to 650 volts resulted in a 1000 A/s dI. Replacement of the non-inductive snubdt

ber resistor with a 20 watt wirewound unit lowered the rate of rise to a non-destructive 170 A/s at 800 V. The inductor gave an 80 A/s rise at 800 V with the noninductive resistor.
The Snubber Capacitor

A damping factor of 0.3 minimizes the size of the snubber capacitor for a given value of dV. This reduces the cost and physical dimensions of the capacitor. However, it raises voltage causing a counter balancing cost increase. Snubber operation relies on the charging of the snubber capacitor. Turn-off snubbers need a minimum conduction angle long enough to discharge the capacitor. It should be at least several time constants (RS CS).
dt

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AN1048/D
STORED ENERGY Inductive Switching Transients E + 1 L I 0 2 Wattseconds or Joules 2

snubber inductor and limits the rate of inrush current if the device does turn on. Resistance in the load lowers dV and VPK (Figure 16).
1.4 E 2.2 dV dt 2.1 2 1.9 M = 0.75 NORMALIZED PEAK VOLTAGE VPK /E 1.8 1.7 1.6 M = 0.5 0.6 M = 0.25 L I 0.4 M=0 0.2 OPTIONAL FAST SLOW 0 0 0.2 M = RS / (RL + RS) 0.4 0.6 DAMPING FACTOR 0.8 1 RS R L ) RS 1.5 1.4 1.3 1.2 1.1 1 0.9

dt

current in Amperes flowing in the inductor at t = 0. Resonant charging cannot boost the supply voltage at turn-off by more than 2. If there is an initial current flowing in the load inductance at turn-off, much higher voltages are possible. Energy storage is negligible when a TRIAC turns off because of its low holding or recovery current. The presence of an additional switch such as a relay, thermostat or breaker allows the interruption of load current and the generation of high spike voltages at switch opening. The energy in the inductance transfers into the circuit capacitance and determines the peak voltage (Figure 15).

I0 =

1.2

VPK

1 M=1 NORMALIZED dV dt

R VPK C

(dV dt )/ (E W0 )

0.8

dV + I V + I dt C PK

L C
(b.) Unprotected Circuit

M + RESISTIVE DIVISION RATIO + I RRM + 0

(a.) Protected Circuit

Figure 6.16. 0 To 63% dV dt

Figure 6.15. Interrupting Inductive Load Current Capacitor Discharge

CHARACTERISTIC VOLTAGE WAVES Damping factor and reverse recovery current determine the shape of the voltage wave. It is not exponential when the snubber damping factor is less than 0.5 (Figure 17) or when significant recovery currents are present.
=0 = 0.1

thyristor every time it turns on. The power loss is proportional to frequency (PAV = 120 Ec @ 60 Hz).
CURRENT DIVERSION

Ec + 1 C V 2 2

T h e e n e rg y s t o r e d i n t h e s n u b b e r c a p a c i t o r transfers to the snubber resistor and

The current flowing in the load inductor cannot change instantly. This current diverts through the snubber resistor equal to (IRRM R) or (IH R).
LOAD PHASE ANGLE

V MT (VOLTS) 21

500 400 300 200 100 0 0

0.3

0.1 = 0.3 0 =1

causing a spike of theoretically infinite dV with magnitude dt

0.7

1.4

2.1

2.8 3.5 4.2 TIME (s)

4.9

5.6

6.3

dV dt

Highly inductive loads cause increased voltage and

c

at turn-off. However, they help to protect the

0*63% dV + 100 Vms, E + 250 V, dt s R + 0, I RRM + 0 L

thyristor from transients and dV

dt . The load serves as the

s

Figure 6.17. Voltage Waves For Different Damping Factors

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2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 10-63 dV % dt VPK 10-63%

COMPLEX LOADS
E 0-63% dV dt

NORMALIZED PEAK VOLTAGE AND

dV MAX dt

dV dt

V PK dVdt NORMALIZED V PK + NORMALIZED dV + E dt E w0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 DAMPING FACTOR () (R L + 0, M + 1, I RRM + 0)

Many real-world inductances are non-linear. Their core materials are not gapped causing inductance to vary with current amplitude. Small signal measurements poorly characterize them. For modeling purposes, it is best to measure them in the actual application. Complex load circuits should be checked for transient voltages and currents at turn-on and off. With a capacitive load, turn-on at peak input voltage causes the maximum surge current. Motor starting current runs 4 to 6 times the steady state value. Generator action can boost voltages above the line value. Incandescent lamps have cold start currents 10 to 20 times the steady state value. Transformers generate voltage spikes when they are energized. Power factor correction circuits and switching devices create complex loads. In most cases, the simple CRL model allows an approximate snubber design. However, there is no substitute for testing and measuring the worst case load conditions.
SURGE CURRENTS IN INDUCTIVE CIRCUITS

Figure 6.18. Trade-Off Between VPK and dV dt

dV dt

Some are easy to solve for and assist understanding. These include the initial dV, the maximum instantaneous dV, and
dt dt

A variety of wave parameters (Figure 18) describe dV dt

Inductive loads with long L/R time constants cause asymmetric multi-cycle surges at start up (Figure 20). Triggering at zero voltage crossing is the worst case condition. The surge can be eliminated by triggering at the zero current crossing angle.
20 MHY i

the average dV to the peak reapplied voltage. The 0 to 63%

dV dt

dt

sheets are easy to measure but difficult to compute. NON-IDEAL BEHAVIORS

CORE LOSSES

and 10 to 63% dV

dt

definitions on device data

240 VAC

0.1

The magnetic core materials in typical 60 Hz loads introduce losses at the snubber natural frequency. They appear as a resistance in series with the load inductance and winding dc resistance (Figure 19). This causes actual dV to dt be less than the theoretical value.
L R

i (AMPERES)

90

0 ZERO VOLTAGE TRIGGERING, IRMS = 30 A 40 80 120 TIME (MILLISECONDS) 160 200

Figure 6.20. Start-Up Surge For Inductive Circuit

C L DEPENDS ON CURRENT AMPLITUDE, CORE SATURATION R INCLUDES CORE LOSS, WINDING R. INCREASES WITH FREQUENCY C WINDING CAPACITANCE. DEPENDS ON INSULATION, WIRE SIZE, GEOMETRY

Figure 6.19. Inductor Model

Core remanence and saturation cause surge currents. They depend on trigger angle, line impedance, core characteristics, and direction of the residual magnetization. For example, a 2.8 kVA 120 V 1:1 transformer with a 1.0 ampere load produced 160 ampere currents at start-up. Soft starting the circuit at a small conduction angle reduces this current. Transformer cores are usually not gapped and saturate easily. A small asymmetry in the conduction angle causes magnetic saturation and multi-cycle current surges.

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Steps to achieve reliable operation include: 1. Supply sufficient trigger current amplitude. TRIACs have different trigger currents depending on their quadrant of operation. Marginal gate current or optocoupler LED current causes halfwave operation. 2. Supply sufficient gate current duration to achieve latching. Inductive loads slow down the main terminal current rise. The gate current must remain above the specified IGT until the main terminal current exceeds the latching value. Both a resistive bleeder around the load and the snubber discharge current help latching. 3. Use a snubber to prevent TRIAC dV resistor. The non-inductive snubber circuit is useful when the load resistance is much larger than the snubber resistor.
RL E e RS CS e E V step + E t=0 e(t + o)) + E R S R ) RL S = (RL + RS) CS

dt

4. Minimize designed-in trigger asymmetry. Triggering must be correct every half-cycle including the first. Use a storage scope to investigate circuit behavior during the first few cycles of turn-on. Alternatively, get the gate circuit up and running before energizing the load. 5. Derive the trigger synchronization from the line instead of the TRIAC main terminal voltage. This avoids regenerative interaction between the core hysteresis and the triggering angle preventing trigger runaway, halfwave operation, and core saturation. 6. Avoid high surge currents at start-up. Use a current probe to determine surge amplitude. Use a soft start circuit to reduce inrush current.
DISTRIBUTED WINDING CAPACITANCE

failure.

TIME

RS e*tt ) (1 * e *tt) R S ) RL

RESISTOR COMPONENT

CAPACITOR COMPONENT

Figure 6.21. Non-Inductive Snubber Circuit Opto-TRIAC Examples Single Snubber, Time Constant Design

There are small capacitances between the turns and layers of a coil. Lumped together, they model as a single shunt capacitance. The load inductor behaves like a capacitor at frequencies above its self-resonance. It becomes ineffective in controlling dV and VPK when a fast transient such as that resulting from the closing of a switch occurs. This problem can be solved by adding a small snubber across the line.
SELF-CAPACITANCE dt

Figure 22 illustrates the use of the RC time constant design method. The optocoupler sees only the voltage across the snubber capacitor. The resistor R1 supplies the trigger current of the power TRIAC. A worst case design procedure assumes that the voltage across the power TRIAC changes instantly. The capacitor voltage rises to 63% of the maximum in one time constant. Then:
R1 CS + t + 0.63 E

dV dt s

where dV is the rated static dV dt s dt

for the optocoupler.

1 A, 60 Hz 10 V/s MOC 3021 CNTL 0.63 (170) 240 s (0.63)(170) DESIGN dV + + 0.45Vms dt (2400)(0.1mF) TIME
dV (Vms) dt Power TRIAC 0.99 Optocoupler 0.35

A thyristor has self-capacitance which limits dV when the load inductance is large. Large load inductances, high power factors, and low voltages may allow snubberless operation. SNUBBER EXAMPLES
WITHOUT INDUCTANCE Power TRIAC Example dt

L = 318 MHY 6 4 180 0.1 F 2.4 k C1 2N6073A 1 V/s 170 V

VCC

Rin 1 2

Figure 21 shows a transient voltage applied to a TRIAC controlling a resistive load. Theoretically there will be an instantaneous step of voltage across the TRIAC. The only elements slowing this rate are the inductance of the wiring and the self-capacitance of the thyristor. There is an exponential capacitor charging component added along with a decaying component because of the IR drop in the snubber

Figure 6.22. Single Snubber For Sensitive Gate TRIAC and Phase Controllable Optocoupler ( = 0.67)

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The optocoupler conducts current only long enough to trigger the power device. When it turns on, the voltage between MT2 and the gate drops below the forward threshold voltage of the opto-TRIAC causing turn-off. The optocoupler sees dV However a power TRIAC along with the optocoupler should be used for higher load currents.
80 70 LOAD CURRENT (mA RMS) 60 50 40 30 20 NO SNUBBER 10 0 1N4001 MCR265-4 430 120 V 400 Hz 0.022 F 20 30 40 50 60 70 80 TA, AMBIENT TEMPERATURE (C) 90 100 CS = 0.001 CS = 0.01

dt

in the conduction cycle at zero current crossing. Therefore, it is not necessary to design for the lower optocoupler

when the power TRIAC turns off later

dV dt

for the optocoupler protects both devices.

1 MHY VCC 2 3 MOC3031 1 4 5 6 100

rating. In this example, a single snubber designed

51

MCR265-4 100 1N4001

(RS = 100 , VRMS = 220 V, POWER FACTOR = 0.5)

Figure 6.24. MOC3062 Inductive Load Current versus TA

(50 V/s SNUBBER, = 1.0)

Figure 6.23. Anti-Parallel SCR Driver

A phase controllable optocoupler is recommended with a power device. When the load current is small, a MAC97A TRIAC is suitable. Unusual circuit conditions sometimes lead to unwanted operation of an optocoupler in dV
dt

Optocouplers with SCRs

dt

Anti-parallel SCR circuits result in the same dV across the optocoupler and SCR (Figure 23). Phase controllable opto-couplers require the SCRs to be snubbed to their lower charge storage behaviors that reduce the turn-off capability of TRIACs. Each SCR conducts for a half-cycle and has the next half cycle of the ac line in which to recover. The turnoff dV of the conducting SCR becomes a static forward dt blocking dV for the other device. Use the SCR data sheet dt dV rating in the snubber design. dt s
dV rating. Anti-parallel SCR circuits are free from the dt

rents in the power device cause increased voltages between MT2 and the gate that hold the optocoupler on. Use of a larger TRIAC or other measures that limit inrush current solve this problem. Very short conduction times leave residual charge in the optocoupler. A minimum conduction angle allows recovery before voltage reapplication.
THE SNUBBER WITH INDUCTANCE

mode. Very large cur-

Consider an overdamped snubber using a large capacitor whose voltage changes insignificantly during the time under consideration. The circuit reduces to an equivalent L/R series charging circuit. The current through the snubber resistor is:
i+ V Rt

A SCR used inside a rectifier bridge to control an ac load will not have a half cycle in which to recover. The available time decreases with increasing line voltage. This makes the circuit less attractive. Inductive transients can be suppressed by a snubber at the input to the bridge or across the SCR. However, the time limitation still applies.
OPTO dV dt c

1 * e*tt ,

and the voltage across the TRIAC is:

e + i R S.

The voltage wave across the TRIAC has an exponential rise with maximum rate at t = 0. Taking its derivative gives its value as:

Zero-crossing optocouplers can be used to switch inductive loads at currents less than 100 mA (Figure 24).

dV dt

V RS L

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Highly overdamped snubber circuits are not practical designs. The example illustrates several properties: 1. The initial voltage appears completely across the circuit inductance. Thus, it determines the rate of change of current through the snubber resistor and the initial dV. This result does not change when there is resistance in the load and holds true for all damping factors. 2. The snubber works because the inductor controls the rate of current change through the resistor and the rate of capacitor charging. Snubber design cannot ignore the inductance. This approach suggests that the snubber capacitance is not important but that is only true for this hypothetical condition. The snubber resistor shunts the thyristor causing unacceptable leakage when the capacitor is not present. If the power loss is tolerable, example is the soft-start circuit used to limit inrush current in switching power supplies (Figure 25).
dV can be controlled without the capacitor. An dt dt

= measured phase angle between line V and load I RL = measured dc resistance of the load. Then
Z+ V RMS I RMS XL 2 p f Line

RL2 ) XL2
.

XL +

Z2 * RL2 and

L+

If only the load current is known, assume a pure inductance. This gives a conservative design. Then:
L+ V RMS 2 p f Line I RMS where E + 2 V RMS.

For example:
E + 2 120 + 170 V; L + 120 + 39.8 mH. (8 A) (377 rps) + 1.0.

Read from the graph at = 0.6, VPK = (1.25) 170 = 213 V. Use 400 V TRIAC. Read dV 2. Apply the resonance criterion:
dt (+0.6)

Snubber With No C

w0 + spec dV dV E . dt dt (P)
RS

E AC LINE SNUBBER L RECTIFIER BRIDGE

C1

5 10 6 VS w0 + + 29.4 (1) (170 V) C+ 1 + 0.029 m F w0 2 L

10 3 r ps.

RS E AC LINE SNUBBER L

ER dV + S dt f L

3. Apply the damping criterion:

C1

RECTIFIER BRIDGE

RS + 2

L + 2 (0.6) 39.8 C 0.029

10 *3 + 1400 ohms. 10 *6

Figure 6.25. Surge Current Limiting For a Switching Power Supply

dV SAFE AREA CURVE dt c

Figure 26 shows a MAC15 TRIAC turn-off safe operating area curve. Turn-off occurs without problem
dt dI values of and delay time at high currents. Reduction dt c

TRIAC DESIGN PROCEDURE dV dt c 1. Refer to Figure 18 and select a particular damping factor () giving a suitable trade-off between VPK and dV. dt Determine the normalized dV corresponding to the chosen dt damping factor. The voltage E depends on the load phase angle:
XL E + 2 VRMS Sin (f) where f + tan*1 RL

under the curve. The region is bounded by static dV at low

of the peak current permits operation at higher line frequency. This TRIAC operated at f = 400 Hz, TJ = 125C, and ITM = 6.0 amperes using a 30 ohm and 0.068 F snubber. Low damping factors extend operation to higher saturable commutation inductor extends the allowed current rate by introducing recovery delay time.
c

dI , but capacitor sizes increase. The addition of a small, dt

where

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One hundred H is a suggested value for starting the design. Plug the assumed inductance into the equation for C. Larger values of inductance result in higher snubber resistance and reduced dI. For example: Given E = 240 2 + 340 V. Pick = 0.3. Then from Figure 18, VPK = 1.42 (340) = 483 V. Thus, it will be necessary to use a 600 V device. Using the previously stated formulas for 0, C and R we find:
50 10 6 VS w0 + + 201450 rps (0.73) (340 V) C+
0.1 10 14 18

-ITM = 15 A 100

dt

dI + 6fITM dt c

10 *3Ams

(V/ s) ( dV dt )c

10

WITH COMMUTATION L

1 (201450) 2 (100

10 *6)

+ 0.2464 m F

dI AMPERESMILLISECOND dt
c

22

26

30

34

38

42

46

50

R + 2 (0.3)

MAC16-8, COMMUTATIONALL + 33TURNS# 18, 52000-1ATAPEWOUNDCORE34INCHOD

100 10 *6 + 12 ohms 0.2464 10 *6

VARIABLE LOADS The snubber should be designed for the smallest load inductance because dV will then be highest because of its dependence on 0. This requires a higher voltage device for operation with the largest inductance because of the corresponding low damping factor. Figure 28 describes dV for an 8.0 ampere load at various power factors. The minimum inductance is a component added to prevent static dV firing with a resistive load.
dt dt dt

Figure 6.26.

dI dV versus dt T dt c c

= 125C

STATIC dV DESIGN dt There is usually some inductance in the ac main and power wiring. The inductance may be more than 100 H if there is a transformer in the circuit or nearly zero when a shunt power factor correction capacitor is present. Usually the line inductance is roughly several H. The minimum inductance must be known or defined by adding a series inductor to insure reliable operation (Figure 27).

8 A LOAD R BTA08-800CW3G 68 0.033 F L 120 V 60 Hz

10 100 H 20 A
LS 1

0.33 F

t 50 V/s

dV dt
12 HEATER
0.75 0.03 0.04 0.06 R

+ 100 Vms

dV dt
V

+ 5 Vms

340 V

L MHY 0.1 39.8 28.1 17.3

Vstep V 170 170 120 74

VPK

dv dt V/s 86 4.0 3.3 2.6

15 0 10.6 13.5

191 325 225 136

Figure 6.27. Snubbing For a Resistive Load

Figure 6.28. Snubber For a Variable Load

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AN1048/D
EXAMPLES OF SNUBBER DESIGNS Table 2 describes snubber RC values for V/s dV

dV . dt
s

Figures 31 and 32 show possible R and C values for a 5.0

80 A RMS

dt

assuming a pure inductive load.

0.1

40 A 20 A C S ( F) 10 A 5A 0.01 2.5 A

dV Designs dt (E = 340 V, Vpeak = 500 V, = 0.3) Table 2. Static

5.0 V/s L H 47 100 220 500 1000 C F R Ohm 50 V/s C F 0.33 0.15 0.068 0.033 R Ohm 10 22 51 100 100 V/s C F 0.15 0.1 0.033 0.015 R Ohm 10 20 47 110

3.0

11

0.6 A 0.001 0

TRANSIENT AND NOISE SUPPRESSION Transients arise internally from normal circuit operation or externally from the environment. The latter is particularly frustrating because the transient characteristics are undefined. A statistical description applies. Greater or smaller stresses are possible. Long duration high voltage transients are much less probable than those of lower amplitude and higher frequency. Environments with infrequent lightning and load switching see transient voltages below 3.0 kV.
10K 0.6 A RMS

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

DAMPING FACTOR

Figure 6.30. Snubber Capacitor For dV = 5.0 V/s dt c

PURE INDUCTIVE LOAD, V + 120 V RMS, I RRM + 0

2.5 A 5A

1000 R S (OHMS)

10 A 20 A 40 A 80 A

100

10 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

DAMPING FACTOR

Figure 6.29. Snubber Resistor For dV = 5.0 V/s dt c

PURE INDUCTIVE LOAD, V + 120 V RMS, I RRM + 0

The natural frequencies and impedances of indoor ac wiring result in damped oscillatory surges with typical frequencies ranging from 30 kHz to 1.5 MHz. Surge amplitude depends on both the wiring and the source of surge energy. Disturbances tend to die out at locations far away from the source. Spark-over (6.0 kV in indoor ac wiring) sets the maximum voltage when transient suppressors are not present. Transients closer to the service entrance or in heavy wiring have higher amplitudes, longer durations, and more damping because of the lower inductance at those locations. The simple CRL snubber is a low pass filter attenuating frequencies above its natural resonance. A steady state sinusoidal input voltage results in a sine wave output at the same frequency. With no snubber resistor, the rate of roll off approaches 12 dB per octave. The corner frequency is at the snubbers natural resonance. If the damping factor is low, the response peaks at this frequency. The snubber resistor degrades filter characteristics introducing an up-turn at = 1 / (RC). The roll-off approaches 6.0 dB/octave at frequencies above this. Inductance in the snubber resistor further reduces the roll-off rate. Figure 32 describes the frequency response of the circuit in Figure 27. Figure 31 gives the theoretical response to a 3.0 kV 100 kHz ring-wave. The snubber reduces the peak voltage across the thyristor. However, the fast rise input causes a high dV step when series inductance is added to the snubber resistor. Limiting the input voltage with a transient suppressor reduces the step.
dt

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400 VMT (VOLTS) 21 WITHOUT 5 HY WITH 5 HY AND 450 V MOV AT AC INPUT

0 WITH 5 HY

In Figure 32, there is a separate suppressor across each thyristor. The load impedance limits the surge energy delivered from the line. This allows the use of a smaller device but omits load protection. This arrangement protects each thyristor when its load is a possible transient source.

-400 0 1 2 3 TIME (s) 4 5 6

Figure 6.31. Theoretical Response of Figure 33 Circuit to 3.0 kV IEEE 587 Ring Wave (RSC = 27.5 )

VMAX

+10

Figure 6.33. Limiting Line Voltage

0 VOLTAGE GAIN (dB) -10 100 H -20 Vin -30 -40 10K 12 5 H 10 Vout WITHOUT 5HY 100K FREQUENCY (Hz) 1M 0.33 F WITH 5 HY

Figure 6.32. Snubber Frequency Response

V out V in Figure 6.34. Limiting Thyristor Voltage

dt dI when coupling is by stray capacitance, and when the dt

The noise induced into a circuit is proportional to dV

coupling is by mutual inductance. Best suppression requires the use of a voltage limiting device along with a rate limiting CRL snubber. The thyristor is best protected by preventing turn-on from dV or breakover. The circuit should be designed for dt

It is desirable to place the suppression device directly across the source of transient energy to prevent the induction of energy into other circuits. However, there is no protection for energy injected between the load and its controlling thyristor. Placing the suppressor directly across each thyristor positively limits maximum voltage and snubber discharge dI .
dt

what can happen instead of what normally occurs. In Figure 30, a MOV connected across the line protects many parallel circuit branches and their loads. The MOV defines the maximum input voltage and dI through the load. across the thyristor. The MOV must be large because there is little surge limiting impedance to prevent its burn-out.
dt dV With the snubber, it sets the maximum and peak voltage dt

EXAMPLES OF SNUBBER APPLICATIONS In Figure 35, TRIACs switch a 3 phase motor on and off and reverse its rotation. Each TRIAC pair functions as a SPDT switch. The turn-on of one TRIAC applies the differential voltage between line phases across the blocking device without the benefit of the motor impedance to constrain the rate of voltage rise. The inductors are added to prevent static dV firing and a line-to-line short.
dt

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SNUBBER 1 100 H 300 4 MOC 3081 FWD SNUBBER 2 300 4 MOC 3081 REV SNUBBER 2 100 H 300 4 MOC 3081 FWD SNUBBER 2 300 6 3 N MOC 3081 REV 4 1 G 91 43 6 2 1 6 G 91 MOC 3081 4 6 1 G 91 SNUBBER ALL MOVS ARE 275 VRMS ALL TRIACS ARE BTA088003W3G 1/3 HP 208 V 3 PHASE 6 2 1 G 91 0.15 F 22 2W WIREWOUND

91 G 1 2 SNUBBER

Figure 6.35. 3 Phase Reversing Motor

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Figure 36 shows a split phase capacitor-run motor with reversing accomplished by switching the capacitor in series with one or the other winding. The forward and reverse TRIACs function as a SPDT switch. Reversing the motor applies the voltage on the capacitor abruptly across the blocking thyristor. Again, the inductor L is added to prevent less dV capability than similar non-sensitive devices. A non-sensitive thyristor should be used for high dV .
dt dt dV TRIAC commutating ratings are 5 to 20 times less dt dV ratings. than static dt

dV dt

forward and reverse TRIACs short the capacitors (Cs) resulting in damage to them. It is wise to add the resistor RS to limit the discharge current.

firing of the blocking TRIAC. If turn-on occurs, the

SNUBBER INDUCTOR D1 C1 D3 D4 RL 240 V 0 G C2 CS + + -

D2 120 VAC OR 240 VAC 46 V/s MAX 3.75 LS 330 V 500 H 5.6 MOTOR 1/70 HP 0.26 A

REV 91 0.1

91 RS 115 2N6073

FWD 0.1 CS

120 V RS

Figure 6.37. Tap Changer For Dual Voltage Switching Power Supply

Phase controllable optocouplers have lower dV ratings

Figure 6.36. Split Phase Reversing Motor

Figure 37 shows a tap changer. This circuit allows the operation of switching power supplies from a 120 or 240 vac line. When the TRIAC is on, the circuit functions as a conventional voltage doubler with diodes D1 and D2 conducting on alternate half-cycles. In this mode of operation, inrush current and dI are hazards to TRIAC reliability. Series impedance is necessary to prevent damage to the TRIAC. The TRIAC is off when the circuit is not doubling. In this state, the TRIAC sees the difference between the line voltage and the voltage at the intersection of C1 and C2. Transients on the line cause dV
dt dt

than zero crossing optocouplers and power TRIACs. These should be used when a dc voltage component is present, or to prevent turn-on delay. Zero crossing optocouplers have more dV capability than power thyristors; and they should be used in place of phase controllable devices in static switching applications. APPENDIX A
dt

dt

MEASURING dV

dt

s dt

Figure 38 shows a test circuit for measuring the static dV of power thyristors. A 1000 volt FET switch insures that the voltage across the device under test (D.U.T.) rises rapidly from zero. A differential preamp allows the use of a N-channel device while keeping the storage scope chassis at ground for safety purposes. The rate of voltage rise is adjusted by a variable RC time constant. The charging resistance is low to avoid waveform distortion because of the thyristors self-capacitance but is large enough to prevent damage to the D.U.T. from turn-on dI. Mounting the miniature range switches, capacitors, and G-K network close to the device under test reduces stray inductance and allows testing at more than 10 kV/s.
dt

dt

inrush current, dI, and overvoltage damage to the filter capacitor are possibilities. Prevention requires the addition of a RC snubber across the TRIAC and an inductor in series with the line. THYRISTOR TYPES Sensitive gate thyristors are easy to turn-on because of their low trigger current requirements. However, they have

firing of the TRIAC. High

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27 VDRM/VRRM SELECT 2 DUT X100 PROBE G RGK MOUNT DUT ON TEMPERATURE CONTROLLED C PLATE dV dt VERNIER 1 470 pF 0.001 0.005 82 2W 0.01 2W POWER 0.047 1N914 20 V 56 2W 1000 1/4 W MTP1N100 0.47 1N967A 18 V 0-1000 V 10 mA 0.1 TEST 20 k 2W 2W 1000 10 WATT WIREWOUND 0.33 1000 V

X100 PROBE DIFFERENTIAL PREAMP

0.047 1000 V

100 2W

1 MEG

2 W EACH 1.2 MEG

f = 10 Hz PW = 100 s 50 PULSE GENERATOR

ALL COMPONENTS ARE NONINDUCTIVE UNLESS OTHERWISE SHOWN

Figure 6.38. Circuit For Static dV Measurement of Power Thyristors dt

APPENDIX B

MEASURING dV

dt

c dt

A test fixture to measure commutating dV is shown in Figure 39. It is a capacitor discharge circuit with the load series resonant. The single pulse test aids temperature control and allows the use of lower power components. The limited energy in the load capacitor reduces burn and shock hazards. The conventional load and snubber circuit provides recovery and damping behaviors like those in the application. The voltage across the load capacitor triggers the D.U.T. It terminates the gate current when the load capacitor voltage crosses zero and the TRIAC current is at its peak. Each VDRM, ITM combination requires different components. Calculate their values using the equations given in Figure 39.

Commercial chokes simplify the construction of the necessary inductors. Their inductance should be adjusted by increasing the air gap in the core. Removal of the magnetic pole piece reduces inductance by 4 to 6 but extends the current without saturation. The load capacitor consists of a parallel bank of 1500 Vdc non-polar units, with individual bleeders mounted at each capacitor for safety purposes. An optional adjustable voltage clamp prevents TRIAC breakdown. To measure dV

dt , synchronize the storage scope on the

c

current waveform and verify the proper current amplitude and period. Increase the initial voltage on the capacitor to compensate for losses within the coil if necessary. Adjust the snubber until the device fails to turn off after the first half-cycle. Inspect the rate of voltage rise at the fastest passing condition.

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HG = W AT LOW NONINDUCTIVE RESISTOR DECADE 0-10 k, 1 STEP + CLAMP 2.2 M, 2W 51 k 2W 2.2 M, 2W - CLAMP

LD1010001000 LL RL TRIAD C30X 50 H, 3500 910 k 2W C L (NONPOLAR) Q3 Q1 MR760 MR760 2.2 M

MR760 2.2 M

CAPACITOR DECADE 1-10 F, 0.01-1 F, 100 pF- 0.01 F

51 k RS 2N3904

2W 2N3906 0.01

2.2 M

01 kV 20 mA

0.01

120 1/2 W

1/2 W 120

2N3906 -5 PEARSON 301 X 360 1k

150 k

6.2 MEG 2N3904 +5

2W

2N3906 0.1 2N3904

2N3904 0.1 2N3906 2 51 2W 51 1 2W -5 G TRIAC UNDER TEST CASE CONTROLLED HEATSINK 56 2 WATT 0.22

Q3

Q1

1/2 W

360

1/2 W 1k

2N3904 Q3 270 k + Q1 270 k 2N3906 0.22

CS

+5

dV dt SYNC

2.2 k 1/2

1N5343 7.5 V

CL +

Ip T I PK + W 0 V Ci 2 p V Ci

LL +

V Ci 2 + T W 0 I PK 4 p 2C

W0 +

LL

dI dt

+ 6f I PK

10 *6 Ams

Figure 6.39.

dV Test Circuit For Power TRIACs dt

c

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2.2 M

62 F 1 kV

910 k 2W
6.2 MEG 2W

+ 1.5 kV - 70 mA

AN1048/D
APPENDIX C dV DERIVATIONS dt
DEFINITIONS 1.0 R T + R L ) R S + Total Resistance 1.1 M + RS RT + Snubber Divider Ratio CONSTANTS (depending on the damping factor): 2.1 No Damping ( + 0) w + w0 RT + a + + 0 2.2 Underdamped (0 t t 1) w + w0 2 * a 2 + w0

1 * 2
L, C C+ 2 a RT

2.3 Critical Damped ( + 1) a + w0, w + 0, R + 2 2.4 Overdamped ( u 1) w + a 2 * w0 2 + w0 + Wave Decrement Factor

1.2 w0 +

1 + Undamped Natural Frequency L CS

w + Damped Natural Frequency RT 2L

2 * 1

1.3 a +

Laplace transforms for the current and voltage in Figure 40 are:

3.0 i (S) + S V 0 L* c EL)SI ; e +E * S RT RT S 2) ) 1 S) 1 S 2) S L L LC LC

1.4 2 +

12 LI2 Initial Energy In Inductor + 2 Final Energy In Capacitor 12 CV L + Initial Current Factor C

1.5 + I E 1.6 +

RT

C + a + Damping Factor w0 2 L

RL t=0 I

1.7 V 0 + E * R S I + Initial Voltage drop at t + 0 L across the load E RL 1.8 c + I * L CS dV + Initial instantaneous dV at t + 0, ignoring dt 0 dt any initial instantaneous voltage step at t + 0 because of I RRM

RS e CS

INITIALCONDITIONS I + I RRM VC + 0 S

Figure 6.40. Equivalent Circuit for Load and Snubber

The inverse laplace transform for each of the conditions gives:

UNDERDAMPED (Typical Snubber Design) 4.0 e + E * V 0 L a Cos (wt) * w sin (wt)e * at )

1.9

dV dt

+ V OL

RT L

) c. For all damping conditions

E RS 2.0 When I + 0, dV + dt 0 L dV + Maximum instantaneous dV dt max dt

c *at w sin (wt) e (w 2 * a 2 ) 4.1 de + V0 2a Cos (wt) ) sin (wt) eat) w L dt c Cos (wt) * a sin (wt) e at w

tmax + Time of maximum instantaneous dV dt tpeak + Time of maximum instantaneous peak voltage across thyristor

Average dV + V PK tPK + Slope of the secant line dt from t + 0 through V PK V PK + Maximum instantaneous voltage across the thyristor.

4.2

2a V0 L ) c 1 tan*1 * t PK + w 2 a2 ca V 0 w * * w L w
When M + 0, R S + 0, I + 0 : w t PK + p

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AN1048/D
2 2 2 4.3 V PK + E ) a * a tPK w0 V0 L ) 2ac V0 L) c w0 When I + 0, R L + 0, M + 1: 4.4 V PK E + (1 ) e * a t PK)

6.3 V PK + E * V0 (1a t PK)c tPK ea t PK L V PK 6.4 Average dV + tPK dt When I + 0, R S + 0, M + 0 e(t) rises asymptotically to E. t PK and average dV dt do not exist.

V PK Average dV + t PK dt 1 ATN 4.5 t max + w

w (2ac * V0 (w 2 * 3a 2)) L V0 (a 3 * 3aw 2) ) c(a 2 * w 2) L

6.5 t max +

4.6

dV +V0L2 w02) 2ac V0L ) c2 eatmax dt max

I sin (w t) 0 C w0 6.6

NO DAMPING 5.0 e + E (1 * Cos (w0t)) ) 5.1 5.2

3aV0 ) 2c L a 2V0 ) ac L When I + 0, t max + 0 RS y34, For RT + dV then dV dt 0 dt max

de + E w sin (w t) ) I Cos (w t) 0 0 0 dt C

dV dt

dV + I + 0 when I + 0 dt 0 C p * tan *1

+ a V0 (2a t max) ) c (1a t max) e a t max L

max

5.3 t PK + 5.4 V PK + E ) 5.5

CEIw0
I2 w 0 2C 2

w0

APPENDIX D SNUBBER DISCHARGE dI DERIVATIONS dt

OVERDAMPED 1.0 i + VC S a at sinh (wt) w LS

E2 )

V PK dV + t dt AVG PK

w0 EC 5.6 t max + 1 tan *1 w0 I 5.7

+ w10 p when I + 0 2

1.1 i PK + VC S

CS LS

e a t

PK

dV dt

max

+ I C

E2w02 C2)I2 + w0E when I+ 0

1 tanh 1 w 1.2 t PK + w a CRITICAL DAMPED 2.0 i + VC S te at LS

CRITICAL DAMPING 6.0 e + E * V0 (1 * at)e *at ) cte *at L 6.1 de + a V *at O L (2 * at) ) c(1 * at) e dt 2) 6.2 t PK + c 2 V 0L c V0 L

VC S 2.1 i PK + 0.736 RS 1 2.2 t PK + a

a)

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AN1048/D
UNDERDAMPED VC S e at sin (wt) 3.0 i + w LS 3.1 i PK + VC S NO DAMPING 4.0 i + VC S sin (wt) w LS

CS LS

e a t

PK

4.1 i PK + VC S 4.2 t PK + p 2w

CS LS

1 tan 1 w 3.2 t PK + w a

RS t=0
VC S

LS

CS

INITIALCONDITIONS : i + 0, V C + INITIALVOLTAGE S

Figure 6.41. Equivalent Circuit for Snubber Discharge

BIBLIOGRAPHY Bird, B. M. and K. G. King. An Introduction To Power Electronics. John Wiley & Sons, 1983, pp. 250281. Blicher, Adolph. Thyristor Physics. Springer-Verlag, 1976. Gempe, Horst. Applications of Zero Voltage Crossing Optically Isolated TRIAC Drivers, AN982, Motorola Inc., 1987. Guide for Surge Withstand Capability (SWC) Tests, ANSI 337.90A-1974, IEEE Std 4721974. IEEE Guide for Surge Voltages in Low-Voltage AC Power Circuits, ANSI/IEEE C62.41-1980, IEEE Std 5871980. Ikeda, Shigeru and Tsuneo Araki. The dI Capability of Thyristors, Proceedings of the IEEE, Vol. 53, No. 8, August 1967.
dt

Kervin, Doug. The MOC3011 and MOC3021, EB-101, Motorola Inc., 1982. McMurray, William. Optimum Snubbers For Power Semiconductors, IEEE Transactions On Industry Applications, Vol. IA-8, September/October 1972. Rice, L. R. Why R-C Networks And Which One For Your Converter, Westinghouse Tech Tips 5-2. Saturable Reactor For Increasing Turn-On Switching Capability, SCR Manual Sixth Edition, General Electric, 1979. Zell, H. P. Design Chart For Capacitor-Discharge Pulse Circuits, EDN Magazine, June 10, 1968.

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